TW339469B - Methods to prevent divot formation in shallow trench isolation areas and integrated circuit chip formed thereby - Google Patents
Methods to prevent divot formation in shallow trench isolation areas and integrated circuit chip formed therebyInfo
- Publication number
- TW339469B TW339469B TW086110104A TW86110104A TW339469B TW 339469 B TW339469 B TW 339469B TW 086110104 A TW086110104 A TW 086110104A TW 86110104 A TW86110104 A TW 86110104A TW 339469 B TW339469 B TW 339469B
- Authority
- TW
- Taiwan
- Prior art keywords
- methods
- integrated circuit
- circuit chip
- trench isolation
- shallow trench
- Prior art date
Links
- 230000015572 biosynthetic process Effects 0.000 title abstract 2
- 238000000034 method Methods 0.000 title abstract 2
- 238000002955 isolation Methods 0.000 title 1
- 239000000463 material Substances 0.000 abstract 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 238000005530 etching Methods 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
- 238000001039 wet etching Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/740,907 US5923991A (en) | 1996-11-05 | 1996-11-05 | Methods to prevent divot formation in shallow trench isolation areas |
Publications (1)
Publication Number | Publication Date |
---|---|
TW339469B true TW339469B (en) | 1998-09-01 |
Family
ID=24978563
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW086110104A TW339469B (en) | 1996-11-05 | 1997-07-16 | Methods to prevent divot formation in shallow trench isolation areas and integrated circuit chip formed thereby |
Country Status (3)
Country | Link |
---|---|
US (1) | US5923991A (zh) |
KR (1) | KR100244847B1 (zh) |
TW (1) | TW339469B (zh) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6319794B1 (en) * | 1998-10-14 | 2001-11-20 | International Business Machines Corporation | Structure and method for producing low leakage isolation devices |
US6316815B1 (en) * | 1999-03-26 | 2001-11-13 | Vanguard International Semiconductor Corporation | Structure for isolating integrated circuits in semiconductor substrate and method for making it |
US6207513B1 (en) | 1999-11-02 | 2001-03-27 | Infineon Technologies North America Corp. | Spacer process to eliminate corner transistor device |
US6277710B1 (en) | 1999-11-15 | 2001-08-21 | Chartered Semiconductor Manufacturing Ltd. | Method of forming shallow trench isolation |
US6541351B1 (en) * | 2001-11-20 | 2003-04-01 | International Business Machines Corporation | Method for limiting divot formation in post shallow trench isolation processes |
US6524938B1 (en) | 2002-02-13 | 2003-02-25 | Taiwan Semiconductor Manufacturing Company | Method for gate formation with improved spacer profile control |
US7666746B2 (en) * | 2008-01-14 | 2010-02-23 | International Business Machines Corporation | Semiconductor transistors having high-K gate dielectric layers, metal gate electrode regions, and low fringing capacitances |
US8546219B2 (en) | 2011-10-13 | 2013-10-01 | International Business Machines Corporation | Reducing performance variation of narrow channel devices |
US8603895B1 (en) | 2012-09-11 | 2013-12-10 | Globalfoundries Inc. | Methods of forming isolation structures for semiconductor devices by performing a deposition-etch-deposition sequence |
US9698043B1 (en) | 2016-05-20 | 2017-07-04 | International Business Machines Corporation | Shallow trench isolation for semiconductor devices |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4755479A (en) * | 1986-02-17 | 1988-07-05 | Fujitsu Limited | Manufacturing method of insulated gate field effect transistor using reflowable sidewall spacers |
US4942137A (en) * | 1989-08-14 | 1990-07-17 | Motorola, Inc. | Self-aligned trench with selective trench fill |
US5118382A (en) * | 1990-08-10 | 1992-06-02 | Ibm Corporation | Elimination of etch stop undercut |
US5234852A (en) * | 1990-10-10 | 1993-08-10 | Sgs-Thomson Microelectronics, Inc. | Sloped spacer for MOS field effect devices comprising reflowable glass layer |
US5498565A (en) * | 1991-11-29 | 1996-03-12 | Sony Corporation | Method of forming trench isolation having polishing step and method of manufacturing semiconductor device |
US5229316A (en) * | 1992-04-16 | 1993-07-20 | Micron Technology, Inc. | Semiconductor processing method for forming substrate isolation trenches |
KR950002951B1 (ko) * | 1992-06-18 | 1995-03-28 | 현대전자산업 주식회사 | 트렌치 소자분리막 제조방법 |
US5382541A (en) * | 1992-08-26 | 1995-01-17 | Harris Corporation | Method for forming recessed oxide isolation containing deep and shallow trenches |
US5433794A (en) * | 1992-12-10 | 1995-07-18 | Micron Technology, Inc. | Spacers used to form isolation trenches with improved corners |
US5494857A (en) * | 1993-07-28 | 1996-02-27 | Digital Equipment Corporation | Chemical mechanical planarization of shallow trenches in semiconductor substrates |
US5472904A (en) * | 1994-03-02 | 1995-12-05 | Micron Technology, Inc. | Thermal trench isolation |
US5492858A (en) * | 1994-04-20 | 1996-02-20 | Digital Equipment Corporation | Shallow trench isolation process for high aspect ratio trenches |
US5447884A (en) * | 1994-06-29 | 1995-09-05 | International Business Machines Corporation | Shallow trench isolation with thin nitride liner |
US5459096A (en) * | 1994-07-05 | 1995-10-17 | Motorola Inc. | Process for fabricating a semiconductor device using dual planarization layers |
US5521422A (en) * | 1994-12-02 | 1996-05-28 | International Business Machines Corporation | Corner protected shallow trench isolation device |
FR2734403B1 (fr) * | 1995-05-19 | 1997-08-01 | Sgs Thomson Microelectronics | Isolement plan dans des circuits integres |
-
1996
- 1996-11-05 US US08/740,907 patent/US5923991A/en not_active Expired - Fee Related
-
1997
- 1997-07-16 TW TW086110104A patent/TW339469B/zh active
- 1997-08-14 KR KR1019970038798A patent/KR100244847B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR19980041816A (ko) | 1998-08-17 |
US5923991A (en) | 1999-07-13 |
KR100244847B1 (ko) | 2000-03-02 |
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