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A semiconductor memory module includes 1st plural addressable memory devices responding to 1st and 2nd timing signal to activate one or more selected devices. Its features are: The memory module includes 2nd plural addressable memory devices, which can substitute 1st plural addressable memory devices and respond to 3rd and 4th timing signal separately corresponding to 1st and 2nd timing signal. And control device that is responding to one or more received timing signal to generate one of 3rd or 4th timing signal.