TW332291B - Semiconductor memory, device for driving data signal of circuit to wanted level, circuit for driving first and second signal to wanted level, DRAM structure, method for driving data signal to wanted level, method for driving first and second signal to wa - Google Patents

Semiconductor memory, device for driving data signal of circuit to wanted level, circuit for driving first and second signal to wanted level, DRAM structure, method for driving data signal to wanted level, method for driving first and second signal to wa

Info

Publication number
TW332291B
TW332291B TW086100328A TW86100328A TW332291B TW 332291 B TW332291 B TW 332291B TW 086100328 A TW086100328 A TW 086100328A TW 86100328 A TW86100328 A TW 86100328A TW 332291 B TW332291 B TW 332291B
Authority
TW
Taiwan
Prior art keywords
driving
voltage
signal
pair
power terminal
Prior art date
Application number
TW086100328A
Other languages
Chinese (zh)
Inventor
Rex Plunkett George
Takesada Akiba
Gorou Kitsukawa
Hugh Mcadams
Original Assignee
Hitachi Ltd
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Texas Instruments Inc filed Critical Hitachi Ltd
Application granted granted Critical
Publication of TW332291B publication Critical patent/TW332291B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)

Abstract

A semiconductor memory have (1) Bit line pair; (2) A plurality of word lines; (3) A plurality of dynamic cells, each is combined with one of bit lines constituting said bit line pair and one of said a plurality of word lines; (4) Sense amplifier including a pair of PMOS transistors and a pair of NMOS transistors, in which the PMOS transistor pair and the NMOS transistor pair have commonly connected source respectively, and drain respectively connected to said bit line pair, and gate cross-connected to the drain; (5) First power terminal; (6) Second power terminal; (7) First switch transistor connected between said first power terminal and said source of said PMOS transistor; (8) Second switch transistor connected between said second power terminal and said source of said PMOS transistor; (9) Voltage generator for providing first voltage lower than second voltage provided by said second power terminal; And comprises the features: (1) Said sense amplifier for providing complementary signals having H-side voltage and L-side voltage to said bit line pair based on relating information of memory cell selected by said a plurality of dynamic memory; (2) During first period, in response to enable state of said second switch transistor, the said H-side voltage rises to above said first voltage; (3) During second period after said first period, in response to enable state of said first switch transistor, the said H-side voltage falls, thereby forces said H-side voltage to be set to said first voltage.
TW086100328A 1996-01-26 1997-01-14 Semiconductor memory, device for driving data signal of circuit to wanted level, circuit for driving first and second signal to wanted level, DRAM structure, method for driving data signal to wanted level, method for driving first and second signal to wa TW332291B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US998496P 1996-01-26 1996-01-26

Publications (1)

Publication Number Publication Date
TW332291B true TW332291B (en) 1998-05-21

Family

ID=21740850

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086100328A TW332291B (en) 1996-01-26 1997-01-14 Semiconductor memory, device for driving data signal of circuit to wanted level, circuit for driving first and second signal to wanted level, DRAM structure, method for driving data signal to wanted level, method for driving first and second signal to wa

Country Status (4)

Country Link
JP (1) JP3810160B2 (en)
KR (1) KR100443100B1 (en)
SG (1) SG63689A1 (en)
TW (1) TW332291B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7423911B2 (en) 2005-09-29 2008-09-09 Hynix Semiconductor Inc. Bit line control circuit for semiconductor memory device

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6535415B2 (en) 1999-02-22 2003-03-18 Hitachi, Ltd. Semiconductor device
KR100551070B1 (en) * 2000-12-30 2006-02-10 주식회사 하이닉스반도체 Sense amp overdrive circuit for increasing current efficiency and stability
KR100746615B1 (en) 2006-02-20 2007-08-06 주식회사 하이닉스반도체 Sense amplifier control circuit and semiconductor device
KR100869341B1 (en) * 2007-04-02 2008-11-19 주식회사 하이닉스반도체 Semiconductor memory device and operation method thereof
JP4998443B2 (en) * 2008-12-01 2012-08-15 富士通セミコンダクター株式会社 Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7423911B2 (en) 2005-09-29 2008-09-09 Hynix Semiconductor Inc. Bit line control circuit for semiconductor memory device

Also Published As

Publication number Publication date
KR100443100B1 (en) 2004-10-28
JP3810160B2 (en) 2006-08-16
KR970060232A (en) 1997-08-12
SG63689A1 (en) 1999-03-30
JPH09204777A (en) 1997-08-05

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees