TW329044B - Method for defining via pattern - Google Patents
Method for defining via patternInfo
- Publication number
- TW329044B TW329044B TW086105701A TW86105701A TW329044B TW 329044 B TW329044 B TW 329044B TW 086105701 A TW086105701 A TW 086105701A TW 86105701 A TW86105701 A TW 86105701A TW 329044 B TW329044 B TW 329044B
- Authority
- TW
- Taiwan
- Prior art keywords
- photo resist
- layer
- hardmask
- resist layer
- dielectric layer
- Prior art date
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A method for defining via pattern comprises the following steps: - providing a substrate with at least one MOS on it and a dielectric layer being formed nakedly on the MOS; - forming a hardmask on the surface of the dielectric layer; - spreading a photo resist layer on the hard mask; - defining the pattern of the photo resist layer and removing the hardmask formed by the photo resist layer to form an opening for the dielectric layer; - using the hardmask and the photo resist layer as a mask and removing simultaneously the photo resist layer and the dielectric layer to form via and to form a polymer layer on the surface of the hardmask; - and removing the polymer layer to obtain a hard mask.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW086105701A TW329044B (en) | 1997-04-30 | 1997-04-30 | Method for defining via pattern |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW086105701A TW329044B (en) | 1997-04-30 | 1997-04-30 | Method for defining via pattern |
Publications (1)
Publication Number | Publication Date |
---|---|
TW329044B true TW329044B (en) | 1998-04-01 |
Family
ID=58262490
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW086105701A TW329044B (en) | 1997-04-30 | 1997-04-30 | Method for defining via pattern |
Country Status (1)
Country | Link |
---|---|
TW (1) | TW329044B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7452821B2 (en) | 2001-06-08 | 2008-11-18 | Infineon Technologies Ag | Method for the formation of contact holes for a number of contact regions for components integrated in a substrate |
-
1997
- 1997-04-30 TW TW086105701A patent/TW329044B/en not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7452821B2 (en) | 2001-06-08 | 2008-11-18 | Infineon Technologies Ag | Method for the formation of contact holes for a number of contact regions for components integrated in a substrate |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2000031775A3 (en) | A method of manufacturing an electronic device comprising two layers of organic-containing material | |
GB2387028A (en) | Control trimming of hard mask for transistor gate | |
EP1022771A3 (en) | Improved contact and deep trench patterning | |
TW344866B (en) | Method for forming damage free patterned layers adjoining the edges of high step height apertures | |
WO2002080239A3 (en) | Process for forming sub-lithographic photoresist features | |
MY113878A (en) | Semiconductor apparatus having wiring groove and contact hole formed in self-alignment manner and method of fabricating the same | |
WO2002017387A3 (en) | Conductive material patterning methods | |
EP1321821A4 (en) | Photoresist composition for forming insulation film, insulation film for organic electroluminescence element and method for its formation | |
TW328147B (en) | Semiconductor device fabrication | |
TW353775B (en) | Production of semiconductor device | |
EP1732371A3 (en) | Method of forming a conductive pattern on a substrate | |
KR950000658B1 (en) | Forming method of contact hole in semiconductor devices | |
WO1998002913A3 (en) | Method of forming a gate electrode for an igfet | |
WO2001099164A3 (en) | Patterning method using a removable inorganic antireflection coating | |
AU2001292199A1 (en) | Method for the formation of a pattern on an insulating substrate | |
EP0779556A3 (en) | Method of fabricating a semiconductor device | |
TW329044B (en) | Method for defining via pattern | |
TW346668B (en) | Contact formation for a semiconductor device | |
EP0984328A3 (en) | A method of surface etching silica glass, for instance for fabricating phase masks | |
TW430943B (en) | Method of forming contact or wiring in semiconductor device | |
TW399298B (en) | Manufacturing method of via hole | |
TW331699B (en) | Fabricating a surface laminar circuit | |
WO2001065595A3 (en) | A method of forming an opening or cavity in a substrate for receiving an electronic component | |
CA2324675A1 (en) | A substrate for mounting an optical component, a method for producing the same, and an optical module using the same | |
KR970013022A (en) | Method for forming contact hole in semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MK4A | Expiration of patent term of an invention patent |