TW325569B - Parallel non-volatile semiconductor memory device and method of using the same - Google Patents

Parallel non-volatile semiconductor memory device and method of using the same

Info

Publication number
TW325569B
TW325569B TW085104085A TW85104085A TW325569B TW 325569 B TW325569 B TW 325569B TW 085104085 A TW085104085 A TW 085104085A TW 85104085 A TW85104085 A TW 85104085A TW 325569 B TW325569 B TW 325569B
Authority
TW
Taiwan
Prior art keywords
individual
domain
source
drain
memory device
Prior art date
Application number
TW085104085A
Other languages
Chinese (zh)
Inventor
Masataka Kato
Tetsuo Ashitate
Hitoshi Kume
Takashi Kobayashi
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP08100395A external-priority patent/JP3328463B2/en
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of TW325569B publication Critical patent/TW325569B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G11C5/146—Substrate bias generators

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)

Abstract

A parallel non-volatile semiconductor memory device comprising a plurality of memory cells arranged in a matrix comprised of, on a semiconductor substrate, MOS type electric field effect transistors (hereinafter referred as MOS transistors) with a control gate, a floating gate, a gate insulation membrane, a drain domain and a source domain, in which the control gates in each column are connected with each other through individual word lines, the drain domains in each row are connected with each other through individual data lines, and the source domains in each row are connected with each other through individual source lines and constitute memory rows connected in parallel, which is characterized in that: the individual MOS transistor on a conductive type semiconductor substrate is electrically separated from a well of the same conductive type on the substrate and separately forms a drain domain and a source domain, and the wells in each memory cell are connected with each other through a well wiring.
TW085104085A 1995-04-06 1996-04-08 Parallel non-volatile semiconductor memory device and method of using the same TW325569B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP08100395A JP3328463B2 (en) 1995-04-06 1995-04-06 Parallel nonvolatile semiconductor memory device and method of using the same

Publications (1)

Publication Number Publication Date
TW325569B true TW325569B (en) 1998-01-21

Family

ID=49515848

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085104085A TW325569B (en) 1995-04-06 1996-04-08 Parallel non-volatile semiconductor memory device and method of using the same

Country Status (2)

Country Link
KR (1) KR100375427B1 (en)
TW (1) TW325569B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102179035B1 (en) * 2014-03-07 2020-11-16 삼성전자주식회사 Semiconductor device

Also Published As

Publication number Publication date
KR960039364A (en) 1996-11-25
KR100375427B1 (en) 2003-07-18

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees