A7 τ *" ----— 五、發明説明（1) * ---- 本發明是有關於半遙辨 、千導體記憶裝置，特別是有關於和時 脈信號同步動作的同步裀主 7 '導體記憶裝置。 背景技術 (請先閲讀背面之注意事項再填寫本頁) 現在已經量產化的J51 at 〇问步型半導體記憶裝置(以下稱爲 SDAM)，其内部具備模式暫 、w 仔為（mode register)。在 4吏用 者使用時，可以在模式智左览 . , 、货呑姦（mode register)中設定裁讯 長度（BL)和CAS潛伏時間（丨atency)。 但是，所謂载訊長度，是表示在一次存取周期★中， 連續讀出或者寫入的資料數目。以SDRAM @言，具有 BL=!，2,4,8 ，依晶片而有不同的整頁模式（full_page mode)。另外，所謂CAS潛伏時間，是表示讀出命令被賦 7* -<後’ Η料從輸出緩衝器到輸出爲止的時脈周波數。以 SDRAM而言，通常具有CL=23 ，依晶片而具有 CL—1,4。 在此f莫式暫存姦（m〇c[e regjster)中設定的载訊長度和 C A S潛伏時間的動作模式在被重新設定之前雖然並没^重 新寫入，一旦電源關畢，因爲糢式暫存器（m〇de registe^ 被重新設定而使已設定的資料遺失。 經濟部中央標準局員工消費合作杜印製 本發明的目的是提供一種即使關掉電源也不會讓已詁 定的動作模式遺失的同步型半導體記憶裳置。 本發明的目的可由提供具有下列特徵的同步型半導體 記憶裝置來達成：記憶資料的記德體、可產生和外部時腺 信號連接的内部時脈信號的時脈緩衝器、可產生與内部時 脉信號響應並與外部控制信號連接的内部控制信號的輸人 本紙张尺度適用中國國家標準（CNS) A4規格（210x297公釐） ---- A7 B7 五、發明説明（2) 緩衝.器、可產,生與内部時脈信號響應並與外部位址尸號 連接的内部位址信號的位址緩衝器、從記憶體讀：資：： 讀出回路:將外部資料寫入記憶體的寫入回路、與内部時 脈信號及》^控制信號響應而同時記憶動作模式益依此動 作模式控制讀出回路與寫入回路的非揮發性記情體。· 而且，本發明的主要優點在於：因爲讓動作模式記情 在非揮發性記憶體，即使電源關閉後再打開 ~ : *祕動作模式…利用記憶在非揮發 作模式舟起動同步型半導體記憶裝置。 屬弍說明 第1圖是闢於實現本發明的最佳型態的同步型半導體 記德裝置之構成圖。 ' 第2圖是説明在第！圖中表示的記憶體與模式解碼器 的動作而用來簡啗表示其構成之構成圖。 實施例之説明 經濟部中央標準局員工消費合作社印製 ---------裝—— (請先閱讀背面之注意事項再填寫本頁) 接下來，參照圖面説明作爲實現本發明的最佳型態的 同步型半導體記憶裝置。再者’目中同—符號表示相；或 怕贫的部.h c參知、第1圖，關於本發明的同步型半導體纪 憶裝置具備下列特徵：資料輸出入端子20。記憶ϋ 枓_出入端子20的外部資料的記憶格陣列35。在記惊袼 陣列Μ中選擇成爲資料的讀出或寫入對象之行的行選擇 同路33 。相同地，選擇成爲資料的讀出或寫入對象 的列選擇回路29。與外部時脈信號Ext clk連接的輸入綉 衝器3。遠接從輸入緩衝器3轎出的信號而產生與内部時 ^張尺度適用中國國家標準（(：阳）厶4規格（210乂297公釐） 經濟部中央標準局員工消f合作社印製 A7 B7 五、發明説明（3) '~—— 脈信號Int. c!k.的時脈緩衝器5。與同步於在時脈緩衝哭 5產生的内部時脈信號Int. clk.的列位址重覆信號 /’RAS(r〇w address strobe)、行位址重覆信號/CAS (c〇i聰〇 address strobe)、寫入致能信號/WE(wnte enable)、晶片選 擇信號/CS(c丨ιΦ select)等的外部控制信號輸入相連接並產 生内部控制信號的輪入緩衝器丨。與同步於上逑内部時脈 信號丨nt. elk.的外部位址信號A1〜An輸入相連接並產生 内部位址信號的位址緩衝器7。將上述内部位址信號之中 的列位垃信號解碼而驅動列選擇回路29的列解碼器。 將上述内部位址信號之中的行位址信號解碼而驅動行選擇 :路33的行解碼器31。按照在上述輸入緩衝器丨輸入的 HAS、CAS、WE.的組合，產生能輸出讀出命令信號 Read、舄入命令信號Wnte、模式暫存器設定信號（_知 哪ster set)MRS的命令解碼器9。包含cAS潛伏時間嗲 :區丨30、载訊長度設定區⑶和载訊形式設定區(未圖 印依照模式暫存器設定信號（_de卿如叫咖作 號，随著輪入位址緩衝器7的外部位址信號Μ,的紐 ^㈤潛伏時間和裁訊長度等之動作模式的模式 。記憶爲設定動作模式的上述内部位址信號與 U 號（m〇de register set)MRS 信號的記 。將記料Π記憶的信號解碼而供給模式暫存哭 糢气=解碼器！2。響應在模式暫存器Π中設定的動作 時脈信號ilU *以及讀出命令信號㈤而產 一…口動信號_和讀出控制信號的讀出控制回路 (〇奶）人4規格（210/ 297公羞A7 τ * " ----— V. Description of the invention (1) * ---- The present invention relates to a semi-remote discrimination and a thousand-conductor memory device, in particular, to a synchronous master that operates synchronously with a clock signal 7 'Conductor memory device. 2. Description of the Related Art (Please read the precautions on the back and then fill out this page) The J51 at 〇Walk-step semiconductor memory device (hereinafter referred to as SDAM), which has been mass-produced, has a mode temporary and mode register inside. . When using it by 4 users, you can set the arbitration length (BL) and CAS latency (丨 atency) in the mode view.., Mode register. However, the so-called carrier length refers to the number of data continuously read or written in one access cycle ★. Taking SDRAM @ 言, with BL = !, 2,4,8, there are different full page modes (full_page mode) according to the chip. In addition, the CAS latency indicates the number of clock cycles from the output buffer to the output after the read command is assigned to 7 *-<. In terms of SDRAM, it usually has CL = 23 and CL-1,4 depending on the chip. In this mode, the operation mode of the carrier length and CAS latency set in mοc [e regjster) is not rewritten before it is reset. Once the power is turned off, because the mode is temporarily The memory (m〇de registe ^ is reset and the set data is lost. The Central Standards Bureau of the Ministry of Economic Affairs employee consumption cooperation du printing. The purpose of the present invention is to provide a kind of action that will not make it even if the power is turned off Synchronous semiconductor memory device with lost mode. The object of the present invention can be achieved by providing a synchronous semiconductor memory device with the following characteristics: a memory for storing data, a time for generating an internal clock signal connected to an external clock signal Pulse buffer, input paper that can generate internal control signal that responds to internal clock signal and connects to external control signal applies to China National Standard (CNS) A4 specification (210x297 mm) ---- A7 B7 5. Description of the invention (2) Buffer. Device, productive, address buffer for internal address signals that responds to internal clock signals and connects to external addresses, read from memory: data ：: Readout circuit: write circuit that writes external data into the memory, and responds to internal clock signal and》 ^ control signal while memorizing the operation mode. According to this operation mode, the readout circuit and the write circuit are nonvolatile. Sexual memory. · Moreover, the main advantage of the present invention is: because the action mode is remembered in non-volatile memory, even after the power is turned off and then turned on ~: * Secret action mode ... use memory to start in non-volatile operation mode Synchronous semiconductor memory device. The description of Figure 1 is a configuration diagram of a synchronous semiconductor memory device that realizes the best type of the present invention. Figure 2 is a diagram illustrating the memory and The operation of the mode decoder is used to simply show the composition of the composition. The description of the embodiments is printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs --------- installed ---- (please read the notes on the back first Please fill in this page again.) Next, the synchronous semiconductor memory device as the best type for realizing the present invention will be described with reference to the drawings. Furthermore, the same symbol in the head indicates the phase; or the poverty-stricken department. Figure 1, the synchronous semiconductor memory device of the present invention has the following features: data input / output terminal 20. Memory _ memory cell array 35 of external data of the input / output terminal 20. Selected as data in the memory array M The row selection line of the line to be read or written is the same as the channel 33. Similarly, the column selection circuit 29 to be read or written to the data is selected. The input embroidery device 3 is connected to the external clock signal Ext clk. The signal output from the input buffer 3 car is generated remotely and the internal time ^ Zhang scale is applicable to the Chinese national standard ((: Yang) 厶 4 specifications (210 to 297 mm). The A7 is printed by the employees ’cooperative of the Central Standard Bureau of the Ministry of Economic Affairs B7 5. Description of the invention (3) '~ ——The clock buffer 5 of the pulse signal Int. C! K. Column address repeat signal / 'RAS (r〇w address strobe), row address repeat signal / CAS (c〇i 聪) synchronized with the internal clock signal Int. Clk. Generated in the clock buffer 5 ○ address strobe), write enable signal / WE (wnte enable), wafer select signal / CS (cIO Φ select) and other external control signal inputs are connected to generate a round-robin buffer for internal control signals. The address buffer 7 is connected to the external address signals A1 ~ An input synchronized with the internal clock signal nt. Elk. And generates an internal address signal. The column decoder of the column selection circuit 29 is driven by decoding the column bit signal among the internal address signals. The row address signal among the above-mentioned internal address signals is decoded to drive the row selection: the row decoder 31 of the way 33. According to the combination of HAS, CAS, WE. Input in the above input buffer, the command decoding that can output the read command signal Read, the input command signal Wnte, the mode register setting signal (_ 知 哪 ster set) MRS is generated器 9. Including cAS latency time zone: zone 丨 30, carrier length setting zone (3) and carrier form setting zone (not picture printed according to the mode register setting signal (_deqing is called as a work number, with the address buffer in turn 7. The external address signal M, the button ^ (latency time and clipping length, etc.) of the operation mode mode. The memory is set to the operation mode of the internal address signal and U (m〇de register set) MRS signal. Decode the signal of the memory Π and supply it to the mode temporary storage mode = decoder! 2. In response to the action clock signal ilU * set in the mode temporary memory Π and the read command signal (i), produce a ... Signal_ and readout control circuit (〇 milk) of readout control signal 4 specifications (210/297 gong)
(請先閲讀背面之>i意事項'再梭每本百C .裝 丁 . 、=0 a濟部中央標準局員工消费合作社印製 32S369 五、發明説明（4 ) ?。響應讀出控制信號而讀出記憶在記 貧料的讀出回路丨7。被戍 車巧3 5的 风啓動信號OEM啓動，、* 4、 出回路1 7所讀出的資料而扒 連接由讀 车則出貧料輸出入端子）n i 緩衝器ί9。響應在模式暫在~〇的輪出 部時脈信號hn.clk.以及^二3中設足的動作模式和内 „ 呙入命令信號Wme而產生奁 制信號的寫入控制回路2丨。 度生冩入控 广接在輸出料輸出入端子2〇輸入的外 入繼23。響應寫入控制信號，將從輸入緩衝= 出的資料寫人記憶格陣列35的寫人回路。。…輸 示意^’圖2是上述記憶區11與模式解碼&的“ 、細，如圖2上所表示，記憶區丨1是包 一 個位7L貧料的兩個非揮發性記憶元件】1〇、丨】1 Ϊ2是由反相器和NAND回路所構成。 ，早碼器 。接下來，説明此同步型半導體記憶裝置的動作。 ;ms、CAS、WE、cs應答内部時脈信號而全部以 低位準的狀態輸入輪入緩衝器， 暫存器設定《.嶋㈣式料9即輸出模式 ^者，此模式暫存器設定信號MRS在命令解… 輸出卜個模式暫存器設定信號MRS之前 憶區！ i 。 -.心仁也 ⑺且’接受此模式暫存器設定㈣MRs _式暫存 器13同時按照輸人位址緩衝器7而記憶在記憶區！|的外 邵位址信號A卜Ail的组合，分別在CAS潛伏時間設定區 b纸張尺度剌巾關家縣（CNS〉Λ<ί規格（2丨Qχ 29?公楚 (請先閱讀背面之注意事項再填寫本頁 -------^ 訂 經濟部中央標率局貞工消費合作社印聚 A7 B7 五'發明説明（5) Π0設定CAS潛伏時間、以及在載訊長度設定區13丨設定 裁訊長度。更具體的説，例如，裁訊長度是由外部^ 址信號AO、Al 、A2的組合所指定，而cAS潛伏時 是由外部位址信號A4、A5、八6的組合所指定。 如釔，一旦1買出控制回路1 5接到讀出命令信妒 Read，就會和部時脈信號hu dk同步而隨著設定在模式 暫存器i3的CAS潛伏時間及載訊長度來控制讀出回^ 】7 ，同時輸出的爲啓動輸出緩衝器丨9的輸出啓動俨 OEM【 " - 在另一万面，一旦寫入控制回路21接到寫入命令信 號Wnte，就會和部時脈信號int clk同步而随著設定二^ 式暫存器H CAS潛伏時間及栽訊長度來控制寫入回龄 25。 " 在此，如果關掉此同步型半導體記憶裝置的電源，雖 然一度設定在模式暫存器j3的CAS潛伏時間及载訊長戶 會消失掉，當電源再度投入時，基於記憶在記憶區丨丨$ 模式暫存器設定信號MRS以及内部位址信號，而在模式 暫存器13中設定和電源_之前相同的〔:As潛伏時間及 载訊長度。 以下，用圖2來説明記憶區丨丨的動作。 例如說，在記憶區丨1包含—個位元的兩個非揮發性 記憶元件}丨0、m的場合，假如記憶在非揮發性記憶元 件n〇,、丨11的位址資料爲（χ:γ)，當電源關掉時，若 ί〜皮汜饫爲（〇。〇) ’電源再度投Λ時，（〇 〇)會從記憶區 本紙張尺度適用中國國家榡準（CNS ) Λ4規格（210X297公釐） 裝— f請先閔讀背面之注意事項再填寫本ΪΓj 訂 .1 n II ---1- « - ;.n . A7 A7 經濟部中央標準局員工消費合作社印製 五、發明説明（6) "輸出，由解碼器丨2的反相器丨20輪出的信號八爲丨， 同時由f相器U〇、121、122輸出的信號B、C、D爲 〇〜冰來，再度設定由信號A爲丨來決定的C AS潛 伏時間的動作糢式。 同樣地’若（χ,γ)被記憶爲（〇,丨）的話，只有由反相器 121輸出的信號β爲！；若被記憶爲（⑽的話，只有由反 相請輸出的信號…；若被記憶爲。J)的話，只有 由反相益！ 23輸出的信號D爲1。 冉者，Τ以具體地考慮EPR〇M(電性可規劃唯讀記憶 體）和EEPRQM(電性可抹除再規劃唯讀記憶體刺爲上述 的非揮發性記憶元件11〇、ηι/以 ‘ 成的話’能約重覆的寫入更換。 。把的裝置來構 ，藉由以上的同步型半導體記憶裝置，因爲記憶 揮發性记億元件形成的記憶區丨丨的設 ^ 载訊長度等之動作模式的資料的緣故::伏％間和 ;新投入，讓—= 再者，上述記憶區Η是在糢式暫存器丨3 •虑輸入糢式暫存器13的模式暫存器設定俨號 解碼器12輪出的信號。或者，在相同二式=和從 内，記憶從CAS潛伏時間設定區！3〇和載訊長度 b丨輸出的信號也可得到同樣的效果。 、〜二 本紙張尺度適用中國國家榡準（CNS)八4規格（21〇χ 297公釐 (請先閱讀背面之注意事項再填.：-本頁 ---裝 '11(Please read the “I's Matters” on the back of the page, and then shuttle every 100 C. Ding., = 0 a 32S369 printed by the Employee Consumer Cooperative of the Central Bureau of Standards and Economics. V. Description of invention (4) ?. Responsive read control The signal is read and the memory is read in the reading circuit of the poor material. 7. The wind start signal OEM of the car Qiao 3 5 is started, * 4, the data read out of the circuit 17 is connected, and the connection is output by the car. Lean material input and output terminals) ni buffer ί9. In response to the clock signal hn.clk. And the operation mode and the internal command signal Wme set in the second out of the clock mode at the mode of ~ 0, the write control loop 2 which generates the limit signal is generated. The raw input control is widely connected to the external input of the input and output terminal 20. In response to the write control signal, the data from the input buffer = output is written to the write circuit of the memory array 35 .... ^ 'Figure 2 is the above memory area 11 and mode decoding & ", fine, as shown in Figure 2, memory area 丨 1 is a 7L lean material containing two non-volatile memory elements] 1〇, 丨】 1 Ϊ2 is composed of inverter and NAND circuit. , Early Coder. Next, the operation of this synchronous semiconductor memory device will be described. ; ms, CAS, WE, cs respond to the internal clock signal and all input into the buffer in a low level state, the register setting ". 嶋 ㈣ 式 料 9 is the output mode ^, this mode register setting signal The MRS is in the command solution ... The memory area before outputting a mode register setting signal MRS! i. -. Xinren also ⑺ and ‘accept this mode register setting (MRs _ type register 13 at the same time according to the input address buffer 7 and stored in the memory area! | The combination of the outer Shao address signal A Bu Ail, respectively in the CAS latent time setting area b paper scale 剌 涌 家 县 (CNS> Λ < ί specification (2 丨 Qχ 29? Gongchu (please read the back of the first Matters needing attention and then fill out this page ------- ^ Order the Ministry of Economic Affairs Central Standardization Bureau Zhengong Consumer Cooperative Printed A7 B7 Five 'Invention Description (5) Π0 Set the CAS latency time, and in the carrier length setting area 13丨 Set the clipping length. More specifically, for example, the clipping length is specified by the combination of external address signals AO, Al, and A2, while the latency of cAS is the combination of external address signals A4, A5, and 8. As specified, for example, yttrium, once 1 buys the control loop 15 and receives the read command letter Read, it will synchronize with the local clock signal hu dk and follow the CAS latency and load set in the mode register i3 Length to control the read back ^】 7, while the output is to start the output buffer 丨 9 output start OEM 【"-On the other side, once the write control circuit 21 receives the write command signal Wnte, it will It will be synchronized with the local clock signal int clk and set the ^ type register H CAS latency and plant length To control the write-back age of 25. " Here, if the power of this synchronous semiconductor memory device is turned off, although the CAS latency and the long-term carrier of the mode register j3 once set will disappear, when the power When re-input, based on the memory in the memory area, the mode register setting signal MRS and the internal address signal are set, and the mode register 13 is set with the same [: As latency and carrier length as before before the power supply. Hereinafter, the operation of the memory area 丨 丨 will be described using FIG. 2. For example, in the case where the memory area 丨 1 contains two nonvolatile memory elements of one bit} 丨 0, m, if the memory is in a non-volatile memory The address data of the components n〇, and 丨 11 is (χ: γ). When the power is turned off, if ί ~ 皮 汜 餫 is (〇.〇) 'When the power is turned on again, (〇〇) will be from the memory The size of the local paper is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297 mm). — F Please read the precautions on the back before filling in this ΪΓj order. 1 n II --- 1- «-; .n. A7 A7 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of Invention (6) & qu ot; output, the signal eight rounded by the inverter 丨 20 of the decoder 丨 2 is eight, while the signals B, C, and D output by the f-phase U〇, 121, 122 are 〇 ~ ice, set again The action mode of the latency of the AS is determined by the signal A as 丨. Similarly, if (χ, γ) is memorized as (〇, 丨), only the signal β output by the inverter 121 is! The memory is (⑽, only the signal output by the reverse phase ...; if it is remembered as .J), only the reverse phase benefits! 23 The output signal D is 1. Ran, T specifically considers EPR〇M (Electrically Programmable Read-Only Memory) and EEPRQM (Electrically Programmable Erase-Reprogrammable Read-Only Memory) as the above-mentioned non-volatile memory elements 11〇, ηι / 'Successful words' can be written and replaced repeatedly. The structure of the device is constructed by the above synchronous semiconductor memory device, because the memory area formed by the memory of the volatile billion-memory device is designed ^ the load length, etc. The reason for the data of the operation mode :: volt% time; new input, let — = Furthermore, the above memory area Η is in the mode register 丨 3 • Consider the mode register setting of input mode register 13 No. decoder 12 signal. Or, in the same two == and within, memorize the CAS latent time setting area! 3〇 and the signal length b 丨 output signal can also get the same effect. The paper size is applicable to the Chinese National Standard (CNS) 84 specifications (21〇χ 297 mm (please read the precautions on the back and then fill in.:-This page --- install '11