經濟部中央標準局員工消費合作社印製 38^38 Λ7 B7五'發明説明（1) 本發明係有關於一種薄膜電晶體及其製造方法，特別 是有關於一種用以製造一種平坦通道（flat-channel)底閘極 (bottom-gate)薄膜電晶體（TFT)之方法及其架構，此薄膜電 晶體應用於靜態隨機存取記憶體（S R A Μ)之記憶單元。 第1圖概要顯示一 SRAM記憶單元10。SRAM記憶 元10包含第1和第2驅動器N1和N2。實例上，驅動器 N1和N2是下拉NMOS元件N1和N2。N1的源極12和 N2的源極14連接至一參考電壓Vss，例如是一接地。N2 的汲極16和N1的閘極18相連接。N1的汲極20和N2的 閘極22相連接。第1圖中的SRAM記憶單元10亦包含兩 個負载元件L1和L2。每一負载元件L1和L2之一端24和 26均與參考電壓Vcc相連接，另外一端28和30分別與N1 和N2之汲極20和16相連接。參考電壓Vcc相對於Vss 係爲正値。 SRAM記憶單元10亦包含兩個附加之NMOS元件N3 和N4。元件N3和N4係作爲通行電晶體。N3和N4之閘 極32和34連接至一字元線其訊號値表示爲WORD。N3 和N4之源極36和38連接至兩位元線其訊號値分別表示爲 BIT和BIT。N3和N4之汲極40和42分別連接至N1和 N2之汲極20和16。 寫入記憶單元時，DATA(邏辑“1”或邏辑“0”)係置於 BIT訊號線上而DATA係置於BIT訊號線上。則WORD訊 號即可以確定。一讀取動作係開始於將BIT和BIT信號線 預先充電。WORD訊號即可以確定而BIT和BIT信號線其 3 -------i ,丨裝------訂------ _ ^ (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS〉Α4規格（210Χ297公釐） 320638 ΑΊ 經濟部中央標準局員工消費合作社印製 Β7 五、發明説明（2 ) 中一個信號將被下拉電晶體N1和N2其中之一放電。 負载元件L1和L2之目的係爲了反制在N1和N2之汲 極20和16之充電的漏電效果。負载元件L1和L2可能是 複晶矽電阻器或是PMOS元件。如果L1和L2是PMOS元 件之情況下，PMOS元件之源極連接至Vcc ; PMOS元件 之汲極連接至N1和N2之汲極20和16 ;以及PMOS元件 L1和L2之閘極連接至NMOS下拉電晶體N1和N2之閘 極。 爲了減少SRAM記憶單元10之尺寸以利於未來之高 密度和低待機功率之用途，負载元件L1和L2可能將以薄 膜PMOS電晶體來實施。在此一情形下，此一 SRAM記憶 單元10都被稱爲TFT SRAM記憶單元。負載元件L1和L2 亦可使用完全CMOS記憶單元來實施。然而，一完全CMOS 元件所需之面積遠大於相對之TFT記憶單元所需之面積。 此外，以完全CMOS元件作爲負载其成本遠大於以TFT元 件作爲負载所需。因此，在低功率應用中均以TFT元件來 作爲負载元件L1和L2。 第2圖顯示TFT SRAM記憶單元50。TFT SRAM記 憶單元50之負载元件以P1和P2表示，其係由PMOS薄膜 電晶體（TFT)所構成。P1和P2之源極52和54連接至Vcc 而P1和P2之汲極56和58連接至N1和N2之汲極20和 16(以及N3和N4之汲極40和42)。P1和P2之閘極60和 62分別連接至N1和N2之閘極18和22。 分支70包含P1和N1，當P1導通時流過分支70之電 I I 裝—11.— 11訂 九 泳 - J (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 322638 A7 B7 五、發明説明（3 ) 流表示爲Ion，當P1開路時流過分支70之電流表示爲 Ioff。（同此方式，Ion和Ioff也用以表示流過包含P2和 N25之分支80之電流）。對每一低功率應用而言需要節省 功率，也就是低待機功率，所以其需要大導通電流Ion和 一小的漏電電流Ioff使得Ion/Ioff之比例最大。 第3a到3c圖和第4圖顯示第2圖中之TFT SRAM記 憶單元50之習知TFT SRAM架構100的形成，圖中僅顯示 其中之一分支例如分支70。如第3a圖所示，TFT SRAM 架構100有一 N型矽基材112在其中有一 P型丼114形成。 N+型汲極116和N+型源極118在P型丼114中形成，兩者 之間有一通道120分隔開。一閘極氧化層122於源極118， 汲極116和通道120之上形成。蝕刻部份氧化層122以在 部份汲極116之上露出一開口 124。沈積一第1複晶矽層 126(poly-l)於氧化層122和開口 124之上。 如第3b圖所示，定義poly-1層126圖案並使用N型離 子128實行掺雜以形成一 N+型閘極130於通道120之上和 一 N+型汲極連接140於汲極116之暴露部份之上（也就是於 開口 114之上）。汲極116、源極118和閘極130相對於第 1和第2圖所示N1下拉電體晶之汲極20、源極12和閘極 18。接著，在閘極130和氧化曆122之上形成一厚複晶矽 間介電廣 145 (inter-poly dielectric，IPD)。定義 IPD 層 145圖案以露出N+型汲極連接140。IPD層145隔離第2 圖之TFT P1和位於其下方之驅動器N1。定義IPD層145 圖案以形成一露出部份N+型汲極連接140之通孔洞或開口 II I 1111 訂-_ n —^^ - > (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（4 ) 146 ° 第2圖所示之TFT P1接著如以下方法形成於IPD層 145之上。一 poly-2層147形成於IPD層145之上，和經 由開口 146之N+型汲極連接140之露出部份之上如第3c 圖所示。此一 poly-2層147係利用高濃度之N型離子149 參雜而成。如第4圖所示，接著定義N型poly-2層147圖 案以形成N+型poly-2連接155和一 N+型TFT閘極160。 N+型poly-2連接155和N+型汲極連接140做電性上之接 觸。 一 TFT閘極氧化層165在N+型poly-2連接155和TFT 閘極160以及殘餘之IPD層145之上形成。定義TFT閘極 氧化層165圖案，再蝕刻以露出部份N+型poly-2連接155。 N+型poly-2連接155用以連接汲極連接140以及沈積於其 上之一 poly-3 TFT本體層170。 此一 poly-3本體層170，參照爲一 TFT本體層，形成 在定義好之TFT氧化層165之上。定義後去除部份之poly-3 層170(第4圖之剖面圖並未顯示）以形成TFT之汲極 180、源極185、通道190以及偏移（offset)區192。此poly-3 層170是由N型離子參雜而成。 沈積N型TFT本體層170後，一額外附加之P型離子 175選擇性地佈植於其中，以形成TFT之P+型汲極180和 P+型源極185區。TFT之P+型汲極180和P+型源極185 區由一 TFT通道190分隔開。TFT通道190圍繞著TFT閘 極160。一低濃度參雜或未參雜偏移區192位於通道190 ^ ^ L, n H ϋ n ϋ ^ 11 n IL-v (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（5 ) 和汲極180之間的TFT本體層170中。TFT偏移區降低正 常之TFT高截止電流（Ioff)，此係因通道190和汲極180之 間的高電場使得截止電流（Ioff)很大。 因爲許多TFT是使用底閘極（bottom gate)，所以TFT 閘極160無法用來使TFT之汲極180和源極185區對準。 故而需使用光罩和微影步驟來定義TFT之汲極180和源極 185區之位置。此一步驟易使TFT之汲極180和源極185 區之位置移位（misalignment)而導致偏移區192之長度少於 其最佳値。偏移區192之尺寸大小對TFT元件之特性和效 能表現有重大之影響。（在Manning等人之美國專利，編號 5,334,862中亦有闡述）。 參照第2圖，N+型poly-2連接155用以將下拉NMOS N1和TFT P1的汲極56連接起來。 TFT本體層170有一非平面之通道區190。此TFT本 體層170之非平面化導致某些問題。 此一彎曲通道之一缺點爲在TFT偏移區192和TFT汲 極190之間的高場接面很接近TFT閘極。這一接面產生TFT 截止狀態時之電流。由於此一彎曲之幾何之緣故，高場接 面之截止電流和侧面電場皆很大。 習知TFT元件之第2缺點爲通道有效長度的定義非常 困難。這是由於包圍TFT閘極側壁之TFT通道的垂直部份 的關係。通道有效長度的定義困難已導致源極和汲極區定 義之困難。此外，在微影步驟來定義通道有效長度時之移 位問題會大大地改變通道之有效長度，由於受到TFT通道 . 裝1TL^ - - . (請先聞讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0X297公釐） 經濟部中央標準局員工消費合作社印製 322638 A7 B7 五、發明説明（6 ) 的垂直部份影響的關係。 習知TFT元件之第3缺點爲其不佳之表面拓蹼和TFT 元件上表面之非平面化。爲了改進不佳之表面拓蹼和提供 一平坦之上表面，則需要额外之平坦化步驟。 習知TFT元件之第4缺點爲在截止狀態時之漏電流路 徑，以及在導通狀態時在通道角落之陷附中心（trap centers)。由於在通道角落之複晶矽薄膜爲彎曲狀，一部份 之單結晶區段將會於通道角落發生，其將產生晶粒邊界而 造成漏電流路徑和陷阱中心。漏電流路徑和陷阱中心將會 同時使得截止電流增加和導通電流減少而降低TFT之效能 表現·。 美國專利，編號5,334,862，揭露一 TFT其在一半導 體基材上形成之凹入處中形成一如同平面化插拴的閘極。 此一閘極係在凹入處底部以薄膜之形式生成且沒有將凹入 處填滿。一閘極絕緣層形成於閘極和凹入處之側壁上。一 TFT本體層接著形成於閘極和凹入處之側壁上其中TFT本 體層和閘極以閘極絕緣層隔開。 上述之TF丁有數個缺點。第1，TFT本體層彎曲所以 將造成某些部份單結晶區段於角落處。這將增加晶粒邊界 和漏電路徑。此外，凹入處將會破壞結構之平坦性。 在所參照之TFT中，源極和汲極之製作都很困難。汲 極和源極之植入係在某一角度進行，因爲是要植入至凹入 處之側壁上。因爲如此，某些植入之雜質可能會反射進入 TFT本體層之通道區。這將會明顯地改變通道區中之雜質 -------^--〖丨裝------訂-----」.锨 (請先聞讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 A7 B7五、發明説明（7 ) 濃度而造成嚴重之問題。此外，在某些情形中TFT已經位 於特定之方位。所以上述之美國專利，編號5,334,862所揭 露之TFT很難以實際應用。 有鑑於此，本發明之一目的係爲形成一本體層不彎曲 而是平面之TFT，以克服上述由於TFT本體層彎曲所造成 之問題。 本發明係針對一 TFT架構其具有一平坦之TFT本體 層。本發明之TFT消除由於TFT本體層彎曲所造成之上述 問題。 本發明之程序開始於一以形成MOS電晶體之基材。一 閘極（poly I)在介於汲極和源極之間的通道之上形成。汲極 和源極例如是利用離子佈植法在基村中形成，閘極和通道 係由閘極氧化層分隔開。 本發明之步驟包含以下步驟： 1.沈積一複晶矽間介電質層（IPD)於驅動電晶體之 上，並形成一開口在IPD中以露出驅動電晶體之閘極。實 例上，在相同之步驟中形成另動電晶體一開口在IPD中以 露出驅動電晶體之沒極。 2. 沈積一氮化物層於定義好圖案之IPD和露出之閘極 的上方，接著再沈積一厚CVD絕緣層於氮化物層之上。 3. 形成一凹入處於氮化物層和絕緣層中以露出IPD 層。此外，在絕緣層和氮化物層中形成一通孔開口以露出 驅動電晶體之閘極。實例上，驅動電晶體之汲極亦可在此 步驟中露出。 (請先閲讀背面之注意事項再填寫本頁) •裝'38 ^ 38 Λ7 B7 Five 'invention description printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (1) The present invention relates to a thin film transistor and its manufacturing method, in particular to a method for manufacturing a flat channel (flat- channel) bottom-gate thin film transistor (TFT) method and its structure, this thin film transistor is used in static random access memory (SRA M) memory cells. Figure 1 schematically shows an SRAM memory cell 10. The SRAM memory cell 10 includes first and second drivers N1 and N2. In the example, the drivers N1 and N2 are pull-down NMOS elements N1 and N2. The source 12 of N1 and the source 14 of N2 are connected to a reference voltage Vss, for example, a ground. The drain 16 of N2 is connected to the gate 18 of N1. The drain 20 of N1 is connected to the gate 22 of N2. The SRAM memory cell 10 in Fig. 1 also includes two load elements L1 and L2. One end 24 and 26 of each load element L1 and L2 is connected to the reference voltage Vcc, and the other end 28 and 30 is connected to the drains 20 and 16 of N1 and N2, respectively. The reference voltage Vcc is positive with respect to Vss. The SRAM memory cell 10 also includes two additional NMOS devices N3 and N4. Elements N3 and N4 act as pass transistors. The gates 32 and 34 of N3 and N4 are connected to a word line whose signal value is expressed as WORD. The source electrodes 36 and 38 of N3 and N4 are connected to the two-element line and their signal values are expressed as BIT and BIT, respectively. The drains 40 and 42 of N3 and N4 are connected to the drains 20 and 16 of N1 and N2, respectively. When writing to the memory unit, DATA (logic "1" or logic "0") is placed on the BIT signal line and DATA is placed on the BIT signal line. The WORD signal can be determined. A reading operation begins with precharging the BIT and BIT signal lines. The WORD signal can be determined and the BIT and BIT signal lines are 3 ------- i, 丨 installed ------ ordered ---- _ ^ (please read the precautions on the back before filling in this Page) This paper scale is applicable to the Chinese National Standard (CNS> Α4 specification (210Χ297 mm) 320638 ΑΊ Printed by the Employees ’Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Β5. Invention Description (2) A signal will be pulled down transistors N1 and N2 One of them is discharged. The purpose of the load elements L1 and L2 is to counteract the leakage effect of charging at the drains 20 and 16 of N1 and N2. The load elements L1 and L2 may be polycrystalline silicon resistors or PMOS elements. If In the case where L1 and L2 are PMOS elements, the source of the PMOS element is connected to Vcc; the drain of the PMOS element is connected to the drains 20 and 16 of N1 and N2; and the gates of the PMOS elements L1 and L2 are connected to the NMOS pull-down Gates of crystals N1 and N2. In order to reduce the size of SRAM memory cell 10 for future high-density and low standby power usage, load elements L1 and L2 may be implemented with thin-film PMOS transistors. In this case, This SRAM memory cell 10 is called a TFT SRAM memory cell. Load Devices L1 and L2 can also be implemented with full CMOS memory cells. However, the area required for a full CMOS device is much larger than the area required for the opposite TFT memory cell. In addition, the cost of using a full CMOS device as a load is much greater than that for TFT The components are required for the load. Therefore, in low-power applications, the TFT elements are used as the load elements L1 and L2. Figure 2 shows the TFT SRAM memory cell 50. The load element of the TFT SRAM memory cell 50 is represented by P1 and P2, which It is composed of PMOS thin film transistor (TFT). Sources 52 and 54 of P1 and P2 are connected to Vcc and drains 56 and 58 of P1 and P2 are connected to drains 20 and 16 of N1 and N2 (and N3 and N4 Drains 40 and 42). The gates 60 and 62 of P1 and P2 are connected to the gates 18 and 22 of N1 and N2, respectively. The branch 70 contains P1 and N1. . — 11 order Jiu Yong-J (please read the precautions on the back before filling in this page) This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 322638 A7 B7 5. Description of the invention (3) The flow is expressed as Ion, when P1 is on The current flowing through branch 70 is expressed as Ioff. (In the same way, Ion and Ioff are also used to indicate the current flowing through branch 80 including P2 and N25.) For each low power application, power saving is required, that is, low Standby power, so it requires a large on current Ion and a small leakage current Ioff to maximize the ratio of Ion / Ioff. Figures 3a to 3c and Figure 4 show the formation of the conventional TFT SRAM architecture 100 of the TFT SRAM memory cell 50 in Figure 2, and only one of the branches, such as branch 70, is shown in the figure. As shown in FIG. 3a, the TFT SRAM structure 100 has an N-type silicon substrate 112 in which a P-type substrate 114 is formed. The N + -type drain 116 and the N + -type source 118 are formed in the P-type metal 114, and a channel 120 separates the two. A gate oxide layer 122 is formed on the source 118, the drain 116 and the channel 120. Part of the oxide layer 122 is etched to expose an opening 124 above part of the drain 116. A first polycrystalline silicon layer 126 (poly-1) is deposited on the oxide layer 122 and the opening 124. As shown in FIG. 3b, a poly-1 layer 126 pattern is defined and doped with N-type ions 128 to form an N + -type gate 130 above the channel 120 and an N + -type drain connection 140 exposed to the drain 116 Above part (ie above opening 114). The drain 116, the source 118, and the gate 130 are relative to the drain 20, source 12, and gate 18 of the N1 pull-down body crystal shown in FIGS. 1 and 2. Next, a thick inter-poly dielectric (IPD) 145 (IPD) is formed on the gate 130 and the oxide calendar 122. The pattern of the IPD layer 145 is defined to expose the N + type drain connection 140. The IPD layer 145 isolates the TFT P1 of FIG. 2 from the driver N1 located below it. Define the pattern of the IPD layer 145 to form a through hole or opening that exposes part of the N + type drain connection 140 II I 1111 Order -_ n — ^^-> (please read the precautions on the back before filling this page) This paper The standard is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm). The A7 B7 is printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention (4). 146 ° The TFT P1 shown in Figure 2 is then formed as follows: Above the IPD layer 145. A poly-2 layer 147 is formed on the IPD layer 145, and on the exposed portion of the N + type drain connection 140 through the opening 146 as shown in FIG. 3c. This poly-2 layer 147 is doped with a high concentration of N-type ions 149. As shown in FIG. 4, an N-type poly-2 layer 147 pattern is then defined to form an N + -type poly-2 connection 155 and an N + -type TFT gate 160. The N + type poly-2 connection 155 and the N + type drain connection 140 make electrical contact. A TFT gate oxide layer 165 is formed over the N + type poly-2 connection 155 and the TFT gate 160 and the residual IPD layer 145. The pattern of the TFT gate oxide layer 165 is defined, and then etched to expose part of the N + type poly-2 connection 155. The N + type poly-2 connection 155 is used to connect the drain connection 140 and a poly-3 TFT body layer 170 deposited thereon. This poly-3 body layer 170, referred to as a TFT body layer, is formed on the defined TFT oxide layer 165. After the definition, part of the poly-3 layer 170 is removed (not shown in the cross-sectional view in FIG. 4) to form the drain 180, source 185, channel 190, and offset region 192 of the TFT. The poly-3 layer 170 is doped with N-type ions. After depositing the N-type TFT body layer 170, an additional P-type ion 175 is selectively implanted therein to form the P + -type drain 180 and P + -type source 185 regions of the TFT. The P + type drain 180 and P + type source 185 regions of the TFT are separated by a TFT channel 190. The TFT channel 190 surrounds the TFT gate 160. A low-concentration mixed or undoped offset area 192 is located in channel 190 ^ ^ L, n H ϋ n ϋ ^ 11 n IL-v (please read the precautions on the back before filling this page) This paper size is for China Standard (CNS) A4 specification (210X297 mm) A7 B7 printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs V. Invention description (5) In the TFT body layer 170 between the drain 180 and the drain electrode 180. The TFT offset region reduces the normal high TFT off current (Ioff). This is because the high electric field between the channel 190 and the drain 180 causes the off current (Ioff) to be large. Because many TFTs use a bottom gate, the TFT gate 160 cannot be used to align the drain 180 and source 185 regions of the TFT. Therefore, mask and lithography steps are needed to define the positions of the drain 180 and source 185 regions of the TFT. This step may easily misalignment the drain 180 and source 185 regions of the TFT, resulting in the offset region 192 having a length less than its optimal value. The size of the offset region 192 has a significant influence on the characteristics and performance of the TFT device. (Also described in Manning et al. US Patent No. 5,334,862). Referring to FIG. 2, an N + type poly-2 connection 155 is used to connect the pull-down NMOS N1 and the drain electrode 56 of the TFT P1. The TFT body layer 170 has a non-planar channel region 190. This non-planarization of the TFT body layer 170 causes some problems. One disadvantage of this curved channel is that the high field junction between the TFT offset region 192 and the TFT drain 190 is very close to the TFT gate. This junction generates the current when the TFT is off. Due to this curved geometry, the cut-off current and side electric field of the high-field interface are very large. The second disadvantage of conventional TFT devices is that it is very difficult to define the effective channel length. This is due to the relationship of the vertical portion of the TFT channel surrounding the TFT gate sidewall. The difficulty in defining the effective length of the channel has led to difficulties in the definition of the source and drain regions. In addition, the displacement problem when defining the effective length of the channel in the lithography step will greatly change the effective length of the channel, due to the TFT channel. Install 1TL ^--. (Please read the precautions on the back before filling this page) This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 0X297mm). Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 322638 A7 B7 V. The relationship between the vertical part of the invention description (6). The third disadvantage of the conventional TFT device is its poor surface topography and non-planarization of the upper surface of the TFT device. In order to improve the poor surface topography and provide a flat upper surface, an additional planarization step is required. The fourth disadvantage of the conventional TFT device is the leakage current path in the off state and the trap centers in the corners of the channel in the on state. Since the polycrystalline silicon thin film at the corner of the channel is curved, a part of the single crystalline section will occur at the corner of the channel, which will generate grain boundaries and cause leakage current paths and trap centers. The leakage current path and the trap center will simultaneously increase the off current and reduce the on current to reduce the performance of the TFT. U.S. Patent No. 5,334,862 discloses that a TFT forms a gate like a planarized plug in a recess formed in half of a semiconductor substrate. This gate is formed in the form of a thin film at the bottom of the recess and does not fill the recess. A gate insulating layer is formed on the sidewalls of the gate and the recess. A TFT body layer is then formed on the sidewalls of the gate and recess where the TFT body layer and the gate are separated by a gate insulating layer. The above TF D has several disadvantages. First, the bending of the TFT body layer will cause some single-crystal sections to be at the corners. This will increase grain boundaries and leakage paths. In addition, the recess will destroy the flatness of the structure. In the referenced TFT, the production of the source and the drain is very difficult. The implantation of the drain and source is performed at an angle because it is implanted on the side wall of the recess. Because of this, some implanted impurities may be reflected into the channel region of the TFT body layer. This will obviously change the impurities in the channel area ------- ^-〖丨 install ------ order ----- ''. Shovel (please read the notes on the back before filling in (This page) This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm). The A7 B7 printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. The description of invention (7) The concentration causes serious problems. In addition, in some cases the TFT is already in a specific orientation. Therefore, the TFT disclosed in the above-mentioned US Patent No. 5,334,862 is difficult to be practically applied. In view of this, an object of the present invention is to form a TFT with a body layer that is not curved but flat to overcome the above-mentioned problems caused by the bending of the TFT body layer. The present invention is directed to a TFT architecture with a flat TFT body layer. The TFT of the present invention eliminates the above-mentioned problems caused by bending of the TFT body layer. The process of the present invention begins with a substrate for forming MOS transistors. A gate (poly I) is formed on the channel between the drain and the source. The drain electrode and the source electrode are formed in the base village by ion implantation, for example, and the gate electrode and the channel are separated by the gate oxide layer. The steps of the present invention include the following steps: 1. Deposit a polycrystalline inter-silicon dielectric layer (IPD) on the driving transistor, and form an opening in the IPD to expose the gate of the driving transistor. In practice, another moving transistor is formed in the same step. An opening is formed in the IPD to expose the electrode of the driving transistor. 2. Deposit a nitride layer on top of the patterned IPD and exposed gate, and then deposit a thick CVD insulating layer on the nitride layer. 3. Form a recess in the nitride layer and the insulating layer to expose the IPD layer. In addition, a via opening is formed in the insulating layer and the nitride layer to expose the gate electrode of the driving transistor. In practice, the drain of the driving transistor can also be exposed in this step. (Please read the precautions on the back before filling this page) • Install '
、1T 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） 經濟部中央標準局員工消費合作社印策 A7 B7 五、發明説明（8 ) 4. 沈積一厚複晶插拴層（poly II)將TFT閘極凹入處和 通孔開口填塞。此poly II層是平坦的。一平坦之TFT複晶 矽閘極現在填入前述之TFT閘極凹入處，以及一與驅動電 晶體閘極相連之複晶矽通孔填入前述之通孔開口。複晶矽 閘極之上表面實質上與絕緣層之表面是同等平坦。 5. — TFT閘極絕缘物沈積在絕緣物和露出之TFT閘極 和複晶秒通孔之上方。 6. —平坦之TFT本體層接著沈積於TFT閘極絕緣層之 上，以及在其中以佈植法形成一源極和汲極。 本發明之平坦TFT有數個明顯之優點。高側邊電場， TFT上不佳之拓蹼，以及在角落之部份單結晶區段等之缺 點都被消除。TFT之特性穩定因爲本發明之TFT其幾何架 構較簡易。再者，根據本發明用以製造TFT之方法與習知 底閘極TFT之製造方法相比並不需要額外之微影步驟。 爲使本發明之特徵、優點和步驟能更顯而易懂，故特 舉一較佳實施例並配合圖式説明如下。 圖式之簡單説明： 第1圖係顯示習知SRAM記憶單元之線路方塊圖。 第2圖係詳細顯示習知TFT SRAM記憶單元之線路方 塊圖。 第3a到3c圖和第4圖係顯示其形成如第2圖所示之 習知TFT SRAM記憶單元之一部份（分支70)之製作流程。 第5到11圖係顯示製作根據本發明之TFTSRAM記憶 單元之一部份（分支70)之製作流程。 10 (請先閱讀背面之注意事項再填寫本頁) .裝. 訂 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 A7 B7五、發明説明（9 ) 第12圖係顯示根據本發明之一 TFT SRAM記憶單元。 實施例： 本發明針對一例如是使用於SRAM記憶單元之TFT架 構及其製造方法。本發明之TFT具有一乎坦通道可使截止 電流（Ioff)降低。於是，增進TFT之效能。 根據本發明之一實施例之開始係如第5圖所顯示。第5 圖顯示一半導體具有一驅動器MOS元件302其上覆蓋有一 厚IPD厝145。IPD層145和這特別之驅動器M0S元件 302相似於第3a到3c圖和第4圖所示之IPD層145和位於 IPD層145下面之特別之驅動器M0S元件302。也就是説， 此一 MOS驅動元件302係依第3a到3c圖所述之方式而形 成。驅動器元件302具有一 P型丼114於其基材112中形 成。以N型離子佈植進入P型丼114以形成N+型汲極116 和源極118，兩者以通道120分隔開。閘極氧化層122於 汲極116、源極118和通道120之上形成。一第1複晶矽 層（poly-1)沈積於氧化層之上。定義此一 poly-1看圖案再以 N型離子佈植形成N+型閘極130於通道120之上。雖然第 5圖中並未顯示，一用以連接汲極116的汲極連接也在 poly-1層中形成（參照第3b圖之汲極連接140)。如第5圖 所示，一 IPD層145於M0S驅動器元件302上形成。 如第5圖所示，一 IPD層145於閘極130和氧化層122 之上形成。實例上，IPD層145係爲一以化學氣相沈積法 (CVD)形成之四乙氧基矽甲烷（丁 EOS)層其厚度近於 1000A。如圖所示，使用CVD製程而形成之IPD層145使 11 m- I In mf n In ) nn n - . (請先閱讀背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（1〇 ) 得晶元300之表面輪廓趨向一致。 如第6圖所示，定義IPD層145以形成一開口 305用 以露出部份閘極130。雖然於第6圖之剖面圖中未顯示， 但實例上也定義了用以露出驅動電晶體之N+型汲極116的 開口。如第2圖所示，這是用以連接每一驅動電晶體之汲 極116，例如連接N1電晶體之汲極20至驅動電晶體之閘 極，和另一驅動器TFT負载電晶體對之負載TFT例如驅動 器N2之閘極22和負载P1之閘極62。 如第6圖所示，利用微影步驟形成之開口 305其中光 阻罩幕310於IPD層145上形成且定義露出位於閘極130 之上的部份IPD層145。蝕刻露出之部份IPD層145以形 成開口 305。爲簡化下列之圖示，MOS驅動器302將不于 圖示僅保留閘極氧化層122和閛極130。 如第7圖所示，去除微影罩幕310並形成一薄絕緣層 320例如是氮化矽於IPD層145和閘極130之露出部份之 上。實例上，氮化矽層320之厚度爲200A。接著，一厚介 電層330形成於氮化矽層320之上。隨後將更明顯，介電 層330的厚度等於將要形成之TFT閘極的厚度。因此，介 電層330的厚度係根據所需之TFT閘極的厚度而定。實例 上，介電層330是一 CVD沈積之TEOS層其厚度是1000A。 如第8圖所示，使用微影步驟定義介電層330以露出 部份氮化矽層320，例如其可藉著在氮化矽層320之上形 成一光阻罩幕340而達成。定義光阻罩幕340圖案並使用 電漿蝕刻介電層330以露出部份氮化矽層320。如此便形 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） i vm Aim mu M flm nn nn ^IBI— ί U3-s (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 B7五、發明説明（11 ) 成一複晶矽通孔開口 350以及一 TFT閘極凹入處355。實 例上，在介電居330至氮化妙廣320中也形成一開口位於 驅動器之汲極116之上（此一開口位於不同之剖面故未予 圖示）。 氮化矽層320係作爲一蝕刻終止層所以複晶矽通孔開 口 350和TFT閘極凹入處355都終止於此。接著，去除露 出於複晶矽通孔開口 350和TFT閘極凹入處355之部份氮 化妙廣320，例如使用熱鱗酸來去除。如此造成一終止於 驅動器閘極130之複晶矽通孔開口 350，以及一終止於IPD 層145之TFT閘極凹入處355。實例上，於氮化矽層中也 形成一開口露出驅動器之汲極116。此一開口無法在圖示 之平面上看到。 如第9圖所示，去除剩餘之光阻罩幕340，沈積一非 常厚之複晶矽層360(poly-2)於晶原300之上。複晶矽層360 之厚度足夠填滿複晶矽通孔開口 350和TFT閘極凹入處 355(實例上，複晶矽層360亦填塞驅動電晶體N+型汲極之 開口），以造成一平順之平面。實例上，複晶矽層360之厚 度爲8000人。 如第10圖所示，回餘複晶秒廣（poly-2)360，例如使用 電漿蝕刻，以去除在TFT閘極凹入處355(第9圖），（驅動 電晶體N+型沒極之開口）以及複晶秒通孔開口之外的複晶 矽。如此可使晶元300之表面平順，介電層330之表面幾 乎與填塞有複晶矽之TFT閘極凹入處355(第9圖）的表面以 及填滿複晶矽之通孔開口 350的表面相連續。也就是説， 13 ---^---;--卜丨裝------訂-----1^ ^ (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（12 ) 存留於通孔開口 350和凹入處355中之複晶矽（poly-2)層 360其上表面與介電層330相連續。於凹入處355中之 poly-2 370的上表面510實質上與介電層330的上表面520 共平面。位於通孔開口 350之複晶矽（poly-2)是一交連複晶 矽插拴365。於凹入處355之複晶矽（poly-2)是一 TFT閘極 370 ° 定義poly-2層360之後，於poly-2層區370和365植 入N型離子例如是P31，而此離子佈植使用每平方公分1〇15 之濃度和40keV之能量來實施。 如第11圖所示，一 TFT閘極絕緣物如一 TFT閘極氧 化層375使用CVD沈積於晶元300之上。實例上，TFT閘 極氧化層375之厚度爲300A。接著，一非結晶矽薄膜380 亦稱爲TFT本體層沈積於TFT閘極氧化層375之上。實例 上，TFT本體層之厚度爲300A。 TFT本體層380接著於低溫下進行一段長時間之回火 (annealing)。實例上，此 poly-3 TFT 本體層 38〇 在約 600 °C溫度下進行12小時之回火。此一步驟將poly-3 TFT本體 層380轉換成品質較好之複晶矽薄膜（poly-3)有平滑之表 面。使用例如是N型離子來執行TFT通道離子佈植以便形 成一 N型通道385於TFT本體層380之中。實施额外之佈 植例如使用P型離子以形成TFT P+汲極390和TFT P+源極 395區。習知之TFT其通道有角落具有垂直和水平之部分 包圍著TFT閘極370，而上述之TFT與習知不同其TFT源 極395和汲極390以及閘極385係形成一平坦表面。亦可 14 -------」，—裝------訂------！ 一 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS > A4规格（210X297公釐） 經濟部中央標準局員工消費合作社印裝 A7 B7 五、發明説明（13 ) 形成一未掺雜或低摻雜之偏移區其分隔TFT閘極385以及 TFT 通道 385 ° 接下來，定義佈植好之TFT本體層並加以蝕刻，例如 使用習知微影程序和電漿蝕刻以形成一 TFT具有正確成型 之源極395和汲極390之所需外觀形狀。實施一氧化步驟 以形成一氧化層於TFT本體層380之上。 實施後段製程以提供例如金屬接觸。此後段製程包括 一預先金屬介電質（Pre-Metal-ielectric，IPD)看之沈積與 回火。定義此PMD層以形成金屬接觸開口。在開口中形成 金屬接觸後，於PMD層和金屬接觸之上形成金屬化。最後 形成一保護層以完成全部之製程。 雖然，爲了清楚之目的而未予以圖示，在TFT閘極、 驅動器閘極和另一個驅動器之汲極之間都有連接。例如， 若是第11圖之一對TFT驅動器電晶體相對於TFT負裁電 晶體P1和驅動器電晶體N1(第2圖），那麼這些電晶體P1 和N1都連接至另一驅動電晶體N2(第2圖）之汲極。 第12圖顯示根據本發明形成之一平坦通道、底閘極之 TFT 400其漏電電流很低。TFT 400之通道385是平坦的 可由一偏移區410將其與汲極390隔開。第12圖亦顯示一 介於偏移區410和TFT汲極390之間的接面420。一側邊 電場產生TFT截止電流（Ioff)，出現於接面410。此平坦通 道、底閘極之TFT 400之形成與習知方法比較其不需要額 外之微影成像步驟。TFT 400係如上所述於一 MOS驅動器 元件之上。交連複晶矽插栓365連接驅動器閘極130和其 15 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS >八4規格（210X297公釐） 經濟部中央標準局負工消費合作社印製 A7 B7 五、發明説明（14 ) 他元件。 根據本發明形成之一平坦通道、底閘極之TFT 400有 低漏電電流，並減少陷阱中心，和低側邊電場故可具有低 截止電流（Ioff)以及高導通電電流（Ion)。因此，TFT400有 一高Ion/Ioff比例。通道385之長度以及源極395和汲極 390之長度可較容易控制。此外，具有平坦通道可減小在 使用微影步驟形成TFT通道385源極395和汲極390時， 移位對通道長度造成之影響。此一平坦通道、底閘極之TFT 400有平坦之上表面於是比習知製程之TFT SRAM較少有 乎坦化之問題。 本發明之方法可用以製造一 TFT具有一平坦通道和一 底閘極，其有低截止電流（Ioff)以及高導通電電流（Ion)，以 及高Ion/Ioff比例和低待機功率。 最後，上述關於本發明之一較佳實施例係僅用以舉例 説明。例如，本發明上述所使用之TFT 400爲一 PMOS元 件。但是，本發明亦可同等地應用NMOS TFT元件。對於 熟悉此項技術者在不出本發明之範疇内當可對本發明加以 修改和潤飾，故本發明之保護範圍當依照專利申請範圍所 述爲準。 ---------i ί 裝-- - . (請先閲讀背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐）、 1T The size of this paper is applicable to China National Standard (CNS) Α4 specification (210X297mm) Printed by A7 B7, Employee Cooperative of Central Bureau of Standards, Ministry of Economic Affairs V. Invention description (8) 4. Deposit a thick polycrystalline interlocking layer (poly II) Fill the recess of the TFT gate and the opening of the through hole. This poly II layer is flat. A flat TFT polycrystalline silicon gate is now filled into the aforementioned TFT gate recess, and a polycrystalline silicon through-hole connected to the driving transistor gate is filled into the aforementioned through-hole opening. The upper surface of the polycrystalline silicon gate is substantially equal to the surface of the insulating layer. 5. — The TFT gate insulator is deposited above the insulator and the exposed TFT gate and polycrystalline second via. 6.-A flat TFT body layer is then deposited on the TFT gate insulating layer, and a source and drain are formed by implantation. The flat TFT of the present invention has several obvious advantages. The shortcomings of the high-side electric field, poor topography on the TFT, and the single crystal section in the corner are eliminated. The characteristics of the TFT are stable because the TFT of the present invention has a relatively simple geometric structure. Furthermore, the method for manufacturing TFTs according to the present invention does not require an additional lithography step compared to conventional bottom gate TFT manufacturing methods. In order to make the features, advantages and steps of the present invention more obvious and easier to understand, a preferred embodiment is described in conjunction with the drawings as follows. Brief description of the drawings: Figure 1 shows the circuit block diagram of the conventional SRAM memory cell. Figure 2 shows a detailed circuit block diagram of a conventional TFT SRAM memory cell. Figures 3a to 3c and Figure 4 show the manufacturing process for forming a part (branch 70) of the conventional TFT SRAM memory cell as shown in Figure 2. Figures 5 to 11 show the manufacturing process of making a part (branch 70) of the TFTSRAM memory cell according to the present invention. 10 (Please read the precautions on the back before filling in this page). Packed. The size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). The A7 B7 is printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. Description (9) Figure 12 shows a TFT SRAM memory cell according to the present invention. Embodiments: The present invention is directed to a TFT structure used in SRAM memory cells and a manufacturing method thereof, for example. The TFT of the present invention has a smooth channel to reduce the off current (Ioff). Therefore, the efficiency of the TFT is improved. The beginning according to an embodiment of the present invention is shown in FIG. 5. Figure 5 shows a semiconductor with a driver MOS device 302 covered with a thick IPD 145. The IPD layer 145 and this special driver MOS element 302 are similar to the IPD layer 145 shown in FIGS. 3a to 3c and 4 and the special driver MOS element 302 located below the IPD layer 145. That is, this MOS driving element 302 is formed in the manner described in FIGS. 3a to 3c. The driver element 302 has a P-type socket 114 formed in the substrate 112. The N-type ions are implanted into the P-type Ion 114 to form an N + -type drain 116 and a source 118, which are separated by a channel 120. Gate oxide layer 122 is formed over drain 116, source 118, and channel 120. A first polycrystalline silicon layer (poly-1) is deposited on the oxide layer. Define this poly-1 to see the pattern and then use N-type ion implantation to form N + -type gate 130 on the channel 120. Although not shown in FIG. 5, a drain connection for connecting the drain 116 is also formed in the poly-1 layer (refer to the drain connection 140 in FIG. 3b). As shown in FIG. 5, an IPD layer 145 is formed on the MOS driver element 302. As shown in FIG. 5, an IPD layer 145 is formed on the gate 130 and the oxide layer 122. In an example, the IPD layer 145 is a tetraethoxysilyl methane (butyl EOS) layer formed by chemical vapor deposition (CVD) with a thickness of approximately 1000A. As shown in the figure, the IPD layer 145 formed using the CVD process is 11 m- I In mf n In) nn n-. (Please read the precautions on the back before filling in this page) The standard of this paper is applicable to Chinese national standards ( CNS) A4 specification (210X297 mm) A7 B7 printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (1〇) The surface profile of Epistar 300 tends to be consistent. As shown in FIG. 6, the IPD layer 145 is defined to form an opening 305 to expose a portion of the gate 130. Although not shown in the cross-sectional view of FIG. 6, an opening for exposing the N + type drain 116 of the driving transistor is also defined in the example. As shown in Figure 2, this is used to connect the drain 116 of each driver transistor, for example, the drain 20 of the N1 transistor to the gate of the driver transistor, and the load of another driver TFT load transistor pair The TFT is, for example, the gate 22 of the driver N2 and the gate 62 of the load P1. As shown in FIG. 6, the opening 305 formed by the lithography step in which the photoresist mask 310 is formed on the IPD layer 145 and defines to expose a part of the IPD layer 145 above the gate 130. The exposed portion of the IPD layer 145 is etched to form an opening 305. To simplify the following illustration, the MOS driver 302 will not retain the gate oxide layer 122 and the gate electrode 130 as shown. As shown in FIG. 7, the lithographic mask 310 is removed and a thin insulating layer 320 is formed, for example, silicon nitride on the exposed portions of the IPD layer 145 and the gate 130. In an example, the thickness of the silicon nitride layer 320 is 200A. Next, a thick dielectric layer 330 is formed on the silicon nitride layer 320. It will become more apparent later that the thickness of the dielectric layer 330 is equal to the thickness of the TFT gate to be formed. Therefore, the thickness of the dielectric layer 330 depends on the required thickness of the TFT gate. In the above example, the dielectric layer 330 is a CVD deposited TEOS layer with a thickness of 1000A. As shown in FIG. 8, the lithography step is used to define the dielectric layer 330 to expose a portion of the silicon nitride layer 320. For example, it can be achieved by forming a photoresist mask 340 on the silicon nitride layer 320. The pattern of the photoresist mask 340 is defined and the dielectric layer 330 is etched using plasma to expose a portion of the silicon nitride layer 320. The size of this paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) i vm Aim mu M flm nn nn ^ IBI— ί U3-s (please read the precautions on the back before filling this page) Ministry of Economic Affairs Printed A7 B7 by the Consumer Cooperative of the Central Bureau of Standards. 5. Description of the invention (11) A polycrystalline silicon through-hole opening 350 and a TFT gate recess 355. In practice, an opening is also formed in the dielectric Ju 330 to Miao Guang 320 320 above the drain 116 of the driver (this opening is located in a different cross-section and is not shown). The silicon nitride layer 320 serves as an etch stop layer, so both the polycrystalline silicon through hole opening 350 and the TFT gate recess 355 terminate here. Next, the portions of the through-silicon via openings 350 and the TFT gate recesses 355 are removed by nitriding 320, for example, using hot scaly acid. This results in a polycrystalline TSV opening 350 that terminates in the driver gate 130, and a TFT gate recess 355 that terminates in the IPD layer 145. In an example, an opening is also formed in the silicon nitride layer to expose the drain 116 of the driver. This opening cannot be seen on the plane shown. As shown in FIG. 9, the remaining photoresist mask 340 is removed, and a very thick polycrystalline silicon layer 360 (poly-2) is deposited on the crystal 300. The thickness of the polycrystalline silicon layer 360 is sufficient to fill the polycrystalline silicon through-hole opening 350 and the TFT gate recess 355 (in the example, the polycrystalline silicon layer 360 also fills the opening of the driver transistor N + type drain) to create a Smooth plane. In an example, the thickness of the polycrystalline silicon layer 360 is 8000 people. As shown in Figure 10, the polymorphic second (poly-2) 360, for example, using plasma etching to remove the recess 355 in the gate of the TFT (Figure 9), (drive transistor N + type electrode Opening) and polycrystalline silicon outside the opening of the polycrystalline second via. In this way, the surface of the wafer 300 can be made smooth. The surface of the dielectric layer 330 is almost the same as the surface of the TFT gate recess 355 (figure 9) filled with polycrystalline silicon and the via opening 350 filled with polycrystalline silicon The surface is continuous. In other words, 13 --- ^ ---;-Bu 丨 installed ------ order ----- 1 ^ ^ (please read the precautions on the back before filling this page) This paper size is applicable China National Standards (CNS) A4 specification (210X297 mm) A7 B7 printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Invention Description (12) Polycrystalline silicon (poly) stored in the through hole opening 350 and the recess 355 -2) The upper surface of the layer 360 is continuous with the dielectric layer 330. The upper surface 510 of poly-2 370 in the recess 355 is substantially coplanar with the upper surface 520 of the dielectric layer 330. The polycrystalline silicon (poly-2) located in the through hole opening 350 is a cross-linked polycrystalline silicon plug 365. Polycrystalline silicon (poly-2) at the recess 355 is a TFT gate 370 °. After defining the poly-2 layer 360, N-type ions such as P31 are implanted in the poly-2 layer regions 370 and 365, and this ion The implantation was performed using a concentration of 1015 per square centimeter and an energy of 40keV. As shown in FIG. 11, a TFT gate insulator such as a TFT gate oxide layer 375 is deposited on the wafer 300 using CVD. In the example, the thickness of the TFT gate oxide layer 375 is 300A. Next, an amorphous silicon film 380, also called a TFT body layer, is deposited on the TFT gate oxide layer 375. In an example, the thickness of the TFT body layer is 300A. The TFT body layer 380 is then annealed at a low temperature for a long period of time. As an example, the poly-3 TFT body layer 38 is tempered at about 600 ° C for 12 hours. This step converts the poly-3 TFT body layer 380 into a better quality polycrystalline silicon film (poly-3) with a smooth surface. TFT channel ion implantation is performed using, for example, N-type ions to form an N-type channel 385 in the TFT body layer 380. Additional placement is implemented, for example, using P-type ions to form the TFT P + drain 390 and TFT P + source 395 regions. The conventional TFT has vertical and horizontal portions at the corners of the channel and surrounds the TFT gate 370. Unlike the conventional TFT, the TFT source 395 and the drain 390 and the gate 385 form a flat surface. Can also 14 ------- ",-installed ----- ordered -----! 1. (Please read the precautions on the back before filling out this page.) This paper scale is applicable to the Chinese national standard (CNS & A4 specifications (210X297 mm). The A7 B7 printed by the Employees ’Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Invention description (13 ) Form an undoped or low-doped offset region that separates the TFT gate 385 and TFT channel 385 ° Next, define the implanted TFT body layer and etch it, for example using conventional lithography procedures and plasma Etching to form a TFT with the correct appearance of the source electrode 395 and the drain electrode 390. Perform an oxidation step to form an oxide layer on the TFT body layer 380. Implement a post-process to provide, for example, metal contacts. The process includes a pre-Metal-ielectric (IPD) deposition and tempering. The PMD layer is defined to form a metal contact opening. After the metal contact is formed in the opening, above the PMD layer and the metal contact Metallization is formed. Finally, a protective layer is formed to complete the entire process. Although, not shown for clarity, the TFT gate, driver gate and another driver There are connections between the drains. For example, if one of the pair of TFT driver transistors in Figure 11 is opposite to the TFT negative transistor P1 and the driver transistor N1 (Figure 2), then these transistors P1 and N1 are connected To the drain of another driving transistor N2 (Figure 2). Figure 12 shows that the TFT 400 with a flat channel and bottom gate formed according to the present invention has low leakage current. The channel 385 of the TFT 400 is flat An offset region 410 separates it from the drain 390. Figure 12 also shows a junction 420 between the offset region 410 and the TFT drain 390. The electric field on one side generates the TFT off current (Ioff), which appears At junction 410. The formation of this flat channel, bottom gate TFT 400 does not require an additional lithography imaging step compared to conventional methods. TFT 400 is as described above on a MOS driver device. Cross-linked polycrystalline silicon Plug 365 connects the driver gate 130 and its 15 (please read the precautions on the back before filling in this page) This paper scale is applicable to China National Standards (CNS > 84 specifications (210X297mm). A7 B7 printed by consumer cooperatives V. Description of invention (1 4) Other components. A flat channel, bottom gate TFT 400 formed according to the present invention has low leakage current and reduces the trap center, and the low side electric field can have low off current (Ioff) and high on current ( Ion). Therefore, the TFT 400 has a high Ion / Ioff ratio. The length of the channel 385 and the length of the source 395 and the drain 390 can be more easily controlled. In addition, having a flat channel can reduce the use of the lithography step to form the TFT channel 385 source For pole 395 and drain 390, the effect of displacement on the channel length. This flat channel, bottom gate TFT 400 has a flat upper surface, so it has fewer problems than the conventional process TFT SRAM. The method of the present invention can be used to manufacture a TFT with a flat channel and a bottom gate, which has a low off current (Ioff) and a high on current (Ion), as well as a high Ion / Ioff ratio and low standby power. Finally, the above-mentioned one preferred embodiment of the present invention is for illustration only. For example, the above-mentioned TFT 400 used in the present invention is a PMOS device. However, the present invention can equally apply NMOS TFT elements. Those who are familiar with this technology can modify and retouch the invention within the scope of the invention, so the protection scope of the invention should be in accordance with the scope of the patent application. --------- i ί Installation--. (Please read the precautions on the back before filling in this page) Order This paper size is applicable to China National Standard (CNS) Α4 specification (210X297mm)