^21772 經濟部中央標準局貝工消費合作社印製 五、發明说明（1 ) 發明背景 1 .發明領域 本發明係關於使用於半導體記憶裝置之^源供應器， 尤指一種可用於一般模式（normal mode)及燒入模式 (burn-in mode)之電源供應器。 2 .相關習知技術說明 隨著半導體記憶裝置設計技術的進步，設計規則的誤 差越來越降低。因此，記憶單元所增加的數目應該被設置 於有限的區域內。此外，用以修補（repairing)缺陷的一 般單元的多餘單元也設置於有限的區域中。在半導體記憶 裝置的製造完成之後，好的晶粒（die)藉由不同的性能測試 而被選擇包裝。然而，在性能測試後，在晶圓狀態上爲好 的晶粒通常惡化爲壞晶粒。這種缺陷通常是因爲字元線之 間，位元線之間，或記憶單元之間的短路（short-circuit) 或短路橋（short bridge)所引起。 習知用以掃描壞晶粒以便消除缺陷的方法是提供電壓 應力給字元線的晶圓燒入測試。爲確保晶圓測試後的可靠 度，晶片需要通過燒入測試。 2 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 士衣- 訂 ^ 五、發明説明（2 ) A7 B7 經濟部中央標準局員工消費合作枉印製 這種燒入測試，特別是晶圓燒入測試電路及其方法在 申請人1996年9月16日所申請之美國第08/714,577號專 利申請案中有詳細的揭示。近來，在次字元線驅動器結構 中，NMOS驅動器一般被用來取代習知的PMOS驅動器以 便降低單元陣列區塊所占據的區域。在上述申請案的燒入 測試電路中，電源電壓VCCA被設定爲低於燒入模式之外 供應電壓EVCC或應力電壓VPP(stress voltage)(即燒 入電壓 >。因此，在燒入模式的運作，供應電壓V C C A不能 被用來當做字元線驅動訊號PXiB。也就是說，既然字元線 驅動器中的NMOS電晶體的臨界電壓因爲低供應電壓而不 夠高，字元線並未被提供合適的應力電壓，即合適的燒入 電壓。此外，如果字元線驅動訊號PXiB的準位在一般模式 中被當做應力電壓VPP使用，字元線驅動訊號PXiB的擺盪 (swing)寬度因爲高電壓VPP的負載增加而增加，因此造 成電流消耗增加。 如前所述，當使用於近來發展的記憶裝置內時，習知 的電源供應不能在燒入模式中提供合適的應力電壓給字元 線。因此’如果在晶片內提供個別模式用的電源電壓，晶 片尺寸將產生我們所不想要的增加。 發明綜合說明 (請先閲讀背面之注意事項再填寫本頁) 裝. 訂 3 本紙張尺度適用中國國家標準（CNS ) Λ4規格（2丨〇Χ297公货） 五、發明説明（3 ) A7 B7 經濟部中央標準局員工消費合作社印繁 因此，本發明之一目的在提供一種電源供應器用以產 生足夠燒入測試用之高度的燒入電壓。 本發明之另一目的在提供一種電源供應電壓器用以在 一般模式內產生陣列電壓並在燒入模式中產生高於陣列電 壓的燒入電壓。 本發明之又一目的在提供一種電源供應器能夠降低一 般模式中的電流消耗。 依據本發明之一形式，一電源供應器用以依據一燒入 模式致能訊號在一般模式中提供該字元線一陣列電壓以及 在燒入模式中提供燒入電壓，該陣列電壓低於該燒入電 壓。 此電源供應器包括：一差動放大器，用以比較陣列電 壓與一參考電壓以產生第一邏輯準位，當該陣列電壓具有 與該參考電壓相同準位時，該差動放大器依據該燒入模式 致能訊號而被致能；一邏輯電路，用以於該外控制訊號被 激勵（activated)至該邏輯高準位時產生一邏輯低準位， 並於該外控制訊號被解激勵（i n a c t i v a t e d )至一邏輯低準 位時傳輸一來自該差動放大器之輸出；以及一驅動電晶 體，其源-汲通道連接於一外電源供應電壓與該陣列電壓之 間而其閘極連接至該邏輯電路之—輸出。 該電源供應器更包括一 PMOS電晶體，其源-汲通道位 於一外電源供應電壓與該差動放大器之間’而其閘極連接 至該燒入模式致能訊號。 4 本紙浓尺度適用中國國家標準（CNS ) Λ4規格（2丨0X297公釐） (請先閲讀背面之注意事項再填寫本頁) 裝. 訂 A7 B7五、發明説明（4 ) 經濟部中央標準局貝工消費合作社印製 圖式簡要說明 本發明上述目的及其它特徵及優點將藉由下列實施例 說明參照所附圖式而獲較佳之了解，其中 圖一係本發明電源供應器之一較佳實施例電路圖；以 及 圖二係使用本發明之半導體記憶裝置之電路圖。 較佳實施例詳細說明 本發明之實施例將參照所附圖式而爲說明》 參照圖一，本發明電源供應之實施例包括一差動放大 器2, —邏輯電路50，以及一驅動電晶體20。差動放大器2 被提供外電源供應電壓EVCC並且被致能，當與之連接之 Ρ Μ O S電晶體4回應一被解激勵至低準位的燒入模式致能訊 號PWBE_M而導通（turn on)時。差動放大器2比較陣列 1壓VCCA與參考電壓VREFA以產生高邏輯準位如果陣列 電壓VCCA等於或高於參考電壓VREFA。邏輯電路50包 括一NMOS電晶體6，反相器8，10，12，14，一？]\1〇8電晶 體1 6以及一NMOS電晶體1 8。尤其是，PMOS電晶體6之 汲-源通道連接於差動放大器2之一輸出與地之間，而其閘 極連接至燒入模式致能訊號PWBE_M。反相器8,10, 12及 5 本紙张尺度適用中國國家標準（CNS ) Α4規格（210Χ297公嬸） (請先閲讀背面之注意事項再填μ•本頁) 裝. -訂 321772 kl ___B7 五、發明説明（5 ) 14在差動放大器2之輸出端緩衝一電壓準位因而控制驅動 電晶體20。此外，PMOS電晶體16及NMOS電晶體18串 連於外電源供應電壓EVCC與地之間以便組成一反相器。 驅動電晶體20之源-汲通道連接於外電源供應電壓EVCC與 陣列電壓V C C A之間，而閘極連接至形成於Ρ Μ O S電晶體 1 6與Ν Μ Ο S電晶體1、8之交點的點Ν 1 » 應該注意的是，在燒入模式中外電源供應電壓EVCC 的準位實質上與應力電壓（即燒入電壓）相同。此外，燒入 模式致能訊號PW B E_M係由從晶片接點自外部接收之邏極 性結合訊號所產生。燒入模式致能訊號燒入模 式中被激勵至邏輯高準位，而於一般模式中被解激勵至邏 輯低準位。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁)^ 21772 Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of the invention (1) Background of the invention 1. Field of the invention The present invention relates to a ^ source supplier used in semiconductor memory devices, in particular, it can be used in normal mode (normal mode) and burn-in mode (burn-in mode) power supply. 2. Description of related conventional technology With the advancement of the design technology of semiconductor memory devices, the error of design rules is decreasing. Therefore, the increased number of memory cells should be set in a limited area. In addition, the excess cells of the general cells used for repairing defects are also provided in the limited area. After the manufacture of the semiconductor memory device is completed, good dies are selected for packaging through different performance tests. However, after performance testing, the dies that are good in the wafer state usually deteriorate to bad dies. This defect is usually caused by a short-circuit or short bridge between word lines, bit lines, or memory cells. A conventional method for scanning bad dies to eliminate defects is to provide voltage stress to the word line wafer burn-in test. To ensure the reliability of the wafer after the test, the chip needs to pass the burn-in test. 2 The size of this paper applies to China National Standard (CNS) A4 (210X297mm) (please read the precautions on the back before filling in this page) Shi Yi-Order ^ V. Description of Invention (2) A7 B7 Central Bureau of Standards, Ministry of Economic Affairs Employee consumer cooperation has printed such a burn-in test, especially the wafer burn-in test circuit and its method are disclosed in detail in the US Patent Application No. 08 / 714,577 filed by the applicant on September 16, 1996. Recently, in the structure of sub-word line drivers, NMOS drivers are generally used to replace conventional PMOS drivers in order to reduce the area occupied by the cell array block. In the burn-in test circuit of the above application, the power supply voltage VCCA is set to be lower than the supply voltage EVCC or the stress voltage VPP (stress voltage) (i.e. burn-in voltage>). Therefore, in the burn-in mode Operation, the supply voltage VCCA cannot be used as the word line drive signal PXiB. That is to say, since the critical voltage of the NMOS transistor in the word line driver is not high enough because of the low supply voltage, the word line is not provided properly The stress voltage is the proper burn-in voltage. In addition, if the level of the word line drive signal PXiB is used as the stress voltage VPP in the general mode, the swing width of the word line drive signal PXiB is due to the high voltage VPP The load increases and the current consumption increases. As mentioned above, when used in recently developed memory devices, the conventional power supply cannot provide an appropriate stress voltage to the word line in the burn-in mode. Therefore 'If the power supply voltage for individual modes is provided in the chip, the chip size will produce an increase that we do not want. Comprehensive description of the invention (please read first Please pay attention to this page and then fill out this page). Binding. 3 This paper size is applicable to the Chinese National Standard (CNS) Λ4 specifications (2 丨 〇297 public goods) 5. Description of the invention (3) A7 B7 Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Therefore, one object of the present invention is to provide a power supply for generating a burn-in voltage of sufficient height for burn-in test. Another object of the present invention is to provide a power supply for generating an array voltage in a general mode In the burn-in mode, a burn-in voltage higher than the array voltage is generated. Another object of the present invention is to provide a power supply capable of reducing the current consumption in the general mode. According to one form of the present invention, a power supply is used to A burn-in mode enable signal provides an array voltage of the word line in the normal mode and a burn-in voltage in the burn-in mode, and the array voltage is lower than the burn-in voltage. The power supply includes: a differential amplifier , Used to compare the array voltage with a reference voltage to generate a first logic level, when the array voltage has the same as the reference voltage When in position, the differential amplifier is enabled according to the burn-in mode enable signal; a logic circuit for generating a logic low level when the external control signal is activated to the logic high level, And transmit an output from the differential amplifier when the external control signal is inactivated to a logic low level; and a driving transistor whose source-drain channel is connected to an external power supply voltage and the array The gate is connected between the voltage and the output of the logic circuit. The power supply further includes a PMOS transistor, the source-drain channel is located between an external power supply voltage and the differential amplifier, and the gate Connect to the burn-in mode enable signal. 4 The paper thickness scale is applicable to the Chinese National Standard (CNS) Λ4 specification (2 丨 0X297mm) (please read the precautions on the back and then fill out this page) to install. Order A7 B7 5. Invention description (4) Central Bureau of Standards, Ministry of Economic Affairs The printed drawings of Beigong Consumer Cooperative Society briefly explain the above-mentioned objects and other features and advantages of the present invention. The following embodiments will be better understood with reference to the drawings, in which FIG. 1 is one of the power supplies of the present invention. Embodiment circuit diagram; and FIG. 2 is a circuit diagram of a semiconductor memory device using the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in detail with reference to the attached drawings. Referring to FIG. 1, an embodiment of the power supply of the present invention includes a differential amplifier 2, a logic circuit 50, and a driving transistor 20 . The differential amplifier 2 is provided with an external power supply voltage EVCC and is enabled. When connected to it, the MOS transistor 4 is turned on in response to a burn-in mode enable signal PWBE_M that is de-energized to a low level. Time. The differential amplifier 2 compares the array voltage VCCA with the reference voltage VREFA to generate a high logic level if the array voltage VCCA is equal to or higher than the reference voltage VREFA. The logic circuit 50 includes an NMOS transistor 6, inverters 8, 10, 12, 14, one? ] \ 1〇8 transistor 16 and an NMOS transistor 18. In particular, the drain-source channel of the PMOS transistor 6 is connected between an output of the differential amplifier 2 and ground, and its gate is connected to the burn-in mode enable signal PWBE_M. Inverters 8, 10, 12 and 5 The paper size is in accordance with Chinese National Standard (CNS) Α4 specification (210Χ297 aunt) (please read the precautions on the back and then fill in μ • this page) to install.-Order 321772 kl ___B7 5 Description of the invention (5) 14 A voltage level is buffered at the output of the differential amplifier 2 to control the driving transistor 20. In addition, the PMOS transistor 16 and the NMOS transistor 18 are connected in series between the external power supply voltage EVCC and ground to form an inverter. The source-drain channel of the driving transistor 20 is connected between the external power supply voltage EVCC and the array voltage VCCA, and the gate is connected to the intersection formed at the intersection of the PMOS transistor 16 and the NMOS transistor 1, 8 Point Ν 1 »It should be noted that the level of the external power supply voltage EVCC in the burn-in mode is substantially the same as the stress voltage (ie the burn-in voltage). In addition, the burn-in mode enable signal PW B E_M is generated by the logic-polarity combination signal received from the chip contacts from the outside. The burn-in mode enables the signal to be driven to the logic high level in the burn-in mode, and is de-energized to the logic low level in the general mode. Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling this page)
在運作時，如果燒入模式致能訊號燒入模 式中被激勵至邏輯高準位，PMOS電晶體4關閉（turn off) 而NMOS電晶體6導通。因此，差動放大器2被禁能而其輸 出電壓經由NM0S電晶體6的汲-源通道放電至地。然後， 高邏輯準位訊號藉由反相器8, 10, 12, 14被施加至PMOS電 晶體1 6及Ν Μ O S電晶體1 8的閘極。因此，Ρ Μ O S電晶體 1 6關閉而Ν Μ 0 S電晶體1 8導通，因此點Ν 1的電壓準位變 成低邏輯準位。所以，驅動電晶體2 0導通，產生依據連接 至驅動電晶體20之源極的外電源供應電壓EVCC而定之燒 入電壓Vburii。燒入電壓被輸入字元線驅動器（未示出）並 被當做字元線驅動訊號PXiB使用。在此方式中，大約5V 6 本紙乐尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 五、發明説明（6 ) A7 B7 經濟部中央標準局員工消費合作社印聚 的外電源供應電壓EVCC，當成燒入電壓Vburn，被提供 至一被選擇記憶單元之字元線，以便施加應力至被選擇的 記憶單元。 然而，相反地，如果燒入模式致能訊號在一般模式中 被解激勵爲邏輯低準位訊號，PMOS電晶體4導通而 NMOS電晶體6關閉。因此，差動放大器2之輸出端產生高 準位訊號。然後，P Μ 0 S電晶體1 6導通而P Μ 0 S電晶體1 8 關閉，因此點Ν 1的準位變成高邏輯準位。然後，驅動電晶 體20關閉，而輸出電壓變成大約2.8 V的陣列電壓VCCA。 陣列電壓V C C Α被提供至字元線驅動器並當成字元線驅動 器PXiB使用。 參照圖二，其電路表示了陣列電壓VCCA被輸入至與 記憶單元連接之感測電路2 0 0。由圖可以明顯看出，陣列 電壓產生器101的功能與圖一之電源供應器100相等，除了 它與燒入模式致能訊號？〜8£_1\4獨立之外。此外，感測電 路200包括相互親合（cross-coupled)於位元線對B/L與 互71之間的PMOS電晶體202及203，以及一 PM0S電晶體 2 〇 1用以回應低邏輯準位的感測控制訊號L A P G而提供陣 列電壓VCCA至點LA。陣列電壓產生器1〇1提供低於外電 源供應電壓E V C C的陣列電壓V C C A至感測電路2 0 0。此 外，陣列電壓V C C A被當成運作單元陣列之不同控制訊號 的電源。 7 本紙浓尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐） (請先閲讀背面之注意事項再填寫本頁)During operation, if the burn-in enable signal is driven to a logic high level in the burn-in mode, the PMOS transistor 4 turns off and the NMOS transistor 6 turns on. Therefore, the differential amplifier 2 is disabled and its output voltage is discharged to ground via the drain-source channel of the NMOS transistor 6. Then, high logic level signals are applied to the gates of the PMOS transistor 16 and the NMOS transistor 18 through the inverters 8, 10, 12, and 14. Therefore, P MOS transistor 16 is turned off and N MOS transistor 18 is turned on, so the voltage level at point N 1 becomes a low logic level. Therefore, the driving transistor 20 is turned on to generate the burn-in voltage Vburii according to the external power supply voltage EVCC connected to the source of the driving transistor 20. The burn-in voltage is input to the word line driver (not shown) and used as the word line drive signal PXiB. In this way, about 5V 6 paper music standards are applicable to the Chinese National Standard (CNS) A4 specifications (210X297 mm) 5. Invention description (6) A7 B7 External power supply voltage EVCC printed by the Employees Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs When the burn-in voltage Vburn is supplied to a word line of a selected memory cell, stress is applied to the selected memory cell. However, conversely, if the burn-in mode enable signal is de-excited as a logic low level signal in the normal mode, the PMOS transistor 4 is turned on and the NMOS transistor 6 is turned off. Therefore, the output terminal of the differential amplifier 2 generates a high-level signal. Then, P MOS transistor 16 is turned on and P MOS transistor 18 is turned off, so the level of point N 1 becomes a high logic level. Then, the driving transistor 20 is turned off, and the output voltage becomes an array voltage VCCA of about 2.8V. The array voltage V CC A is supplied to the word line driver and used as the word line driver PXiB. Referring to FIG. 2, the circuit shows that the array voltage VCCA is input to the sensing circuit 200 connected to the memory cell. It can be clearly seen from the figure that the function of the array voltage generator 101 is the same as that of the power supply 100 of FIG. 1, except that it is the burn-in mode enable signal? ~ 8 £ _1 \ 4 independent outside. In addition, the sensing circuit 200 includes PMOS transistors 202 and 203 cross-coupled between the bit line pair B / L and the mutual 71, and a PMOS transistor 210 to respond to a low logic level The bit sensing control signal LAPG provides the array voltage VCCA to point LA. The array voltage generator 101 provides an array voltage V C C A lower than the external power supply voltage E V C C to the sensing circuit 200. In addition, the array voltage V C C A is used as a power source for different control signals of the operating cell array. 7 The paper thickness scale is applicable to the Chinese National Standard (CNS) Λ4 specification (210X 297mm) (please read the precautions on the back before filling this page)
T A7 ____B7 五、發明説明（7 ) 如前所述，本發明之電源供應電壓產生燒入模式中的 燒入電壓，以及一般模式的陣列電壓。因此，可以在燒入 模式及一般模式中使用。 本發明得由熟悉本技藝之人士任施匠思而爲諸般修 飾，然皆不脫如附申請專利範圍所欲保護者。 I ----T n - I —L ---I I I 訂 (請先閱讀背面之注意事項再填离本頁) 經濟部中央標準局員工消費合作社印裂 本紙依尺度適用中國國家標隼（CNS ) Λ4規格（210X297公蝥）T A7 ____B7 5. Description of the invention (7) As mentioned above, the power supply voltage of the present invention generates the burn-in voltage in the burn-in mode and the array voltage in the general mode. Therefore, it can be used in burn-in mode and normal mode. The present invention may be modified by any person familiar with the art and any kind of craftsmanship, but none of them may be as protected as the scope of the patent application. I ---- T n-I —L --- III (Please read the precautions on the back before filling out this page) The cracked paper printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs is applicable to the Chinese National Standard Falcon (CNS ) Λ4 specification (210X297 male assemblage)