TW318962B

TW318962B - Manufacturing method of lightly doped drain thin-film transistor

Info

Publication number: TW318962B
Application number: TW85109778A
Authority: TW
Inventors: Shyong-Guang Tsay; Shenq-Kae Hwang
Original assignee: Ind Tech Res Inst; Chi Mei Optoelectronics Corp; Toppoly Optoelectronics Corp; Prime View Int Corp Ltd
Priority date: 1996-08-09
Filing date: 1996-08-09
Publication date: 1997-11-01

Abstract

A manufacturing method of lightly doped drain thin-film transistor comprises of the steps: (1) preparing one glass substrate; (2) on one portion of the glass substrate forming one gate region; (3) on the gate region and substrate depositing one insulator; (4) on the insulator depositing one semiconductor layer; (5) on the semiconductor layer forming first photoresist; (6) with the gate region as mask, using back-side exposure technology, making first photoresist a little over-exposed; (7) to the first photoresist performing development, forming first un-exposed region smaller than gate region; (8) on semiconductor layer except the first un-exposed region, forming one lightly doped region; (9) on the first un-exposed region, removing the first photoresist; (10) on the semiconductor layer and insulator, forming second photoresist; (11) with the gate region as mask, using back-side exposure technology, making second photoresist layer a litter under-exposed; (12) to the second photoresist performing development, forming second un-exposed region larger than gate region; (13) on semiconductor layer except the second un-exposed region, forming one heavily doped region; (14) on the second un-exposed region, removing the second photoresist; (15) by conventional photolithography technology, removing outside part of semiconductor layer, forming one island region, which includes first un-exposed region, lightly doped region, and heavily doped region; (16) on one end of the island region forming one drain, which covers partial heavily doped region, and extends onto the insulator; (17) on another end of the island region forming one source, which covers partial heavily doped region, and extends onto the insulator.

Description

318962 經濟部中央揉準局員工消費合作社印製 A7 B7 五、發明説明（/) (1)發明領域本發明係關於一種薄膜電晶體(TFT)的製造方法，更仔細地說，係關於一種具有淡摻雜汲極(LDD)之薄膜電晶體的製造方法》 ⑵發明背景薄膜電晶體一般用在靜態隨機存取記憶體元件(SRAM)和主動矩陣液晶顯示器，而人們也積極地硏究製造薄膜電晶體的方法。其中，最理想的方法是利用自動對準的技術來製造薄膜電晶體，因爲它能使源極與汲極之間的通道間隔達到最佳化，而且非常均勻。Hayden等人1993年8月10日所取得5,235,189號美國專利中，就掲露了 —種自動對準的薄膜電晶體。Possin等人1993年8月31日所取得5,241,192號美國專利中，也揭露了一種降低端面漏電流的自動對準薄膜電晶體，並在1994年6月28曰所取得5,324,674號美國專利中，揭露了這種電晶體的製造方法》此外，Kwasnick等人在1995年2月21曰所取得5,391,507號美國專利中，提出了一種以掀去技術製造自動對準薄膜電晶體的方法。Rha 1995年4月4日所取得5,403,761號2美國專利中，則說明了一種不一樣的薄膜電晶體及其製法，這種電晶體具有自動對準擴散的源極和汲極區，可以提高開關電流比》目前持續進行中的硏發工作，大都集中在提高薄膜電晶體的切換速度、降低負載電流.、或提高動態範圍。例如，Zhao等人在刊於IEEE Electron Device Letters，vol. 15，No. 15，Oct. 1994的論文「A Vertical Submicron Polysilicon Thin-Film Transistor Using A Low Temperature Process」中，提出了一種毋需次微米微影設備，艮P能製造垂直型次微米複晶矽薄膜電晶體的技術。. 淡摻雜的汲極區可以降低薄膜電晶體元件汲極區附近的電場，所以能夠降低元件的負載電流。Manning等人1994年8月2日所取得5,334,862號美國專利中，揭露了 —種具有淡摻雜汲極之準薄膜電晶體的製造方法》Chae在1995年8月15日所取得 5,442,215號美國專利中，則進一步提出一種具有不對稱之淡摻雜汲極結構的薄膜電晶體。包括淡摻雜汲極技術在內的製程，通常都用在以矽晶圓基板製造CMOS元件之薄膜電晶體的製程上。這種薄膜電晶體通常是頂部閘極結構，所形成的源極、汲極和通道區都在閘極區的底下，而且都是採用共平面的結構。但在AMLCD中，薄膜電晶本紙張尺度適用中國國家標準（CNS ) A4現格（210X297公釐） I------------^------.ίτ------A . ; i - i . {請先閲讀背面之注意事項再填寫本頁) 318962 經濟部中央標準局負工消費合作杜印製 A7 B7 五、發明説明（二-) 體具有玻璃基板，大都採用源極、汲極和通道區都在閘極區上方的反轉式堆疊結構。如果以反轉式堆叠結構來製造具有淡摻雜汲極的複晶矽薄膜電晶體，電晶體的關閉電流通常會過大。 (3)發明的簡要說明提出本發明就是要克服上述的問題。本發明的目的是提出一種反轉式堆疊結構，用在具有淡摻雜汲極和玻璃基板的薄膜電晶體。淡摻雜的汲極可以降低汲極的電場，並使薄膜電晶體的關閉電流很低》本發明另一個目的是提出一種利用自動對準和背面曝光的技術，在玻璃基板上製造薄膜電晶體的製程》在本發明中，先在一面玻璃基板上沉積一層Cr膜，形成一個閘極。然後在閘極和基板上沉積一層絕緣層和一層半導體層。接著以閘極作爲光罩，利用自動對準背面曝光技術和高能的光源，進行光阻製程，形成一個略小於閘極區域、未經曝光的區域。然後在暴露出來的區域，以很低的能量進行離子植入，淡淡地摻雜半導體層。然後再進行一次類似的光阻製程，形成一個略大於閘極區域、未經曝光的區域》然後以高能對暴露出來的半導體層進行離子植入。去除光阻之後，利用傳統的光學微影技術形成一個島形區域|包括了未摻雜的半導體層、淡慘雜區和濃摻雜區，然後再製作薄膜電晶體的汲極和源極。 (4)圖示的簡要說明圖1說明了本發明尙未养成之薄膜電晶體中，玻璃基板、Cr閘極、絕緣層和半導體層的橫剖面圖。 . 圖2說明在圖1之元件上塗佈一層光阻，並利用閘極作爲自動對準光罩進行背面曝光的情形。圖3說明了圖2之元件的光阻層顯影之後，所得略小於閘極區域、未經曝光的光阻區，以及進行低能離子植入製程的情形。本紙張尺度適用中國國家榡準（CNS ) A4規格（210X 297公釐) ' ：^、1Τ------^ . ; j -- f * (請先閱讀背面之I意事項再填寫本頁) ___B7 五、發明説明〇 ) 圖4說明了圖3的元件經過第二次背面曝光並光阻顯影的處理後，所得略大於閘極區域、未經曝光的光阻區。圖5說明了在圖4的元件上進行高能離子直入的情形。圖6說明本發明具有反轉式堆疊結構之薄膜電晶體完成後的結構。 (5)發明較佳實施例說明圖1中，作爲薄膜電晶體起始基板的是一面玻璃基板1()。首先在基板上沉積一層 Cr膜，形成閫極1。Cr膜厚約1500至2500埃，而以2000埃最爲理想。然後在閘極1和基板10上，利用化學氣相沉積(CVD)製程連續沉積一層絕緣層2和一層半導體層3。半導體層厚約300埃，可以是200至600埃。形成半導體層3時，也可以在絕緣層2和閘極1上，直接沉積未經摻雜的複晶矽層》或者利用非晶矽作爲半導體層3 ,再以任何現有的回火製程使非晶矽再結晶爲複晶矽。回火製程可以用雷射光束進行，也可以用熱處理進行》圖2中，半導體層3上面已經塗佈一層厚約1.5微米的正光阻4。接著以聞極1作爲自動對準光罩，利用紫外光11，以背面曝光技術使光阻4曝光。此時，所用的光源是約爲lOGOmj/cm2的高能光源，使光阻4曝光過度。顯影之後，複晶矽層3未經曝光區域的寬度會略小於閘極區域1，在圖3中，兩端各約小於閘極區域0.5微米。然後進行低能的離子植入12，形成了讎雜區域N— 5。形成區域後，隨即去除光阻層4。然後在半導體層3和絕緣層2的上方，再塗佈一層新的光阻層。經濟部中央標準局男工消費合作杜印製隨即以閘極1作爲光罩，進行第二次的自動對準背面曝光製程，使光阻曝光。這次曝光所用的能量較低，約爲8〇〇mj/on2，使得接受曝光的光阻略有些曝光不足。因此’未經曝光區域6的寬度會略大於閘極區域1，在圖4中，兩端各約大於閘極區域 0.5微米。然後就進行圖5中的高能離子植入13，而產生了濃慘雜區域N+ 7 »從以上的說明可以知道，兩次的光阻製程在半導體層3未經曝光區域的兩側上，形成寬度各約爲1微米(0.5 + 0.5微米)的淡摻雜區域r 5。離子植入以後，光阻層6即可去除。本紙張尺度適用中國國家標準（CNS ) A4規格（2 I 〇 χ 297公釐） S18962 A7 _B7_ 五、發明説明（汊）最後，以傳統的光學微影製程去除部份的濃摻雜半導體層’形成了圖6中的島形區域，然後再形成源極8和汲極9 °島形區域包括了半導體層3 '低能離子植入區域N一 5和高能離子植入區域N+ 7。源極和汲極各自覆蓋住部份的濃摻雜區域’並且往外延伸覆蓋住部份的絕緣層。這樣就完成了圖6中具有淡摻雜汲極之薄膜電晶體的反轉式堆疊結構。有了淡摻雜區域5，會使薄膜電晶體的關閉電流得以降低。實驗顯示，關閉電流可以低於1 pA » 雖然以上的說明中，只說明了本發明的具體實施例’但任何在本發明精神底下所作之修改或結合仍應受到保護。 -------------裝-------訂------Λ . .. : i -· < . (請先閲讀背面之注意事項再填寫本頁) 經濟部中央橾準局男工消費合作社印製適尺浪紙一準一榡一家 Λ318962 A7 B7 printed by the Employee Consumer Cooperative of the Central Bureau of Economic Development of the Ministry of Economic Affairs V. Description of the invention (/) (1) Field of the invention The present invention relates to a method for manufacturing a thin film transistor (TFT). Manufacturing method of lightly doped drain (LDD) thin film transistors "(2) Background of the invention Thin film transistors are generally used in static random access memory devices (SRAM) and active matrix liquid crystal displays, and people are also actively investigating the manufacture of thin films Transistor method. Among them, the most ideal method is to use automatic alignment technology to manufacture thin film transistors, because it can optimize the channel spacing between the source and the drain, and it is very uniform. In US Patent No. 5,235,189 obtained by Hayden et al. On August 10, 1993, a self-aligned thin film transistor was disclosed. Possin et al., U.S. Patent No. 5,241,192, obtained on August 31, 1993, also disclosed a self-aligning thin-film transistor to reduce end-surface leakage current, and disclosed in U.S. Patent No. 5,324,674, obtained on June 28, 1994 In addition, Kwasnick et al. In US Patent No. 5,391,507, obtained on February 21, 1995, proposed a method for manufacturing self-aligned thin-film transistors using lift-off technology. Rha ’s US Patent No. 5,403,761, obtained on April 4, 1995, describes a different type of thin film transistor and its manufacturing method. This transistor has a source and a drain region that are automatically aligned and diffused, which can improve the switching. Current Ratio "The ongoing ongoing work is mostly focused on increasing the switching speed of thin film transistors, reducing the load current, or increasing the dynamic range. For example, in the paper "A Vertical Submicron Polysilicon Thin-Film Transistor Using A Low Temperature Process" published in IEEE Electron Device Letters, vol. 15, No. 15, Oct. 1994, Zhao et al. Lithography equipment, GenP can manufacture vertical sub-micron polycrystalline silicon thin film transistor technology. The lightly doped drain region can reduce the electric field near the drain region of the thin film transistor element, so it can reduce the load current of the element. Manning et al., U.S. Patent No. 5,334,862, obtained on August 2, 1994, discloses a method for manufacturing quasi-thin film transistors with lightly doped drains. Chae obtained U.S. Patent No. 5,442,215 on August 15, 1995 In the paper, a thin film transistor with an asymmetric lightly doped drain structure is further proposed. Processes including lightly doped drain technology are commonly used in the process of manufacturing thin film transistors for CMOS devices on silicon wafer substrates. This type of thin film transistor is usually a top gate structure, and the source, drain and channel regions formed are all under the gate region, and all adopt a coplanar structure. However, in AMLCD, the standard of thin-film electro-crystalline paper is in accordance with Chinese National Standard (CNS) A4 (210X297mm) I ------------ ^ ------. Ίτ-- ---- A.; I-i. (Please read the precautions on the back before filling in this page) 318962 Ministry of Economic Affairs, Central Standards Bureau, negative labor consumption cooperation, du printed A7 B7 V. Description of invention (two-) body with glass Most of the substrates adopt an inverted stack structure in which the source electrode, the drain electrode and the channel region are all above the gate region. If the inverted stacked structure is used to fabricate a polycrystalline silicon thin film transistor with a lightly doped drain, the turn-off current of the transistor is usually too large. (3) Brief description of the invention The present invention is proposed to overcome the above-mentioned problems. The object of the present invention is to propose an inverted stack structure for thin film transistors with lightly doped drains and glass substrates. The lightly doped drain can reduce the electric field of the drain and make the turn-off current of the thin film transistor very low. Another object of the present invention is to propose a technique that uses automatic alignment and back exposure to manufacture thin film transistors on a glass substrate In the present invention, a Cr film is first deposited on a glass substrate to form a gate electrode. Then deposit an insulating layer and a semiconductor layer on the gate and substrate. Then, using the gate as a mask, the automatic resist alignment technology and high-energy light source are used to perform a photoresist process to form an unexposed area that is slightly smaller than the gate area. Then, in the exposed area, ion implantation is performed at a very low energy, and the semiconductor layer is lightly doped. Then, a similar photoresist process is performed to form an unexposed area slightly larger than the gate area, and then the exposed semiconductor layer is ion implanted with high energy. After removing the photoresist, the traditional optical lithography technology is used to form an island-shaped region | including an undoped semiconductor layer, a lightly doped region and a heavily doped region, and then the drain and source of the thin film transistor are fabricated. (4) Brief description of the drawings Fig. 1 illustrates a cross-sectional view of a glass substrate, a Cr gate, an insulating layer and a semiconductor layer in the undeveloped thin film transistor of the present invention. Fig. 2 illustrates the case of coating a layer of photoresist on the element of Fig. 1 and using the gate as an automatic alignment mask for back exposure. FIG. 3 illustrates that after the photoresist layer of the device of FIG. 2 is developed, the result is slightly smaller than the gate area, the unexposed photoresist area, and the low energy ion implantation process. This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X 297mm) ': ^, 1Τ ------ ^ .; j-f * (Please read the I matters on the back before filling in this Page) ___B7 5. Description of the invention 〇) Figure 4 illustrates the device of Figure 3 after the second back exposure and photoresist development process, resulting in a slightly larger gate area, unexposed photoresist area. FIG. 5 illustrates the situation of performing high-energy ion direct injection on the element of FIG. 4. FIG. 6 illustrates the structure of the thin-film transistor with an inverted stack structure of the present invention after completion. (5) Description of the preferred embodiment of the invention In FIG. 1, a glass substrate 1 () is used as a thin film transistor starting substrate. First deposit a layer of Cr film on the substrate to form the electrode 1. The Cr film thickness is about 1500 to 2500 Angstroms, and 2000 Angstroms is the most ideal. Then, on the gate 1 and the substrate 10, an insulating layer 2 and a semiconductor layer 3 are successively deposited by a chemical vapor deposition (CVD) process. The semiconductor layer is about 300 Angstroms thick, and may be 200 to 600 Angstroms. When the semiconductor layer 3 is formed, an undoped polycrystalline silicon layer can also be directly deposited on the insulating layer 2 and the gate electrode 1 or using amorphous silicon as the semiconductor layer 3, and then using any existing tempering process The crystalline silicon is recrystallized into polycrystalline silicon. The tempering process can be performed with a laser beam or a heat treatment. In Figure 2, a positive photoresist 4 with a thickness of about 1.5 microns has been coated on the semiconductor layer 3. Next, the Wenji 1 is used as an automatic alignment mask, the ultraviolet light 11 is used, and the photoresist 4 is exposed by a back exposure technique. At this time, the light source used is a high-energy light source of about 10GOmj / cm2, and the photoresist 4 is overexposed. After development, the width of the unexposed area of the polycrystalline silicon layer 3 will be slightly smaller than that of the gate area 1. In FIG. 3, both ends are approximately smaller than the gate area by 0.5 microns. Then, low-energy ion implantation 12 is performed to form an impurity region N-5. After the region is formed, the photoresist layer 4 is removed. Then, on the semiconductor layer 3 and the insulating layer 2, a new photoresist layer is coated. Du Yin, a male worker of the Central Standards Bureau of the Ministry of Economic Affairs, used the gate 1 as a mask to perform the second automatic alignment back exposure process to expose the photoresist. The energy used for this exposure is relatively low, about 800mj / on2, making the photoresist that is exposed to the exposure slightly underexposed. Therefore, the width of the 'unexposed region 6 will be slightly larger than that of the gate region 1. In Fig. 4, both ends are approximately 0.5 microns larger than the gate region. Then, the high-energy ion implantation 13 in FIG. 5 is performed, and a densely doped region N + 7 is generated. From the above description, it can be seen that the two photoresist processes are formed on both sides of the unexposed region of the semiconductor layer 3. Lightly doped regions r 5 each having a width of approximately 1 micrometer (0.5 + 0.5 micrometer). After ion implantation, the photoresist layer 6 can be removed. This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (2 I 〇χ 297 mm) S18962 A7 _B7_ 5. Description of the invention (汊) Finally, the traditional optical lithography process is used to remove part of the densely doped semiconductor layer ' The island-shaped region in FIG. 6 is formed, and then the source 8 and the drain 9 are formed. The island-shaped region includes the semiconductor layer 3 ′ low-energy ion implantation region N-5 and high-energy ion implantation region N + 7. The source electrode and the drain electrode each cover a portion of the heavily doped region 'and extend outward to cover the portion of the insulating layer. This completes the inverted stack structure of the thin film transistor with lightly doped drain in FIG. 6. With the lightly doped region 5, the off current of the thin film transistor can be reduced. Experiments have shown that the shutdown current can be lower than 1 pA »Although the above description only describes specific embodiments of the present invention, any modifications or combinations made under the spirit of the present invention should still be protected. ------------- installed ------- order ------ Λ...: I-· <. (Please read the notes on the back before filling in this Page) The Ministry of Economic Affairs, Central Bureau of Accreditation, and the Men ’s Workers ’Consumer Cooperative printed a suitable size paper, one for each family.

Claims

Printed by ABCD Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 6. Patent application scope 1. The manufacturing method of @ 淡 DOS 掳极极 Thick Film Transistor, the steps include: preparing a glass substrate; on a part of the glass substrate Forming a hearing region; depositing an insulating layer on the gate region and the substrate; depositing a semiconductor layer on the insulating layer; forming a first photoresist layer on the semiconductor layer; using the gate region as a photomask, Using back exposure technology, the first photoresist layer is slightly overexposed; the first photoresist layer is developed to form a first-unexposed area slightly smaller than the gate area; outside the first unexposed area On the semiconductor layer, a lightly doped region is formed; from the first unexposed region, the first photoresist layer is removed; on the semiconductor layer and the insulating layer, a second photoresist layer is formed; with the gate The area is used as a photomask 'using back exposure technology to make the second photoresist layer slightly underexposed; developing the second photoresist layer to form a second photoresist that is slightly larger than the gate area An exposed area; on the semiconductor layer other than the second unexposed area, a densely doped area is formed; from the second unexposed area, the second photoresist layer is removed; using a conventional optical lithography method , The outer portion of the semiconductor layer is removed to form an island-shaped region, the island-shaped region includes a first unexposed region, a lightly doped region, and a heavily doped region; forming an end on the island-shaped region Drain, the drain covers part of the concentrated impurity region and extends above the insulating layer; and a source electrode is formed on the other end of the island-shaped region Region and extend above the insulating layer. 2. A method for manufacturing a lightly doped thin film transistor as claimed in item 1 of the patent scope, in which the low energy ion implantation process is used when forming the lightly doped region on the semiconductor layer other than the first-unexposed region . 3. A method for manufacturing a lightly doped thin film transistor as claimed in item 1 of the patent scope, wherein the high-energy ion implantation process is used when forming the heavily doped region on the semiconductor layer other than the second unexposed region . 4. The manufacturing method of lightly doped thin film transistor as claimed in item 1 of the patent scope, in which the deposited semiconductor layer is an undoped polycrystalline silicon layer. This paper scale is applicable to China National Standards (CNS) Μ specifications (210X297mm) J---* (please read the precautions on the back before filling in this page), printed by the Central Bureau of Economics, Ministry of Economic Affairs, Beigong Consumer Cooperative 318362 A8 B8 C8 D8 6. Scope of patent application 5. The manufacturing method of lightly doped thin film transistors as claimed in item 1 of the scope of patent application, in which the semiconductor layer is deposited by first depositing a layer of amorphous silicon and then tempering process Or heat treatment to recrystallize amorphous silicon into a polycrystalline silicon layer, which serves as the semiconductor layer. 6. A thin-film transistor with a lightly doped drain, which includes:-a surface glass substrate;-a gate 'on the glass substrate;-an insulating layer on the substrate and the gate; a semiconductor layer , Located on the insulating layer, the semiconductor layer includes a heavily doped outer region, a lightly doped intermediary region, and an undoped central region located above the gate region, the central The area is slightly smaller than the gate area, and the intermediary area extends from the central area to the outside of the gate area and is connected to the external area; a drain is located at one end of the external area, the drain An electrode covering part of the outer region and extending above the insulating layer; and a source electrode located at the other end of the outer region, the source covering part of the outer region and extending above the insulating layer . 7. The thin-film transistor with lightly doped drain as in item 6 of the patent application, in which the gate contains a complex layer. 8. The thin-film transistor with lightly doped drain as in item 6 of the patent application, wherein the gate electrode is about 1500 to 2500 Angstroms thick. 9. Thin-film transistors with lightly doped drains as claimed in item 6 of the patent scope, wherein the semiconductor layer is about 200 to 600 Angstroms thick. 10. For example, the thin-film transistor with a lightly mixed drain in Item 6 of the patent application, in which the lightly doped intermediate region is formed by automatic alignment and low energy ion implantation. 11. The thin-film transistor with lightly doped drain as claimed in item 6 of the patent scope, wherein the heavily doped outer region is formed by auto-alignment method and high-energy ion implantation. 12. The thin-film transistor of lightly doped drain as claimed in item 6 of the patent application, wherein the width of the lightly doped intermediary region on each side is 0.5 to 2 microns. 13. As claimed in item 6 of the patent application scope, the thinly-doped thin-film transistor, in which the semiconductor layer is formed by a layer of amorphous silicon, is recrystallized into a polycrystalline silicon layer through a tempering process. The size of this paper is applicable to the Chinese National Standard (CNS> A4 specification (210X297mm) --- r ---: --- 'pack ------- order: ------, · ^: -· · · (Please read the notes on the back before filling this page)