TW318282B - Differential poly-oxidization for stabilizing SRAM memory cell - Google Patents

Abstract

A SRAM features multiple SRAM memory cells performing addressing with bit line, in which those SRAM memory cells comprises of: (1) one high reference voltage contact and one low reference voltage contact; (2) one charge storage node; (3) one pull-down transistor connected to the charge storage node and the low reference voltage contact, in which the pull-down resistor has one source, one drain and one pull-down transistor gate; (4) one pass transistor connected to the charge storage node and one bit line, in which the pass transistor has one source, one drain and one pass transistor gate, and has one down surface with higher bending level than the one of the pull-down transistor gate.

Description

318J2? T ^ F.DOC / 002 A7 B7 ___ .--------— V. Description of Invention (i) The present invention relates to static random access memory ( static random-access memory, SRAM), and especially about an SRAM with improved stability. The density of components within an integrated circuit can use the reduced geometry integrated circuit designs principle to increase the performance of the integrated circuit and reduce its true cost. Modern integrated circuit memory devices, including DRAM 'SRAM, ROM, EEPROM, etc., are obvious examples of using this strategic principle. The density of the memory cells in the integrated circuit memory device is continuously increasing, which is accompanied by a corresponding decrease in the unit storage cost of such devices. The increase in density is achieved by making smaller structures within the element, and by reducing the separation space between the elements or the structures that make up the elements. Generally, such small-size design rules are accompanied by layout, design, and construction corrections. When using such small-size design rules, these correction changes are only possible because the size of the components is reduced. It is also necessary to maintain component performance. As an example, the reduction in operating voltage in various conventional integrated circuits is only possible due to, for example, reducing the thickness of the gate oxide and increasing the degree of error in the control of lithography processes. On the other hand, the size reduction design criterion also makes it necessary to lower the operating voltage so that small-sized components can limit the hot carriers that can be generated when operating at higher operating voltages as previously known. When the SRAM is fabricated according to the reduced design criteria and operated at a reduced internal voltage, the stability of the SRAM memory may be reduced. Reduced operating voltage and other design changes 3 (Please read the precautions on the back before filling in this page) The size of this booklet is applicable to the Chinese National Standard (CNS > A4 specification (210X297 mm) " 318282 03 2 5TWF.DOC / 002 A7 B7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economy V. Invention description (meaning). The change may change the voltage used to ensure that the SRAM can maintain a stable data state during the data reading operation The scope is reduced, and the possibility of reading the data in the middle of the data stored in the SRAM memory cell or even the entire loss of data is increased. The typical SRAM design includes coupling together to form a latch structure. Two or four MOS transistors with two charge storage nodes for storing the charge state corresponding to the data. Each charge storage node is selectively coupled to a pair of complementary bit lines by using The corresponding one of them can read the data from the conventional SRAM cell in a non-destructive way. This selective coupling uses a pair of pass Pass transistor, and each pass transistor is connected between one of the two charge storage nodes and one of its corresponding complementary bit lines. The word line signal is used to give pass power The gate of the crystal to turn on the Pietron transistor during the data reading operation. Charge will flow through the Pietron transistor in the ON dog state to the charge storage node, or flow out of the charge storage node The transistor is turned on to allow one of the bit lines to discharge and charge the other bit line. The voltage fluctuation on the bit line can be sensed by a differential amplifier. In order to maintain the stability of the SRAM memory cell flash lock during this data reading operation, at least one charge storage node in the SRAM must be charged or discharged at a faster rate than the charge flows into and out of the corresponding bit line In the past, this type of control was made using a channel connecting the transistor to a specific charge storage node Dutch ---------------- ^ ______ This paper is suitable for China National Standard (CNS) Λ4 specification (210X297mm) (please read the precautions on the back before filling this page)装 _ A7 B7 0325TWF.D〇C / 〇〇2 V. Description of the invention (more) At least one channel of the SRAM memory cell transistor of the storage node should be narrower and / or longer. This geometric arrangement allows flow The current flowing through at least one SRAM memory cell transistor is more than the current flowing through the corresponding pass transistor; as a result, the charge storage node is more charged or discharged than the corresponding bit line discharge or charge fast. However, this geometric arrangement has certain disadvantages and limitations. For example, making the channels of the transistors narrower and longer will slow down the reading and writing of data. In addition, the relative geometric structure of different memory cells and petron transistors will cause some limitations on how small a particular SRAM memory cell can be made accurately. It is therefore an object of the present invention to provide an SRAM that has improved stability, can operate at a reduced voltage, or can be manufactured using design criteria of smaller size. The gate electrode of the pass transistor used for extracting a SRAM memory cell is better than the memory cell transistor in its configuration to provide reduced transconductance, which can increase the stability of the SRAM memory cell. A particular embodiment of the method of the present invention allows the cross-sectional shape of the gate of the transistor to be fabricated in a manner that improves stability. An embodiment of the present invention provides an SRAM having a plurality of SRAM memory cells addressed by bit lines. The SRAM memory cells include a high reference potential contact and a low reference potential contact, and a charge storage node. The memory cells also include a pull-down transistor and a Piezo transistor. The pull-down transistor is connected to the charge storage node and is in contact with a low reference potential, and the pull-down transistor has a source, a drain, and a pull-down transistor gate 5 (read the precautions on the back before filling this page). The size of the paper printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs is applicable to the Chinese National Standard (CNS) 84 specifications (21〇χ297 mm). 〇3 ^ 5Τ WF.DOC / 002 A7 B7 5_____ 蛵 济 、 邵Description of the invention of the consumer cooperation of the Central Standard Falcon Bureau for consumer printed printing (γ). The petatransistor is connected to the charge storage node and a bit line 'and the petatransistor has a source, a drain and a petatransistor gate electrode. The petatransistor gate electrode has a lower surface than its gate The surface under the electrode is bent to a greater degree. Another embodiment of the SRAM of the present invention has a plurality of SRAM memory cells addressed by bit lines. The SRAM memory cells include a high reference potential contact and a low reference potential contact, and a charge storage node. A pull-down transistor is connected to the charge storage node and is in contact with a low reference potential, and the pull-down transistor has a source electrode, a drain electrode, and a pull-down transistor gate electrode. ~ Paitong Transistor is connected to the charge storage node and a bit line, and the Pitong Transistor has a source, a drain 'a channel and a Paitong transistor gate electrode An electric field with a shape is generated in the channel area of the crystal, where the generated electric field is reduced in intensity in the channel shield immediately after the source and drain of the transistor. Another different aspect of the present invention provides a method of making SRAM. Firstly, a substrate and wires formed on the substrate are provided, wherein a first wire is formed on the channel region of the pull-down transistor, and a second wire is formed on the channel region of the transistor. The first lead is made in a way to protect the first lead from oxidation. Finally, the second wire is exposed to an oxidizing environment while the first wire is shielded so that the first and second wires have different cross-sectional configurations. In order to make the above and other objects, features, and advantages of the present invention more obvious and understandable, a few preferred embodiments are described below in conjunction with the attached drawings, which are described in detail as follows: 6 (Please read the notes on the back first (Fill in this page again) This paper scale is applicable to the Chinese National Falcon (CNS) Λ4 specification (2 丨 0x297mm) ^ 18282 〇: 325TWF.DOC / 002 A7 B7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (Ί) Brief description of the drawings Figure 1 shows a circuit diagram of a specific embodiment of the invention. Figure 2 is a partial cross-sectional view of a paragraph of the SRAM shown in Figure 1. Figures 3 and 4 are partial cross-sectional views. In order to show the flow of making the device in Figure 2. Embodiments The preferred embodiment of the present invention can utilize the mutual conduction of the transistors that selectively construct a SRAM memory cell to limit the current flowing through the transistors, but The geometry and layout of the SRAM transistor are not changed, and the stability of the SRAM memory cell is improved. A particularly preferred embodiment of the present invention can be used to change the transconductance of the Patron transistor by changing the gate of the Patron transistor. For example, a differential oxidation process can oxidize the gate of the transistor, to produce a gate whose bottom edge is lifted by the substrate, which can reduce the passage of the transistor through the transistor This kind of oxidation process, because at least some of the gates of the memory cell transistors are protected during the oxidation process, so that the configuration of the gate electrode of the transistor is changed, and it is protected The configuration of the gate of the transistor is not changed by the oxidation process, so it is a differential arrangement. Figure 1 shows a SRAM memory cell (a group of six transistors or 6T memory cells) 'which contains There are two PMOS load transistors 10, 12 and two NMOS pull-down transistors 14 and 16 connected to form a cross-coupled inverter. Each PMOS load transistor 10 '12, Each gate is connected to a corresponding NM0S pull-down transistor____ 7 This paper size is suitable for Guanjia County (CNS) 44 secret (21GX297mm) ~ '(Please read the precautions on the back before filling this page ) Pack-0325 TWF.DOC / 002 A7 0325TWF.DOC / 002 A7 Printed by the Employee Consumer Cooperative of the Ministry of Economic Affairs of the Ministry of Economy V. Invention description (i?) — Body I4 '16. The drains of PMOS load transistors 10, 12 are each Connected to the drain of the corresponding NMOS transistor M, 16, to form an inverter with a conventional configuration. The source of the load transistor is connected to a high reference potential, usually Vcc, while the source of the pull-down transistor is It is connected to a lower reference potential, usually Vss. The gates of the PMOS transistor 10 and NMOS transistor 14 forming an inverter are connected to the drains of the other inverter transistors 12, 16. Similarly, the gates of the PMOS transistor I2 and the NMOS transistor 16 which constitute another inverter are connected to the drains of the transistors 10 and I4. Therefore, the potential appearing at the drain (node N1) of the first inverter transistors 10, 14 is supplied to the gates of the second inverter transistors 12, 16, and the electric charge is used to transfer the second The inverter remains ON or OFF. A logically opposite potential appears at the drain (node N2) of the second inverter transistors 12, 16 and at the gate of the first inverter transistors 10, 14 to hold the first inverter In complementary OFF or ON state. In this way, the latch of the SRAM memory cell shown in the figure can have two stable states: a state where a predetermined potential appears at the charge storage node N1 and a low potential appears at the charge storage node N2, and a low potential out Now the charge storage node N1 and the predetermined potential appear in the second state of the charge storage node N2. Binary data can be recorded by changing between the two states of the latch. Sufficient charge must be stored on the charge storage node and on the coupling gate of the relevant inverter so that one inverter can be kept in the ON state and the other The phase device is kept in the OFF state, thus maintaining the memory state. The stability of a SRAM memory cell can be used in 8 ϋ standards applicable to Chinese national standards (CNsTa4 specifications ((please read the precautions on the back and fill in this page).

、 1T 5TWF.DOC / 002 A7 B7 V. Description of invention (q) When the potential on its charge storage node changes relative to its nominal value, it can still keep the SRAM memory cell in its original state To measure. The state of the SRAM memory cell is usually read by selectively connecting the two charge storage nodes N1, N2 of the memory cell to a pair of complementary bit lines (BL, M). A pair of transfer transistors 18, 20 are connected between the charge storage nodes N1, N2 and the corresponding bit line BL, tile, respectively. Before performing a read operation, the bit line BL is equalized to a voltage midpoint between the high and low reference voltage, which is usually 1/2 · (Vcc-Vss), and then the word line WL A signal on the switch will switch the transistor to the ON state. For example, consider a case where N1 is charged to a predetermined potential Vcc and N2 is discharged to a low potential Vss. When the transistors 18, 20 are switched to the ON state, the charge starts to flow from the node N1 through the transistor 18 to the bit line BL. The charge on the node N1 starts to be drawn from the bit line BL and is supplemented by the current flowing through the load transistor 10 to the node N1. At the same time, charge will flow from the bit line to the node N2 through the pass transistor 20, and there will be charge flowing from the node N2 through the pull-down transistor 16. If there is more current flowing through the transistor 18 than the transistor 10, the charge will start to be drawn from the node N1, and when it is reduced to a certain level, the pull-down transistor 16 can be switched to the OFF status. If there is more current flowing through the transistor 20 than the transistor 16, the charge will start to accumulate at the node N2, and when charging to a certain level, the load transistor 10 can be switched to the OFF state .

The discharge and charging of the charge storage nodes Nl, N2 can cause SRAM 9 (please read the precautions on the back before filling out this page). The Central Standard Falcon Bureau Employee Consumer Cooperative of the Ministry of Economy -9

This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 0325TWF.DOC / 002 0325TWF.DOC / 002 Printed B7 by the Consumer Standardization Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs V. Description of the invention (?) Memory cell in memory Switching between states' results in erroneous data being stored in SRAM memory cells. Therefore, it is necessary to be able to control the current that can flow through the transistor to a relative level. The relative level must be lower than that flowing through at least some memory cell transistors. That is, a relatively high current should flow through one of the load or pull-down transistors connected to each charge storage node. Generally, the fabrication of a six-transistor SRAM memory cell is to make two load transistors 10 and 12 into a thin-film transistor (TFT). In terms of this dual TFT SRAM memory cell architecture, the source, drain and channel regions of the load transistors 10, 12 and the gate electrode are all made of polycrystalline silicon deposited on a layer of insulating material. The insulating material covers an underlying SRAM circuit, which includes a pass transistor and a pull-down transistor formed on the surface of the substrate. It is often necessary to fabricate load transistors with a high degree of transconductance, because polycrystalline silicon transistors tend to leak current, making high-conductivity TFT load transistors consume unacceptable power. In this way, the pull-down transistor should be easier to conduct more current than the pass-through transistor, to the extent that it can ensure that a read operation does not change the data state of the SRAM memory cell. Due to the provision of relatively narrow and long channels of pass transistors and the provision of relatively wide and short channels of pull-down transistors, in the application of conventional SRAM's Conductance has been different. However, when using smaller size design guidelines in the field, or when designing to use lower operating voltages, due to manufacturing process limitations including minimum structure size, this strategy should be applied to this paper scale and the Chinese National Standard (CNS ) A4 specification (2 丨 OX 297mm) (Please read the precautions on the back before filling this page) -'5 5TWF.DOC / 002 A7 B7 Fifth, the invention description (Bian) It is not feasible to exceed the current application level . It is extremely difficult to maintain a fixed ratio between the transconductance of the pull-down transistor and the Pyrton transistor while further reducing the size of the memory cell. Similarly, if the operating voltage is reduced, unless the memory cell size is made larger in an undesirable manner, it is extremely difficult to ensure that there is a sufficient voltage range for the memory cell to operate stably. Therefore, the embodiments of the present invention provide a different method that can reduce the conductance of the pass transistor, but does not reduce the conductance of the pull-down transistor. FIG. 2 shows a cross-sectional portion of a SRAM according to a preferred embodiment of the present invention. In particular, the pull-down transistor 14 and the pass transistor 18 of a preferred SRAM embodiment are shown schematically in FIG. 2. Configuration. The embodiment shown in the figure includes a pass transistor gate electrode 44 that can generate an electric field in the pass transistor channel, which generates an electric field that is significantly different from that of a conventionally shaped pass transistor gate electrode electric field. The electric field generated by the gate transistor 44 of the embodiment of FIG. 2 is most different in that the passage area of the gate transistor 44 is adjacent to the @ drain electrode. The lower electric field strength in this area will only attract fewer free carriers, which reduces the conductance through the transistors compared to conventional gate transistors. In order to enhance the change of the electric field generated in the channel region, it is preferable that the edge of the lower surface of the gate transistor of the pass transistor be rounded until it extends beyond the surrounding source / drain regions and covers the channel region itself. In this way, the lower surface edge of the transistor gate electrode can be lifted above the surface of the substrate, and the channel region beyond the substrate is between the diffusion range of the source / drain electrodes 40, 42. (Please read the precautions on the back and then fill out this page). Packing. This paper is printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. The paper standard is applicable to the Chinese National Standard (CNS) Λ4 specification (210X 297 mm) 0325TWF.DOC / 002 A7 0325TWF.DOC / 002 A7 Printed by B7 Employee Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs B. V. Description of Invention (π) The conventional Patel transistor gate electrode has a flat lower surface separated from the channel area by an average distance. With respect to similar potentials applied to similar channel regions, the gate electrode 44 in FIG. 2 may generate a lower-intensity electric field at the edge of the channel region or within the source / drain electrodes, resulting in the channel region having a conductivity ratio of It is known that the channel area of the gate transistor of the planar gate electrode is low. In either case, fewer conductors will appear in the area of the transistor directly after the source / drain regions. Therefore, the different electric fields generated by the gate transistors of the transistors shown in the figure will reduce the mutual conductance of the channels passing through the transistors, and the amount of current flowing through the pull-down transistor 14 will reduce the current flowing through the transistors 18 The amount of current. As shown in FIG. 2, the cross-sectional configuration of the gate electrode 38 of the pull-down transistor 14 has not changed significantly from the configuration fabricated in the conventional SRAM, making the gate electrode 44 of the transistor 18 The adjustment and modification of the cross-sectional configuration can reduce the conductance of the transistor 18 by using a method that can increase the stability of the SRAM memory cell. The SRAM in FIG. 2 is fabricated on a silicon substrate 30, and the field oxide element insulating region U is formed on the surface of the substrate 30. The pull-down transistor 14 is composed of source / drain regions 34, 36 formed on the surface of the substrate 30, and a gate electrode 38 formed on a gate oxide layer (not shown) formed on the surface of the substrate 30 of. Piezo transistor 18 is composed of source / drain regions 40, 42 formed on the surface of the substrate, and a gate electrode 44 formed on a gate oxide layer (not shown). The gate electrodes 38, 44 of the pull-down and transistor transistors are at least partially composed of doped polycrystalline silicon. When the gate electrode is made of multiple layers of conductive materials, up to the size of this paper, the Chinese National Standard (CNS) A4 specification (210X 297 mm) is applicable (please read the precautions on the back before filling in this page). Install, τ 0325TWF .DOC / 002 A7 0325TWF.DOC / 002 A7 Printed B7 by the Employees ’Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs _ 5. Invention Description (M) The lowest part of the gate-less electrode should be composed of a layer of doped polycrystalline silicon . The lowest layer of the gate electrodes 38, 44 of the pull-down and transistor transistors can be made of a single layer of polycrystalline silicon, or, in other SRAM memory cell structures, different layers of polycrystalline silicon can be added to the pull-down and Inside the gate electrode of the transistor. The structure shown in Figure 2 can be fabricated using a differential oxidation process. In this process, the gate electrode of the pull-down transistor and the load transistor are masked by a layer if they are also fabricated on the substrate level. Covered by the cover to protect the gate electrode from oxidation. The gate electrode of the Piston transistor remains exposed, or the mask covering the Piston transistor is removed to expose the gate electrode of the Piston transistor. The polycrystalline silicon gate electrode is then exposed to an oxidizing environment, for example, to oxygen at a temperature of about 950 to 1050 ° C. The exposure time lasts long enough to oxidize the lower edge of the gate electrode to the required degree. The top edge of the transistor gate electrode is often oxidized during this process. However, if the gate electrode of the Piston transistor is formed in a multilayer structure, such as a layer of metal silicide formed on the surface of the polycrystalline silicon electrode, the upper edge of the gate electrode of the Piston transistor will not be oxidized, or It was only slightly oxidized. In this case, the upper edge of the transistor gate electrode can maintain a conventional shape, such as the shape shown in the embodiment of FIG. 2. The gate electrode 38 'of the pull-down transistor 14 is generally rectangular in shape. Some rounding of the upper edge of the gate electrode 38 can occur when different oxide layers are formed around the gate electrode ', but this rounding is only secondary and does not change significantly in the channel of the pull-down transistor The resulting electric field distribution. Although the paper size shown in the figure is suitable for China National Standard (CNS) Λ4 specification (210X297mm) (please read the precautions on the back before filling this page).

* 1T 0325TWF.DOC / 002 A7 0325TWF.DOC / 002 A7 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs --_ B7__ V. Description of Invention (丨)) Pull down and send transistors at their respective sources / drains The channels between the pole regions have approximately the same length, but in many cases, the channel of the transistor is made longer than the channel of the pull-down transistor. After the oxidation, an etching process is then performed to remove the polycrystalline silicon oxide, and then further processes are performed in a conventional manner to complete the fabrication of the SRAM. The extent to which the transconductance of the Patek transistor is reduced by the process of differential oxidation 'depends on how much the lower edge of the gate electrode of the Patek transistor is removed. In this way, it is necessary to determine the time of the polysilicon oxidation process, and thus the degree to which the relative conductance of the pass transistor can be reduced. And this can be used to determine between the transistor and the pull-down transistor, to obtain a stable memory cell for a given transistor size and geometry, and other transistor and memory cell characteristics, during which the current flows The difference is determined. Of course, reducing the amount of current that can flow through the Piezo transistor will have an impact on other performance characteristics of the SRAM, such as access speed, etc. Therefore, the current capacity of the Piezo transistor should not be reduced too much. If the edge of the Piston transistor gate electrode is made of a material with a work function different from that of the N-type polycrystalline silicon used in the central portion of the Piston transistor gate electrode, it can be obtained as An effect similar to that obtained by the embodiment in Figure 2 is obtained. For example, the gate electrode of the Patel transistor can be made of P-type polycrystalline silicon, which has a different work function than N-type polycrystalline sand relative to silicon. In such an embodiment, a layer of tungsten silicide formed on the surface of the Patron transistor electrode can be used with the polycrystalline silicon gate electrode (please read the precautions on the back before filling this page). National Code of Practice (CNS --- 0325TWF.DOC / 002 A7 0325TWF.DOC / 002 A7 Printed by the Employee Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs _____B7 V. The N-type central part and P-type edge of the description (β) Some of the two are in contact to maintain the entire gate electrode as an equipotential surface. The difference in the number of power culverts on the edge of the gate electrode of the transistor will significantly change the mutual conduction of the transistor. It substantially changes the electric field generated in the channel and at the edge of the source / drain contact area. The width and doping of the P-type edge portion of the gate electrode can be changed to bring the transconductance of the transistor to the pull The transistor is adjusted to the required level. The embodiment in FIG. 2 is a better embodiment than this change, because the embodiment in FIG. 2 uses fewer process steps and looser design criteria , You can make It is shown in Figures 3 and 4 that some of the process steps involved in making an SRAM that contains memory cells that adjust the transistors according to the method shown in Figure 2. Most of the structure and process of SRAM are conventional, so they will not be discussed in detail here. First, refer to Figure 3, which shows the memory cell of SRAM in the middle stage of the process. Field oxide device insulation region 32 It has been formed on the substrate 30, a layer of gate oxide (not shown) has also been formed on the substrate 30, and a layer of doped polycrystalline silicon has also been formed on the gate oxide layer. The doped polycrystalline silicon layer has been imaged in a conventional manner in order to provide a pull-down transistor gate electrode with a conventional configuration and provide an unshaped electrode on the channel of the transistor 18. Source / The implantation of the drain is automatically aligned with the gate electrodes 38, 43. If these transistors are to use a lightly doped drain (LDD) source / drain structure, only the implanted The lightly doped drain part is usually carried out at this time. With reference to Figure 4, the electrode is defined as shown in Figure 3. Figure 15 The paper size is applicable to the Chinese national standard CNS) A4 specification (210X297mm)-(Please read the precautions on the back before filling this page)

* 1T A7 318282 0325TWF.DOC / 002 _B7 _ 5. After the invention (丨 f), a mask 46 was formed on the gate electrode of the pull-down transistor to protect the polycrystalline silicon layer in the gate electrode. Several different masking materials can be used to protect the gate electrode of the pull-down transistor. For example, a layer of silicon oxide with a thickness of 50 to 500 A formed by chemical vapor deposition using TEOS (tetm-ethyl-orth〇-Silicate), or a high-temperature oxide layer formed by a similar method. A protective mask formed by a layer of silicon nitride or pull-down can provide better resistance to further oxidation. After the mask 46 is formed, any oxide or mask material formed on the gate electrode of the pass transistor 18 is removed. This can be achieved by forming a protective photoresist mask on at least the gate electrode of the pull-down transistor, and when the load transistor is formed on the SRAM substrate, it is also formed on the load transistor. Any oxide layer on the gate electrode surface of the transistor can be removed using a diluted HF solution or an isotropic fluoride-based oxide dry etch procedure. Other mask materials are also removed as needed. Of course, the photoresist mask of the previous process step will be ashed in any oxidation process step, so it may not be necessary to include a special step to remove the photoresist mask. Next, an extended oxidation process is performed to oxidize the polycrystalline silicon layer of the gate transistor gate electrode to the desired level. Further process steps can then continue to complete the production of SRAM. If some or all of the SRAM transistors use LDD source / drain regions, the oxide or other mask layer on the appropriate gate electrode is removed. The oxide separation layer is then formed on one of the two sides of the gate electrode by a general CVD oxide deposition and etch back process, and then the paper standard is applicable to the Chinese National Standard Falcon (CNS) Λ4 specification (2 丨 Οχ297 Mm) (please read the precautions on the back before filling in this page). Packing. Printed and printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 0325TWF.DOC / 002 A7 B7 5. Description of the invention (K) Concentrated doping to form LDD electrodes Part. If no further source / drain region doping is required, the fabrication process structured in Figure 4 continues with the deposition of a thick insulating layer. Regardless of the situation, further conventional process steps will need to be used to complete the fabrication of this device. Although the present invention has been disclosed as above with preferred embodiments, these embodiments are not intended to limit the present invention. Anyone who is familiar with this skill can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be deemed as defined by the scope of the attached patent application. (Please read the precautions on the back and then fill out this page), 、 1T Printed by the Employees ’Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs The paper size is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297mm)

Claims (1)

Duo Printing A8 〇325TWF_〇02? 8 D8 by the consumer cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs VI. Patent application 1. An SRAM with a plurality of SRAM memory cells addressed by bit lines, the SRAM memory cells It includes: a high reference potential contact and a low reference potential contact; a charge storage node; a pull-down transistor connected to the charge storage node and the low reference potential contact, the pull-down transistor has a source, a drain and A pull-down \ transistor gate electrode; and a faction transistor connected to the charge storage node and a bit line, the faction transistor has a source, a drain and a faction transistor gate electrode, the faction transistor gate electrode has The surface is curved to a greater extent than the surface under the gate electrode of the pull-down transistor. 2. The SRAM as described in item 1 of the patent application scope, wherein the lower edge of the gate transistor gate electrode is disposed above the surface of a substrate at a position higher than the lower edge of the pull-down transistor gate electrode. '3. The SRAM as described in item 2 of the scope of the patent application, wherein the lower edge of the gate transistor gate electrode is placed on the surface of the substrate with a sufficient height to compare with a flat lower electrode The electric field generated by the Patel transistor can change the electric field formed in a channel area of the Patel transistor by a sufficient amount to change the mutual conductance of the Petit transistor. 4. The SRAM as described in item 2 of the scope of the patent application, in which the lower edge of the gate electrode of the Piston transistor is lifted away from the base surface of the channel region of the Piston transistor, the degree of lift is greater than the The central part of the lower surface of the gate electrode of the Piton transistor. 5. A kind of SRAM, which has a plurality of SRAM 'rr addressed by the bit line ....................... installed -..... .......... tr ................ Line (please read the precautions on the back before filling in this page) This paper size is applicable to China National Standards (CNS ) A4 specification (210X 297 mm) 8 8 8 8 AB c D WF.DOC / 002 6. Patent application memory cells, these SRAM memory cells include: a high reference potential contact and a low reference potential contact; Charge storage node; a pull-down transistor connected to the charge storage node in contact with the low reference potential, the pull-down transistor has a source, a drain and a pull-down transistor gate electrode; and a pass transistor connected to the A charge storage node and a bit line, the Piezo transistor has a source, a drain, a channel and a Piezo transistor gate electrode, the Piezo transistor gate electrode has a device in the channel area of the Piezo transistor An electric field with a specific configuration is generated in the field, where the generated electric field is reduced in intensity in the channel region immediately after the source and drain of the transistor. 6. A method for manufacturing SRAM, the steps of which include: providing a substrate and wires formed on the substrate, wherein a first wire is formed on the channel region of the pull-down transistor, and a second wire is formed on a pie Above the channel area of the energizing crystal; shielding the first wire in a way to protect the first wire from oxidation; and exposing the second wire to an oxidizing environment, and the first wire is shielded to The first and second wires have different cross-sectional configurations. 7. The method as described in item 6 of the patent application scope, wherein at least one lower portion of the first and second wires is doped polysilicon. 19 (Please read the precautions on the back before writing this page) Packing • Printed by the Consumer Cooperation Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm)