317004 A7 ----------B7五、發明説明（） 域 領 明 發 别坦 特平 ^進 製法 匕方 W磨 平研 之械 中機 程學 製化 體之 導層 半止 種停 一層 舆一 明成。 發形果 本用效 利之 是化 經濟部中央標準局員工消費合作杜印裝 發明背景： 半導髖工業不僅包含以矽爲主之產業，而且還包含其 他三五族舆二六族化合物半導體之工業，積體電路由數以 萬計之固態電子元件组合而成，積鳢電路之生產主要包含 (1)矽晶片之製造（2)積體電路之製作（3)積體重路之構 裝。其中半導體晶片中之元件由謨層間之導電性内連線做 電性接觸’这些内連線之間均有絶緣層隔離防止短路之發 生。隨晶片表面膑層之高低起伏之介電沈積層因沈積表面 不平坦，將使得後續沈積膜層之微影、曝光聚焦之困難而 影響到蝕刻或沈積之品質，因此平坦化製程於半導禮製程 中格外重要》 目前平坦化製程中有數種平坦化之方法，例如熱流 法、回蝕刻法、旋塗式玻璃法（s p i η ο n g丨a s s)及化學機械 研磨法（chemical mechanical polishing)。熱流法所需之 溫度相當高，且一但當以鋁爲主之金屬層覆蓋晶片之後此 法便不太適用，蝕刻法只能達到局部平坦化之效果，無法 達到全面性平坦化，旋塗式玻璃法亦只能提供介電層之局 本紙張尺度適用中國國家標準（CNS ) A4规格（21〇><297公釐） (請先閱讀背面之注意事項再填寫本頁) -訂 -線f 五、發明説明（ Α7 Β7 部平坦化且成隸、U及㈣，要㈣全面性平扭 化之效果必須使用化學機械研磨法，此法已儼然成爲業界 追求全面性平坦化之方法。 化學機械研磨法（chemical mechanical polishing ; CMP)爲半導體製程中全面性平坦化的—種技術。利用機 械式研磨之原理，配合適當之化學助劑把晶片表面高低起 伏不一之輪廓加以磨平，若各種製程參數控制得宜cMP 可以提供被研磨表面高達94 %以上之平坦度。但是因爲 半導禮之製程於結構與材料上更爲複雜，而CMP平坦化 製程依賴製程中半導體之結耩舆材料，因此傳统之化學機 械研磨法並不能提供很好之平坦化效果。傳統之平坦化製 程如第一圈所示，於半導禮基板2形成元件之後（B中未 示），接著形成氧化層4於上迷之基板之上，接著形成金 屬内連線6及一氮化矽層8形成於於金屬内連線6之上， 然後以旋塗式玻璃法（spin on glass ; SOG)形成之氧化 層10場入金屬内連線6間之溝槽，參閲第二圈，最後再 以化學機械研磨法平坦化，由第二圈可知由於氮化矽與氧 化層之研磨速率不同因此於金屬内連線6間隔較大之區 域將形成過度研磨而呈現凹陷之外觀12。 (讀先閱讀背面之注意事項再填寫本頁)317004 A7 ---------- B7 Fifth, the description of the invention () The domain leader clearly sent Betantepin ^ hexadecimal method dagger square W Mopingyan machine in the mechanical system of the mechanical guide half This kind of halt is one thing. The benefits of hair shape and fruit are beneficial to the consumer cooperation of the Central Bureau of Standardization of the Ministry of Economy and Economics. The background of the invention: the semi-conductive hip industry not only includes silicon-based industries, but also other semiconductors of the three or five groups and the second and sixth groups. In industry, integrated circuits are composed of tens of thousands of solid electronic components. The production of integrated circuits mainly includes (1) the manufacture of silicon chips (2) the manufacture of integrated circuits (3) the construction of integrated circuits. Among them, the elements in the semiconductor chip are electrically contacted by conductive interconnects between the mo layers. These interconnects are insulated by an insulating layer to prevent the occurrence of short circuits. The unevenness of the dielectric deposition layer along with the unevenness of the wafer layer on the wafer surface will make the lithography of the subsequent deposited film and the difficulty of focusing the exposure affect the etching or deposition quality, so the planarization process is semi-guided Especially important in the process "At present, there are several methods of planarization in the planarization process, such as heat flow method, etch back method, spin-on glass method (spi η ο ng 丨 ass) and chemical mechanical polishing method (chemical mechanical polishing). The temperature required by the heat flow method is quite high, and once the metal layer mainly covered with aluminum covers the wafer, this method is not suitable. The etching method can only achieve the effect of local planarization, and cannot achieve comprehensive planarization. Spin coating The glass method can only provide the dielectric layer. This paper standard is applicable to the Chinese National Standard (CNS) A4 specification (21〇 < 297mm) (please read the precautions on the back before filling this page) -subscribe -Line f V. Description of the invention (Α7 Β7 part is flattened and formed into parts, U and ㈣, for the effect of comprehensive flattening and twisting must use chemical mechanical polishing method, this method has become the industry's pursuit of comprehensive flattening method Chemical mechanical polishing (CMP) is a technique for comprehensive planarization in the semiconductor process. The principle of mechanical polishing is used to smooth the uneven contours of the wafer surface with appropriate chemical additives. If various process parameters are properly controlled, cMP can provide a flatness of up to 94% of the polished surface. However, because the semi-conducting process is more complicated in structure and materials, the CMP is flat The flattening process depends on the semiconductor materials in the process, so the traditional chemical mechanical polishing method can not provide a good planarization effect. The traditional planarization process is shown in the first circle, and the device is formed on the semiconductor substrate 2 Afterwards (not shown in B), an oxide layer 4 is formed on the substrate above, then a metal interconnect 6 and a silicon nitride layer 8 are formed on the metal interconnect 6, and then spin-coated The oxide layer 10 formed by spin on glass (SOG) enters the trench between the metal interconnects 6 in the field, refer to the second circle, and finally flattened by chemical mechanical polishing. From the second circle, it can be seen that due to nitrogen The silicon carbide and the oxide layer have different polishing rates. Therefore, areas with large spacing between the metal interconnects 6 will be over-polished and present a concave appearance. 12. (Read the precautions on the back before filling this page)
-1 1 I S -Γ 訂 線f-1 1 I S -Γ line f
中 橾 準 局 Ά 工 合 作 社 印 製 3 本紙張尺度逋用中國國家榡準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 3l7〇〇4 Α7 ------ B7 五、發明説明（） 發明目的及概述： 本發明之主要目的爲提供一種應用於半導雅製程中 之平坦化製程。 本發明之次一目的爲提供一種應用於半導體製程中 之化學機械研磨停止層之形成方法。 形成介電層於半導體基板之上作爲絶緣層，接著沈積 一金屬層於上述之介電層之上用以做爲電性傳遞之金屬 内連緩（interconnection)，以微影及蝕刻技術將金屬廣形 成内連線之圈索，内金屬介電層（intermeta丨die丨eetNc ; IMD)形成於金屬層之上做爲絶緣層，s〇g層（spiri on glass )將形成於内金屬介重層之上，接著將氮離子以離 子植入方式形成控制化學機械研平坦化製程研磨厚度之 停止層，此氮離子穿越SOG層進入内金屬介重層之中以 形成控制研磨厚度之停止層，最後化學機械研平坦化製程 將晶片平坦化至停止層。 圈式簡單説明： 第一圈至第一圈爲習用之化學機械研磨平坦化製程之截 面圈。 第三®爲本發明之化學機械研磨平坦化製程之形成金屬 内連線之截面圈。 本紙張尺度逍用中國國家橾準（CNS ) Μ規格（2〖〇Χ297公釐） * - 、 ;S,— (諳先閱讀背面之注意事項再填寫本頁)Printed by the China Central Bureau of Industry Co., Ltd. 3 This paper is printed in China National Standard (CNS) A4 (210X297 mm). Printed by the Ministry of Economic Affairs Central Standards Bureau Employee Consumer Cooperative 3l70〇4 Α7 ------ B7 Fifth, the description of the invention () The purpose and summary of the invention: The main purpose of the present invention is to provide a flattening process applied in the semi-conducting elegant process. The second object of the present invention is to provide a method for forming a chemical mechanical polishing stop layer used in a semiconductor manufacturing process. A dielectric layer is formed on the semiconductor substrate as an insulating layer, and then a metal layer is deposited on the above dielectric layer to serve as an electrical transmission metal interconnection (interconnection), using lithography and etching technology to metal Widely form a loop of internal wiring, an internal metal dielectric layer (intermeta 丨 die 丨 eetNc; IMD) is formed on the metal layer as an insulating layer, and a s〇g layer (spiri on glass) will be formed on the internal metal dielectric layer Then, nitrogen ions are ion implanted to form a stop layer that controls the polishing thickness of the chemical mechanical polishing planarization process. The nitrogen ions pass through the SOG layer into the inner metal dielectric layer to form a stop layer that controls the polishing thickness. The mechanical polishing planarization process planarizes the wafer to the stop layer. Brief description of the circle type: The first circle to the first circle are the cross-section circles of the conventional chemical mechanical grinding and planarization process. The third ® is the cross-section ring of the metal mechanical interconnection formed by the chemical mechanical polishing and planarization process of the present invention. The standard size of this paper is the Chinese National Standard (CNS) Μ specifications (2 〖〇Χ297mm) *-,; S, — (Be sure to read the precautions on the back before filling this page)
,1T 五、發明説明（） A7 B7 金止學 内停化 成成以 形形 施 之 之 之 程程程 製製製 匕匕匕 #1 /1 坦。坦 坦 平ffl平 平 磨面磨 磨 研截研 研 械之械 械。 機廣機.機圖 學璃學 學面 化玻化 化截 之式之 之之 明塗明 明化 發旋發。發坦 本與本圈本平 爲層爲面爲磨 圈電圈截圖研 四介五之六械 第屬第層第機 —：——^----.--C------訂------- (諳先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作社印製 本紙張尺度適用中國國家標準（CMS ) A4规格（210X2_97公釐） A7, 1T V. Description of the invention () A7 B7 Jin Zhixue Stopped in the process of forming into the form of the process of making the system dagger dagger # 1/1 Tan. Tan Tan Ping flat ffl flat grinding surface grinding grinding research research research equipment mechanical equipment. Machine wide machine. Machine drawing Learning glass learning The face of vitrification and cutting of the formula of Ming Tu Ming Ming hair twist hair. Fatan Ben and Ben Ping Ben Ping are the layers, and the surface is the grinding ring. The screenshot of the electric circle is the fourth and fifth machines of the fourth, fifth, fifth, and fifth machines ————— ^ ----.-- C ------ Order ------- (Be sure to read the precautions on the back and then fill out this page) The paper standard printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs applies the Chinese National Standard (CMS) A4 specification (210X2_97mm) A7
發明蛘細説明： 爲了增進化學機械研平坦化之效果，一種利用停止層 控制平坦化之厚度將於下述，本發明以停止層深埋於内金 屬介電層（inter metal dielectric layer，·，丨MD)或是内層 介電層（interlevel dielectric ; ILD)中，此停止廣將是以 緣子植入方式形成於内金屬介電層（inter meta丨 dielectric ; IMD)或是丨LD之中。如第三圈所示於半導鱧 基板20上形成元件（圏中未示出）及其相關製程之後形成 介電層22於半導體基板20之上作爲絶緣層，接著沈積一 金屬層24於上述之介電層22之上用以做爲電性傳遞之 金屬内連線（interconnection)，上述之金屬層24厚度範 園介於6500至7200埃之間，然後以微影及蝕刻技術將 金屬層24形成内連線之圈案。 參閲第四圏 一内金屬介電層（inter metal (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央梂準局貝工消費合作社印裝 dielectric ; IMD)26形成於金屬層24之上做爲金屬層24 間或是與其他金屬層間之絶緣層，此内金屬介電層26是 以電漿增強式化學氣相沈積法形成（plasma enhance chemical vapor deposition ; PECVD)之氧化層，上述之 内金屬介電層26之厚度爲150 00至20000埃之間。爲了 提供較佳之平面以利後續之化學機械研平坦化製程，一旋 塗式玻璃層（spin on glass ; S0G )28將形成於内金屬介 電層26之上，此步驟爲利用旋塗式玻璃法（spin on 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐）Detailed description of the invention: In order to enhance the effect of chemical mechanical research on planarization, a stop layer is used to control the thickness of the planarization will be described below. In the present invention, the stop layer is buried deep in the inner metal dielectric layer (inter metal dielectric layer,丨 MD) or interlevel dielectric (ILD), this stop will be formed in the inner metal dielectric layer (IMD) or LD by means of edge implantation. As shown in the third circle, a device (not shown) and its related processes are formed on the semiconductor substrate 20, and then a dielectric layer 22 is formed on the semiconductor substrate 20 as an insulating layer, and then a metal layer 24 is deposited on the above The dielectric layer 22 is used as a metal interconnection for electrical transmission. The thickness of the metal layer 24 is between 6500 and 7200 angstroms, and then the metal layer is formed by lithography and etching technology. 24. Form a circle case of interconnection. Please refer to the fourth inner metal dielectric layer (inter metal (please read the precautions on the back before filling out this page). The Ministry of Economic Affairs, Central Bureau of Economic and Technical Affairs, Beigong Consumer Cooperative Printed Dielectric; IMD) 26 is formed on the metal layer 24 It is used as an insulating layer between the metal layers 24 or other metal layers. The inner metal dielectric layer 26 is an oxide layer formed by plasma enhanced chemical vapor deposition (PECVD). The thickness of the above-mentioned inner metal dielectric layer 26 is between 150,000 and 20,000 angstroms. In order to provide a better plane to facilitate the subsequent chemical-mechanical planarization process, a spin-on glass layer (spin on glass; SOG) 28 will be formed on the inner metal dielectric layer 26, this step is to use spin-on glass Law (spin on this paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm)
glass’· SOG)將溶於溶劑中之介電材料以塗佈之方式形 成氧化層28，因其可隨溶劑在晶片上流動因此可以；易 的填入-¾凹溝之巾’經過—些熱處理以去除溶劑以較 佳實施例而言該SOG層厚度範圍爲4〇〇〇至6〇〇〇埃之 間。 、 如第五圈所示，將氮離子以離子植入方式形成控制化 學機械研平坦化製程研磨厚度之停止層，此離子植入以劑 量2E15-4E15at〇m/cm'植入能量35〇至45〇_將氮離 子穿越SOG層28進入内金屬介電層26之中以形成控制 研磨厚度之停止層30，利用氧化層與氮離子研磨速率不 同利於研磨停止點（end point)之偵測而控制研磨厚度， 氮的植入使介電層26(氧化物）更緻密難磨，另外化學機 械研磨包含氧化物輿研磨液間之化學反應及機械研磨，氮 與氧化物的研磨液不易起化學反應故會延遲研磨速率，因 此氮植入的氧化物部份可以扮演停止層之角色。 (請先閱讀背面之注意事項再填寫本頁) 訂 經涛部中央梯準局貝工消費合作社印製 如第六圖所示，以化學機械研磨平坦化製程將晶片 | 平坦化至停止層30,利用機械式研磨之原理，配合適當 ^ 之化學助劑把晶片表面高低起伏不一之輪麻加以磨平，上 j 述之内金屬介電層26研磨後之厚度爲8000至ι2〇〇〇埃之 .| 間， ' 丨丨 本發明以離子植入方式形成一停止層30於内金屬介 ! 本紙伕尺度適财關家揉準（CNS ) M規格（21Gx297公釐 317〇〇4 A7 B7 五、發明説明（ 霣層26之中以利於控制研磨之厚度且不會有 氮化發與氣化層之研磨速率不同(氮切研磨 化層研磨速率之1/3-1/5)造成平坦化效 良之外觀不利後續膜層之沈積。 果不佳而形成不 本發明以一較佳實施例説明如上，而熟悉此領域技藝 者，在不脱離本發明之精神範圍内，當可作些許更動满 飾’其專利保護範面更當視後附之申請專利範面及其等同 領域而定。glass' · SOG) The dielectric material dissolved in the solvent is coated to form the oxide layer 28, because it can flow with the solvent on the wafer, so it can be easily filled in Heat treatment to remove the solvent. In the preferred embodiment, the thickness of the SOG layer ranges from 4,000 to 6,000 angstroms. As shown in the fifth circle, nitrogen ions are ion implanted to form a stop layer that controls the grinding thickness of the chemical mechanical polishing planarization process. This ion implantation uses a dose of 2E15-4E15at〇m / cm 'implantation energy of 35〇 to 45〇_ Nitrogen ions pass through the SOG layer 28 into the inner metal dielectric layer 26 to form a stop layer 30 to control the thickness of the polishing, using the oxide layer and the nitrogen ion polishing rate is different to facilitate the end point of the grinding (end point) detection and Controlling the polishing thickness, the implantation of nitrogen makes the dielectric layer 26 (oxide) denser and harder to grind. In addition, chemical mechanical polishing includes chemical reaction between the oxide and the polishing liquid and mechanical polishing. The polishing liquid of nitrogen and oxide is not easy to chemical The reaction will delay the polishing rate, so the oxide part of the nitrogen implant can act as a stop layer. (Please read the precautions on the back before filling out this page) Printed by Taobei Central Equatorial Bureau Beigong Consumer Cooperative Printed as shown in the sixth figure, chemical mechanical polishing planarization process to planarize the chip | to the stop layer 30 , Using the principle of mechanical grinding, with appropriate chemical additives to smooth the uneven surface of the wafer surface roughness, the thickness of the inner metal dielectric layer 26 after grinding is 8000 to ι2〇〇 Ai Zhi. | Time, '丨 丨 The present invention uses ion implantation to form a stop layer 30 in the metal intermediary! This paper is suitable for the size of the financial standards (CNS) M specifications (21Gx297 mm 317〇〇4 A7 B7 V. Description of the invention (In the 霣 layer 26 to facilitate the control of the thickness of the grinding and there will be no difference between the grinding rate of the nitrided layer and the vaporized layer (1 / 3-1 / 5 of the grinding rate of the nitrogen-cut grinding layer) resulting in flatness The appearance of good effect is unfavorable for the subsequent deposition of the film layer. If it is not good, it will not be formed. The present invention is described above in a preferred embodiment, and those skilled in the art can do a little without departing from the spirit of the present invention. "Motion full decoration", its patent protection is more visible The patent art Fan surface and equivalents may be.
Is I Id K. n. I ·, I. - I I - - I !-*I .1 · (锖先聞讀背面之注意事項再填寫本頁} -訂 經濟部中央標準局負工消費合作社印裝 8 本紙張尺度遑用中國國家標準（CNS ) M規格（210X297公釐〉 五、發明説明（ 研磨停止點（end point)之偵測而控制研磨厚度，該離子 植入劑量爲2E15-4E15 atom/cm2，植入能量爲350- 450KeV ;及 ， 施以化學機械研磨法將該基板平坦化。 9.如申請專利範面第8項之平坦化方法其中上述之内金 屬介雩層是以雩漿增強式化學氣相沈積法形成（p|asma enhance chemical vapor deposition ; PECVD)之氡化 層。 1〇_如申請專利範_第9項之平坦化方法，其中上述之内 金屬介雹層做爲金屬層間之絶緣層。 11. 如申請專利範面第項之平坦化方法，其中上述之内 金屬介電層厚度範面介於15000至20000埃之間。 12. 如申請專利範固第8項之平坦化方法，其中上述之金 屬層厚度範团介於65 00至72 0 0埃之間。 13.如申請專利範面第8項之平坦化方法，其中上述之旋 塗式玻璃層厚度範圍介於4000至6000埃之間。 經濟部中央標準局男工消费合作社印裝 本紙張尺度逋用中國國家棣準（CNS ) Α4規格（210χ297公釐）Is I Id K. n. I ·, I.-II--I!-* I .1 · (Read the precautions on the back before filling this page) Pack 8 pieces of paper using Chinese National Standard (CNS) M specifications (210X297mm). 5. Description of the invention (detection of end point of grinding to control the thickness of grinding. The ion implantation dose is 2E15-4E15 atom / cm2, the implantation energy is 350-450KeV; and, the chemical mechanical polishing method is used to planarize the substrate. 9. The planarization method as described in item 8 of the patent application scope, in which the above-mentioned inner metal dielectric layer is The radon layer formed by the psas enhanced chemical vapor deposition (PECVD) method. 10_ The flattening method as described in patent application item # 9, in which the inner metal-mediated hail layer is used as It is an insulating layer between metal layers. 11. For example, the planarization method in the patent application section, where the thickness of the inner metal dielectric layer is between 15,000 and 20,000 angstroms. 12. If the patent application is in the 8th Item of the planarization method, wherein the above-mentioned metal layer thickness range is between 65 00 72 0 0 Angstroms. 13. The flattening method as described in item 8 of the patent application, where the thickness of the spin-on glass layer is between 4000 and 6000 Angstroms. Male Workers ’Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs The size of the printed paper adopts China National Standards (CNS) Α4 specification (210 × 297 mm)