316971 經濟部中央標準局貝工消费合作社印裂 A7 ________B7五、發明説明（）S-ι發明領域： 本發明係關於一種陰極射線管（Cath〇de Ray Tube， CRT)顯示系統，特别是指利用一單晶片顯示系统控制器 來控制的CRT顯示系統，該晶片之積體電路 Circuit, 1C)中包含一少部份之類比電路，即可有效的降低 類示系統的成本’同時增加該顯示系統的效能。5-2發明背景： 目前的CRT顯示系统主要多以類比電路來控制，水 平輿垂直偏向控制電路仍經由類比元件與電路來構築；另 一方面，另使用一數位顯示系统控制器，來控制系統顯示 特性與數位控制監視器的偏向控制。該數位顯示系统控制 器在典型中係利用由一微控制器（Mier〇c〇ntr〇1ier)、關聯 記憶雅（Associated memory)、以及經由習知的低價位數位 半導體處理器所處理的控制軟鳢所組成。習知中，該顯示 系统控制器透過兩種方式與類比偏向電路交換資訊，第一 種方式係提供一類比界面與類比偏向電路做溝通；第二種 方式係提供一數位界面，與該類比電路的數位界面電路相 接。所以一些偏向的相關係數，諸如，水平大小、水平對 中度（Horizontal centering)、垂直大小與垂直對中度皆可 獲得調聲。 (請先閱讀背面之注意事項再填寫本頁) 裝.316971 Beigong Consumer Cooperative of Central Bureau of Standards, Ministry of Economic Affairs, printing A7 ________B7 V. Description of invention () S-ι Field of invention: The present invention relates to a cathode ray tube (Cathode Ray Tube, CRT) display system, in particular refers to the use of A CRT display system controlled by a single-chip display system controller. The chip's integrated circuit (Circuit, 1C) contains a small number of analog circuits, which can effectively reduce the cost of the display system and increase the display system. Performance. 5-2 Background of the invention: The current CRT display systems are mostly controlled by analog circuits. The horizontal and vertical deflection control circuits are still constructed by analog components and circuits; on the other hand, a digital display system controller is used to control the system Display characteristics and digital control monitor bias control. The digital display system controller typically uses a microcontroller (Mier〇c〇ntr〇1ier), associated memory (Associated memory) (Associated memory), and through the processing of conventional low-priced digit semiconductor processors Composed of soft snakeheads. In the conventional knowledge, the display system controller exchanges information with the analog bias circuit through two methods. The first method provides an analog interface to communicate with the analog bias circuit; the second method provides a digital interface to communicate with the analog circuit. The digital interface circuits are connected. Therefore, some biased correlation coefficients, such as horizontal size, horizontal centering, vertical size and vertical centering can be tuned. (Please read the precautions on the back before filling out this page).
、1T 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 316971 A7 B7 經濟部中央標準局貝工消費合作社印製 五、發明説明（） 至於勞幕重4顯示（〇nScreenDisplay，OSD)之應用方 面，亦需要一獨立的積體電路來產生所需的視訊資訊’數 位顯示系統控制器必須與該OSD晶片做溝通，以獲得視 訊内容輿視訊資訊所類示之位置。 第一圈描述一習知的頻示控制系统之架構方塊圖，圈 中包括一顯示系統控制器 （Display system controller)l 01，控制前端面板（Control panel)l 07、電源 1〇8、視訊處理器106、視訊電路111、螢幕重疊顯示（〇SD) 處理器105、垂直處理器（Vertical processor)104、以及 水平處理器（Horizontal processor)103 ，每個單元方塊中 仍包含個别的電路於其中，水平偏向電路1〇9透過水平線 圏（Horizontal yoke)來控制水平偏向，並產生一回歸脈衝 (Flyback pulse)回授至水平處理器1〇3;與垂直處理器1〇4 耗合的垂直偏向電路1 1 〇則經由垂直線圏（Vertical y〇ke) 來控制垂直偏向。 習知技術中，對於偏向控制、〇SD之產生、以及數 位顯π系统控制器而言，皆需要獨立的積體電路來完成。 因爲製造這些電路之製程皆有其特定的要求，所以目前並 沒有將上述之偏向控制、〇SD之產生、以及數位顯示系 统控制器結合於一單—晶片的產品問世基於商業與成本 的考量’將該偏向控制、產生0SD、以及數位類示系統 控制器結合於一單一晶片中是有其需要的。 (請先閱讀背面之注意事項再填寫本頁) 裝. 訂 本紙張尺度適用中 316971 經濟部中央標準局貝工消費合作社印装 A7 B7五、發明説明（） 5-3發明目的及概述： 鑒於上述之發明背景中，習知技術中將偏向控制、 OSD之產生、以及數位類示系統控制器分離於數個獨立 的晶片中，而如此之作法不符成本效益，本發明即針對該 項缺點提出一改良方式，將上述之偏向控制' 〇SD之產 生、以及數位顯示系统控制器結合於一單一晶片之中，同 時具消耗低電能以降低系统造償之特性。 本發明的另一目的，在利用相位閉鎖迴圈（Phase Lock Loop, PLL)之來控制偏向方式來建立顯示系统控制器，顯 示相位校準（Display phase adjustment)、大小校準（Size adjustment)、以及線性校準（Linearity adjustment)等皆可 利用該單一晶片來完成。 本發明更進一步之目的，在於提供一同步參考時序， 其可用於OSD的視訊資訊之產生，與視訊空白輸出之控 制。 根據以上所述之目的，本發明提供了一單晶片，其包 含顯示系统控制器、水平處理器、垂直處理器、以及可選 用的OSD處理器，顯示系統控制器控制水平處理器、垂 直處理器、以及OSD處理器的動作。水平處理器更包含 一相位閉鎖迴圏電路（PLL)，用以控制水平偏向與產生該 本紙張尺度適用中國國家橾準（CNS ) Α4规格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) *Ί». 裝. 訂 ^16971 A7 B7 經濟部中央標準局貝工消費合作社印裝 五、發明説明（ 同步參考時序。垂直處理器係由複數個計數除法器 (Counter divider)、脈衝宽度調變產生器（puise m〇dulation generator)、低通濾波器（L〇w fiher)、輿 積分器（Integrator)所組成，用以控制垂直偏向與產生垂 直梯度（Vertical ramp)。該同步參考時序係於不同的應用 環境下，調整OSD的顯像大小之用。 5-4圖式簡單説明： 本發明的較佳實施例將於往後之説明文字中輔以下 列圉形做更詳細的闞述： 第一圖描述習知技術中，對於類示控制系統的架構方塊 圖； 第二圈爲本發明所揭露之用於CRT顯示系统的單晶片積 禮電路，該積想電路包含一類示系统處理器； 第三A圖爲一時序圈，用以描述當水平同步信號與視訊信 號間存在一延遲之情形； 第三B圖爲一用以改變水平視訊位置之廷遲電路； 第四A圈描迷一用做電壓控制振盪器的調變電路； 第四B圖爲一波形圏，描述當不同的電容運用於第四a 圈所示之電路時，所產生之頻率變動的情形； 第五圈爲水平處理器之架構方塊圈； 第六圈爲垂直處理器之架構方塊圖； 第七圈爲一波形圏，描述垂直梯度產生器電路所產生之脈 本纸張尺度適用中國國家標準（CNS ) A4規格（210x297公釐） -----.------¾-------IT (請先閲讀背面之注意事項再填寫本頁) 五、發明説明（ A7 B7 波宽度調變輸出； 第八圈描述當不使用積分器於垂直媒电认 评及輸出之情形. 第九圈爲本發明之單晶片積想電路φ说i ’ ^ ^ Λ ^所附加之OSD架構 方塊圈；及 第十圈爲一時序圏，描述當利用八個答胳Mr_ . 個等時間區隔之方式， 來由左至右分割CRT顯示系统之類示區塊的情形。 5-5發明詳知説明： 第二闽爲本發明所揭露之用於CRT顯示系统的單晶 片積體電路，該積體電路包含一颟示系統處理器2〇，其 用於控制前潘面板23、電源27、視訊處理器22、視訊 電路26等之操作，每個單元方塊中更包含個别電路於其 中。 水平偏向電路24經由水平線圏（H〇riz〇ntaly〇ke)控制 水平偏向，並產生一脈衝飛回至顯示系統處理器2〇 ;垂 直偏向電路與顯示系统處理器20相权合，且經由垂直線 圏（Vertical yoke)控制垂直偏向。 (請先閱讀背面之注意事項再填寫本頁) 裝. -訂. 經濟部中央橾準局貝工消費合作社印裝 顯示系統處理器20結合複數個單元於一單晶片之 中，這些單元包括一數位系统控制器201、一水平處理器 203、一垂直處理器2〇4、以及一螢幕重疊顯示（〇SD)處 理器205 。數位顯示系统控制器201更包含一微處理器 (Microprocessor)、複數個暫存器（Register)、計數'器 本紙張尺度適用中國國家榡準（CNS ) A4規格（210X297公釐） 316971 A7 ______ B7_^ 五、發明説明（） (Counter)、與随機存取記憶雅（Random Access Memory, RAM)，該數位顯示系統控制器201產生控制信號以控制 CRT顯示系统的運作°例如，數位頰示系统控制器201包 括一與前端面板23相接的介面卑（interfaceport)，用以接 收使用者的輸入；一輿電源27相連的介面埠用以管理電 源之運作；一輿視訊處理器22相接的介面埠用以控制對 比（Contrast)與色彩溫度（Color temperature)之調整；以及 一與視訊電路26相連接的介面埠，用做薄示亮度之調 整。水平偏向電路24與垂直偏向電路25同樣受控於顯示 系统控制器201，用以控制大小與線性性質（Linearity)的 控制。 水平處理器203更包含一相位閉鎖迴围（phase L〇ck Loop, PLL)單元，用於比較水平同步信號與由水平偏向電 路所回授之信號21，以使CRT所顯示的影像能穩定於其 螢幕之上。 經濟部中央樣準局員工消费合作社印装 (請先閱讀背面之注意事項再填寫本頁) 第三A圈爲一時序圈，用以描述當水平同步信號與視 訊信號間存在一延遲之情形。當水平同步信號HSync發生 一微小之延遲（如第三A圖中的Tl)時，其將使CRT所顯 不的影像偏向螢暮的左方；若水平同步信號Hsync發生— 大量延遲（如第三A國中的T2)時，其將使CRT所顯示的 影像偏向螢幕的右方。第三B圈爲一用以消除上述之水平 移位之延遲電路，此電路係將數位延遲電路（Digital delay 本紙張尺纽财( 210X297^« ) A7 £7_ 五、發明説明（） line)31之輸出送往PLL 32之中，顯示系統處理器20可藉 由控制該延遲電路之延遲時間，來達到控制顯示影像位置 的目的》 一較詳盡的水平處理器203的内部架構方塊圈描述 於第五圈中，該水平處理器2〇3係由控制水平相位的數位 延遲電路 501 、PLL 單元 50 與 51 、一 VCO(Voltage、 1T This paper scale is applicable to China National Standard (CNS) A4 specification (210X297mm) 316971 A7 B7 Printed by Beigong Consumer Cooperative of Central Bureau of Standards, Ministry of Economic Affairs V. Invention description () As for labor screen weight 4 display (〇nScreenDisplay, OSD ), It also needs an independent integrated circuit to generate the required video information. The digital display system controller must communicate with the OSD chip to obtain the location of the video content and the video information. The first circle describes a block diagram of a conventional frequency display control system. The circle includes a display system controller (L01), control front panel (Control panel) 107, power supply 108, and video processing. 106, video circuit 111, screen overlay display (〇SD) processor 105, vertical processor (Vertical processor) 104, and horizontal processor (Horizontal processor) 103, each unit block still contains individual circuits in it , The horizontal deflection circuit 109 controls the horizontal deflection through a horizontal yoke, and generates a return pulse (Flyback pulse) to the horizontal processor 103; the vertical deflection consumed by the vertical processor 104 The circuit 1 1 〇 controls the vertical deflection via a vertical coil. In the conventional technology, for the bias control, the generation of OSD, and the digital display pi system controller, an independent integrated circuit is required. Because the manufacturing process of these circuits has its specific requirements, there is currently no combination of the above-mentioned bias control, the generation of 〇SD, and the digital display system controller in a single-chip product based on commercial and cost considerations. It is necessary to combine the bias control, the generation of OSD, and the digital display system controller in a single chip. (Please read the precautions on the back before filling in this page) Packing. The size of the printed paper is applicable. 316971 Printed by the Central Standards Bureau of the Ministry of Economic Affairs Beigong Consumer Cooperative A7 B7 5. Description of the invention () 5-3 Purpose of the invention and summary: In the background of the above-mentioned invention, in the prior art, the bias control, the generation of OSD, and the digital display system controller are separated into several independent chips, and this is not cost-effective. The present invention proposes to address this shortcoming In an improved way, the above-mentioned bias control 'generation of SD and digital display system controller are combined into a single chip, which has the characteristics of low power consumption to reduce system compensation. Another object of the present invention is to use a phase lock loop (Phase Lock Loop, PLL) to control the bias mode to establish a display system controller, display phase adjustment (Display phase adjustment), size adjustment (Size adjustment), and linear Calibration (Linearity adjustment), etc. can be done using the single chip. A further object of the present invention is to provide a synchronous reference timing, which can be used for the generation of OSD video information and the control of video blank output. According to the above purpose, the present invention provides a single chip, which includes a display system controller, a horizontal processor, a vertical processor, and an optional OSD processor. The display system controller controls the horizontal processor and the vertical processor And the action of the OSD processor. The horizontal processor further includes a phase-locked loop circuit (PLL) to control the horizontal deviation and to produce the paper size applicable to China National Standard (CNS) Α4 specification (210X297 mm) (please read the precautions on the back first (Fill in this page) * Ί ». Packing. Ordering ^ 16971 A7 B7 Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of invention (synchronous reference timing. The vertical processor is composed of a number of counter dividers, The pulse width modulation generator (puise modulation generator), low pass filter (Low fiher), and integrator (Integrator) are used to control the vertical deviation and generate a vertical gradient (Vertical ramp). The synchronization The reference timing is used to adjust the display size of the OSD in different application environments. 5-4 Brief description of the diagram: The preferred embodiment of the present invention will be supplemented by the following pictograms in the following description text for more details The description of the following: The first figure describes the block diagram of the architecture of the analog control system in the conventional technology; the second circle is the single-chip accumulation circuit for the CRT display system disclosed by the present invention. Imagine that the circuit includes a type of system processor; the third diagram A is a timing circle to describe the situation when there is a delay between the horizontal synchronization signal and the video signal; the third diagram B is a delay to change the horizontal video position Circuit; the fourth circle A depicts a modulation circuit used as a voltage-controlled oscillator; the fourth diagram B is a waveform coil describing the different capacitors used in the circuit shown in the fourth circle a The frequency changes; the fifth circle is the architecture block circle of the horizontal processor; the sixth circle is the architecture block diagram of the vertical processor; the seventh circle is a waveform ring, describing the pulse paper generated by the vertical gradient generator circuit The standard is applicable to the Chinese National Standard (CNS) A4 specification (210x297mm) -----.------ ¾ ------- IT (please read the precautions on the back before filling this page) 2. Description of the invention (A7 B7 wave width modulation output; the eighth circle describes the situation when the integrator is not used in the vertical dielectric evaluation and output. The ninth circle is the single-chip integrated circuit of the invention. Φ said i ^ ^ Λ ^ The attached OSD architecture block circle; and the tenth circle is a timing ring, describing When using eight answer Mr_. Equal time intervals to divide the display block of the CRT display system from left to right. 5-5 Detailed description of the invention: Second Min is the disclosure of the invention A single-chip integrated circuit for a CRT display system. The integrated circuit includes a display system processor 20, which is used to control the operation of the front panel 23, power supply 27, video processor 22, video circuit 26, etc. Each unit block contains individual circuits in it. The horizontal deflection circuit 24 controls the horizontal deflection via a horizontal coil (Horizontaloke) and generates a pulse to fly back to the display system processor 2; the vertical deflection circuit It is combined with the display system processor 20, and the vertical deflection is controlled via a vertical yoke. (Please read the precautions on the back before filling out this page). Install.-Order. The processor 20 of the Ministry of Economic Affairs, Central Bureau of Industry and Commerce, Pongong Consumer Cooperative Printed Display System processor 20 combines multiple units into a single chip, these units include a The digital system controller 201, a horizontal processor 203, a vertical processor 204, and a screen overlay display (〇SD) processor 205. The digital display system controller 201 further includes a microprocessor, a plurality of registers, and a counter. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 316971 A7 ______ B7_ ^ 5. Description of the invention () (Counter) and Random Access Memory (RAM), the digital display system controller 201 generates control signals to control the operation of the CRT display system ° For example, digital cheek display system The controller 201 includes an interface port connected to the front panel 23 for receiving user input; an interface port connected to the power supply 27 for managing the operation of the power supply; and a video processor 22 connected to the The interface port is used to control the adjustment of contrast and color temperature; and an interface port connected to the video circuit 26 is used to adjust the brightness of the thin display. The horizontal deflection circuit 24 and the vertical deflection circuit 25 are also controlled by the display system controller 201 to control the size and linearity. The horizontal processor 203 further includes a phase loop loop (PLL) unit for comparing the horizontal synchronization signal and the signal 21 fed back by the horizontal deflection circuit, so that the image displayed by the CRT can be stabilized at On its screen. Printed by the Employees' Consumer Cooperative of the Central Bureau of Samples of the Ministry of Economic Affairs (please read the precautions on the back before filling in this page). The third circle is a timing circle to describe the situation when there is a delay between the horizontal synchronization signal and the video signal. When there is a slight delay in the horizontal sync signal HSync (such as Tl in the third diagram A), it will deflect the image displayed by the CRT to the left of the fluorescent twilight; if the horizontal sync signal Hsync occurs-a large delay (such as the first) In the case of T2) in country A, it will deflect the image displayed by the CRT to the right of the screen. The third circle B is a delay circuit to eliminate the horizontal shift mentioned above. This circuit is a digital delay circuit (Digital delay (Paper delay) (210X297 ^ «) A7 £ 7_ V. Invention description () line) 31 The output is sent to the PLL 32. The display system processor 20 can control the position of the displayed image by controlling the delay time of the delay circuit. A more detailed description of the internal structure of the horizontal processor 203 In five laps, the horizontal processor 202 is composed of a digital delay circuit 501 that controls the horizontal phase, PLL units 50 and 51, and a VCO (Voltage
Controlled Oscillator, VCO)調變範圍選擇控制器（VCO tuning range select)、以及一計數-除法器511所組成。 PLL 50包含一栢位比較器502，用以比較HSync與水 平回授信號21之相位，在產生其差値（Difference)時，先 輸入至低通滅波器（Low pass filter)503做處理後，再迭往 電塵·控制震盪器（VCO)504之中，電壓控制震盪器504的 輸出被堪動器（Driver)505所放大並鎮住其相位。pll 5〇 之輸出被送往水平偏向電路24做更進一步之放大，以產 生一適合於水平偏向線圈的梯度信號。 經濟部中央樣準局貝工消費合作社印製 1-— I ........I— y ί - Ji -ϊι1*^-.·- —---- · - I · I ---. 03-* (請先閲讀背面之注意事項再填寫本買) PLL 50之輸出亦被送往PLL51之中，而PLL50係由 相位比較器507、低通濾波器508、VCO 509、與—堪動 器510所組成，一計數·除法器511在VC0 509的之輸出 送至相位比較器507之前，利用VCO 509的頻率產生一更 高頻的SCLK。因爲計數-除法器511的輸出與HSync同步， 所以VC0 509的頻率亦與水平電路同步，只不過其頻率 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）Controlled Oscillator (VCO) modulation range selection controller (VCO tuning range select), and a count-divider 511. The PLL 50 includes a comparator 502 for comparing the phases of the HSync and the horizontal feedback signal 21, and when the difference is generated, it is first input to a low pass filter 503 for processing Then, it goes to the dust-controlled oscillator (VCO) 504, and the output of the voltage-controlled oscillator 504 is amplified by the driver 505 and its phase is suppressed. The output of pll 50 is sent to the horizontal deflection circuit 24 for further amplification to generate a gradient signal suitable for the horizontal deflection coil. Printed by Beigong Consumer Cooperative of the Central Bureau of Samples of the Ministry of Economic Affairs 1-— I ........ I— y ί-Ji -ϊι1 * ^-. ·-—---- ·-I · I- -. 03- * (Please read the precautions on the back before filling in the purchase) The output of PLL 50 is also sent to PLL51, and PLL50 is composed of phase comparator 507, low-pass filter 508, VCO 509, and- Composed of the actuator 510, a count divider 511 uses the frequency of the VCO 509 to generate a higher frequency SCLK before the output of the VC0 509 is sent to the phase comparator 507. Because the output of the counter-divider 511 is synchronized with HSync, the frequency of VC0 509 is also synchronized with the horizontal circuit, but its frequency. This paper standard is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm)
經濟部中央揉準局貝工消費合作社印$L A7 _______ B7 五、發明説明（） 爲計數-除法器511中設定値的倍數而已。舉例來説，若 計數-除法器511被設定爲1024,則將SCLK爲HSync的1024 倍；又若計數-除法器511被設定爲512,則將SCLK爲HSync 的5 12倍，此高頻之SCLK更可用於視訊應用的像素時序 (Pixel clock)之中。 利用該高頻水平同步信號時序SCLK，一驅動器電路可 據以產生一倍數於水平同步信號的時序，以第十圏爲例， 其描述當利用八個等時間區隔之方式，來由左至右分割 CRT顯示系統之顯示區塊的情形。該時間區隔替類比輸出 開放一溝通管道，而該類比輸出係經由一同個電路板之脈 波寬度調變方式（Pulse Width Modulation，PWM)，或另一 個電路板類比方式所產生。上述之時間區隔波形輸出，或 先經由低通濾波器之處理，可用於CRT顯示系統在水平 方向之幾何（Geometry)校準、色彩測定（Colorimetry)較 準、收歛度（Convergence)校準、或色彩純度性質（purity attributes)之上。例如，水平線性校正可利用該時間區隔 之波形輸出而達成，不再需要昂贵的類比電路來產生類似 之波形輸出， 在電子槍飛回之時亦需要視訊空白信號（video blanking signal)以增進顯示效果，該視訊空白信號可藉由 高頻之sCLK時序，將其送往第五囷中的計數-除法器512 中而產生，而該計數-除法器512可利用驅動器505之輸 本紙張尺度適用令國國家標準（CNS )八4規格（210X297公釐） (請先聞讀背面之注意事項再填寫本頁) 、裝. 訂 經濟部中央標準局員工消費合作社印製 316971 A7 ____—_ B7 __ 五、發明説明（） 出獲得重置（Reset)，該水平空白信號之脈波寬度則受控 於顯示系统控制器201，吾人可利用程式瑪來控制該脈波 宽度。 VCO調變範困選擇控制器（往後以“VCO調變電路”簡 稱之）5〇6之目的係於加大PLL的水平震盪頻率範園之 用，該VCO之調變同樣受控於顯示系統控制器201 » PLL 電路鎖定後的調變範圍，通常被侷限於VCO調變中心頻 率附近範团中，從事極小的範团的調變，此種情形需要加 以改進》 更詳盡的VCO調變電路506描繪於第四A圖中，其包 括一 PLL震盪電路41與一調變用的RC網路所組成。PLL 震盪電路41更包含一比較器411、一缓衝器412、一金 屬氧化物半’導雜電晶趙（Metal Oxide Semiconductor transistor, MOS transistor)4 1 3 ； RC 網路則包含一電阻 401、用作切換開關的MOS電晶體402、403、404，以 及電容 405、406、407、408。 電阻401將比較器411的正相輸入端拉至高電位，甚 至超過RC迴路所決定的時間常數，因此當比較器的輸入 超過參考電廢Vref時，比較器411的輪出端電塵_亦將被拉 至高電位，使得緩衝器412亦被拉至高電位，再經由M〇s 電晶體413將比較器411的正相輸入端放電；當正相輪入 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) -裝- 訂 經濟部中央標隼局員工消費合作社印装 A7 _______B7 五、發明説明（） 端的電壓低於參考電恩Vrcf時，比較器411的輸出端電恩 亦降至低電位，而MOS嘗晶體413被關閉，以使RC網路 能再次提昇電塵。上述之情形持續進行，於是便產生第四 B 所示的蘇兹波（Sawtooth waveform)。 第四B圈描繪出一些基於調變頻率之不同而改變的 震盪波形。曲線I描績·當RC網路中，只運用電阻401與電 容408的情形，而當PLL震盪電路41開始運作後，即產 生曲線II所描繪之波形；同樣的，曲線ΠΙ描繪當MOS電 晶體402、403、404皆被打開，以使電容405、406、 407、408皆同時被使用所產生的波形。經由MOS電晶雄 402、403、404的切換動作，不同電容値的電容405、 406、407、408可輿電阻401相接，進而改變重壓控制 震盪器的調變頻率。於是加大後的PLL操作頻率，便可 視CRT顯示系統的水平輿垂直頻率之需求而調整。 第六圈爲垂直處理器204之内部架構方塊圖，其包含 計數·除法器601、602、603、與605，一延遲計數-除 法器604，以及一脈波寬度調變（pulse Width Modulation， PWM)產生器。計數-除法器601降低高頻時序SCLk的頻 率，使其成爲HSync類率的兩倍，這個信號將成爲計數-除法器603與605，以及廷遲計數-除法器604的同步時 序。因爲在交錯式（Interlaced)择描方式之下，VSync將於 HSync時序的一半時間中到達，所以VSync必須爲水平時 本紙張尺度適用中國國家標準（CNS ) A4規格（210x29*7公董〉 .-----袭------、訂------1 (請先閱讀背面之注意事項再填寫本頁) — — A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（ 序的兩倍（或更高）。垂直延遲電路的架構類似於第三B圈 所示的水平廷遲電路。 VSync亦被用於重置計數_除法器以控制Pwm產生器 602 ’ PWM產生器602的輸出被低通濾波器606所處理、 轉換爲類比型態後，再送往積分器607用以產生垂直偏向 電路25所需的梯度信號。VSync同時重置計數-除法器 605用以產生視訊空白信號，其寬度亦受控於顯示系統控 制器201。 VSync亦可運用在重置附加的積分器607以終結垂直 梯度信號，並確定在垂直飛回之後，垂直梯度信號會起始 於同一個電壓位準。頰示系統控制器201可對計數·除法 器601、603、6〇4與605從事存取的動作，以改變儲存 於其中的内容；顯示系統控制器201亦可存取PWM產生 器的内容’以改變腺波宽度調整的内容。顯示系統控制器 201亦可利用程式控制碼，來計數-除法器603以產生可用 於線性校準的可程式化的時間延遲脈波。 第七圈描繪由積分器607輸出端所獲得的垂直梯 度。VSync係用於重置積分器的輸出，其將於一時間週期 之後，將積分器607之輸出放電至低電位。在時間Tl中， 顯示系统控制器201載入一 PWM値至PWM產生器602， 而積分器607將產生一積分波形；在時間Τ'2中，顯示系 13 衣紙張尺度適用中國國家標準（CNS ) Α4規格（2Ι〇Χ：297公釐） . , ^、裝------訂------^T (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消费合作社印裝 kl B7 五、發明説明（） 统控制器201載入一不同的PWM値至PWM產生器602， 猜分器60 7將產生不同的猜分波形。藉著改變垂直样度的 斜率，垂直揮除比例（Vertical sweep rate)或垂直線性性質 (Verticallinearity)將被改變。此外，顯示系统控制器20 1 可以經由時間延遲之設定與產生符合規格的PWM，來調 整垂直線性性質。 第八圈描述當不使用積分器之時，垂直梯度電路所輸 出的波形。類似銀兹狀（Jagged)的波形輪出爲數位類比轉 換器（Digital to Analog Converter, DAC)的直接輸出，其 爲數位數値在呰微改變時所形成喑梯型波形，即使透過低 通濾波器之處理以去除高頻的鋸齒波，在低頻部份的鋸齒 波卻依然存在；若欲使用一低通濾波器以除去低頻部份之 鋸齒波，又會引起極嚴重的高頻失眞，一利用數位方式的 解決方法，係利用增加解析度的方式來減少該鋸齒波的大 小。將然而這種方法卻需要爲數極多的DACs，而且需要 大量的記憶空間以儲存波形資訊，而這兩個缺點卻會增加 1C的造償。但如第六囷所示，利用積分器607連接於DAC 之後，所獲得的梯度波形將十分平滑，而且所需要的DAC 數量與記憶空間皆不多，因此得以大量降低1C的造價。 如第六圈所示之產生垂直梯度的電路，其可產生任意 波形輿週期的脈波’就如同前述的水平同步镇率，以及其 同步但頻率爲其倍數之脈波一般。所產生的抛物校正波形 14 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） -----.-----(裝------訂-------k (請先閲讀背面之注意事項再填寫本頁) 316971 A7 _B7 __ 五、發明説明（） 可用於頻示針塾失眞（Pincushion)校準，垂直偏向處理器 亦可硬體來取代，唯一的差别在襄示系統控制器2〇1需下 載（Download)該針垫失眞校準値至PWM產生器6〇2，以 及不同的時間失效（Lapse)資訊於計數-除法器603之中， 此電路之輸出埃輿水平大小調整電路相接以從事針整失 眞校準。經由相同的電路，可產生焦距抛物校準波形作爲 焦距一致性（Uniform focus)之校準；亦可產生亮度校準抛 物波以作爲亮度一致性（Brightness uniformity)校準之 用，其他的CRT參數校準亦可用同樣的方式獲得校準。 第九圖描述在本發明之單晶片積體電路中，所附加之 OSD内部架構方塊圈’基本的單元有延遲電路9〇2，圈像 記憶 St (Graphic memory)903、904、905，串列輪出器 (Serializer)906、907、908，以及 DACs 909、910、 911。顯示系統控制器201可基於微處理器韌體之需求， 或前碟面板之輸入’對圈像記德禮903、904、輿905填 入圖樣或文字資訊（分别處理紅（Red)、綠（Green)、藍（Blue) 三個頻宽（Channel)之視訊資訊），而圖像記憶體903 、 9〇4、與9〇5的内容値，接著利用串列輸出器906、907、 經濟部中央標準局貝工消費合作社印装 (請先閱讀背面之注意事項再填寫本頁) 9 08，輿SCLK同步高頻時序9〇1形成串列輸出。串列輸出 器9 06、90 7、908的功用，在於將儲存於圈像記憶禮 903、904、與905的平行輸出的圈樣資訊轉換成像素資 料’並輸入至DACs 909、910、911以轉換成類比視訊 資訊。 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐） 經濟部中央標準局貝工消費合作社印製 A7 B7 五、發明説明（) 對於低償位的應用而言，因爲使用顏色上的限制，其 並不需要DACs 909、910、9U ’串列輸出资訊亦直接 被輸出，每個顏色亦僅包含開啓與關閉之狀態，故全部只 需要八種顏色（包括Black)。串列輸出器9〇6、9〇7、9〇8 亦可輸入HSync與VSync以獲知開啓之時間；延遲電路 902輸入HSync輿VSync以改變〇SD視訊資料的位置；藉 由改變高頻之像素時序，其將可改變〇SD視訊資料的顯 示大小；高頻的像素時序亦可經由改變計數-除珐器511 的除數，以輕易的獲得修正。因爲像素時序輿顯示時序同 步，視訊資訊可與CRT顯示系统標準的視訊輸出合併或 重疊，所以可達到穩定OSD類示之目的。 此外，上述所有的應用可於彩色監視器，、單色監視 器、電膝彩色終端機、電腦單色终端機、電視機、高解析 度電視機、以及内含監視器之電腦（m〇niputer)等系統之 中，多媒體顯示系統，輿上述系統的衍生產品亦包含在 内。 縱合以上所述，本發明所揭露之靳穎電路，將水平處 理器、垂直處理器、與顯示系統處理器結合於一單一晶片 中’主要使用一數位電路與部份之PLL類比電路來完成。 類示影像的同步性、位置與大小，或是線性與針垫失眞的 校準亦可輕易達成，視訊空白電路亦十分輕易地整合於其 中’透過VCO調變範圓選擇控制器，PLL的有效範圍^ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ---------.裝— (請先閱讀背面之注意事項再填寫本頁) 訂 A7 B7 五、發明説明（） 明顯的加大，以涵括更多的時序需求，OSD亦可選擇性 的加入於該新穎電路之中。 之 明圍 發範. 本利 爲專 僅請 述申 所之 上明 以發 本 定 已 而 例 施 實 佳 較 它 其 凡 飾 修 或 變 改 效 等 之 成。 完内 所圍 下範 神利 精專 本 離 脱 未均 限之 以示 用揭 非所 並明 發 請 中 之 述 下 在 含 包 應 (請先閱讀背面之注意事項再填寫本頁) •裝. 訂 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐）Printed by the Ministry of Economic Affairs of the Central Bureau of Economics and Technology Co., Ltd. Peking Consumer Co., Ltd. $ L A7 _______ B7 V. Description of invention () It is a multiple of the value set in the counter-divider 511. For example, if the count-divider 511 is set to 1024, then SCLK is set to 1024 times HSync; and if the count-divider 511 is set to 512, then SCLK is set to 5 12 times HSync, this high frequency SCLK can also be used in pixel timing for video applications. Using the high-frequency horizontal synchronization signal timing SCLK, a driver circuit can generate a multiple of the timing of the horizontal synchronization signal. Taking the tenth ring as an example, it describes when eight equal time intervals are used, from left to right. The right splits the display block of the CRT display system. The time interval opens up a communication channel for the analog output, and the analog output is generated by Pulse Width Modulation (PWM) on the same circuit board or another circuit board analog method. The above time-divided waveform output, or first processed by a low-pass filter, can be used for horizontal Geometry calibration, colorimetry calibration, Convergence calibration, or color of the CRT display system Above purity attributes. For example, horizontal linearity correction can be achieved using the waveform output at this time interval. No expensive analog circuits are needed to generate a similar waveform output. A video blanking signal is also required to improve the display when the electron gun flies back As a result, the video blank signal can be generated by sending the high-frequency sCLK timing to the count-divider 512 in the fifth channel, and the count-divider 512 can be adapted to the input paper size of the driver 505. Linguo National Standard (CNS) 84 specifications (210X297mm) (please read the notes on the back before filling in this page), install. Printed by the Ministry of Economic Affairs Central Standards Bureau employee consumer cooperative printed 316971 A7 ____—_ B7 __ V. Description of the invention () When the reset is obtained, the pulse width of the horizontal blank signal is controlled by the display system controller 201. We can use the program to control the pulse width. The purpose of the VCO modulation range selection controller (hereinafter referred to as "VCO modulation circuit") is for the purpose of increasing the horizontal oscillation frequency range of the PLL. The modulation of the VCO is also controlled by Display system controller 201 »The modulation range after the PLL circuit is locked is usually limited to the model group near the center frequency of the VCO modulation. It is engaged in the modulation of a very small model group. This situation needs to be improved. More detailed VCO modulation The transformation circuit 506 is depicted in the fourth diagram A, which includes a PLL oscillation circuit 41 and an RC network for modulation. The PLL oscillator circuit 41 further includes a comparator 411, a buffer 412, and a metal oxide semiconductor transistor (MOS transistor) 4 1 3; the RC network includes a resistor 401, MOS transistors 402, 403, 404 used as changeover switches, and capacitors 405, 406, 407, 408. The resistor 401 pulls the non-inverting input of the comparator 411 to a high potential, even exceeding the time constant determined by the RC loop. Therefore, when the input of the comparator exceeds the reference waste Vref, the dust at the wheel-out end of the comparator 411 will also It is pulled to a high potential, so that the buffer 412 is also pulled to a high potential, and then the positive phase input terminal of the comparator 411 is discharged through the Mos transistor 413; when the positive phase turns into this paper standard, the Chinese National Standard (CNS) A4 specification is applied (210X297mm) (Please read the precautions on the back before filling in this page)-Binding-Order A7 _______B7 printed by the Central Consumer Falcon Bureau of the Ministry of Economic Affairs A. _______B7 V. Description of invention () When the voltage at the terminal is lower than the reference DV Vrcf At the output of the comparator 411, the electrical current also drops to a low level, and the MOS transistor 413 is turned off, so that the RC network can raise the dust again. The above situation continues, and the Sawtooth waveform shown in the fourth B is generated. The fourth circle B depicts some oscillation waveforms that change based on the modulation frequency. Curve I depicts the case where only the resistor 401 and the capacitor 408 are used in the RC network, and when the PLL oscillation circuit 41 starts to operate, the waveform depicted by the curve II is generated; similarly, the curve III depicts the MOS transistor 402, 403, and 404 are all turned on so that the waveforms generated by capacitors 405, 406, 407, and 408 are all used at the same time. Through the switching operation of the MOS transistors 402, 403, and 404, the capacitors 405, 406, 407, and 408 of different capacitance values can be connected to the resistor 401, thereby changing the modulation frequency of the heavy voltage control oscillator. Therefore, the increased PLL operating frequency can be adjusted according to the horizontal and vertical frequency requirements of the CRT display system. The sixth circle is a block diagram of the internal architecture of the vertical processor 204, which includes counter-dividers 601, 602, 603, and 605, a delay counter-divider 604, and a pulse width modulation (PWM) ) Generator. The counter-divider 601 reduces the frequency of the high-frequency timing SCLk to twice the HSync class rate, and this signal will become the synchronization timing of the counter-dividers 603 and 605, and the late counter-divider 604. Because under the interlaced selection mode, VSync will arrive in half of the time of HSync sequence, so when VSync must be horizontal, the paper scale applies the Chinese National Standard (CNS) A4 specification (210x29 * 7 public directors). ----- Attack ------, Order ------ 1 (please read the notes on the back before filling out this page) — — A7 B7 Printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Description of the invention (twice the order (or higher). The vertical delay circuit has a structure similar to the horizontal delay circuit shown in the third circle B. VSync is also used to reset the counter_divider to control the Pwm generator 602 ' The output of the PWM generator 602 is processed by the low-pass filter 606 and converted into an analog form, and then sent to the integrator 607 to generate the gradient signal required by the vertical deflection circuit 25. VSync also resets the counter-divider 605 It is used to generate the video blank signal, and its width is also controlled by the display system controller 201. VSync can also be used to reset the additional integrator 607 to terminate the vertical gradient signal, and to determine that the vertical gradient signal will start after flying back vertically Start at the same voltage level The buccal display system controller 201 can perform access operations on the counter · dividers 601, 603, 604, and 605 to change the content stored therein; the display system controller 201 can also access the content of the PWM generator 'To change the content of glandular wave width adjustment. The display system controller 201 can also use a program control code to count-divider 603 to generate a programmable time-delay pulse wave that can be used for linear calibration. The seventh circle depicts the integral The vertical gradient obtained at the output of the integrator 607. VSync is used to reset the output of the integrator, which will discharge the output of the integrator 607 to a low potential after a period of time. At time T1, the system controller 201 is displayed Load a PWM value to the PWM generator 602, and the integrator 607 will generate an integrated waveform; at time T'2, the display system is based on 13 clothing paper standards applicable to the Chinese National Standard (CNS) Α4 specification (2Ι〇Χ: 297 Ali)., ^, Install ------ order ------ ^ T (please read the notes on the back before filling this page) Printed kl B7 by Beigong Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs Description of the invention The PWM value to the PWM generator 602, the guesser 607 will generate different guess waveforms. By changing the slope of the vertical sample, the vertical sweep rate (Vertical sweep rate) or vertical linearity (Verticallinearity) will be changed In addition, the display system controller 20 1 can adjust the vertical linearity property by setting the time delay and generating a PWM that meets the specifications. The eighth circle describes the waveform output by the vertical gradient circuit when the integrator is not used. The Jagged-like waveform is rounded out to the direct output of the Digital to Analog Converter (DAC), which is a trapezoidal waveform formed when the digital value changes slightly, even through low-pass filtering To remove the high-frequency sawtooth wave, but the low-frequency sawtooth wave still exists; if you want to use a low-pass filter to remove the low-frequency sawtooth wave, it will cause very serious high-frequency loss A solution using a digital method is to increase the resolution to reduce the size of the sawtooth wave. However, this method requires a large number of DACs and a large amount of memory space to store waveform information. These two shortcomings will increase the compensation of 1C. However, as shown in the sixth example, after the integrator 607 is connected to the DAC, the gradient waveform obtained will be very smooth, and the number of DACs and memory space required are not many, so the cost of 1C can be greatly reduced. As shown in the sixth circle, a circuit that generates a vertical gradient can generate a pulse wave of arbitrary waveform and period 'just like the aforementioned horizontal synchronized township, and its synchronized pulse wave with a frequency that is a multiple of it. The generated parabolic correction waveform 14 This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210x297 mm) -----.----- (installed ------ ordered ------ -k (Please read the precautions on the back before filling in this page) 316971 A7 _B7 __ V. Description of invention () Can be used for frequency pin calibration (Pincushion) calibration, vertical deviation processor can also be replaced by hardware, only The difference is that in the display system controller 201, the pin pad missing calibration value needs to be downloaded to the PWM generator 6〇2, and different time-lapse (Lapse) information is included in the counter-divider 603. The output of the circuit is connected to the horizontal size adjustment circuit to perform needle alignment correction. Through the same circuit, a parabolic calibration waveform of the focal length can be generated as the calibration of the focus consistency (Uniform focus); a parabolic wave of brightness calibration can also be generated as Brightness uniformity (Brightness uniformity) calibration, other CRT parameter calibration can also be calibrated in the same way. The ninth figure describes the single-chip integrated circuit of the present invention, the attached OSD internal architecture block circle 'basic Unit has delayed power 902, circle memory St (Graphic memory) 903, 904, 905, serializers 906, 907, 908, and DACs 909, 910, 911. The display system controller 201 may be based on a microprocessor The requirements of the firmware, or the input of the front disc panel, fill in the pattern or text information of the circle image Deli 903, 904, and 905 (respectively deal with the three frequencies of Red, Green, and Blue) Wide (Channel) video information), and the content values of the image memory 903, 904, and 905, then printed using serial output devices 906, 907, Beigong Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs ( Please read the precautions on the back before filling this page) 9 08, SCLK synchronizes the high frequency timing 9〇1 to form a serial output. The function of the serial output device 9 06, 90 7, 908 is to store it in the circle image memory Li 903, 904, and 905 parallel output circle-like information is converted into pixel data 'and input to DACs 909, 910, 911 to be converted into analog video information. This paper scale is applicable to China National Standard Falcon (CNS) A4 specification (210X297 Mm) A7 B printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 7 5. Description of the invention () For low-paying applications, because of the limitation of the use of color, it does not require DACs 909, 910, 9U 'serial output information is also directly output, and each color only contains Open and closed state, so all only need eight colors (including Black). The serial output devices 9〇6, 9〇7, 9〇8 can also input HSync and VSync to know the opening time; the delay circuit 902 inputs HSync and VSync to change the position of 〇SD video data; by changing the high frequency pixels Timing, which can change the display size of the SD video data; high-frequency pixel timing can also be easily corrected by changing the divisor of the counter-divider 511. Because the pixel timing and display timing are synchronized, the video information can be merged or overlapped with the standard video output of the CRT display system, so the purpose of stabilizing the OSD display can be achieved. In addition, all the above-mentioned applications can be applied to color monitors, monochrome monitors, electric knee color terminals, computer monochrome terminals, televisions, high-resolution televisions, and computers with monitors (m〇niputer ) And other systems, multimedia display systems, and derivatives of these systems are also included. In view of the above, the Jin Ying circuit disclosed in the present invention combines a horizontal processor, a vertical processor, and a display system processor in a single chip, which is mainly completed by a digital circuit and some PLL analog circuits . The calibration of image synchronization, position and size, or the calibration of linearity and pin pad miss can also be easily achieved, and the video blank circuit is also very easy to integrate into it Scope ^ This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) ---------. Packing-(please read the precautions on the back before filling this page) Order A7 B7 V. Invention Explanation () is obviously increased to cover more timing requirements, OSD can also be selectively added to the novel circuit. The Mingwei issue model. Benevolence is only for the purpose of making a statement, and it is better to use the original version to exemplify it than to perform other modifications or changes. After the end of the encirclement, the Fan Shenli essence is not limited to the use of the book, and it is not used for disclosure. It is clearly stated in the request, and the package should be included (please read the precautions on the back before filling out this page). The size of the paper printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs is applicable to the Chinese National Standard (CNS) Α4 specification (210X297 mm)