TW313698B - Read only memory structure and manufacturing method thereof - Google Patents

Abstract

A read only memory structure comprises of: (1) one substrate whose surface has one first insulating layer; (2) one grid-arranged semiconductor layer, which is formed on the first insulating layer, and divided into bit line separated in parallel along first direction, channel region separated in parallel along second direction which is perpendicular to the first direction and connecting each bit line, and one grid gap between the bit line and channel region;(3) one second insulating layer, filling those grid gaps; (4) one third insulating layer, formed on the above each layer surface; (5) one conductive layer, formed on the third insulating layer, and etched to multiple conductive lines separated in parallel along the second direction, in which the multiple conductive lines position overlap those channel regions.

Description

3136 m 1TWF / CHOU / 001 A7 B7 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of the invention (1) The present invention relates to a read-only memory structure and its manufacturing method, and in particular relates to an amorphous Silicon read-only memory structure and its manufacturing method. Read-only memory has been widely used in digital devices such as minicomputers and microprocessor systems. It can be used to store some system data, such as BIOS and other resident programs. Because the manufacturing process of read-only memory (ROM for short) is very complicated and requires many time-consuming steps and material processing, customers usually first hand the program data to the memory manufacturing factory, and then the factory encodes it in the ROM Made in China. Most of the ROM components have the same structure except that the data stored in the programming stage is different. Therefore, the read-only memory can be made to the step before programming and the unprogrammed semi-finished product can be stored in stock After the customer sends an order for a specific program, the mask can be quickly made for programming and then shipped to the customer, so the above-mentioned post-programmed mask-type read-only memory has become a common method in the industry. Commonly used read-only memory systems use channel transistors as memory cells, and in the programming stage, selectively implant impurities into designated channel regions to achieve control by changing the threshold voltage The purpose of turning on (ON) or turning off (OFF) the memory unit. Among them, the structure of the read-only memory, the polycrystalline silicon word line WL (Word Line) crosses the bit line BL (Bit Line), the channel of the memory cell is formed under the word line WL, and the bit The area between the element lines BL. The read-only memory uses channel ion implantation or not to store second-order bit data "^ \ / X 〇3 (please read the notes on the back. ^ Before filling out this page) --- order.- ^ n! This paper scale is applicable to the Central Circle Falcon (CNS) A4 specification (210X297mm) 1TWF / CHOU / 001 Α7 Β7 Ministry of Economic Affairs Central Standards Bureau Bei X Consumer Cooperative Seal 5. Invention description (>) Please refer to FIG. 1 is a partial equivalent circuit diagram of a conventional mask-only mnemonic body 10, which includes the word bit lines WL arranged in a parallel array and the bits arranged in a parallel array Line BL. The data stored after the mask read-only memory 10 is programmed is determined by selecting the memory cells located at the interleaved positions of the word line WL and the bit line BL, for example, by using these at the interleaved positions The upper memory cell has different combinations of threshold voltages to achieve the purpose of storing data. Among them, the transistor 12 located at the interlaced position of the bit line BL0 and the word line WL0 is formed to have a relatively low Starting voltage, and logically "0" or "ON" The data is stored in the transistor I2, or the data "1" or "OFF" is formed by forming the transistor 14 at the interlaced position of the word line WL0 and the bit line BL2 with a relatively high starting voltage "Is stored in the transistor 14. The way of reading the data is to apply a specific potential to the bit line and the word line corresponding to the memory cell position of the data to be read, and measure the Whether the current of the bit line changes to determine whether the transistor that constitutes the memory cell has a low starting voltage. For example, select a transistor location with a low starting voltage, such as 12, for the gate of the transistor ( Connected to the word line) and the drain (connected to the bit line) are applied to a specific potential to turn on the transistor, then the memory cell can be known according to the measured current on the bit line The stored data is logically "O," or "ON". Similarly, in this example, 'if the memory cell is composed of a transistor with a high initial voltage such as 14, the special potential applied to its gate' will not make the transistor conductive, so It can be seen that the stored data is a 4-button new standard (CNS) M brain_ (210X297 male thin) ~~~ --- ~~ (please read the precautions on the back before filling this page)

， 1Τ .ς 0631TWF / CHOU / 001 A7 B7 Printed by the Employees ’Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs V. Description of Invention (彡)“ 1 ”or“ OFF ”in the series. Please refer to FIG. 2. FIG. 2 shows a partial pattern of a conventional mask ROM. These mask ROMs are formed on a P-type silicon substrate 20 and are formed with N-type impurities (N -type Implantations) implanted buried bit lines 22, 26 and complementary bit lines 24, 28 arranged in a parallel array. The bit lines 22, 26 are connected to a power supply line V, the complementary bit lines 24, 28 are grounded, and the transistors serve as memory cells for storing data. The mask read-only memory further has word lines WL0, WL1 and so on. The word lines are approximately perpendicular to the bit lines, and are the gate regions of the transistor. Among the transistors formed by the intersecting positions of the word lines and the bit lines, a part of the transistors form a channel region 30 with a low starting voltage, and the remaining field effect transistors form a relatively high starting voltage的 channel area 32. As for the traditional manufacturing of read-only memory, as shown in Figure 3, it is shown in Figures 1 and 2 of the conventional mask read-only memory as a stylized method. First, N-type impurities, such as arsenic ions, are implanted on the silicon substrate 15 to form a plurality of equally distributed buried bit lines ll, and the buried bit lines 11 form a channel region. Secondly, an oxidation procedure is applied and different oxidation rates are used to form a thicker isolation layer 17a above the buried bit line 11 and a thin oxide layer 17b above the channel region. Then, a polysilicon layer is deposited and patterned with uranium to form word lines 13 across the bit lines to form channel transistors to complete the semi-finished manufacturing of traditional mask read-only memory. Next, the mask read-only memory programming process is applied to form a mask layer 19, exposing the channel region 15 to be encoded, and then implanting P-type impurities, such as boron ions, to complete the code implant process 5 The size of this paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm—) ~~~ (please read the precautions on the back before filling this page)

Order TWF / CHOU / 〇〇1 A7 TWF / CHOU / 〇〇1 A7 Ministry of Economic Affairs Central Standards Bureau Employee Consumer Cooperatives printed policy B7 V. Description of invention (Feng) order, and the process of stylized read-only memory in the mask In the case, different doping sources can be determined according to different transistor characteristics. Wherein in the photomask-only memory, the initial voltage of the transistor depends on the degree of implantation of dopant sources in its channel area, for example, appropriate dopant sources can be implanted into these logical settings. "Or" OFF "in the transistor channel area; and these will be set to logical" 0 "or" ON "in the transistor channel area, then do not implant any doping source. < However, during the programming process of the above reticle read-only memory, the following problems will occur: (1) A plurality of equidistantly distributed buried bit lines are formed by implanting impurities (Implant Dose) on the silicon substrate. When the device size is reduced, if the doping amount is too high, it is easy to cause lateral diffusion (Lateral Diffusion), adjacent junction leakage current (Junction Leakage), and breakdown voltage value cannot be increased, so the device density cannot be effectively increased. (2) Planarization is one of the very important steps in the current semiconductor manufacturing process. Therefore, how to reduce the impact of the surface of the wafer due to the shortening of the distance between the devices, and to flatten the surface fluctuations is already In the current VLSI manufacturing process, it is an urgent matter that must be resolved. However, in the conventional manufacturing process, the thermal oxidation (Thermal Oxide) step is used to form the insulating oxide layer, so the process of forming the memory cell cannot be completely planarized. In view of this, the present invention provides a read-only memory structure, including: a substrate with a first insulating layer on the surface; a semiconductor layer arranged in a lattice, which is formed on the first insulating layer 6 (please read the notes on the back first Please fill in this page for details). The size of the paper is applicable to China National Standards (CNS & A4) (210 X 297 mm) Printed by Employee Consumer Cooperative of Central Bureau of Standards, Ministry of Economic Affairs 0631TWF / CHOU / 001 7 A / ____ B7 Fifth, the invention description (/) Shang 'is divided into bit lines parallel to each other along a first direction, parallel to the channel area connecting to each bit line along a second direction perpendicular to the first direction, and a A lattice gap between the bit line and the channel; a second insulating layer covering the lattice gaps; a third insulating layer formed on the surface of the above layers; a conductor layer formed on the third insulating layer, And are etched into a plurality of conductor lines parallel to each other along the second direction, wherein the positions of the plurality of conductor lines overlap with the channel regions. In the read-only memory structure, the conductor layer may be polycrystalline silicon , Tungsten, or titanium metal layer. The semiconductor layer may be an amorphous silicon layer or a polycrystalline silicon layer. The above-mentioned insulating layer is a silicon oxide layer, and the plurality of bit lines are distributed at equal intervals from each other. After the read-only memory structure is programmed and coded, the channel regions each have a predetermined ion doping concentration to generate different starting voltages. Another read-only memory structure of the present invention includes: an insulating base layer; Lattice structure, consisting of a plurality of bit lines parallel to each other in a first direction, a channel area parallel to each other in a second direction perpendicular to the first direction and connecting each bit line, and a channel area between the bit line and the channel area Consisting of a lattice gap formed on the insulating base layer; a first insulating layer filled with the lattice gaps; a second insulating layer formed on the surface of the above layers; and a plurality of conductors spaced apart in parallel along the second direction Line, formed on the second 7 (please read the precautions on the back before filling in this page). 〇The size of the paper is applicable to China National Standards (CNS) A4 specification (210 X 297 mm) 0631TWF / CH OU / 001 A7 B7 V. Description of the invention (4) ^ The surface of the insulating layer, where the plurality of conductor lines correspond to the channel areas. The conductor line is used as the character line, and the channel areas are coded and implanted. The manufacturing method of the read-only memory of the present invention includes the following steps: (a) a first insulating layer is formed on a substrate; (b) is formed on the first insulating layer Forming a semiconductor layer; (c) defining the semiconductor layer, forming a grid formed by etching a plurality of first direction parts and a plurality of second direction parts perpendicular to each other, and a lattice gap between the two parts Structure; (d) A second insulating layer is filled in the lattice gaps; (e) The second direction portion is defined as a channel area, and the first direction portion is a bit line; (f) In the above A third insulating layer is formed on the surface of each layer; (g) A conductor layer is formed on the second insulating layer, and a plurality of character lines parallel to each other along the second direction are formed by etching, wherein the plurality of character lines are Corresponding to these passage areas; and (h) Corresponding to these passages Definition and implantation encoding steps, the subsequent read only memory of manufacturing. In addition, the above step (a) can also be directly replaced with an insulating substrate. Brief description of the drawings: Figure 1 shows a part of the equivalent circuit diagram of the conventional mask ROM; Figure 2 shows a part of the pattern of a conventional mask ROM; (Please read first Note on the back and then fill in this page)-$ ρ Γ This paper scale is applicable to China National Standard (CNS) A4 specification (210X297mm) 313698

31TWF / CHOU / 00I A7 B7 Printed by the Employee Consumer Cooperative of the Central Prototype Bureau of the Ministry of Economic Affairs 5. Description of invention (1) Figure 3 is a stylized representation of the reticle read-only memory in Figures 1 and 2 Method; and Figures 4A to 4J show the manufacturing process of the preferred embodiment of the read-only memory of the present invention. Embodiments According to a preferred embodiment of the present invention, the process steps of a read-only memory structure are as follows. Please refer to FIGS. 4A-4C, this step is to first select an insulating base layer, or first form an insulating layer 41 on a substrate 40; secondly, form a semiconductor layer 43 on the insulating layer 41, which is engraved And form a lattice structure as shown in 4C. For example, in FIG. 4A, an oxide layer 41 is first formed on the surface of the substrate 40, and then, as shown in FIG. 4B, a semiconductor layer 43 is formed on the oxide layer 41, such as an intrinsic amorphous sand layer. Ion doping step to adjust the concentration, wherein one example of this step is to decompose and deposit SiH4 gas into an amorphous silicon layer by plasma assisted chemical vapor deposition (PECVD) at about 350 ° C ~ 575 ° C Then, the concentration is adjusted by ion doping steps such as boron ions. Next, according to FIG. 4C, a pattern of a lattice structure is defined by a lithography process, and the amorphous silicon layer 43 is etched to form a plurality of parallel X-direction semiconductor layers 43a, 43b spaced apart from the plurality of parallel γ Directional semiconductor layers 50a-50f 'where the Y direction semiconductor layers such as 50a_50f are connected to the X direction semiconductor layers such as 43a, 43b, and a grid is formed between the X direction semiconductor layers 43a' 43b and the Y direction semiconductor layers 50a-50f Gap 9 This paper scale is applicable to the Chinese National Standard (CNS) A4 said grid (210X297mm) '(Read the precautions on the back side and then fill out this amaranth) Order 0631TWF / CHOU / 001 A7 B7 Employee Consumption of the Ministry of Economic Affairs Cooperative Societies V. V. Description of Invention (?) 45. Please refer to FIGS. 4D and 4E. As shown in FIG. 4D, this step is to fill an insulating layer 44 in the lattice gap 45 of the lattice structure with a planarization process. A preferred embodiment is to deposit an oxide layer such as 44 on the surface of the above layers by a "spin on glass" (SOG) process, and after etching back, fill the lattice gap 45 (FIG. 4C) to achieve the effect of planarization, in addition This step can also be replaced by a chemical mechanical grinding (CMP) process. Next, as shown in Figure 4E, this step is used to define a plurality of bit lines and channel areas, and apply an ion implantation procedure to the bit lines. For example, a layer of photoresist is coated first, and after exposure and development, a long strip-shaped photoresist layer 5 1 a, 5 1 b, 5 1 c is formed in the area between the adjacent two-bit lines 43a, 43b, It is used to define the plurality of parallel-spaced Y-direction semiconductor layers 50a-50f as channel regions, and the plurality of parallel-spaced X-direction semiconductor layers 43a, 43b are defined as bit lines connecting each channel region, and then doped Impure ions are added to the bit lines 43a and 43b to reduce their resistance. For example, the first type impurities, N-type arsenic ions (As) are implanted to form a plurality of spaced-apart N + bit lines, which are then removed with a suitable solvent This layer of photoresist 51a-51c. Please refer to FIG. 4F, this step is to form an insulating layer 49 and a conductive layer 53 on the surface of each layer in sequence. For example, an oxide layer 49 is deposited first, and then a conductor layer 53 is formed on the oxide layer 49. A preferred embodiment is that the conductor layer is composed of one of the groups of polycrystalline silicon, tungsten, titanium, aluminum, etc., which can be physically (PVD) or chemical vapor deposition (CVD). Please refer to Figure 4G, this step is to define conductor lines such as word lines. For example, the lithography process steps are used to define the conductor layer 53 and etch to form a plurality of edges (please read the precautions on the back before filling this page).

、 1T The standard of this paper is applicable to the Chinese National Standard (CNS) Α4 specification (210Χ297mm) 0631TWF / CHOU / 001 A7 B7 V. Description of the invention (Ί) Character lines 53a, 53b and grooves 55a spaced parallel to Y , 55b, 55c, wherein the plurality of word lines 53a, 53b correspond to the channel areas 50a-50f. The plurality of metal oxide semiconductor structures formed in this way are respectively used as memory cells for storing data. The above process is the step before the production of the read-only memory until it is programmed. The manufacturer can stock up the unprogrammed semi-finished products. After the customer sends an order for a specific process, the mask can be quickly made for programming. Please refer to Figure 4H and Figure 41, which are cross-sectional structures according to lines AA 'and B-B' of Figure 4G, respectively, to describe the code definition and implantation of these channel areas (code define &; code implant) to generate different starting voltage steps in the metal oxide semiconductor structure as "on" or "off". For example, after depositing a dielectric layer 57, a photoresist 59 covers the channel region of the semiconductor structure to be formed "open" as shown in FIG. 4H 50d, and implants ions into the remaining exposed channel regions as shown in FIGS. 4H and 41 50c , And then make the corresponding memory cells store logic "〇" data or logic "1" data, and then follow the traditional post-stage process, such as making metal contacts (Contact), metal wires (Metallurgy), isolation protection layer (Passivation), And packaging to complete the read-only memory structure of the present invention. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (read the precautions on the back and then fill out this page). In addition, the read-only memory structure as shown in Figure 4G can be obtained according to the above process, which includes: a surface with an insulating layer 41 Substrate 40; — lattice structure, which is an amorphous silicon layer, consisting of a plurality of bit lines 43a, 43b parallel to each other along the X direction, and a channel region 50a-5〇f parallel to each other and connecting to each bit line along the Y direction , Which is formed on the insulating layer 41; an insulating layer 44, which fills the lattice gap 45 in the lattice structure (FIG. 4C); the silicon monoxide layer or the size of this paper is applicable to the Chinese National Standard Falcon (CNS> A4 specification (210X 297 gong) A7 61TWF / CHOU / 001 B7 5. Description of the invention (i.e.) ~ 1 ~ ΟΝΟ layer (silicon oxide / silicon nitride / silicon oxide) 49, formed on the surface of the above layers; and a plurality of strips are spaced in parallel along the Υ direction The word lines 53a, 53b are formed on the surface of the insulating layer 49, wherein the plurality of word lines 53a, 53b correspond to the channel regions 50a-50f. The channel regions have respective predetermined ion doping concentrations to Produce different starting voltages. In the described structure, the plurality of bit lines are distributed at equal intervals from each other. Please refer to Figure 4 · L, which is an equivalent structural schematic diagram according to Figure 4G, which includes word lines WL1 ~ WL3 and Bit lines BL1, BL2, where the lower semiconductor lines 43a, 4% constitute the bit lines BL1, BL2, and the upper conductor lines 53a, 53b constitute the word lines WL1, WL2, according to the figure, it can be seen that the channel The transistor 55 composed of the region 50c remains closed due to the implantation of ions, while the transistor 56 composed of the channel region 50d turns on the channel region 50d after applying a voltage to the word line WL2 and causes the current to flow from the bit The line BL1 flows to the bit line BL2. In summary, the present invention has the following effects: (1) Since the present invention uses a planarization process to replace the conventional thermal oxidation (Thermal Oxide) step to form an insulating oxide layer, such as a CMP process or SOG technology, and the material of the dielectric layer used in the SOG, such as silicon oxide, covers the surface of the wafer in the form of a solvent, so the gap fill capacity of SOG to the appearance of high and low relief is made by chemical vapor deposition Has a good dielectric layer, and it rarely causes holes (Voids). (2) The bit lines of the present invention are not formed by implanting impurities on the silicon substrate, so when the device is reduced, there is no lateral diffusion, leakage current of adjacent junctions, and collapse: a PI-In. I --- --1---1 1 --- —1'1 — ^^ 1-/ ml \ 1-I (Please read the precautions on the back before filling this page)

'' 1T The Ministry of Economic Affairs, China Bureau of Standards, Employees Consumer Cooperatives printed the paper standard applicable to the Chinese National Standard (CNS) Α4 specifications (210X297 mm) 0631TWF / CHOU / 001 A7 __B7 V. Description of invention (f /) Increased phenomenon. As for the operation of the read-only memory structure of the present invention, the bit data stored in the memory cell can be read through the selection of word lines and bit lines and the detection of the current of each memory cell by the sense amplifier. The above descriptions and examples of drawings are purely for convenience of description, and those skilled in the art should understand that the present invention is not limited thereto. In addition, the materials, conductive properties, numerical values, process conditions, etc. mentioned in this specification should not be used to limit the present invention. Although the present invention has been disclosed as above in a preferred embodiment, it is not intended to limit the present invention. Anyone who is familiar with this skill can make some changes and retouching without departing from the spirit and scope of the present invention. The scope of protection of an invention shall be defined as the scope of the attached patent application. (Read the precautions on the back before filling in this page)

, 1T printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs

Claims (1)

ABCD F / CHOU / OOl 6. Patent application scope 1. A read-only memory structure, including: a substrate with a first insulating layer on the surface; a semiconductor layer arranged in a lattice, which is formed on the first insulating layer, It is divided into bit lines parallel to each other along a first direction, parallel to a channel area along a second direction perpendicular to the first direction and connecting each bit line, and a channel area between the bit line and the channel A lattice gap; a second insulating layer covering the lattice gaps; a third insulating layer formed on the surface of each layer; a conductor layer formed on the third insulating layer and etched into a plurality of strips Conductor lines spaced apart in parallel along the second direction, wherein the positions of the plurality of conductor lines overlap on the channel areas. 2. The structure as described in item 1 of the patent application scope, wherein the semiconductor layer is one of the group of an amorphous silicon layer and a polycrystalline silicon layer. 3. The structure as described in item 1 of the patent application scope, wherein the conductor layer is composed of any combination of a polycrystalline silicon layer, a metal titanium, tungsten, and aluminum metal layer group. 4. The structure as described in item 1 of the patent application scope, wherein the conductor wire is a sub-wire. 5. The structure as described in item 1 of the patent application scope, wherein the insulating layer is a silicon oxide layer. 6. The structure as described in item 1 of the patent application scope, in which the channel regions have different starting voltages. 7. The structure as described in item 1 of the patent application scope, in which the plurality of bit lines are distributed at a predetermined interval from each other. n I IF I — *-**.-It— 1 I- I (please read the precautions on the back and then fill out this page) '? τ C! Printed paper size applicable to the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs China National Standard (CNS) Α4 specification (210X297 mm) 0631TWF / CHOU / 001 ABCD Printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economy 6. Scope of patent application 8. The structure as described in item 7 of the scope of patent application, where, The plurality of bit lines are distributed at an equal interval from each other. 9. A read-only memory structure, comprising: an insulating base layer; a lattice structure consisting of a plurality of bit lines spaced apart in parallel in a first direction, and spaced apart in parallel in a second direction perpendicular to the first direction and The channel area connecting the bit lines and a lattice gap between the bit line and the channel area are formed on the insulating base layer; a first insulating layer fills the lattice gaps; a second insulating layer, Formed on the surface of the above-mentioned layers; and a plurality of conductor lines parallel to each other along the second direction are formed on the surface of the second insulation layer, wherein the plurality of conductor lines are placed on the second insulation in a manner corresponding to the channel regions On the floor. 10. A method of manufacturing a read-only memory, including the following steps: (a) forming a first insulating layer on a substrate; (b) forming a semiconductor layer on the first insulating layer; (c) defining the The semiconductor layer is etched to form a lattice structure composed of a plurality of first-direction parts and a plurality of second-direction parts perpendicular thereto and a lattice gap between the two parts; (Sentences in the lattice gaps Forming a second insulating layer; (e) defining the second direction portion as a channel region and the first direction portion as a bit line; (f) forming a third insulating layer on the surface of each layer; (g) A conductor layer is formed on the third insulating layer, and is formed by uranium engraving (please read the precautions on the back before filling in this page)-Order ic .ml If ml I ml nn ml nn Standard, (CNS) A4 specification (2I〇X297 mm) Printed by the Ministry of Economic Affairs Central Standards Bureau Employee Consumer Cooperative A8 0631TWF / CHOO / O01 B8 C8 D8 VI. A number of characters that are parallel to each other along the second direction Line, where the plural character lines correspond to some communication Channel area; and (h) encode and define and implant the channel area through these character lines to complete the subsequent manufacturing of read-only memory. J1. The method as described in item 10 of the patent application scope, wherein, The step (b) is to form a semiconductor layer on the first insulating layer and adjust the concentration through an ion doping step. V '12. The method as described in item 10 of the patent application scope, wherein the step (d ) Is to fill a second insulating layer in the gap of the grid with the SOG planarization process. 13. The method as described in item 10 of the patent application scope, wherein the step (d) is to use a CMP planarization process on the grid The gap is filled with a second insulating layer. 14. The method as described in item 10 of the patent application scope, wherein the step (e) is to form a region between two adjacent first direction portions of the lattice structure The covered photoresist layer is used to define the second direction part as a channel region and the first direction part as a bit line, and then doping the bit line with ions to reduce the resistance and remove the light Barrier layer 15. The method as described in item i〇 of the patent application scope, wherein, The step (h) is to first form a fourth insulating layer and a photoresist layer on the surface of the above-mentioned layers in sequence, and define the photoresist layer by a lithography process, so as to expose the first layer above the channel region to be implanted with ions The windows of the four insulating layers are then ion-doped to complete the coding of the channel areas through the windows and remove the photoresist. The paper size is free to use the Chinese National Standard Falcon (CNS) A4 specification (210X297 mm) ( Please read the precautions on the back before filling in this page) c * —2 Asm timtt nn 1 tn ^ —A8 313 & 9B WF / CHOU / 001 B8 Co ____ D8 printed by the Consumer Labor Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Patent scope 16_-A manufacturing method of read-only memory, including the following steps: 0) forming an insulating substrate; (b) forming a semiconductor layer on the insulating substrate, and adjusting the concentration through an ion doping step; (c) The semiconductor layer is defined by a lithography process, and a lattice structure composed of a plurality of first direction parts and a plurality of second direction parts perpendicular to each other and a lattice gap between the two parts is formed by etching; (d ) Yiping The chemical process is filled with a first insulating layer in the lattice gaps; (e) forming a covered photoresist layer in the area between two adjacent first direction portions of the lattice structure to define the second direction The part is the channel region 'and the first direction part is the bit line, and then doping ions to the bit line to reduce its resistance and remove the photoresist layer; (f) forming a first layer on the surface of each layer Two insulating layers; (g) forming a conductor layer on the second insulating layer, and etching to form a plurality of word lines parallel to each other along the second direction, wherein the plurality of word lines correspond to the channel regions ; And (h) encoding definition and implantation of the channel area through the character lines to complete the subsequent manufacturing of read-only memory. 17. The method as described in item 16 of the patent application scope, wherein the step (b) is to form an amorphous silicon layer on the insulating substrate. 18. The method as described in item 16 of the patent application scope, wherein the semiconductor layer in step (b) is P-type. 19 The method as described in item 16 of the patent application scope, in which the paper size of this step is applicable to the Chinese National Standard Falcon (CNS) A4 specification (2 〖0 father 297 public) ΟΓ% 1 --I 8 in ml mm 1OJn I— I 1 · '1 ml ^ (Please read the precautions on the back before filling in this page) 8 8 8 8 ABCD Printed 0631TWF / CHOU / 001 printed by the Employee Consumer Cooperative of the Central Bureau of Economic Development of the Ministry of Economic Affairs b) The semiconductor layer is N-type. 2〇. The method as described in item 16 of the patent application scope, wherein in the step (h), the code definition and the implantation step are used to increase the starting voltage of the channel area. 21. The method as described in item 16 of the patent application scope, wherein in step (h), the code definition and the implantation step are used to reduce the starting voltage of the channel area. 22. The method as described in item 16 of the patent application scope, wherein in step 0), the code implantation step is to implant P-type impurities. 23_ The method as described in item I6 of the patent application scope, wherein in the step (h), the code implantation step is to implant N-type impurities. The size of this paper is applicable to the Chinese National Standard (CNS) A4 (210X297mm) (Please read the precautions on the back before filling this page)