A7 B7 五;:發明説明( 5-1發明領域: 法,特别靡嫩^之方 經濟部中央標準局員工消費合作社印製 5-2發明背景: 、金屬氧化半導體(MOS)結構爲現代半導體羞 、 設計。任一 MOS場效應電晶體均有二點.‘'瑕’曰遍之 ,極三者。該_制經由 容’當施加電壓於嶋’ U情在糊極下之基_ 電 荷。在閘金屬與反轉基板間跗存有一氧化物薄層。尚電 金屬多晶㈣MOS技術曾被用以製作高效率閘極 極包含頂層衫晶賴氧化物薄層,金屬魏物卿成於多 晶矽上,以減低多晶矽與内連線間之串聯電阻。再者,在 循環(REFLGW)平細:_t,金屬魏__金屬更能 承受/m升。美中不足地,金屬梦化製程中,若干副產雜質, 諸如在形成鎢矽化物(WSix)過程之氟原子會在高溫回火 後,擴散進入閘氧化物中。而閘氧化物愈厚則元件速度愈 慢’且啓始電壓愈高。麥考S.L.Hsu等所著,,Direct evidence of gate oxide thickness increase in tungsten polycide pr〇cesses,,J IEEE Electron Device Let ter , Vol · EDL-12,1"1,第623_625頁更有甚者,上述之氟原子將 本紙張尺度適用中國國家榡準(CNS ) A4规格(2丨〇><297公釐) t請先閲讀背面之注意事項再填寫本X) . I-----. I.....1........ ———-11! 1- 1 - I —1 i . 訂------^---- --IJ - Λ ffim fm ml UK— —i-li 1 313678 A7 B7 _ 五、發明説明() 在鎢矽閘中造成橫向分佈,進一步劣化元件特性。參考 H.Hayashida 等所著’Dopenf redistribution in dual gate W-polycide CMOS and its improvement by RTA,?,VLSi Symp.Tech Dig.1989. 5-3發明目的及概述: 包含在基板上形成一閘氧化物層,至少形成一多晶矽層 於閘氧化物層上,在金屬矽化物及多晶矽作離子植入,做 光罩圖案及餘刻金屬氧化物層及多晶矽層以區隔閘極區 域,並以閘極區當作植入軍幕形成源/汲區。 5-4圖示簡單説明: 借助下面的詳細説明並與附圖相連前述之各方面及本 發明之優點立可獲得較佳之瞭解。其圖爲: 第1圖〜第5圖爲符合本發明製作金屬石夕化物閘各階段之 結構剖視圖。 第1圖_示閘氧化物成長於基板後結構。 第』圖_示兩層多晶石夕層之沉積及施加首次氮離子植入 後之結構。 n^l-· ^ϋ.— m^— —ϊ ^ v ' ΧΎ— (請先閱讀背面之注意事項再填寫本頁) ΐτ AT.. 經濟部中央樣準局員工消费合作社印製 ) A4W ( 21〇~^^7 ^13678 " ~~------— 、發明説明( A7 B7 第3 構 _顯示鎢矽化物沉積及施加二次氮離子植入後之衅 域 第4圖類示光阻之圖案。 第5圖依據本發明顯示金屬石夕化結構與相隨之源/没區 (金:二::本:明:示形成自行對準多晶梦化物 第6圖顯示在二氧化矽層沉锖後之結構。 結構第m依據本發明類示自行對準確性(金屬石夕化物)閑之 5- 5發明詳細說明: (诗先閲讀背面之注意事項再填寫本頁)A7 B7 5 ;: Description of the invention (5-1 Field of invention: Law, particularly popular ^ Fang, Ministry of Economic Affairs, Central Standards Bureau, Employee Consumer Cooperative Printed 5-2 Background of the invention:, Metal oxide semiconductor (MOS) structure for modern semiconductors Design. Any MOS field-effect transistor has two points. "Flaw" is everywhere, and the poles are three. The _ system passes the capacity "when a voltage is applied to the ridge". The base of the _ charge is under the paste electrode. There is a thin layer of oxide between the gate metal and the inverted substrate. Shangdian metal polycrystalline (MOS) technology has been used to make high-efficiency gate electrodes including a thin layer of oxide oxide on the top layer. The metal Wei Wuqing is formed on polysilicon to Reduce the series resistance between polysilicon and interconnects. Furthermore, in the REFLGW leveling: _t, metal ____ metal can withstand / m liters. Inadequate, there are some by-product impurities in the metal dreaming process, For example, fluorine atoms in the process of forming tungsten silicide (WSix) will diffuse into the gate oxide after tempering at high temperature. The thicker the gate oxide, the slower the device's speed and the higher the starting voltage. McCaw SLHsu Etc., Direct evidence of gate oxide th ickness increase in tungsten polycide pr〇cesses ,, J IEEE Electron Device Letter, Vol. EDL-12, 1 " 1, page 623_625. What is more, the above-mentioned fluorine atoms apply this paper standard to the Chinese National Standard (CNS ) A4 specifications (2 丨 〇 < 297mm) t Please read the precautions on the back before filling in this X). I -----. I ..... 1 ....... . ———- 11! 1- 1-I —1 i. Order ------ ^ ---- --IJ-Λ ffim fm ml UK— —i-li 1 313678 A7 B7 _ V. Invention Description () Causes lateral distribution in the tungsten silicon gate, further deteriorating the device characteristics. Refer to H. Hayashida et al.'S "Dopenf redistribution in dual gate W-polycide CMOS and its improvement by RTA,?, VLSi Symp.Tech Dig. 1989. 5-3 Purpose and overview of the invention: including forming a gate oxide on the substrate Layer, at least a polysilicon layer is formed on the gate oxide layer, and ion implantation is performed on the metal silicide and polysilicon to make a mask pattern and the remaining metal oxide layer and polysilicon layer to separate the gate region and the gate The area acts as a source / drain area for implantation of the military curtain. 5-4 Brief description of the diagram: With the help of the following detailed description and the accompanying drawings, the aforementioned aspects and the advantages of the present invention can be obtained immediately. The drawings are as follows: Figure 1 to Figure 5 are cross-sectional views of the structure of each stage of manufacturing a metal stone evening gate in accordance with the present invention. Figure 1_ shows the structure behind the gate oxide grown on the substrate. The first picture_shows the deposition of the two layers of polycrystalline stone and the structure after the first nitrogen ion implantation. n ^ l- · ^ ϋ.— m ^ — —ϊ ^ v 'ΧΎ— (Please read the precautions on the back before filling out this page) Ιτ AT .. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs) A4W 21〇 ~ ^^ 7 ^ 13678 " ~~ ------——, Description of the invention (A7 B7 third structure _ shows the field of provocation after tungsten silicide deposition and the application of secondary nitrogen ion implantation Figure 5 shows the pattern of the photoresist. Figure 5 shows the metal stone evening structure and the corresponding source / no zone according to the present invention (gold: two :: this: clear: shows the formation of self-aligned polycrystalline dreams. Figure 6 is shown in The structure of the silicon dioxide layer after sinking. The structure of the mth according to the present invention shows the accuracy (metal stone evening compound) of the 5-5 invention. Detailed description: (read the precautions on the back of the poem before filling in this page)
------OT n^l 1— ϋ- I Kn I" A! 經濟部中央標準局舅工消費合作社印褽 。第基板關隔離區12之剖示賦。這些隔離 區I2-般猶電魏錄,㈣厚度3刪〜⑽⑽,在基 私10^是—層二氧化砍薄層14,稱後此層被用作閘氧化 物以隔離導體與該半導縣板1G。紐確地講,此二氧化 石夕薄層U赋财容之介質材科。典型_氧化物薄層之------ OT n ^ l 1— ϋ- I Kn I " A! Printed by Uncle Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs. The cross section of the isolation area 12 of the first substrate is shown. These isolation areas I2-Bian Youdian Wei Lu, (3) thickness ~ ~ ⑽ ⑽, in the base private 10 ^ is a layer of thin layer of oxide cut 14, said after this layer is used as a gate oxide to isolate the conductor from the semiconductor County Board 1G. According to Newton, this thin layer of U2 TiO2 has a wealth of materials. Typical_Thin oxide
A7 B7 五、爹明説明( 成長探用傳统之熱氧化製程,其厚度約爲3〇 -250 1 〇 經濟部中夬標準局員工消費合作杜印复 及第-^:所示有兩層多晶辦,即第—多晶赠16 f第—多4層18,二者均雜學氣相沉積法製程於低壓 (〇,卜U托)及溫度樹〜625 1分解發甲燒(咖)所製。如 此形成之該第-多晶铺16及第二多晶销18约分别具 有厚度5〇OA及1000A。如眾所瞭解,不論用—層多晶矽或 一層以上多晶石夕均未背離專利範圍之精神,而達到本發明 之目的。用堆積多晶層的理由係爲減低多晶名夕與金屬石户化 物間之電阻β可參閲Η·ΥΕΝ著作之頁,著作 爲 Thermal treatment and under layer effects on silane and dichlorosilane based tungsten silicide for deep sub-micron interconnection processes”, VLSI Technology’System and Application,1995.此一堆積多晶 矽結構曾被揭示,以備上述減低内阻用之平滑閘表面。參 考 S.L.Wu %所著”Characteristics of polysilico.η contacted shallow junction diode formed with a stacked-amorphous silicon film”, IEEE Electron Device,ED-40,1993 之第 1797〜1803 頁。 次一步離子植入20做在第2圖圖示之結構上。氮原子具 有植入能量20〜100千電子伏(KeV)及施用的劑量爲 1*1015〜。能量之多寡端視多晶矽的厚度而定,使 其植入輪廓峰値約在第二層多晶矽IS之中途。眾所週知’ 5 本紙張又度逋用中國國家標隼(CMS〉A4規格(nOX29]公釐) (請^閱讀背面之注意事項再填寫本頁)A7 B7 V. Description of Da Ming (The traditional thermal oxidation process is used for growth exploration, its thickness is about 30-250 1 〇 The Ministry of Economic Affairs Bureau of Standards and Consumers of the Ministry of Consumer Cooperation Du Yinfu and the first-^: shown there are more than two layers Jingban, that is, the first-polycrystalline gift 16 f first-multiple 4 layers 18, both of which are mixed with the vapor deposition process at low pressure (〇, 卜托托) and temperature tree ~ 625 1 decompose hair fever (coffee) The first-polycrystalline shop 16 and the second polycrystalline pin 18 thus formed have a thickness of about 50 OA and 1000 A, respectively. As everyone knows, no matter whether it is a layer of polycrystalline silicon or more than one layer of polycrystalline stone, it has not diverged The spirit of the patent scope achieves the purpose of the present invention. The reason for depositing the polycrystalline layer is to reduce the resistance β between the polycrystalline name and the metal petrified metal. Please refer to the page of H · ΥΕΝ's work, Thermal Treatment and under layer effects on silane and dichlorosilane based tungsten silicide for deep sub-micron interconnection processes ", VLSI Technology 'System and Application, 1995. This stacked polysilicon structure has been revealed to prepare the smooth gate surface for reducing internal resistance. SLWu% "Characteristics of polysilico. Η contacted shallow junction diode formed with a stacked-amorphous silicon film", IEEE Electron Device, ED-40, 1993, pages 1797 ~ 1803. The next step of ion implantation 20 is done in Figure 2 The structure shown. The nitrogen atom has an implantation energy of 20 ~ 100 kiloelectron volts (KeV) and the applied dose is 1 * 1015 ~. The amount of energy depends on the thickness of the polysilicon, so that its implantation profile peak value is about The second layer of polysilicon IS is halfway through. It is well known that '5 papers are made with the Chinese national standard falcon (CMS> A4 specifications (nOX29) mm) (please ^ read the notes on the back and fill in this page)
T .I---I 訂 A7 B7 五、發明説明() 其它如原子氬,鍺及石夕可用以代替氮達到本發明之相同目 的。 如第3圖所示,次一步驟爲沉積鷄石夕化物(WSiX)層22, 約具厚度別〇〜2〇00 A。鎢金屬Μ是矽鎢同時濺鍍或化學氣 相沉積(CVD)。稍後於沉積之典型熱處理是置入爐中,或用 快速熱處理(RTP)作回火以達成份均勻並將此層晶化成爲 所欲之高導點電性金屬石夕化物。在該RTP回火處理中,晶 圓從低溫快速昇至7〇〇〜1100 。該晶圓以此溫度持續一= 時間,然後约以100〜3〇G °C/秒之速率回復至低溫。相較加 熱爐處利理需時12〇分,RTP處理則減低爲3〇分以下。 相接步驟爲施行另一次離子植入24於第3圖所示之結 構上6。較合意的作法,氮原子具有植入能量5〇〜15〇千電 子伏及施用劑量爲lxl〇15〜5xl〇16at〇ms/ cm2。能量使用之多 寡裙視多晶獨厚度而定,使其植人輪廓峰値約位於到達 第二層多晶石夕層18之中途。其它原子諸如氬,鍺及 用以代替前述之氮。 値得注意的是,與第2 ®及第3 _連細次離子藉 步骤係用以克服傳统製程所遭遇之困難,在 ^款原抒人導致化_加及衫祕中雜質之重 2二„知作兩次植入步驟與僅作-次步 --- I - --*----- (請先閑讀背面之注意事項再填寫本頁j ^'哀------訂 經濟部中央標準局貝工消费合作社_製 到本發明之同樣目的 紙張錢逍齡(CNS ) A4^~ 210X297公釐) 經濟部中央襟準局員工消費合作社印袈 A7 B7 五、發明説明() 稍後如第4圖所示’一層具有閘圖案的光阻層26被形 成於:鶬矽氧化物層22上,圖案之確定係用光阻塗布,曝光 及顯影等標準製程。 用光阻圖案26當作罩幕’在敍刻鱗梦化物層22, 第二層多晶石夕層18第一層多晶石夕層I6及二氧化石夕薄層14 後’第5圖顯示該成品結構。次之,第5圖之結構承受一 次離子植入28,具植入能量约6千電子伏及一次劑量约 6xl015crfcww/cm2如是可形成源/没區29A及29B。於是具有 改良閘氧化物特性的金屬矽化物閘極結構於是形成。 第6圖及第7圖顯示可隨意選擇之步驟,其法是用金屬 氧化物閘結構形成自對準金屬多晶石夕化物(金屬石夕化物)閘 極。此一結構結合了用自對準的金屬矽化物閘極之各項特 色。在第6圖中,一層二氧化矽層3〇或氮化矽層3〇被形 成。該二氧化矽層能以四己基矽酸鹽TEOS(Si(C2H5〇)4)完 美地在65〇〜75〇 10時分解形成。該二氧化矽層3〇.然後以非 等向性蚀刻形成間隙壁,在閘極之侧壁上如第7圖所示。 這些間隙壁3〇作接下來源/汲29A及29B的重量離子植入 32之植入軍幕之用。於是最後之結構終於形成自對準金屬 多晶矽化物(金屬矽化物)閘極結構,該結構具有改良的閘 氧化特性。 氮原子植入結果如第1表所示。 - _________ 7 本紙張尺度適用(肅騰釐了 I^—-----rs衣------_ΐτ------^1 (諳先聞讀背面之注意事項再填寫本頁)T.I --- I Order A7 B7 V. Description of the invention () Others such as atomic argon, germanium and Shixi can be used instead of nitrogen to achieve the same purpose of the present invention. As shown in FIG. 3, the next step is to deposit the WiseX layer 22, which has a thickness of about 0 ~ 200 A. Tungsten metal M is simultaneous sputtering or chemical vapor deposition (CVD) of silicon tungsten. A typical heat treatment for deposition later is to put it in a furnace, or use rapid thermal processing (RTP) for tempering to achieve a uniform composition and crystallize this layer into the desired high-conductivity electrically conductive metal stone evening compound. In this RTP tempering process, the crystal circle rapidly rises from a low temperature to 700 to 1100. The wafer continues at this temperature for one = time, and then returns to a low temperature at a rate of about 100 ~ 30G ° C / sec. Compared with the heating furnace, it takes 12 minutes, and the RTP treatment is reduced to less than 30 minutes. The connecting step is to perform another ion implantation 24 on the structure shown in Figure 3 6. More desirably, the nitrogen atom has an implantation energy of 50 to 15 kiloelectron volts and an applied dose of 1x1015 to 5x1016 at〇ms / cm2. How much energy is used The oligoskirt depends on the thickness of the polycrystalline single, so that the peak value of its implanted contour is about halfway to the second polycrystalline stone evening layer 18. Other atoms such as argon, germanium and nitrogen are used instead. It is worth noting that the second and third _ continuous sub-ion borrowing steps are used to overcome the difficulties encountered in the traditional process, and the ^ section of the original expression leads to _ and the importance of impurities in the shirt secret 2 2 „Knowledge of two implantation steps and only -second step—- I--* ----- (please read the precautions on the back first and then fill out this page j ^ 'sad ------ Order the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs_Paper Money Xiaoling (CNS) A4 ^ ~ 210X297mm, which has the same purpose as the present invention) Employee Cooperative of the Central Bureau of Economics of the Ministry of Economic Affairs A7 B7 V. Description of invention ( ) Later, as shown in Figure 4, a layer of photoresist layer 26 with a gate pattern is formed on the silicon oxide layer 22, and the pattern is determined by standard processes such as photoresist coating, exposure, and development. The pattern 26 is used as a cover screen. After the engraved scale dream layer 22, the second layer of polycrystalline stone evening layer 18, the first layer of polycrystalline stone evening layer I6, and the thin layer of silicon dioxide evening layer 14, the figure 5 shows the finished product Next, the structure in Figure 5 withstands an ion implantation 28, with an implantation energy of about 6 kiloelectron volts and a primary dose of about 6xl015crfcww / cm2. Regions 29A and 29B. A metal silicide gate structure with improved gate oxide characteristics is then formed. Figures 6 and 7 show the steps that can be selected at will. The method is to form a self-aligned metal with a metal oxide gate structure Polycrystalline sintered metal gate (metal sintered metal gate). This structure combines the characteristics of self-aligned metal silicide gates. In Figure 6, a layer of silicon dioxide 30 or nitride The silicon layer 30 is formed. The silicon dioxide layer can be perfectly decomposed and formed with tetrahexyl silicate TEOS (Si (C2H50) 4) at 65 ~ 75〇10. The silicon dioxide layer 30. Then The spacers are formed by anisotropic etching, as shown in Figure 7 on the side walls of the gate. These spacers 30 are used as the implantation screen for the next source / drain 29A and 29B weight ion implantation 32 The final structure finally formed a self-aligned metal polysilicide (metal silicide) gate structure with improved gate oxidation characteristics. The results of nitrogen atom implantation are shown in Table 1.-_________ 7 Paper size Applicable (Sutengli I ^ ------- rs clothing ------_ lτ ------ ^ 1 (Know first Note to fill out the back of this page)
A7 B7 五、發明説明( 第一次N植入 第二次N植入 閘萆度 能量 劑i量 能量 劑量 Ebd(MV/cm ) Tbd(秒)12 MV/cm 多晶矽閘 72.1 25 2E15 -1 L 16.6 269 多晶矽閘 82.1 25 5E15 無 14.59 85 金屬多晶矽化物 閘用Ν植入 74.7 ί %' 80 2E15 16.25 300 金屬多晶矽化物 閘用Ν植入 73.3 無 80 5E15 16-4 641 金屬多晶梦化物 :閘用Ν植入 76.1 無 4 % 16.06 307 金屬多晶矽化物 閘用Ν植入 73.1 無 無 16,59 >10000 (請先閱讀背面之注意事項再填寫本頁) I《衣---- _^| 本 經濟部中央標準局員工消費合作社印^ 如表所見控制樣本僅爲標準多晶矽閘時,具有閘氧化物 厚度72.1A ’崩濟電場(Ebd)16.6meg.V/cm,及崩潰時間 (Tbd)269秒,在用了第一層氮植入或第二層氮植入,其增 加的閘氧化轉度雜於傳蘭多晶賴,晴其它電氣 特性亦類著較佳。 例已團示及申述,凡其它未脱離本發明所揭示 士 β '下%成之修辞,均應包含在下述之申請專利範圍 内0 成張从適用中 環隼( CNS ) A4规格(210X297公釐) -i-raj λA7 B7 V. Description of the invention (The first N implantation, the second N implantation, the energy dosage, the energy dosage, the energy dosage, Ebd (MV / cm), Tbd (seconds), 12 MV / cm, polysilicon gate 72.1 25, 2E15 -1 L 16.6 269 Polysilicon gate 82.1 25 5E15 None 14.59 85 Metal polysilicon gate with N implant 74.7 ί% '80 2E15 16.25 300 Metal polysilicon gate with N implant 73.3 None 80 5E15 16-4 641 Metal polysilicon dream: gate N implant 76.1 None 4% 16.06 307 Metal polysilicon gates N implant 73.1 None None 16,59 > 10000 (Please read the precautions on the back before filling this page) I 《衣 ---- _ ^ | This Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs ^ As shown in the table, when the control sample is only a standard polysilicon gate, it has a gate oxide thickness of 72.1A 'Banji Electric Field (Ebd) 16.6meg.V / cm and a crash time (Tbd) 269 In the second, when the first layer of nitrogen implantation or the second layer of nitrogen implantation is used, the increased gate oxidation rotation is mixed with Chuanlan polycrystalline Lai, and other electrical characteristics are also similar. The examples have been demonstrated and stated , All other rhetoric that does not deviate from the disclosure of the person β 'under% of the present invention should be included in the following Within the range of 0 to patent applicable Central sheets from Falcon (CNS) A4 size (210X297 mm) -i-raj λ