TW310512B - Lossless buffer circuit used between asynchronous media independent interface (MII) in fast Ethernet network hub - Google Patents

Abstract

A lossless buffer circuit used between asynchronous media independentinterface(MII) in fast Ethernet network hub, which consists of two sets of buffer circuits with six buffers and four PAL, comprises of the featuresthat each set of buffer circuit includes three registers and two PAL, whichindependently is in charge of forward and backward data transfer between twoasynchronous MIIs, using PAL to generate clock signal and control signalneeded by register, solving data transfer error caused by different drivingsignal between two asynchronous MIIs.

Description

Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 310512 A7 ___B7 V. Description of the invention (1) The present invention relates to a lossless buffer circuit between synchronous Mil interfaces used in high-speed Ethernet hubs. A register and four PALs are combined into two sets of buffer circuits to solve the transmission errors caused by the asynchronous transmission signals at the two ends of the data transmission. Nowadays in Ethernet, the data transmission interface between each peripheral unit, according to the provisions of IEEE802.3 for MII, the standard connection is MAC (Media

Access Control) and PCS (Physical Layer Sublayer) can be directly wired. There is no need to install any circuit between them. However, for the two peripheral units that are the same interface or the same PCS interface, the wiring needs to consider the function c and MAC, or PCS and PCS asynchronous signal effects. Refer to Fig. 1 for the connection between MAC and PCS. The signal lines on MAC11 include: a TX_CLK (Transmit Clock), a TX_EN (Transm-it Enable), a set of nD < 3: 0 > (Transmit Data), a TX_ER, a RX_CLK (Receive Clock), a RXD < 3: 0 > (Receive Data), one RX_ER (Receive Coding Error), one RX_DV (Receive Data Valid), one CRS (Carrier Sense), one C0L (Collision Detected), where TX_CLK, TX_EN, 111) < 3: 0 > £ 11 is a set of synchronization signals, and RX CLK, RX_DV, RXD < 3: 0 >, RX_ER, CRS and COL are another set of synchronization signals, so there are two sets of synchronization signals, TX_CLK and RX_CLK respectively It is a reference signal. The arrow C on each signal line in the boudoir 1 indicates the transmission direction of the signal. The naming of the signal line on PCS13 is subject to MAC11. For example, PCS13's TXD < 3: 0 > is called Transmit Data, but it is actually receiving the data transmitted by MAC11. The paper standard is applicable to China National Standard (CNS) A4 specification (210X297 I) ^ —1 II Pack III Book II line (please read the notes on the back before filling in this page) A7 B7 printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs V. Invention Instructions (2), and PCS13 RXD < 3: 0> Although it is called Receive Data Line, it is actually sending (Transmit) data to MAC11. The above is the standard specification of IEEE 802 · 3 to Mil, and the corresponding signal lines can be directly connected. Refer to the second, the conventional MAC and MAC connection diagram. MAC21 is connected to MAC23, where each transmission signal of MAC21 (TX_CLK, TX_ΕΝ, ΠΙ) < 3: 0 > and TX_ER are respectively connected to the corresponding reception signal (RX_CLK,

RX_DV, RXD < 3: 0 >, RX_ER), and the reception signals of MAC21 (RX_CLK, RX_DV, RXD < 3: 0 >, RX_ER) are connected to the corresponding transmission signals (TX_ (M, TX_EN, TXD <; 3: 0>, TX_ER). The TX_CLK of MAC21 is connected to the RX_CLK of MAC23 and are both input signals, driven by an external clock signal source 25, so it is a set of synchronization signals. Similarly, the RX_CLK of MAC21 and MAC23 TX_CLK, from another external clock signal source

1 driven by 26 is another set of synchronization signals. Both CRS and Ci) L of MAC21 and MAC23 are input signals, and an external circuit is used to check whether there is CRS or COL. Therefore, the connection between CRS and C0L is not shown in the figure. If there are TX_EN and RX_DV at the same time, it means COL (Collision Detected); if there is Transmit or Receive action, it means CRS (Carrier Sense). MAC21 sends data to MAC23 and MAC23 sends data to MAC21, which are moved by two independent external clock signal sources 25 and 26, respectively. The same data transmission is still synchronized, not affected by the two #synchronous external clock signal sources 25 and 26 Impact, therefore, when MAC is connected to MAC, just send

Transmit) signal line can be connected to the other party's Receive (Receive) signal line. Refer to Figure 3, use PCS and PCS connection diagram. Port-A's PCS31 This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) (please read the precautions on the back before filling in this page) -9 A7 310512 5. Description of the invention (3) and Port-B When the PCS32 is wired, it passes through an asynchronous MII interface 35, in which the transmission signals of PCS31 (TX_CLK, TX_EN, TXD < 3: 0 >, TX_ER) are respectively connected to the corresponding received signals in PCS33 through the asynchronous MI I interface 35 (RX_CLK, Π_ΕΝ, RXD < 3: 0 >, RX_ER), and the received signals of PCS31 (RX_CLK, RX_EN, RXD < 3: 0 >, RX_ER) are connected to the corresponding ones in 0533 through the asynchronous 1111 interface 35 respectively Send signals (11_〇1, down X_EN, TXD < 3: 0 >, TX_ER). Because the TX_CLK of PCS31 and the RX_CLK of PCS33 are independent clock signals, when the data is transmitted from PCS33 to PCS31, the signals at the sending end and the receiving end will be out of synchronization, which will cause the data transmission error. When data is transferred from PCS31 to PCS33, data transmission errors may also occur. For the two side-by-side units using the PCS interface, the purpose of transmitting data correctly cannot be achieved by direct wiring. The main purpose of the present invention is to provide a lossless buffer circuit between any two asynchronous Mil interfaces, so that when data is transmitted between asynchronous MII interfaces, six temporary registers in the lossless buffer circuit are used to store the intended transmission and reception It uses four programmable array delays to generate the clock and control signals required by the scratchpad, so that the data transmission between the two asynchronous MII interfaces is not affected by the asynchronous transmission and reception. Brief description of the diagram: Fig. 1 is the connection diagram of conventional MAC and PCS. Fig. 2 is the connection diagram of conventional MAC and MAC. Figure 3 is the connection diagram of conventional PCS and PCS. Fig. 4 is a connection diagram of the present invention applied to PCS and PCS. This paper scale is applicable to the Chinese National Standard (CNS) A4 (210X297mm) binding line (please read the precautions on the back before filling this page). The Central Standards Bureau of the Ministry of Economic Affairs prints the Central Sample Bureau of the Ministry of Economic Affairs. The reference number in the printed pattern of the industrial and consumer cooperatives 11 mac 21 mac 25 external clock signal source 31 PCS 35 asynchronous Mil interface 41 PCS 501 No lossless buffer circuit 51 No. 1 register 53 No. 3 temporary storage No. 54 No. 1 PAL 60 No. 2 lossless snubber circuit A7-B7 V. Description of the invention (de) ® Fifth is the pin diagram of the register of the No. 1 lossless snubber circuit of the invention. ®6 is the PAL pin socket of the No. 1 lossless bump circuit of the present invention.

13 PCS 23 MAC 26 external time chain signal source

33 PCS

43 PCS 52 No. 2 register 55 No. 2 PAL The following is a detailed description of the preferred embodiment of the present invention in conjunction with the drawings.

Referring to Tan Si, the present invention is applied to a connection between PCS and PCS. It includes: one PCS41, one PCS43, No. 1 lossless buffer circuit 50, and No. 2 lossless buffer circuit 60. PCS41 and PCS43 include signal lines TX_CLK, TXJEN, TXD < 3: 0 >, TX_ER, RX_CLK, RX_DV, RXD < 3: 0 >, RX_ER, while TX_ER of PCS41 and RX_ER of PCS43 are directly connected, RX_ER of PCS41 Direct wiring with TX_ER of PCS43. PCS41's TX_CLK, TX_EN, TXD < 3: 0 > borrow No. 1 lossless snubber circuit 50 and PCS43 R — IIII " H line III line (please read the precautions on the back before filling in this page) This paper The standard is applicable to the Chinese National Standard (CNS) A4 specification (210 · 〆297mm) Printed by the Ministry of Economic Affairs, Central Standards Bureau, Negative Consumer Cooperative 310512 A7 B7 V. Description of invention () X CLK, RX DV, RXD < 3: 0 > Connected, the RX CLK, RX_DV, RXD < 3: 0 > of PCS43 are connected to the TX_CLK, TX_EN, TXD < 3: 0 > of PCS41 by the No. 2 lossless buffer circuit 60. No. 1 lossless buffer circuit 50 is responsible for correctly transmitting the data sent by PC S43 to PCS41, while No. 2 lossless buffer circuit 60 is responsible for correctly transmitting the data sent by PCS41 to PCS43. In order to facilitate the explanation of the entire buffer circuit, the signal lines of PCS 41 are added with A before the names of lossless buffer circuits 50 and 60 without loss, and the signal lines of PCS 43 are prefixed with B. Refer to Circuit 5, the register pin diagram of the lossless buffer circuit No. 1 of the present invention, and FIG. 6, the PAL pin diagram of the lossless buffer circuit No. 1 of the present invention. No. 1 lossless buffer circuit 50 includes: No. 1 register 51, No. 2 register 52, No. 3 register 53, No. 1 PAL54, and No. 2 PAL55. Among them, No. 1 register 51, No. 2 register 52, and No. 3 register 53 form a three-layer FIFO (first-in first-out) temporary storage structure, which temporarily stores the input signal, while No. 1 PAL54 and No. 2 PAL55 Convert the input signal into three groups of pound signals WCLK0, fCLKl, WCLK 2, and three groups of output enable signals (Output Enable) 0E0, 0E1, 0E2. WCLK0 and 0E0 control the writing and reading of data in No. 1 register 51, WCL K1 and 0E1 respectively control the nesting and reading of the data in No. 2 register 52, and WCLK 2 and 0E2 respectively control the temporary storage in No. 3 The data in the device 53 is nested and read. The present invention uses the startup sequence of RX_DV sent by PCS43 to select one of the registers as the start register to store the data sent by the first PCS43. The data will be stored in a cyclic order, immediately after the start register. For example, when the start register is No. 2 register, the second piece of data is stored in No. 3 register, and the third piece of data Stored in No. 1 register, then No. 2, No. 3, No. 1; Continuously follow this paper standard to apply China National Standard (CNS) Α4 specification (210X297 mm) --------:- — (Please read the notes on the back before filling this page)

, 1T line Printed by the Employees and Consumers Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7 B7 V. Description of invention (6) Ring ’until the next RX_DV start sequence reappears. Since the start timing of Rainbow DV is not synchronized with the receiving end, the start register may be any of the three registers and cannot be predicted. The order of reading is the same as the order of nesting, but the read register must lag behind the written register. For example, when RX_DV is activated, register 3 is selected to nest the first data . At the rising edge of the clock signal WCLK2, the input data is written into the No. 3 register 53 for temporary storage, and before the next rising edge of the clock signal WCLK2, the No. 3 register 53 is temporarily stored The put data is read with 0E2, the second data will be nested in the No. 1 register 51, and the second data will also be read from the No. 1 register. By analogy, all data will be transmitted to PCS41, and the data transmission from PCS43 to PCS41 will be completed. In order to correctly drive the reading and nesting operations of the data in the register, PAL54 No. 1 obtains three sets of clock signals WCLKO, m: LKl, WCLE according to the following logic operation: 2 f DRXDV: = BRX_DY FIO: = / F ¥ 0 * / Ffl F ¥ 1: = FWO * / Ffl

LF ¥ 0 = BRX_DV * / DRX_DV * FfO + / RX_DV * LFfO + DRX_DV * LFfO LF ¥ 1 = BRX_DY * / DRX_DV '* Ffl + / RX_DV * LFfl + DRX_DY * LFfl WLCKO = / F ¥ 0 * / Ffl + ICLRO * / ICLK1 WLCK1 = / FfO * / Ffl + WCLK1 * / WCLK2

VLCK2 = / FfO * / Ffl + WCLR2 * / WCLKO 8 > paper wave scale applies to China National Standard (CNS) A4 specification (210X297mm) I --------- ^ ------,玎 ------ Φ. (Please read the precautions on the back before filling in this page) 310512 A7 B7 V. Description of the invention (7) The 20 pin signals of PAL54 are defined as follows, ΡΙΝΙ: BRX.CLK (Input ) PIN11: _0E PIN2: BRX_DV (Input) PIN3: NC (Input) PIN4: BRX_CLK2 (Input)

PIN5: NC PIN6: NC PIN7: NC PIN8: NC PIN9: NC PIN10: GND (Input) PIN12: ¥ CLK0 (Output) PIN13: ¥ CLE1 (Output) PIN14: DRXDV (Output) (Input) PIN15: F ¥ 0 ( Output) (Input) PIN16: F ¥ 1 (Output) (Input) PIN17: LF ¥ 0 (Output) (Input) PIN18: LFW1 (Output) (Input) PIN19: WCLK2 (Output) PIN20: VCC (Input) (Input ) No. 2 PAL55 obtains three sets of control signals OEP, QE1, 0E2 according to the following delay operations: = BRXDV1 * / BRXDV2 * LFWO + / BRXDV1 * / HRO * / HR1 + BRXDV2 * / HRO * / HR1: = BRXDV1 * / BRXDV2 LFW1 + / BRXDV1 * / HRO * / Han 1 + BRXDV2 * / HRO * / HR1 = / HRO * / HR1 * _0E1 * _0E2

HRO HR1 (Please read the precautions on the back before filling out this page) Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs / _OEO / 1 0E1 / _〇E2 0E0 * _0E2 0E0 * 0E1

: / HRO * / HR1: / HRO * / HR1 BRXDV1: = BRX_DV BRXDV2: = BRXDV2 Among them, the 20 pin signals of PAL55 are defined as follows, ΡΙΝΙ: ATX_CLK (Input) PIN11: _0E 聿 (Input) 9 This paper size applies to China National Standard (CNS) A4 specification (210X297mm) A7 B7 printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Invention Description (8) PIN2 BRX_DV (Input) PIN12: _0E0 (Output) PIN3 LF ¥ 0 (Input) PIN13: _0E1 (Output) PIN4 LFW1 (Input) PIN14: BRXDV1 (Output) PIN5 BRX.CLK (Input) PIN15: HR0 (Output) PIN6 NC (Input) PIN16: HR1 (Output) PIN7 NC (Input) PIN17: BRXDV2 ( Output) PIN8 NC (Input) PIN18: NC (Output) PIN9 NC (Input) PIN19: _0E2 (Output) PIN10: GND (Input) PIN20: VCC (Input) For data transfer from PCS41 to PCS43, the number 2 The lossless buffer circuit 60 is completed. The construction unit of the No. 2 lossless buffer circuit 60 is exactly the same as the No. 1 lossless buffer circuit 50, as long as the BRXD (3: 0), BRX_DV, BRX_ER of the No. 2 lossless buffer circuit 60 are connected to the PCS41 respectively RXD (3: 0), RXJDV, RX_ER, and ATXD (3: 0), ATX_EN, ATX_ER of No. 2 lossless buffer circuit 60 are connected to TXD (3: 0), TX_EN, TX_ER on PCS43, Refer to Figure 4. The spirit of the present invention is to disclose that a lossless buffer circuit is composed of at least six registers and four PALs to form two sets of buffer circuits, each of which contains three registers and two PAL The number of devices must be at least three or more. In the description of the embodiments, taking three buffers in each group of buffer circuits as an example is only for the convenience of explaining the spirit of the present invention, and is not limited thereto. In summary, when the invention of this case is known to be practical and creative, and this III is installed with II and II line is installed.-. (Read the precautions on the back and then fill in this page) _____ 10 paper; suitable for financial development (CNS) A4 threat (21GX297 company director) ~~ -___ 310512 Μ V. Description of invention (9) --- The invention has not been seen in any publication, and it should meet the provisions of the Patent Law. The above is only one of the preferred embodiments of the present invention, and it should not be used to limit the scope of the present invention. That is to say, all the equal changes and modifications made by the patent application garden according to the present invention shall fall within the model garden covered by the invention patent. --------- ^ — Qiyi ------ IT ------ ^ (Please read the precautions on the back before filling in this page) Ministry of Economic Affairs, Ministry of Economic Affairs, Industry and Consumer Cooperation The size of the printed paper is in accordance with Chinese National Standard (CNS) Α4 specification (210 X 297 mm)

Claims (1)

A8 B8 C8 D8 VI. Patent application A non-synchronized j (丨 I lossless buffer circuit between interfaces used in high-speed Ethernet hubs. It includes two sets of buffer circuits, a total of six registers, four A PAL, which is characterized in that each group of buffer circuits includes three registers and two PALs, which are respectively responsible for the forward and reverse data transmission between the two asynchronous μπ interfaces, and the PAL is used to generate the required registers The clock signal and the control signal solve the data transmission error caused by the unsynchronized driving signals of the two unsynchronized MII interfaces. --I — I 1-¾ 1 IH Sang | IIIII Order — Θ (Please read the back Matters needing attention and then fill out this page) Printed by the Ministry of Economic Affairs, Central Bureau of Precision Industry and Fisheries Consumer Cooperation 12 Chinese Standard (CNS) A4 Specification (210X297mm)