TW308709B - Electron-beam processed films for microelectronics structures - Google Patents

Electron-beam processed films for microelectronics structures Download PDF

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TW308709B
TW308709B TW85107802A TW85107802A TW308709B TW 308709 B TW308709 B TW 308709B TW 85107802 A TW85107802 A TW 85107802A TW 85107802 A TW85107802 A TW 85107802A TW 308709 B TW308709 B TW 308709B
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Taiwan
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substrate
film
patent application
electron beam
item
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TW85107802A
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Chinese (zh)
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Forester Lynn
H Hendricks Neil
Kyu-Choi Dong
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Allied Signal Inc
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Priority claimed from US08/652,893 external-priority patent/US6652922B1/en
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Abstract

An improved method for producing substrates coated with dielectric films for use in microelectronic applications in which the films are processed by exposing the coated substrate surfaces to a flux of electron beam. Substrates cured via electron beam exposure possess superior dielectric properties, density, uniformity, thermal stability, and oxygen stability.

Description

A7' B7 30S709 五 '發明説明( 本申請案聲明i995年6月15曰提出申請之美國臨時" 案序號60/000,239的益處,該申請案以夂去,,上 f 丁啃木以參考心万式併入 本文中。 ’ 明領域 、本發明係關於用在諸如積體電路(integmed eimh,^ 文簡稱I C )之微電子結構的電子束處理膜。更特定古之, 本發明係關於處理這類膜之方法的改良,該改良造:均: 、緻密的膜’有些膜也擁有低的介電常數和低的濕式蝕亥: 速率。 2·發明背景 諸如多晶片模組、印刷電路板、高速邏輯裝置、平面羅 示器、#體電路和纟它微電子纟置的種種裝置需要沈積或 旋轉塗怖的介電膜。 經濟部中央樣準局員工消費合作社印製 一 -r>u .w m o W 仰, 禮重路電子學微結構科皋f .每約1 984年)[喬西卡];% 產生這麼一種爲人須要之膜到基板上的一種通常使用的 技術,涉及在350X:和90(TC間之溫度範圍,持續約i小時 的热退火或熱硬化。參見聯合訊號公司印行之"用於層間 和金屬間介電平坦化之旋轉塗佈於玻璃上之材料的旋轉/ ’烘烤’硬化程序"(1994)(熱硬化之旋轉塗佈膜)和肯恩 (Kern),W.,"極大型積體電路之沈積介電物",8(7)國際 半導體122 ( 1985年7月)[”肯恩,’];喬西卡(G〇rczyca), T.B·,等人’,介電物之電漿輔助化學氣相沈精” 8M)極大型A7 'B7 30S709 Five' Description of the Invention (This application declares the benefits of the US provisional case number 60 / 000,239 of the application filed on June 15, i995. The ten thousand types are incorporated in this article. 'The field of the art, the present invention relates to electron beam processing films used in microelectronic structures such as integrated circuits (integmed eimh, IC for short). More specifically, the present invention relates to processing The improvement of the method of this kind of film, the improvement is made: both :, dense film 'Some films also have low dielectric constant and low wet etching rate: 2. Background of the invention such as multi-chip modules, printed circuits Boards, high-speed logic devices, flat display devices, #body circuits and other microelectronic devices need to be deposited or spin-coated with dielectric films. Printed by the Consumer Cooperative of the Central Prototype Bureau of the Ministry of Economic Affairs-r > u .wmo W Yang, Li Zhonglu Electronics Microstructure Department, Ga. f. every about 1 984) [Josica];% A commonly used technology that produces such a required film onto a substrate involves 350X: and 90 (temperature range between TC, hold About 1 hour of thermal annealing or thermal hardening. See "Signal Rotation / 'Baking' Hardening Procedure" (1994 for the application of dielectric coating for interlayer and intermetal dielectric flattening on glass) (1994) ) (Thermosetting hard-coated film) and Kern, W., " Deposited Dielectrics for Very Large Integrated Circuits ", 8 (7) International Semiconductor 122 (July 1985) [" Ken, ']; Gorczyca, TB ·, et al.' Plasma-assisted chemical vapor deposition of dielectrics "8M) Very large

A7' B7 3〇87〇9 五、發明説明(2 ) 特森(Mattson),B.,"層間介電物之化學氣相沈積膜"固態 技術60(1980年1月)[梅逖森](熱退火之化學氣相沈積 (CVD)膜)a然而,好幾種缺點與熱處理有關。 在將旋轉塗佈膜(spin-on glass film,下文簡稱S0G)旋轉 塗佈到基板上的諸應用中,矽氧烷型的S〇Gs易受氧電聚 損壞。在接續的I C處理中,已受氧電漿損壞的s〇Gs有濕 氣外露的傾向,經常造成電氣和機械信賴性失效3此外, .為硬化之S Ο G s對乳電聚的不穩定性不僅也造成諸如剝離 的製造困難’同時也造成最終產品中諸如增加之孔隙度、 增加之收縮度、及不良之平坦度的物理性、機械性和外觀 性缺陷= 其次’這種硬化5夕酸鹽s 0 G s的高溫使用也造成矽化物的 氧化和劣化。這經常導致矽化物劣化或高級I C中淺攙雜物 剖面分佈劣化所造成的裝置失效。再者’這種已氧化之表面 層的存在藉由增加阻抗或去除至矽化物的電氣接觸,以及藉 由成電晶體間互連的劣化,而有害地影響該I C的整體電 氣性能。 經濟部中央榡準局員工消费合作杜印製 。在基板塗覆有CVD膜的諸應用中,也需要在高達約1000 c之高溫下的額外退火步驟,以改良該c vd膜的品質。然 而,這造成諸如矽化物劣化、熱載體劣化、裝置不穩定之類 的複雜性和裝置失效問題3雖然這些困難點類似於使用熱處 理所觀察到的那些,但是此等效應的幅度較大,因爲所涉及 的溫度高很多。 成長超薄的閘極氧化物和氮化物於基板上一個爲人所 本,張度適用中國國家榡率規格(加〆297公董) 308709 A7 ______ B7 五、發明説明(3 ) 知的問題是沒有能力控制它們成長的均勻度。成長此類氧化 物的先前技藝方法使用單晶快速熱處理系統(Rapid Thermal Processing systems,下文簡稱RTP)或者如在,例如,席特 斯(Sheets),R.,”快速熱處理系統微電子製造及測試,j 6 (1985年7月)中所説明的爐子。然而,即使污染物存在著像 十億分之幾那麼低的數量’成長失敗也將發生於這些方法中 3這種沒有能力產生此類的均勻氧化物‘氮化物,在丨C的 操作期間,造成該氧化物和氮化物後續的燒毀,並因此影響 它的整體信賴性。 對所有的高級1C而言,擁有具低今電常數的介電材料是爲 人期待的。一般而言,CVD膜不擁有低介電常數,除非它 們攙雜有高含量的氟。參見竹氏(Takeshi),S,等人,,以 N2〇 -电及退火使換雜氟之二氧化夕膜的介電常數穩定化" 極大型/超大型積體電路多層互連介電物研討會(Dielectrics for VLSI/ULSI multilevel Interconnection Conference,下文 簡稱DUMIC )( 1995年2月)。然而,這種攙雜氟的氧化物經 常是不穩足的,且在有濕氣的環境和氧電漿環境中易於劣化 〇 儘管藉由使用旋轉塗佈之含高分子膜(spin_〇n containing films,下文簡稱S〇Ps)可獲得較低的介電常數, 但是這種膜由於它們不良的熱穩定性、它們常暴露於氧電漿 時的劣化傾向、及它們在ICs内金屬層沈積所典型使用:溫 度下的分解傾向,而對製程整合性提油極大的桃戰。再者舰 已經經過熱硬化之SOGs所能達到的最低介電常數典型只有 ___ -6- 本紙張尺度適S中國國*標準ΐ CNTS ) A4規格(210X 29*7公聲) " ----------- ---------1------iT------.^- (請讀背面-之注意事& 填寫本頁) 經濟部中央標準局員工消費合作社印製 五、發明説明(4 A7- B7 經濟部中央標準局員工消費合作社印裳 約3.8-4.1。這樣的介電俊由於機械及電氣效應上更爲嚴苛 的控制。諸如随著裝置大小降低而變得更爲關鍵的電容値, 可能不適用於下一世代微電子應用的最終用途。 提供在低溫下快速處理介電膜塗層於基板上的改良方法, 該方法會造成熱穩定且對氧電漿不敏感的產品,會是爲人期 待的。提供擁有低介電常數之均勻緻密的S〇G或CVD材料 也會是爲人期待的。此外,均勻地成長超薄的閘極氧化物於 基板上會是爲人期待的。 發明摘述 根據本發明,其處在基板上介電材料的硬化上提供改良 ,該改良包括: (a) 施加介電材料至基板的一表面;及 (b) 在足以硬化該介電材料的條件下,將該介電材料暴露至 電子束輻射。 根據本發明的另-方面,其處在塗覆有化學氣相沈積材 料之基板的退火上提供改良,該改良包括_ (a) 施加化學氣相沈積材料至基板的一表面;及 (b) 在足以將化學氣相沈積材料退火的條件下,將該化學氣 相沈積材料暴露至電子束輻射。 根據本發明的另一方S,JL#/· ^ I 万面八處在基板上超薄膜氧化物或 氮化物的成長上提供改良,該改良包括· ⑷在一種氣體狀態之材料的存在下,且在足以使該材料離 ^錢成基板表面上之氧化或氮化反應的條件下,將 基板的一表面暴露至電子束輻射。 -7- 本紙張尺度逋用中國國 ---------t ! (請先W讀背面V注意事文·%'寫本頁) 訂 線A7 'B7 3〇87〇9 V. Description of the invention (2) Mattson, B., " Chemical Vapor Deposition Films of Interlayer Dielectrics " Solid State Technology 60 (January 1980) [Mei Ti Mori] (Thermal Annealed Chemical Vapor Deposition (CVD) Film) a However, several shortcomings are related to heat treatment. In applications where spin-on glass film (hereinafter referred to as SOG) is spin-coated onto a substrate, the silicone-type SOGs are susceptible to damage by oxygen electropolymerization. In the subsequent IC treatment, s〇Gs, which have been damaged by oxygen plasma, have a tendency to expose moisture, often causing electrical and mechanical reliability failure. 3 In addition, the hardened S Ο G s is unstable to the emulsion polymerization Not only causes manufacturing difficulties such as peeling, but also causes physical, mechanical, and appearance defects in the final product such as increased porosity, increased shrinkage, and poor flatness = secondly, this hardening The high temperature use of acid salt s 0 G s also causes the oxidation and deterioration of silicide. This often leads to device failure caused by the deterioration of silicide or the profile distribution of shallow dopants in advanced IC. Furthermore, the presence of this oxidized surface layer adversely affects the overall electrical performance of the IC by increasing resistance or removing electrical contacts to the silicide, and by deteriorating interconnections between transistors. Printed by the Ministry of Economic Affairs, Central Bureau of Precincts, consumer cooperation. In applications where the substrate is coated with a CVD film, an additional annealing step at a high temperature of up to about 1000 c is also required to improve the quality of the c vd film. However, this causes complexity such as silicide degradation, heat carrier degradation, device instability, and device failure issues3. Although these difficulties are similar to those observed using heat treatment, the magnitude of these effects is larger because The temperatures involved are much higher. The ultra-thin gate oxides and nitrides grown on the substrate are one-of-a-kind, and the extension is applicable to the Chinese national rate specification (plus 297 public directors) 308709 A7 ______ B7 5. Description of the invention (3) The known problem is There is no ability to control the uniformity of their growth. Prior art methods to grow such oxides use single crystal rapid thermal processing systems (Rapid Thermal Processing systems, hereinafter referred to as RTP) or as in, for example, Sheets, R., "Microelectronics manufacturing and testing of rapid thermal processing systems , The furnace described in j 6 (July 1985). However, even if the pollutants are present in a quantity as low as a few parts per billion, the growth failure will occur in these methods. 3 This inability to produce such The uniform oxide 'nitride, during the operation of 丨 C, causes the subsequent burning of the oxide and nitride, and thus affects its overall reliability. For all advanced 1C, with a low current constant Dielectric materials are expected. Generally speaking, CVD films do not possess a low dielectric constant unless they are doped with a high content of fluorine. See Takeshi, S, et al., N2〇- 电 和Annealing stabilizes the dielectric constant of the doped fluorine dioxide oxide film " Dielectrics for VLSI / ULSI multilevel Interconnection Conferen ce, hereinafter referred to as DUMIC) (February 1995). However, this doped fluorine oxide is often unstable, and is easily degraded in a moisture environment and an oxygen plasma environment. Despite the use of rotation Coated polymer-containing films (spin_〇n containing films, hereinafter referred to as S〇Ps) can obtain a lower dielectric constant, but such films due to their poor thermal stability, they are often exposed to oxygen plasma The tendency of deterioration and their typical use in the deposition of metal layers in ICs: the tendency to decompose at temperature, which is a great battle for the integrated oil extraction of the process. Furthermore, the lowest dielectric that the ship has undergone through thermally hardened SOGs The constant is typically only ___ -6- The paper size is suitable for China * Standard l CNTS) A4 specification (210X 29 * 7 public sound) " ----------- ------- --1 ------ iT ------. ^-(Please read the back-notes & fill in this page) Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs V. Invention Instructions (4 A7 -B7 Printed garments of the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs about 3.8-4.1. Such dielectric Jun due to mechanical and electrical effects are more stringently controlled Capacitor values, which become more critical as the device size decreases, may not be suitable for the end use of the next generation of microelectronics applications. Provide an improved method for quickly processing dielectric film coatings on substrates at low temperatures, this method Products that are thermally stable and insensitive to oxygen plasmas are expected. It is also expected to provide uniform and dense SOG or CVD materials with low dielectric constants. In addition, it would be desirable to grow an ultra-thin gate oxide uniformly on the substrate. SUMMARY OF THE INVENTION According to the present invention, it provides improvements in the hardening of a dielectric material on a substrate. The improvements include: (a) applying a dielectric material to a surface of the substrate; and (b) sufficient to harden the dielectric material Under conditions, the dielectric material is exposed to electron beam radiation. According to another aspect of the present invention, it provides improvements in the annealing of substrates coated with chemical vapor deposition materials, the improvements including-(a) applying chemical vapor deposition materials to a surface of the substrate; and (b) Under conditions sufficient to anneal the chemical vapor deposition material, the chemical vapor deposition material is exposed to electron beam radiation. According to another aspect of the present invention, JL # / · ^ I provides improvements in the growth of ultra-thin film oxides or nitrides on the substrate. The improvements include: ⑷ in the presence of a gaseous material, and Under a condition sufficient to separate the material into an oxidation or nitridation reaction on the surface of the substrate, a surface of the substrate is exposed to electron beam radiation. -7- The size of this paper is in Chinese --------- t! (Please read the back V and note the text% 'to write this page first)

'I 1 I I- ml . B7 經濟部中央標準局負工消費合作社印裝 五、發明说明(5 ) 根據本發明的另外一個方面,其處提供塗覆有根據上述 製程所產生之電子束處理膜的基板。 根據本發明的另一個方面,其處提供降低塗覆介電膜和 化學氣相沈積膜之基板之介電常數的製程,該製程包含在 足以處理該膜的條件下,將該膜暴露至電子束輻射。 根據本發明的另一個方面,其處提供自化學氣相沈積塗 層產生富含碎之膜的製程,該製程包含在足以處理該膜的 條件下’將該塗層暴露至電子束輻射。 在本發明的另外一個具體實施例中,其處提供含有塗覆 有電子束處理膜之基板的微電子黎置,其中該電子束處理 膜的介電常數小於約3。 本發明的電子束處理膜不僅有益地形成緻密、均勻的塗 層於基板上’也有益地形成電子束硬化的S〇g膜,該類膜 擁有遠低於在高溫下熱處理之類似組成所報導者的介電常 數。此外,處理此類膜的時間和溫度降低很多。 附圖簡要説明 參考本發明下列的詳細説明和隨附的附圖時,本發明將 更充分地爲人所瞭解,且更多的優點將變得顯而易見,其 中: 圖1是塗覆有矽氧烷SOG之晶圓之傅立葉轉換光譜 (Fourier Transform Infrared Spectra,下文簡稱 FTIR)吸收 對波數(1 /厘米)的圖形’該晶圊不是熱平台烘烤、熱硬化 、就是電子束硬化。 _ 圖2 (a)和(b)是在各種的電子束劑量和硬化溫度下,使用 -----—__- 8 - 本紙張尺度適用中國國家標準(CNS) M規格(公缓)-—-- 裝------訂------線 ·' (請先K讀背面之注意事¾.知寫本頁) 經濟部中央標準局員工消費合作社印製 3〇87〇9 • KV B7 — —— 五、發明説明(6 ) 電子束硬化之塗覆有碎氧燒SOG之晶圓之FTIR光譜吸收對 波數(1 /厘米)的圖形。 圖3是經由加熱且藉由電子束照射而硬化之塗覆有發氧 燒SOG之晶圓之膜收縮百分比對電子束劑量(微庫侖/平方 厘米)的圖形。 圖4是塗覆有電子束硬化矽氧烷SOG之晶圓之膜收縮百 分比對電子束能量(千電子伏特)的圖形。 圖5是塗覆有熱硬化SOG之晶圓、熱氧化物晶圓和塗覆 有電子束硬化SOG之晶圓在5 〇 : 1緩衝氧化物餘刻 (buffered oxide etch,下文簡稱B.O.E.)中濕式蝕刻速率( 埃/秒)爲電子束劑量(微庫命/平方厘米)函數的圖形。 圖6(a)-(d)是塗覆有電子束硬化SOG之晶圓在50 : 1 B. Ο E.中濕式蝕刻速率(埃/秒)爲膜厚之深度(埃)函數的圖 形。 圖7是在各種等級之電子束能量(千電子伏特)下,塗覆 有電子束硬化SOG之晶圓在5 0 ·_ 1 B.O.E.中濕式蝕刻速率 (埃/秒)爲膜厚之深度(埃)函數的圖形。 圖8是在各個處理階段完成之後,塗覆有電子束硬化 SOG之晶圓之FTIR光譜吸收對波數(1 /厘米)的圖形。 圖9是兩者都暴露至硬化後大氣條件之熱硬化s〇G膜和 電子束硬化S0G膜之FTIR光譜吸收對波數(丨/厘米)的圖形 〇 圖1 〇 (a)及(b)是塗覆有電子束硬化S0G之晶圓分別在電 子束硬化之後’以及在接著電子束硬化之浸入水中之後, -9- 本紙浪尺度適用中國國家標準(CNS ) A4規格(210X297公釐) I--------1------ΪΤ------^ (請先閱讀背面之注意事項一如寫本育) A7_'I 1 I I-ml. B7 Printed by the Consumer Labor Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (5) According to another aspect of the present invention, it is provided with an electron beam treatment coated according to the above process Membrane substrate. According to another aspect of the invention, there is provided a process for reducing the dielectric constant of a substrate coated with a dielectric film and a chemical vapor deposition film, the process comprising exposing the film to electrons under conditions sufficient to process the film Beam radiation. According to another aspect of the invention, there is provided a process for producing a fragment-rich film from a chemical vapor deposition coating, the process comprising 'exposure of the coating to electron beam radiation under conditions sufficient to treat the film. In another embodiment of the present invention, a microelectronic device containing a substrate coated with an electron beam treatment film is provided, wherein the dielectric constant of the electron beam treatment film is less than about 3. The electron beam treatment film of the present invention not only beneficially forms a dense and uniform coating on the substrate, but also beneficially forms an electron beam hardened S〇g film, which has a much lower composition than that reported by heat treatment at high temperature. The dielectric constant of the person. In addition, the time and temperature for processing such membranes are much reduced. BRIEF DESCRIPTION OF THE DRAWINGS With reference to the following detailed description of the present invention and the accompanying drawings, the present invention will be more fully understood, and more advantages will become apparent, in which: FIG. 1 is coated with silica The graph of Fourier Transform Infrared Spectra (FTIR) absorption of the wafer of alkane SOG absorbs the wavenumber (1 / cm). The crystal element is either hot plate baking, thermal hardening, or electron beam hardening. _ Figure 2 (a) and (b) are used at various electron beam doses and hardening temperatures ------__- 8-This paper scale is applicable to China National Standard (CNS) M specifications (public slow)- ——— 装 装 ———— 訂 ———— 線 · ”(Please read the notes on the back ¾. Know to write this page) Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 3〇87〇 9 • KV B7 — —— V. Description of the invention (6) FTIR spectrum absorption versus wavenumber (1 / cm) graph of electron beam hardened SOG-coated wafers. Figure 3 is a graph of the percentage of film shrinkage versus electron beam dose (microcoulombs / cm 2) of SOG-coated wafers hardened by heating and electron beam irradiation. Figure 4 is a graph of the film shrinkage percentage of electron beam hardened silicone SOG wafers versus electron beam energy (kiloelectron volts). Fig. 5 shows that the wafers coated with thermally hardened SOG, the thermal oxide wafers, and the wafers coated with electron beam hardened SOG are wetted at 50: 1 buffered oxide etch (hereinafter referred to as BOE) The etching rate (Angstroms / sec) is a graph of the electron beam dose (microcubic / cm2). Figures 6 (a)-(d) are graphs of the wet-etching rate (Angstroms / sec) of 50: 1 B. Ο E. wafers coated with electron beam hardened SOG as a function of the depth of the film thickness (Angstroms) . Fig. 7 shows the wet etching rate (Angstroms / sec) of the wafers coated with electron beam hardened SOG in 50 0 _ 1 BOE at various levels of electron beam energy (kiloelectron volts) as the depth of film thickness ( A) The graph of the function. Figure 8 is a graph of FTIR spectral absorption versus wavenumber (1 / cm) of a wafer coated with electron beam hardened SOG after completion of each processing stage. Figure 9 is a graph of FTIR spectral absorption versus wavenumber (丨 / cm) of thermally hardened SOG film and electron beam hardened SOG film both exposed to atmospheric conditions after hardening. Figure 1 (a) and (b) Wafers coated with electron beam hardening S0G are after electron beam hardening 'and after immersion in water followed by electron beam hardening, -9- This paper wave scale is applicable to China National Standard (CNS) A4 specification (210X297mm) I -------- 1 ------ ΪΤ ------ ^ (Please read the precautions on the back as if writing a book) A7_

經濟部中央梯準局負工消費合作社印製 F Τ I R光譜吸收對波數(丨/厘米)的圖形。 圖11疋在各種乳體存在下,使用電子束硬化之時效處理 膜之F T I R光譜吸收對波數(i /厘米)的圖形。 圖1 2疋具有石夕四乙§旨(tetraethyi orth〇silicate,下文簡 稱TEOS )覆蓋之電子束硬化s〇G之閘極氧化物之崩潰時間 累積機率(cumulative probability of time to breakdown,下 文簡稱QBD )對崩潰時間(秒)的圖形。 圖1 3是穿過該氧化物厚度之鈉、鉀、氫、碳、和氧不純 物之二次離子質請術(secondary ion mass spectroscopy,下 文簡稱SIMS )深度縱剖面分佈分析之深度(微米)對濃度(原 子/立方厘米)的圖形。 較佳具體實施例説明 除非另外指出,否則本文中所有的參考數字係指示重量 。本文中所使用的"劑量"應是指電子束輻射的劑量。 各種材料可經由”旋轉塗佈"、CVD、或成長技術而施加 至本發明的基板上。 合適的介電材料或可旋轉塗佈至基板的SOG包括矽酸鹽 類、磷矽酸鹽類、矽氧烷類、磷矽氧烷類和其中的混合物 。矽氧烷類是較佳的。更令人偏愛的矽氧烷類是非晶質、 交鏈的玻璃型態材料,具有化學式SiOx,其中X大於或等 於1,且小於或等於2,並擁有”預曝照"内含物,其以該矽 氧烷材料的總重量爲準,由從約2 %至約9 0 %,且較好從 約1 0 %至約2 5 %,的有機基组成,諸如具有從約1至約1 0 個碳的烷基,具有從約4至約1 0個碳的芳香族基,具有從 -10- 本紙張尺度逋用中國國家標準(CNS ) Α4规格(2丨〇'〆297公釐) ---------私衣------1T------α { (請先琦讀背面之注意事I%寫本頁} A7- B7 經濟部中央標準局貝工消費合作社印製 五、發明説明(8 约4至约1 0個碳的脂肪族基,及其中的混合物。可選擇地 ,矽氧烷和矽酸鹽材料也可,以該介電材料的總莫耳百分 比爲準,包含從約0%至約丨〇%,且較好是從約2%至約 4 %,的鱗。 適合本發明ι使用的較佳矽氧烷材料可自列訊公司 (八1丨1以51糾311^)購得,具有,,心(;1^355,,@的商品名稱。 合適的矽氧烷材料含有約十億分之1〇〇或更少,較好是 十億分之50或更少,且更好是十億分之1〇或更少,之諸 如納'鉀、氣、鎳'鎂、鉻、銅、錳'鐵、詞之類的微量 元素不純物,且較好具有在從約3〇〇至約5〇〇〇〇,更好是從 約500至約1 〇〇〇〇分子量單位之間的分子量。 介電材料可經由在該技藝中爲人所熟知的傳統旋轉塗佈 、含浸塗佈、灑佈或弯液面塗佈方法施加至基板。這類方 法的細節説明於,例如,積體技術所刊行的"處理設備及 自動化系統"中。 基板上介電膜的厚度可視施加至基板 變化,但典型而言,厚度可從約500埃變化至約删0埃, 且較好從約3〇〇〇埃變化至約9000埃。施加至基板的s〇G液 體數量可在從約!毫升至約10毫升之間變化,且較好從約 2毫升變化至約8毫升。 在較佳具體實施例中,矽氧烷材料從中心地施加至基板 ,然後以在約每分鐘500轉和約每分鐘6〇〇〇轉之間,較好 在約每分鐘1500轉和約每分鐘4000轉之間,變化的速度旋 轉該基板約5至約60秒,較好是約1〇至約3〇秒,以溶 __-_ 11 ~ 本紙張尺度適財關家鮮(CNS ) A4規格(21GX297公釐) 裝· (請先时讀背面*之注意事足.板寫本頁) —訂— 線 經濟部中央樣準局貝工消費合作社印製 3〇87〇9 A7- _________B7 五、發明説明(9 ) 液平均地分散在遠基板表面。 可經由CVD沈積至基板上的合適材料包括電漿強化矽酸 四乙脂(plasma-enhanced tetra-ethyl ortho silicate,下文簡 稱PETEOS ),諸如矽烷和二矽烷的矽烷屬氧化物,硼-嶙 石夕 8¾鹽玻璃(bo-ron-phosphosilicate glass,下文簡稱 BPSG) ’憐碎§£鹽玻璃(卩11〇5卩1105丨1丨。316呂1355,下文簡稱1>5〇), 諸如氮化矽(SiN)的氮化物和含有該氮化物的非化學計量 性混合物,無水物膜,諸如使用矽烷(SiH4)、氨(NH3)、 氮及氧化亞氮(N2 0)和其中之混合物所沈積者的氧氮化物 ,和由四乙基正石夕垸製成之硼磷玻璃(b〇r〇ph〇sph〇 glass from tetraethyl orthosilane,下文簡稱 BPTEOS ),和其中的 混合物。矽燒屬氧化物膜是較佳的。 CVD膜可在氣體存在下’經由在該技藝中爲人所熟知的 傳統CVD方法施加至基板。這類方法的細節在該技藝中爲 人所熟知,且説明於,例如,喬西卡;肯恩,及梅逖森著 作中’其以參考之方式併入於本文中。爲CVD應用所選擇 的氣體視所想要之膜的類型而定,但典型而言,這類氣體 包括TE0S和氧的混合物,或氧、矽烷和選用之二硼烷 (B#6)、磷烷(PH3)、及氧化亞氮(n2〇)的混合物,且較好 是TE0S 。 沈積至基板表面上的CVD塗層數量正比於所想要的膜厚 ’且該膜厚可從約1000埃變化至約3〇〇〇〇埃,較好是從约 3 000埃變化至約800〇埃。施加至基板的cvd數量可根據想 要之膜厚而改變。獲得這些厚度所需要的氣體流量説明於 ---- - - 12 - 本紙張尺纽财) Α4·ΤΤΓ〇χ黯釐) —'''·- ---------^-- (請先βί讀背面%/注意事^-.%寫本頁) 、-0 線 ^〇87〇g A7-The Ministry of Economic Affairs Central Bureau of Standards and Labor under the Consumer Cooperative Printed a graph of F Τ I R spectral absorption versus wave number (丨 / cm). Figure 11 Graph of F T I R spectral absorption versus wave number (i / cm) of aging treatment film using electron beam hardening in the presence of various milk bodies. Fig. 12 Cumulative probability of time to breakdown (QBD for short) with electron beam hardening gate oxide of SOG covered with tetraethyi orthosilicate (TEOS for short) ) The graph of the crash time (seconds). Figure 13 is the depth (microns) of the depth profile analysis of the secondary ion mass spectroscopy (hereinafter referred to as SIMS) through the thickness of the oxides of sodium, potassium, hydrogen, carbon, and oxygen impurities. The graph of concentration (atoms / cubic centimeter). DESCRIPTION OF PREFERRED EMBODIMENTS Unless otherwise indicated, all reference numerals in this document indicate weight. As used herein, "quote" should refer to the dose of electron beam radiation. Various materials can be applied to the substrate of the present invention via "spin coating", CVD, or growth techniques. Suitable dielectric materials or SOGs that can be spin coated onto the substrate include silicates, phosphosilicates , Siloxanes, Phosphosiloxanes and mixtures thereof. Siloxanes are preferred. The more preferred silicones are amorphous, cross-linked glass-type materials with the chemical formula SiOx, Where X is greater than or equal to 1 and less than or equal to 2, and has "pre-exposure" inclusions, which are from about 2% to about 90% based on the total weight of the silicone material, and Preferably, the organic group composition is from about 10% to about 25%, such as an alkyl group having from about 1 to about 10 carbons, an aromatic group having from about 4 to about 10 carbons, having from -10-This paper uses the Chinese National Standard (CNS) Α4 specification (2 丨 〇'〆297mm) --------- private clothing ----- 1T ------ α {(Please read the notes on the back I% to write this page first) A7- B7 Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of invention (8 aliphatic groups of about 4 to about 10 carbons, And its mixture Alternatively, silicone and silicate materials are also possible, based on the total molar percentage of the dielectric material, including from about 0% to about 10%, and preferably from about 2% to Approximately 4% of scales. The preferred silicone materials suitable for use in the present invention are commercially available from Rexon (8-11-1 with 51 corrections 311 ^), with, heart (; 1 ^ 355, @ The trade name of a suitable silicone material contains about 100 parts per billion or less, preferably 50 parts per billion or less, and more preferably 10 parts per billion or less. Trace element impurities such as sodium, potassium, gas, nickel, magnesium, chromium, copper, manganese, iron, and the like, and preferably have from about 300 to about 5,000, more preferably from about A molecular weight between 500 and about 1,000 molecular weight units. The dielectric material can be applied to the substrate via conventional spin coating, dip coating, sprinkling, or meniscus coating methods that are well known in the art The details of this type of method are described in, for example, "Processing Equipment and Automation Systems" published by Integrated Technology. The thickness of the dielectric film on the substrate can be applied to the substrate. However, typically, the thickness can vary from about 500 angstroms to about 0 angstroms, and preferably from about 3,000 angstroms to about 9000 angstroms. The amount of sOG liquid applied to the substrate can range from about 1 angstrom! It varies from milliliters to about 10 milliliters, and preferably from about 2 milliliters to about 8 milliliters. In a preferred embodiment, the silicone material is applied to the substrate from the center, and then at about 500 revolutions per minute and Between about 6000 revolutions per minute, preferably between about 1500 revolutions per minute and about 4000 revolutions per minute, the substrate is rotated at a varying speed for about 5 to about 60 seconds, preferably about 10 to about 3 〇Seconds, to dissolve __-_ 11 ~ This paper is suitable for CNS A4 specifications (21GX297mm). (Please read the back side of the * Notes first. Write this page on the board)-Order — Printed by the Central Sample Bureau of the Ministry of Economic Affairs, Beigong Consumer Cooperative, 3087〇9 A7- _________B7 V. Description of the invention (9) The liquid is evenly distributed on the surface of the far substrate. Suitable materials that can be deposited on the substrate via CVD include plasma-enhanced tetra-ethyl ortho silicate (hereinafter referred to as PETEOS), silane-based oxides such as silane and disilane, boron-zushi 8¾ salt glass (bo-ron-phosphosilicate glass, hereinafter referred to as BPSG) 'pulverized § £ salt glass (ie 11〇5 弩 1105 丨 1 丨. 316 Lu 1355, hereinafter referred to as 1 > 5〇), such as silicon nitride ( SiN) nitrides and non-stoichiometric mixtures containing the nitrides, anhydrous films, such as those deposited using silane (SiH4), ammonia (NH3), nitrogen and nitrous oxide (N2 0) and mixtures thereof Oxynitride, and boron-phosphorus glass from tetraethyl orthosilane (hereinafter referred to as BPTEOS), and mixtures thereof. Silicon oxide film is preferred. The CVD film can be applied to the substrate in the presence of a gas via a conventional CVD method well known in the art. The details of this type of method are well known in the art and are described in, for example, the works of Josica; Ken, and Mei Tiesen, which are incorporated herein by reference. The gas chosen for CVD applications depends on the type of film desired, but typically, such gases include a mixture of TEOS and oxygen, or oxygen, silane, and diborane (B # 6), phosphorus A mixture of alkane (PH3) and nitrous oxide (n2〇), and preferably TEOS. The number of CVD coatings deposited on the substrate surface is proportional to the desired film thickness and the film thickness can vary from about 1000 angstroms to about 3,000 angstroms, preferably from about 3,000 angstroms to about 800 〇Angstroms. The number of cvd applied to the substrate can be changed according to the desired film thickness. The gas flow rate required to obtain these thicknesses is shown in ------12-this paper ruler and money) Α4 · ΤΤΓ〇χ 暗%) — '' '·---------- ^- (Please read βί on the back of the page first / note ^-.% To write this page), -0 line ^ 〇87〇g A7-

經濟部中央標準局as:工消費合作社印裝 月心:喬西卡;和梅逖森著作中。 典型而言’將SOG或CVD膜施加至,並將超'薄氧化物或 化物膜成長於’晶圓或其他平面基板上,諸如具有電路 圖樣於冗們表面上的矽晶圓,以將其處理進I C或其他微電 子裝置。典型而言,基板的直徑從約2英吋變化至約12英 叫· ’雖然本發明對較大的基板仍然會有效。 可選擇地,塗覆有預硬化S0G的基板可在約5 〇。〇至約 25(TC的溫度下加熱約i至約3分鐘。在較佳具體實施例中 ,首先將預硬化的S 〇 G在約5 〇。(:下加熱约3 〇秒至一分鐘 ,然j在約150T:下加熱約3 〇秒至一分鐘,並在約25(^下 加熱第三次’持續約3 0秒至一分鐘。這樣加熱的結果,該 預硬化之液體SOG材料部分地交鏈且固化。 塗覆有SOG的基板藉由在選自含有氧、氬、氮、氦和其 中之混合物,且較好是氧、A、氮、和其中之混合物,之 群體的氣體存在下’將基板表面暴露至電子流量而加以硬 化。鼠氣是更好的。 電子束曝照進行的溫度將視最終形成膜的預期特性及想 要之處理時間的長度而定。在該技藝中具普通技能者可輕 易地使曝照條件最佳化,以得到所宣稱的結果,但溫度一 般而言,將在約25°C至約40(TC的範圍内。電子束硬化期 間的壓力將在從約I 0毫托耳至約2〇〇毫托耳,且較好是從 約1 0党托耳至約4 0毫托耳,之間變化。 電子束曝照的時間將與施加至基板的電流密度和電子束 劑量有關。在該技藝中具有普通技能者可輕易地使曝照條 -13 本紙張尺度適用中國國家標準(CNS ) A4規格(210 x297·^ ¾-- f靖先蚜讀背面<'注意事1%寫本頁} II-------------------- V. - ί —II I -- A7- A7- 經濟部中央樣準局員工消費合作杜印製 五、發明説明(11 ) 件最佳化,以得到所宣稱的結果,但一般而言, 至約50000 ’較好是從約2500至約10000微庫侖/平方 ,疋電子束劑量的應用之下,曝照將從約2變化至約4 5八 鐘’且較好是從約5變化至約25分鐘。電子束的加速電: 可從約1變化至約25仟電子伏特。劑量數量和所選擇的加 速電壓將與要處理之膜的特性和厚度有關。 已塗覆的SOG基板可在任何具有提供電子束輻射至放置 其内之基板之裝置的處理室中暴露至電子束。典型而士, 該處理室也配備有發射電子進入含有氧、氬、氮' 氦和其 中 < 混合物,且較好是氧、氬、和氮,之氣體氛圍的裝置 ,同時配備有電子束曝照。 在較佳具體實施例中,將已塗覆的S〇G基板置入可從加 州聖地牙哥電子視像(Electron Vision)公司購得,商品名稱 爲’’Electr〇nCure”TM,的處理室中,該處理室的操作原理 和性能特性説明於美國專利號碼5,00 1,1 78中,其以參考之 方式併入於本文中。這個處理室有利地提供"寬、大的電 子束"’該電子束可影響從約4至約144平方英吋的面積。 類似地,塗覆有CVD的膜經由硬化塗覆有SOG之膜所說 明之相同的製程,並在相同的條件下退火。 在將超薄閘極氧化物或氮化物成長於基板上的諸應用中 ’所成長之膜的類型視基板的組成和在選定之氣體狀態中 所成長的物質而定。任何諸如砷化鎵(GaAs)的組成,或者 諸如結晶矽、多晶矽、非晶質矽、或磊晶矽,且較好是二 氧化矽(Si02),的含矽組成是合適的基板材料。氧化物或 -14- 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) ---------私衣------ΐτ------0 (請先閱讀背面之注意事項、%寫本頁) 一 經濟部中央標準局員工消費合作社印袈 '、發明説明(12 ) 氮化物的成長在氧、氨、氮、氧化亞氮、及其中之反應產 物和混合物以氣體、昇華之固體或蒸發之液體的型式存在 時發生。氧氣是較佳的。 根據本發明,將氧化物或氮化物超薄膜層成長於基板表 面上,同時在氣體存在下將它暴露至電子束。電子束曝照 時間持續足以容許該氣體同時離子化並與存在於基板表面 上之化合物反應的時間。成長的膜厚度可從約10埃變化而 約1000埃,且較好是從約5 〇埃變化至約8 〇埃。其他方面 ,成長這種氧化物或氮化物超薄膜層的製程和條件類似於 硬化塗覆有SOG之基板所説明的那些。結果,組成的均勻 性和所成長於基板上之超薄氧化物或氮化物膜的厚度兩者 都受到改善。 根據本發明暴露已塗覆之基板至電子束輻射的結果,產 生於其上的膜非預期地受到改質,成爲一種新的、單一的 化學型態。例如’,,FTIR"分析報告出,在將s⑽起始化合 為以電子束硬化之後,不再有c H基連結於它們的主鏈3 然:,一次離子質譜術(Sec〇ndary I〇n Mm Speetr〇sc〇py ’下文簡稱SIMS)分析證明出,碳留存在該膜中。與在硬 化塗層或膜之上層〇.〇5纽3微米中擁有已氧化之竣的孰硬 化塗層相比較’在本發明之硬切氧燒s〇g及含硬s〇p塗 層中的瑗均勻地分佈於整個膜中。 塗覆有根據本.發明所處理之膜的基板可用於微電子製造 中的任何介電及平面化應用。根據本發明所處理之⑽塗 層的-個値得-提的特性是,它們展現出優異的介電性質 本紙張尺度逋财關緖準( 私衣------1T------^ (請先閱讀背面之注意事項/ 卞寫本頁) 3〇S7〇gThe Central Bureau of Standards of the Ministry of Economic Affairs as: Printed by the Industrial and Consumer Cooperatives. Moon Heart: Josica; and Mei Tisen's works. Typically, 'apply an SOG or CVD film to and grow an ultra-thin oxide or compound film on a wafer or other planar substrate, such as a silicon wafer with circuit patterns on the surface Process into IC or other microelectronic devices. Typically, the diameter of the substrate varies from about 2 inches to about 12 inches. 'Although the present invention will still be effective for larger substrates. Alternatively, the substrate coated with pre-hardened SOG may be around 50 °. 〇 to about 25 (TC temperature is heated from about i to about 3 minutes. In a preferred embodiment, first pre-hardened S 〇G at about 50. (: heating for about 30 seconds to one minute, However, at about 150T: heating for about 30 seconds to one minute, and heating for about 30 seconds to one minute at about 25 ° C. As a result of this heating, the pre-hardened liquid SOG material portion The ground is cross-linked and cured. The SOG-coated substrate is present in a group of gases selected from the group consisting of oxygen, argon, nitrogen, helium, and mixtures thereof, preferably oxygen, A, nitrogen, and mixtures thereof. Next, the substrate surface is exposed to electron flux to harden it. Rat gas is better. The temperature at which electron beam exposure is performed will depend on the desired characteristics of the final film formation and the length of the desired processing time. In this technique Those with ordinary skills can easily optimize the exposure conditions to obtain the claimed results, but the temperature will generally be in the range of about 25 ° C to about 40 ° C. The pressure during electron beam hardening will From about 10 mTorr to about 200 mTorr, and preferably from about 10 mTorr It varies from about 40 mTorr. The time of electron beam exposure will be related to the current density and the electron beam dose applied to the substrate. Those with ordinary skills in this skill can easily make the exposure strip The paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210 x297 · ^ ¾-- f Jingxian aphid read the back < 'Note 1% write this page} II ------------- ------- V.-ί —II I-A7- A7- Employee's consumption cooperation of the Central Prototype Bureau of the Ministry of Economic Affairs. Printing 5. Description of invention (11) Optimization of the pieces to get the declared results , But generally speaking, up to about 50000 'is preferably from about 2500 to about 10000 microcoulombs / square. Under the application of electron beam dose, the exposure will vary from about 2 to about 4 5 eight minutes' and better It varies from about 5 to about 25 minutes. Electron beam acceleration: can be changed from about 1 to about 25 thousand electron volts. The dose amount and the selected acceleration voltage will be related to the characteristics and thickness of the film to be processed. The coated SOG substrate can be exposed to the electron beam in any processing chamber having a device that provides electron beam radiation to the substrate placed therein. The chamber is also equipped with a device that emits electrons into a gas atmosphere containing oxygen, argon, nitrogen, helium and a mixture therein, and preferably oxygen, argon, and nitrogen, and is also equipped with electron beam exposure. In the embodiment, the coated SOG substrate is placed in a processing chamber commercially available from Electron Vision, San Diego, Calif., Under the trade name "ElectronCure" TM, and the processing The operating principle and performance characteristics of the chamber are described in US Patent No. 5,00 1,178, which is incorporated herein by reference. This processing chamber advantageously provides " wide, large electron beams " ' The electron beam can affect an area from about 4 to about 144 square inches. Similarly, the CVD-coated film undergoes the same process as described for hardening the SOG-coated film, and is annealed under the same conditions. In applications where ultra-thin gate oxides or nitrides are grown on the substrate, the type of film grown depends on the composition of the substrate and the substance grown in the selected gas state. Any composition such as gallium arsenide (GaAs) or silicon-containing composition such as crystalline silicon, polycrystalline silicon, amorphous silicon, or epitaxial silicon, and preferably silicon dioxide (Si02), is a suitable substrate material. Oxide or -14- This paper scale is applicable to China National Standard (CNS) A4 specification (210X297mm) --------- private clothing ------ lτ ------ 0 (please Read the precautions on the back and% to write this page) 1. Employee Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs of the People's Republic of China, 'Invention Description' (12) The growth of nitrides in oxygen, ammonia, nitrogen, nitrous oxide, and reaction products And the mixture occurs in the form of gas, sublimated solid or vaporized liquid. Oxygen is preferred. According to the present invention, an oxide or nitride ultra-thin film layer is grown on the surface of the substrate while exposing it to an electron beam in the presence of gas. The electron beam exposure time lasts for a time sufficient to allow the gas to ionize simultaneously and react with the compounds present on the substrate surface. The thickness of the grown film can vary from about 10 angstroms to about 1000 angstroms, and preferably from about 50 angstroms to about 80 angstroms. Otherwise, the processes and conditions for growing such an oxide or nitride ultra-thin film layer are similar to those described for hardening SOG-coated substrates. As a result, both the uniformity of the composition and the thickness of the ultra-thin oxide or nitride film grown on the substrate are improved. As a result of exposing the coated substrate to electron beam radiation according to the present invention, the film produced thereon is unexpectedly modified to become a new, single chemical form. For example, ", FTIR" analysis reports that after the initial combination of s⑽ to be electron beam hardened, there are no longer c H groups attached to their main chain. However, primary ion mass spectrometry (Secondary I〇n Mm Speetroscope (hereinafter referred to as SIMS) analysis proved that carbon remained in the film. Compared with the hardened coating with an oxidized finish in a layer of 0.05 mm and 3 microns above the hardened coating or film 'in the hard-cut oxygen-fired sog and hard sop-containing coatings of the present invention The 瑗 is evenly distributed throughout the membrane. The substrate coated with the film processed according to the invention can be used for any dielectric and planarization applications in microelectronic manufacturing. The characteristics of the coatings treated according to the present invention are that they exhibit excellent dielectric properties. The paper standard is related to financial standards (private clothing ----- 1T ---- -^ (Please read the notes on the back first / Bian write this page) 3〇S7〇g

五、發明説明(13 經濟部中央標準局員工消費合作社印製 ,而無須添加額外的聚合物給它們。根據本發明所硬化之 SOG或S0P塗層的介電性質在約25至約3 3之間變化,較 好是在約2.9至約3.0之間。 根據本發明所處理之膜的另一個値得一提的特點是,它 們的密度由於電子束處理步驟的結果而顯著地増加。此外 ’孩處理過的膜塗層不僅在5〇 : 1緩衝氧化物蝕刻 (Buffered Oxide Etch,下文簡稱b〇e )中具有可與熱氧化 物所記綠者相比較的濕式蝕刻速率,而且該膜也對氧電漿 具有抵抗力,能夠加以化學性及機械性地抛光,而具有良 好的均勻度’且能夠忍受與典型之w充填物處理有關的溫 度預估値。更明確地説’根據本發明所硬化且接著在425 C暴露至氮1小時的矽氧烷塗層只收縮* %,且當將該膜在 700 C暴露長達1小時的時候,沒有另外的收縮發生。 對沈積的氧化物而言,本發明提供一種方法,以產生緻 密化的膜而毋需使用高溫退火。更明確地説,折射率分析 顯示出’根據本發明之製程將由PETEOS組成之CVD膜退 火的結果是”富含矽”的膜,該結果無法透過其他在該技藝 中爲人所知的方法,諸如在膜沈積或熱退火期間之氣體比 例的調整,而獲得。這是特別有利的,因爲這種"富含矽" 的膜據知可防止場反轉及熱電子劣化效應。 再者,不僅本發明之處理發生的溫度遠低於先前技藝熱 硬化或退火製程中所使用者,而且硬化或退火這類膜的時 間也顯著地降低。 _ 本發明的使用也爲基板造成改良的超薄膜氧化物或氮化 -16- 木纸張尺度適用中國國家梂準(CNS ) A4規格(2lOX 297公资) ----------私衣------,玎------# . ί (請先閱讀背面之注意事項_.¼寫本頁) A?- ------------ B7 五、發明説明(μ )~~" ~ ' ~~-- 物塗層,因此這類氧化物或氮化物的成長得以受到控制。 本發明可併入於幾個爲人所知的製程,諸如:可隨意 配置的後處理;2 )傳統地蝕刻的接觸處理;及3 )金屬間介 電處理》 :列之非限定的諸實例例示出,將已塗覆基板暴露至電 子束輻射以在基板上產生具有改良特性之膜的效果。 在下列實例中所產生的膜根據以下的測試方法加以分析 1) 膜厚:使用可從毫微計量(Nanometncs)公司購得之經過 校正的Nanospec® AFT 010_180型電腦化膜厚量測系統 ,使從約480毫微米至790毫微米的波長掃描過晶圓’ 並經由它的内部電腦轉換成埃(八)。在晶圓五個不同位 置上的量測受到要求,然後將這五個數値平均。 2) 膜收縮百分比:這個數値是由根據在膜厚測試中説明之 程序所獲得的厚度量測値和在各個處理步驟之後所記錄 者的比例得到。 3 )濕式触刻速率測定:進行這項測試的細節説明於列訊公 司,高級微電子材料部門的一份報告,,相對蝕刻速率測 定”(1995年1 1月3 0曰)中。 4 )介電常數:SOG膜的介電常數以標準的電容_電壓(c v) 曲線技術測定’使用如同任何其他介電薄膜所會使用的 金屬-氧化物半導體(metal-oxide semiconductor,下文 簡稱MO S)電容器結構。介電常數由自CV曲線而得來 的C (取大値)/ C (氧化物),量測到的膜厚,及電容器平 _ -17-_ 本紙張尺度適用中國國家標隼(CNS ) A4規格(210X297公竣) ~ — * HI HI . ^-- (請先蚜讀背面之注意事无.^寫本頁)V. Description of the invention (13 Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs, without the need to add additional polymers to them. The dielectric properties of the SOG or SOP coatings hardened according to the present invention range from about 25 to about 33 The variation between is preferably between about 2.9 and about 3.0. Another unique feature of the films treated according to the present invention is that their density is significantly increased as a result of the electron beam processing step. The film coating processed by the child not only has a wet etching rate comparable to that recorded by thermal oxide in 50: 1 Buffered Oxide Etch (hereinafter referred to as boe), but also the film It is also resistant to oxygen plasma, can be chemically and mechanically polished, and has good uniformity 'and can tolerate the temperature prediction value associated with typical w filler treatment. More specifically, according to this The silicone coating hardened by the invention and then exposed to nitrogen at 425 C for 1 hour only shrinked by *%, and when the film was exposed at 700 C for up to 1 hour, no additional shrinkage occurred. Oxidation of the deposit In terms of things The present invention provides a method to produce a densified film without the use of high temperature annealing. More specifically, refractive index analysis shows that the result of annealing the CVD film composed of PETEOS according to the process of the present invention is "rich in silicon" Film, the result cannot be obtained by other methods known in the art, such as adjustment of the gas ratio during film deposition or thermal annealing. This is particularly advantageous because this " rich in silicon The " film is known to prevent field reversal and thermal electron degradation effects. Furthermore, not only does the process of the present invention occur at temperatures much lower than those used in prior art thermal hardening or annealing processes, but also hardens or anneals such films The time is also significantly reduced. _ The use of the present invention also results in an improved ultra-thin film oxide or nitride on the substrate-16- Wood paper scale is applicable to China National Standards (CNS) A4 specification (2lOX 297 public funds)- -------- private clothing ------, 玎 ------ #. Ί (please read the notes on the back _.¼ to write this page) A?------ ------- B7 5. Description of the invention (μ) ~~ " ~ '~~-Object coating, so this type of oxidation The growth of metal or nitride can be controlled. The present invention can be incorporated into several well-known processes, such as: post-processing that can be arbitrarily configured; 2) traditionally etched contact processing; and 3) intermetal dielectric Treatment >>: The non-limiting examples of the column illustrate the effect of exposing the coated substrate to electron beam radiation to produce a film with improved characteristics on the substrate. The films produced in the following examples were analyzed according to the following test methods 1) Film thickness: A calibrated Nanospec® AFT 010_180 computerized film thickness measurement system available from Nanometncs was used to make A wavelength from about 480 nm to 790 nm is scanned across the wafer 'and converted into angstroms (A) by its internal computer. Measurements at five different locations on the wafer are required, and then these five values are averaged. 2) Percentage of film shrinkage: This value is obtained from the thickness measurement value obtained according to the procedure described in the film thickness test and the ratio of those recorded after each processing step. 3) Wet touch rate determination: The details of performing this test are described in a report by Lexicon, Advanced Microelectronics Materials Division, Relative Etch Rate Measurement "(January 30, 1995). 4 ) Dielectric constant: The dielectric constant of the SOG film is determined by the standard capacitance-voltage (cv) curve technique 'use a metal-oxide semiconductor (MOS), which will be used like any other dielectric film, hereinafter referred to as MOS ) Capacitor structure. The dielectric constant is C (take large value) / C (oxide) derived from the CV curve, the measured film thickness, and the capacitor level _ -17-_ Falcon (CNS) A4 specification (210X297 public completion) ~ — * HI HI. ^-(Please read the notes on the back of the aphid first. ^ Write this page)

'1T 經濟部中央標準局員工消费合作社印裝 A7- B7 經濟部中央標準局貝工消费合作社印裝 五、發明説明(15 ) 板(链點)面積加以計算a 使用主要含有敏感的多頻(1 〇千赫茲_丨〇百萬赫茲)電感 電容及電阻(Induction Capatance and Resistance,下文 簡稱LCR)計' 電流及電壓源、斜波產生器、和微微安 培計的惠普4061A型半導體量測系統,以量測介電膜的 C V西線。量測、計算、和增圖功能以專用的惠普微電 腦透過IEEE-488標準介面匯流排進行。基板在放置於 金屬暗箱内的手動偵測平台上接受偵測。這個步驟的進 一步細節説明於列訊公司,高級微電子材料部門所報告 的"SOG介電常數理論"(i 995年1月3日)中。 5) 折射率··這項數値使用可自魯道夫研究(Rud〇lph Research)公司構得之校正過的Aut〇EL ιι®3〇7修正型橢 率計。校正和量測程序説明於列訊公司,高級微電子材 料部門所報告的"AutoEL II 307修正型橢率計校正與維 護"(1995年6月5曰)中。 6) 傅立葉轉換紅外光譜分析:傅立葉轉換紅外光譜分析顯 示出分子中原子的振動。某些族的原子具有存留於不同 化合物中的特性振動頻率》諸如有些有機矽群體之紅外 光波段特性之頻率位置的細節説明於,例如,勞纳 (Launer) ’ "有機矽化合物的紅外光分析:光譜-結構交 互作用(1990年’無約,焦丘(Burnt Hills))中。 7) 接觸阻抗:接觸阻抗程序説明於羅(L〇h),W_M_等人 ,’’接觸阻抗的模型建立與量測,2中,國際電子及電機 工程學會會報電子裝置512期(1987年3月)。 -18 各紙張尺度適用中國國家標準(CNS ) A4規格ΥΤΪ0Χ297公釐) ---------装------1T------^ ί (請先¾讀背面之注意事¾¼寫本頁) 經濟部中央標準局員工消費合作社印製 A7· B7 五、發明説明(16 ) 8) 裝置及場起始電壓和電晶體電壓(Vts):這些電壓量測 及獲得這種量測値的技術類似於在諸實例中所使用的那 些,該諸實例說明於安多(And〇h),τ等人,,,低電壓 MOSFETS的設計方法論"中,國際電子裝置會議〇994 年1 2月)。 9) 崩潰時間(QBD):這項程序説明於葛洛夫((}r〇ve ),半 導體裝置物理與技術,第10·5節(1967年紐約):陳, K.L.等人,國際電子裝置會議技術文摘484期(1986年) ;及勞恩區利(R0untree),RN ,國際電子裝置會議技 術文摘580期(1988年)。 10) 通孔阻抗:通孔阻抗使用説明於極大型/超大型積體電 路多層互連研討會(1 995年2月)之"旋轉於玻璃上平面 化製程中通孔信賴性強化之通孔接觸的預濺鍍除氣處理 ”中的技術加以量測。 11) 阻抗及矽化物阻抗:矽化物阻抗使用説明於清水 (Shimizu),S .等人,"用於高性能及高信賴性的〇 15 微米CMOS製程"中,國際電子裝置會議(1 994年1 2月) 〇 12) 二次離子質譜術(secondary Ion Mass Spectroscopy,下 文fcl稱SIMS) : SIMS分析用以決定微量元素在s〇g膜 中的存存。首先,使用具有十億分之幾偵測極限的卡默 卡(Cameca) SIMS裝置量測SOG膜。阻抗式陽極編碼器 (resistive anode encoder,下文簡-稱RAE)離子顯像偵測 器的使用接收來自卡默卡裝置的輸入’並隨著用以產 ---------扣衣------ΐτ------^ , ί (請先陴讀背面·<:注意事¾.¼寫本頁)'1T Printed and printed A7-B7 of the Central Bureau of Standards, Employee and Consumer Cooperative of the Ministry of Economic Affairs. Printed and printed on the Peking Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. 5. Description of the invention (15) The area of the board (chain point) is calculated. 1 〇 KHz _ 丨 〇 megahertz) Inductance capacitance and resistance (Induction Capatance and Resistance (hereinafter referred to as LCR) meter 'current and voltage source, ramp generator, and picoammeter HP 4061A semiconductor measurement system, To measure the CV west line of the dielectric film. The measurement, calculation, and drawing enhancement functions are performed on the dedicated HP microcomputer through the IEEE-488 standard interface bus. The substrate is detected on a manual detection platform placed in a metal black box. Further details of this step are described in the "SOG Dielectric Constant Theory" (i January 3, 995) reported by Lexicon, Advanced Microelectronics Materials. 5) Refractive index ... This value uses a corrected Aut〇EL ιι®307 square ellipsometer, which can be constructed from Rudolph Research. The calibration and measurement procedures are described in the "AutoEL II 307 Modified Ellipsometer Calibration and Maintenance" reported by Lexicon, Advanced Microelectronics Materials Department (June 5, 1995). 6) Fourier transform infrared spectroscopy: Fourier transform infrared spectroscopy shows the vibration of atoms in the molecule. Atoms of certain groups have characteristic vibration frequencies that exist in different compounds. Details such as the frequency position of infrared band characteristics of some organosilicon groups are described in, for example, Launer '" Infrared Light of Organosilicon Compounds Analysis: Spectral-Structure Interactions (1990 'Wuyue, Burnt Hills). 7) Contact impedance: The contact impedance procedure is described in Luo (L〇h), W_M_ et al., ”Modeling and measuring of contact impedance, 2nd, International Society of Electronics and Electrical Engineering Reports 512 (1987) March). -18 Each paper size is applicable to the Chinese National Standard (CNS) A4 specification ΥΤΪ0Χ297 mm) --------- 装 ------ 1T ------ ^ ί (please read ¾ first Matters needing attention ¾¼ write this page) A7 · B7 printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Invention description (16) 8) Device and field starting voltage and transistor voltage (Vts): These voltages are measured and obtained The measurement techniques are similar to those used in the examples, which are illustrated in Andoh, τ et al., "Design Methodology of Low Voltage MOSFETS", International Electronic Device Conference 〇994 1 February). 9) Time to collapse (QBD): This procedure is illustrated in Grove ((} r〇ve), Semiconductor Device Physics and Technology, Section 10 · 5 (New York, 1967): Chen, KL et al., International Electronic Devices Conference Technical Digest 484 (1986); and Ronuntree, RN, International Electronic Devices Conference Technical Digest 580 (1988). 10) Through-hole impedance: Through-hole impedance is used for very large / super The technology in the "Multiple Interconnect Seminar on Large Integrated Circuits (February 1 995)" was measured by the technique of "pre-sputtering degassing treatment for through-hole contacts with enhanced through-hole reliability during the planarization process on glass" 11) Impedance and Silicide Impedance: The instruction of Silicide Impedance is used in Shimizu, S. et al. &Quot; for 0.15-micron CMOS process with high performance and high reliability ", International Electronic Device Conference ( 1 February 994) 〇12) Secondary Ion Mass Spectroscopy (secondary Ion Mass Spectroscopy, hereinafter referred to as fcl SIMS): SIMS analysis is used to determine the presence of trace elements in the SG film. First, use a billion Cameca SIMS Set up and measure SOG film. The use of resistive anode encoder (hereinafter referred to as RAE) ion imaging detector receives input from the Camerka device and is used to produce ----- ---- Buttons ------ lsτ ------ ^, ί (please read the back first <: Note ¾.¼ write this page)

經濟部t央棣準局員工消費合作社印製 五、發明説明(17 膜表面上任何元素之直技盐2、 八仗士、 妾離子为佈圖像和在該元素橫向 仝伟中疋變化的時間,收 收集諸如微量離子元素濃度的數 據成馬膜深度的函數s ::析使™6_型四極質讀儀實施,在該儀器中 ::暴:至具有6什電子伏特之淨衝擊能量的氧和铯一次 離子撞擊,以同時獲得正夺& _ 負—,入離子質譜圖。分析條件 報告於表格1中。 表格1Printed by the Employee Consumer Cooperative of the Ministry of Economic Affairs of the Ministry of Economic Affairs 5. Description of the invention (17 direct technical salt of any element on the surface of the film 2, the eight soldiers and concubine ions are cloth images and the time when the element changes horizontally, Collect data such as trace ion element concentration as a function of horse film depth s :: analysis using ™ 6_ type quadrupole mass reader, in this instrument :: burst: to oxygen with a net impact energy of 6 eV One ion collision with cesium to obtain positive & _ negative-, and enter the ion mass spectrum. The analysis conditions are reported in Table 1. Table 1

劑量I離子佈植標準物之分析所得到的相對敏感度係數 (relative sensitivity factors,下文簡 '稱 RSFs )爲基礎。分析 者的二次離子計數與整個氧化物的平均矩陣3〇si訊 成 1 ----------裝 i --線 . ί (請先閣讀背面之注意事項r™\寫本頁) _The relative sensitivity factors (hereinafter referred to simply as RSFs) obtained from the analysis of dose I ion implantation standards are based. The secondary ion count of the analyst and the average matrix of the entire oxide 3〇si information into 1 ---------- install i-line. Ί (Please read the notes on the back r ™ \ write This page) _

3〇87〇9 A7- B7 五、發明説明(18 I-- (請先閱讀背面之注意事^-.%寫本頁) 比値。分析的再現性在1 X 103以上的離子計數速率下,典 型小於± 10%。濺鍍深度藉由使用Tencor P-ίο表面測定器 量測凹孔深度而校正。這項技術的另外特性進—步説明於 查理斯伊凡斯及贊助者(Charles Evans and Associates)所發 行的小册(1993年1 0月)中。 實例 實例1 :塗覆有S0G之基板的製備 將具有6英忖直徑的ί夕晶圓以可從列訊公司購得,商品 名稱爲"Accuglass" ® 3 1 1的矽氧烷s〇G,藉由噴灑約3毫 升至約4耄升的S0G到晶圓表面上,,然後在可從大曰本印 刷公司購得的SOG塗佈機軌道上以72 T、20-30毫米汞柱 、及40%之旋轉罩板溼度下每分鐘約35〇轉旋轉2秒,而加 以塗覆。在該已塗覆晶圓於類似條件下,以约每分鐘3 〇 〇 〇 轉另外旋轉約2 0秒之後’使晶圓於大曰本印刷之s 〇 g塗佈 機軌道中的熱平台上加熱,分別在8 (TC、12〇。(:及175°C下 持續三個120秒的連續時段。 實例2 :塗覆有S Ο Θ之晶圓的熱硬化f比較性、 經濟部中央標率局員工消費合作社印製 然後將根據實例1所產生的一片晶圓在可從M R L工業公 司購得的Black-Max型壚子中,於425°C及1大氣壓氮的存 在下硬化L丨、時。 最終形成之已塗覆晶圓的分析出3000埃的膜厚(硬化後) 、7%的膜收縮、及約37埃/秒旳濕式蝕刻速率。 覆有sog之晶圓的電子走荈化 將根據實例1所產生的諸晶圓置入可從電子視像公司購3〇87〇9 A7- B7 5. Description of the invention (18 I-- (please read the notes on the back ^-.% To write this page first) ratio. The reproducibility of the analysis is at an ion count rate of 1 X 103 or more , Typically less than ± 10%. Sputtering depth is corrected by measuring the depth of the recessed hole using a Tencor P-ίο surface measuring instrument. Additional features of this technology are further explained by Charles Evans and the sponsor (Charles Evans and Associates) in the booklet (October 1993). Examples Example 1: Preparation of SOG-coated substrates will have 6-inch diameter wafers that are commercially available from Lexicon. The name "Accuglass " ® 3 1 1 silicone SG is sprayed on the surface of the wafer by spraying about 3 ml to about 4 liters of SOG, and then can be purchased from the Japanese printing company. The SOG coater track is coated with 72 T, 20-30 mm Hg, and 40% humidity of the rotating cover plate at about 35 ° revolutions per minute for 2 seconds. The coated wafers are similar Under the conditions, after rotating at about 3,000 rpm for about 20 seconds, the wafer was printed on a large-scale coating machine rail. Heating on the hot platform in the, respectively at 8 (TC, 12〇. (: And 175 ° C for three consecutive periods of 120 seconds. Example 2: The thermal hardening of the wafer coated with S Θ Θ 、 Printed by the Employee Consumer Cooperative of the Central Standardization Bureau of the Ministry of Economic Affairs, and then a wafer produced according to Example 1 is present in Black-Max-type Luzi available from MRL Industries, at 425 ° C and 1 atmosphere of nitrogen Under hardening L, when. The final formed coated wafer analyzed a film thickness of 3000 angstroms (after hardening), 7% film shrinkage, and a wet etching rate of about 37 angstroms / second. It is covered with sog The electronic transformation of wafers puts the wafers produced according to Example 1 into the electronic video company

經濟部中央標準局貝工消費合作社印製 A7 B7 五、發明説明(19 ) 得,商品名稱爲ElectronCureTM的處理室中,並分別在包 括氮、氧、氬、及览之各種氣體的存在下,且在從25至 40(TC的溫度及從1〇變化至40毫托耳的壓力之下,將其暴 露至具有8至20毫安培之電流,從1〇〇〇至1〇〇〇〇微庫侖/平 方厘米之劑量’及從5至2 5仟電子伏特之加速電壓的電子 束。 塗覆有電子束硬化SOG之晶圓的分析指出ι〇_3〇0/〇的膜收 縮,及在50: 1(去離子水:氫氟酸(HF))溶液之緩衝氧化 物蚀刻中1 -1 1埃/秒的濕式姓刻速率,視所選定的劑量、 能量和溫度而定。 圖1圖示根據實例2之熱硬化,根據實例3之電子束硬化 ’及根據實例1之未硬化,即熱烘烤,晶圓的FTir光譜。 如同在圖1之FTIR光譜中代表c Η伸展模式之吸收增加的 缺乏,以及在圖13之SIMS光譜中之由竣波峰所表示的碳 均勻分佈所證實’曝照至電子束處理後的膜組成已經改變 且水不爲其吸收於其中,是顯而易見的。 宣列4 : i變化之溫度和電子束劑量下硬化的晶圓 晶圓根據實例1而產生且根據實例3而硬化,除了在氬氣 存在下’於25C、250C、或40〇-C的溫度之下,以1 0仟 電子伏特的能量’將每—片晶圓暴露至1000、3000、5000 、或10000微庫命/平方厘米四種劑量的一種之外。 圖2⑷和2 (b)圖示根據實例4所產生之每一片晶圓的FTIR 光績。如同圖2 (a)中在3600和3700厘米-1間之吸收增加所 4實’在三個溫度之任一個下暴露至1〇〇〇和3〇〇〇微庫侖/ ---------^.-- (請先W讀背面之注意事反填寫本頁) 訂The A7 B7 was printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. 5. The description of the invention (19) was obtained. The trade name was ElectronCureTM in the processing chamber, and in the presence of various gases including nitrogen, oxygen, argon, and lan. And under a temperature from 25 to 40 (TC and a pressure ranging from 10 to 40 mTorr, it is exposed to a current of 8 to 20 mA, from 1000 to 1000 micrometers Coulomb / cm2 dose 'and electron beam with acceleration voltage from 5 to 25 thousand electron volts. Analysis of wafers coated with electron beam hardened SOG indicated that the film shrinkage of ι〇_3〇0 / 〇, and in 50: 1 (deionized water: hydrofluoric acid (HF)) solution of buffer oxide etching at a wet surname rate of 1 -1 1 Angstroms / sec, depending on the selected dose, energy and temperature. Figure 1 Shown are the thermal hardening according to Example 2, the electron beam hardening according to Example 3 'and the unhardened according to Example 1, ie, thermal baking, the FTir spectrum of the wafer. As shown in the FTIR spectrum of Figure 1, the c Η stretching mode The lack of increased absorption and the uniform distribution of carbon in the SIMS spectrum of Figure 13 as indicated by the Jun peak It was confirmed that the composition of the film after exposure to electron beam treatment has changed and water is not absorbed in it, which is obvious. Declaration 4: i Was hardened at varying temperature and electron beam dose according to Example 1 It is produced and hardened according to Example 3, except that in the presence of argon gas' at a temperature of 25C, 250C, or 40O-C, each wafer is exposed to 1000, with an energy of 10 thousand electron volts. One of the four doses of 3000, 5000, or 10000 microcumens per square centimeter. Figures 2⑷ and 2 (b) illustrate the FTIR performance of each wafer produced according to Example 4. As shown in Figure 2 (a) The increase in absorption between 3600 and 3700 cm -1 results in exposure to 100 and 300 microcoulombs at any of the three temperatures / --------- ^ .- -(Please read the notes on the back to fill in this page first)

A7- I------- B7 ________ · 五、發明説明(2〇 ) 平方厘米的晶圓顯示出羥基伸展,該羥基伸展象徵殘留之 水的存在於膜中。然而,藉由增加電子束刮量至等於券大 於5000微庫侖/平方厘米,膜中的水可大量地減少或完全 消二雙,如在圖2(b)中所圖示。 复也之劑糞、能量和溫唐下之電子束硬化晶圓 Hlj更化晶圓的膜收縮比妨 晶圓根據實例1和3而產生及硬化,然後藉由量測烘烤和 笔子米硬化之後的膜厚而分析膜收縮。 圖3在2 5 °C、250°C和4〇〇°C的溫度下將膜收縮圖示成電 子束劑量的函數,與熱硬化膜的辑收縮相比較。圖4顯示 出膜收縮對電子束能量。由圖3和4可顯而易見,電子束硬 化膜的收縮一般而言大於熱硬化膜的收縮。而且,隨著劑 量增加,電子束硬化膜的膜收縮也增加。此外,溫度在膜 收縮上的影響據觀察,只針對以低電子束劑量硬化的膜; 然而’在劑量超過loooo微庫侖/平方厘米且溫度在40(rc 以上時,膜收縮對電子束輻射的變化相對地不敏感。 sog、熱氧化物、及熱硬化sog晶圓在變化乏#丨暑 色溫度下之電子束硬化晶圓濕式蚀刻速率的比較 經濟部中央樣準局員工消費合作杜印製 晶圓根據實例1和3而產生及硬化,然後分析濕式蝕刻速 率。 在未塗覆的晶圓上,於諸如在實例2中所提及者的擴散 爐中’在4升/分鐘之氣體流量氧存在下,於約1 〇5〇 t之溫 度和大氣壓力之下,成長熱氧化物膜。 各種膜在50 ·· 1溶液之緩衝氧化物蝕刻中的濕式蝕刻速 ___ -23- 本紙張尺度適用巾關家縣(CNS ) A4規格(21GX2&公楚)'—~' 經濟部中央標準局員工消費合作社印製 308709 A? ___ 〇7 ______ ____ 五、發明説明(21 ) 率藉由在每一次的浸入於該溶液中丨至5分鐘之後,視該膜 的濕式姓刻速率而定,量測剩餘的膜厚而測定。 圖5主現除了熱硬化晶圓和熱氧化物晶圓之濕式蝕刻速 率以外之電子束硬化晶圓的濕式姓刻速率對劑量關係。由 圖5可顯而易見,以電子束硬化之塗覆s〇G有之晶圓的濕 式蝕刻速率是在3至5埃/秒的範圍中,其非常接近於熱氧 化物晶圓所量測到的3埃/秒蝕刻速率,但比熱硬化s〇g晶 圓所量測到的3 7埃/秒蝕刻速率低相當多。塗覆s〇G之晶 圓所况明的低蝕刻速率代表著,這類s〇G膜在與熱成長氧 化物膜相比較之下,是更爲緻密很多。 圖6(a)至(d)圖示分別在1000、3〇〇〇、5〇〇〇和1〇〇〇〇微庫 侖/平方厘米之劑量下,電子束硬化膜之濕式蝕刻速率與 膜厚足深度的變化。囷6 (a)和可顯而易見,在25。〇至 400 C間變化之溫度條年和丨〇〇〇微庫侖/平方厘米之劑量下 硬化之膜,以及在25 C之溫度和3〇〇〇微庫命/平方厘米下 硬化之膜,的濕式蝕刻速率穿過整個膜厚度都是相當地固 定。這種在濕式蝕刻速率數値上的一致性代表著,使用上 述之電子纟製程f条件產生具有高度肖勻之密度的膜是可能 的。 如在圖6(b)至6(d)中所圖示,對在之溫度 和3 000微庫侖/平方厘米之劑量下硬化之膜,以及在任何 溫度和等於或高於5000微庫侖/平方厘米之劑量下硬化之 膜而言,濕式蝕刻速率隨著高達約M00埃的膜厚增加而增 加,然後維持相對地固定。 -*-- — _ _ 本紙張尺度適用t國國家辟(cnS ) ---------裝-- 一請先閱讀背面之注意事^··决寫本莧) 訂 線 經濟部中央樣準局員工消費合作社印製 Α7- Β*7 五、發明説明(22 ) 類似地’圖7顯示出,在400°C之溫度,於5仟電子伏特 和25仟電子伏特之間變化之電子束能量和1000微庫命/平 方厘米之劑量下硬化之膜的濕式蝕刻速率也是相對地固定 〇 I'J化學-機械式拋光,接著氧電漿灰化之雷早击 ^1匕晶圓的F τ I R、结要 已塗覆的晶圓根據在實例1和3中所説明的製程而產生及 硬化,然後根據在實例1 3中所説明的製程以H F加以抛光 及清潔’接著以氧電漿灰化。氧電漿灰化的細節説明於, 例如’ C.K.王(Wang)等人,"矽氧烷SOG上電漿處理之研 究”,VIMIC研討會(1994年6月)。 圖8呈現出這些在各個硬化階段之膜的ftir光譜:(丨): 使用在10000微庫侖/平方厘米之劑量和20(rc之溫度下之 電子束輻射硬化之後;(2):階段(1)的硬化膜受到化學-機 械式拋光(chemical-mechanical polish,下文簡稱 C Μ P ), 接著在H F溶液中的濕式清潔和氧電漿灰化之後;(3):在 接著階段(2)之3天的暴露於大氣條件中之後:及(4)_·接著 階段(3)的大氣暴露,在啃段(1)之條件下’再次暴露至電 子束輻射之後。 圖8圖示在3600和3700厘米-1間之波長處的吸收增加, 孩增加象徵膜中的羥伸展,因此象徵膜之濕氣吸收的增加 。在階段(2)的CMP和清潔製程之後,羥基伸展特別地明 顯。然而,這種濕氣可藉由膜的再次暴露於電子束處理而 去除,如在圖8所顯示。 ^4· 訂 線 (請先閱讀背面之注意事項填寫本頁) -25- A-? B7 3〇87〇9 五、發明説明(23 實例8 :在暴露於大氣環境和選擇性的浸入水中後之雷子* - ~ 硬化膜的F T I R結果 在根據實例1、2和3中所説明的製程產生且硬化晶圓之 後,進行FTIR分析。 圖9比較在氧存在下,且在425°C之溫度下1小時之熱硬 化晶圓,和以10000微庫侖/平方厘米之劑量與20(TC之溫 度之電子束加以硬化,並暴露於大氣濕氣條件7天之晶圓 ,的FTIR光譜》電子束硬化晶圓在3600-3700 ( 1 /厘米)波 長處之吸收增加的缺乏圖示出,它們,與熱硬化膜相反, 不吸收濕氣。 圖10(a)和(b)比較在氬氣存在下,以10000微庫侖/平方 厘米之劑量和400°C之溫度之電子束輕射硬化,且在各個 能量水準下分別在浸入於具有25Ό之溫度的水中2 4小時之 .............................. . ...... 前和之後的膜FTIR光譜。在浸入水中之前和之後的FTI R 光譜中,目視可見的差異的缺乏表示出,當浸入於水中2 4 小時之時,電子束硬化膜不吸收濕氣。 實例9 :在氮、氬、氦、和氧環境下之電子束硬化膜的 F T I R結果 晶圓根據在實例1、2和3中所説明的製程而產生及硬化 ’除了該膜是分別在氮 '氬、氦、和氧存在下,以10000 微庫侖/平方厘米之劑量與2〇〇°C之溫度暴露至電子束能量 以外。在這些晶圓藉由暴露至大氣濕氣條件7天而時效處 理之後’進行FTIR分析。 · 一 圖11圖示除氦以外之所有氣體在3600-3700 ( 1 /厘米)波 __ -26- 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 私衣-- (請先閱讀背面、V注意事項%寫本頁) 訂 線 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明(24 長處之吸收的微量增加。因&,膜可在氮、氬、和氧的存 在下硬化而不會輕易發生後續的濕氣吸收。 機械式抛光 晶圓根據在實例4中所説明的製程而產生及硬化,然後 根據在實例7和13中所説明的製程加以拋光及清潔。在拋 光後清潔期間,污染物由於在HF中的簡單氧化物蝕刻而 自膜表面去除。這種町含浸典型而言凸顯示了電槳丁廳 中的低密度接合線,其需要覆蓋層沈積以使該接合線之上 平滑。 CMP處理之膜的厚度量測指出,電子束硬化之石夕氧燒材 料擁有易於控制的抛光速率,其類似於未攙雜之了㈣的 速率,且不會在抛光後清潔的膜中展現出任何高#刻速率 的區域。 置·Μ_11 :可任意配置的後裝置晶圚 將可從絲柏(Cypress)半導體公司購得之〇 5微米互補剂 ^屬氧化物半導體靜態隨機存取記憶體的可任意配置後製 程裝置晶圓,根據在實例1中所説明的製程塗覆兩次,然 後根據在實例4中所説明的程序,在uo、2s〇、或3〇〇。〇的 溫度,和5000、7500、及10000微庫侖/平方厘米的劑量下 硬化。可任意配置之後處理的全面細節說明於,例如,克 里夫斯(Cleeves) ’M.等人的著作中,國際電兩 學會技術報告之極大型積體電路技術文摘論文集第6丨期 (1994年)。 - ' 晶圓上最終形成之"雙層塗覆"的厚度是約65〇〇埃。在抛 -27 本紙張尺度適用中國國家標準(CNS ) A4规格(210X297公釐) -II II - · 參-- (請先热讀背面、V注意事^.^寫本育) 經濟部中央標準局員工消費合作社印製 A7- B7 五、發明説明(25 ) 請 先 讀 背 之 注 意 事 項' %焚 本衣 頁 光和處理之後’最终形成的晶圓經過灰化,接著以H F清 潔’如在實例7和1 3中所説明,將Ti-TiW膠質層直接沈積 於該晶圓的已拋光SOG表面上。接著,在45(TC之鶴化學 氣相沈積(tungsten chemical vapor deposition,下文簡稱 CVD W)之前,將晶圓暴露至60(TC的快速熱退火(rapid thermal anneal,下文簡稱rT a) i分鐘。在最終形成的晶 圓中未觀察到該膜的脱落或氣體外露。 訂 電子束硬化的”雙層塗覆”膜也在設定爲425。(:及700 X:間 之溫度的爐子中烘烤3 0分鐘。在425X:溫度下烘烤之膜的 膜收縮分析指出’以在快速熱退火之後直接量測之厚度爲 基礎的4 %厚度收縮。沒有另外的收縮發生於高達7〇(rc的 溫度。因此,由實例1 1可顯而易見,膜收縮的數量與溫度 無關。再者,最終形成的晶圓是沒有裂隙且平面化良好的 〇 复上! 1 2 :蝕刻的接觸裝置晶圓 經濟部中央樣準局員工消費合作社印製 將0 _ 5微米互補型金屬氧化物半導體靜態随機存取記憶 體的傳統蝕刻接觸裝置晶圓,根據在實例1 1中所説明的程 序加以產生 '硬化、抛光、清潔,除了同時製備單一塗覆 和雙層塗覆晶圓兩者之外。在所有這些裝置之製造所需的 製私步骤期間’觀察不到膜的脱落或氣體外露。 复3 ··直接在金屬上的CMP晶圓 將兩層ACCUglass® 311 s〇G製成的塗層直接沈積於以金 屬1,即’銘’形成圖樣的矽晶圓上,並根據説明於實例4 中的條件以電子束硬化。將9〇〇〇埃的TE〇s以cVD之方式 28 本紙張尺度關家標準(叫A4i^x 297公整 經濟部中央標準局負工消費合作杜印製A7- I ------- B7 ________ · V. Description of the invention (2〇) A square centimeter wafer shows hydroxyl stretching, which signifies the presence of residual water in the membrane. However, by increasing the amount of electron beam scraping to be equal to or greater than 5000 microcoulombs / cm2, the water in the film can be greatly reduced or completely eliminated, as shown in Figure 2 (b). Fuye's agent dung, energy, and electron beam hardening wafer Hlj under Wentang can reduce the film shrinkage of the wafer. The wafer is generated and hardened according to Examples 1 and 3, and then measured by baking and pen rice. The film thickness after hardening was analyzed for film shrinkage. Figure 3 graphically illustrates the film shrinkage as a function of electron beam dose at temperatures of 25 ° C, 250 ° C, and 400 ° C, compared to the shrinkage of the thermoset film. Figure 4 shows the film contraction versus electron beam energy. As is apparent from FIGS. 3 and 4, the shrinkage of the electron beam hardened film is generally larger than that of the thermoset film. Moreover, as the dose increases, the film shrinkage of the electron beam cured film also increases. In addition, the effect of temperature on film shrinkage has been observed only for films hardened at low electron beam doses; however, when the dose exceeds loooo microcoulombs / cm2 and the temperature is above 40 (rc The change is relatively insensitive. Sog, thermal oxide, and thermally hardened sog wafers are in a state of change # 丨 Comparison of the wet etching rate of electron beam hardened wafers at summer temperature Wafers were produced and hardened according to Examples 1 and 3, and then the wet etching rate was analyzed. On uncoated wafers, in a diffusion furnace such as that mentioned in Example 2, at 4 liters / minute In the presence of gas flow oxygen, a thermal oxide film grows at a temperature of about 1050t and atmospheric pressure. Wet etching rate of various films in 50 ·· 1 solution of buffer oxide etching___ -23 -This paper scale is applicable to the A4 specification (21GX2 & Gongchu) of Guanguan County (CNGX), printed by the Ministry of Economic Affairs Central Standards Bureau Employee Consumer Cooperative 308709 A? ___ 〇7 ______ ____ V. Invention description (21) By being immersed in it every time After 5 minutes in the liquid, depending on the wet etch rate of the film, measure the remaining film thickness and measure it. Figure 5 shows the wet etch rate except for the thermally hardened wafer and the thermal oxide wafer Wet etch rate of electron beam hardened wafers vs. dose. As can be seen from FIG. 5, the wet etch rate of wafers coated with electron beam hardened SG is 3 to 5 Angstroms / sec. In the range, it is very close to the etch rate of 3 Angstroms / sec measured by thermal oxide wafers, but is considerably lower than the etch rate of 37 Angstroms / sec measured by thermally hardened SOG wafers. The low etching rate of s〇G wafers indicates that this type of sOG film is much denser than the thermally grown oxide film. Figure 6 (a) to (d) It shows the changes of the wet etching rate and the thickness of the film thickness of the electron beam hardened film at the doses of 1000, 3,000, 5,000, and 10,000 microcoulombs per square centimeter, respectively. 囷 6 (a ) And it is obvious that the film hardened at a temperature ranging from 25.0 to 400 C and a dose of 10,000 microcoulombs per square centimeter, and The wet etching rate of the film hardened at a temperature of 25 C and 3,000 microcubits per square centimeter is fairly constant across the entire film thickness. This consistency in the number of wet etching rates is representative of Therefore, it is possible to produce a film with a highly uniform density using the above-mentioned electron process f conditions. As illustrated in Figures 6 (b) to 6 (d), for the temperature and 3 000 microcoulombs / For films that are hardened at a dose of square centimeters, and films that are hardened at any temperature and at a dose equal to or higher than 5000 microcoulombs / square centimeter, the wet etching rate increases as the film thickness increases up to about M00 Angstroms, Then remain relatively fixed. -*-— _ _ This paper scale is applicable to country t (cnS) --------- installed-Please read the notes on the back first ^ ·· The final copy of the book Amaranth) The Ministry of Economic Affairs Sample A7- Β * 7 printed by the Consumer Cooperatives of the Prospective Bureau V. Description of invention (22) Similarly, 'Figure 7 shows the electrons that change between 5 thousand eV and 25 thousand eV at a temperature of 400 ° C The beam energy and the wet etching rate of the hardened film at a dose of 1000 microkumbs / cm2 are also relatively fixed. I'J chemical-mechanical polishing, followed by an early lightning strike of oxygen plasma ashing 1 wafer F τ IR, the coated wafers are produced and hardened according to the process described in Examples 1 and 3, and then polished and cleaned with HF according to the process described in Example 1 3 followed by oxygen Plasma ashing. The details of oxygen plasma ashing are described in, for example, 'CK Wang (Wang) et al. &Quot; Research on Plasma Treatment on Siloxane SOG ", VIMIC Seminar (June 1994). Figure 8 shows these in The ftir spectrum of the film in each hardening stage: (丨): After using electron beam radiation hardening at a dose of 10,000 microcoulombs / cm 2 and a temperature of 20 (rc); (2): the hardened film of stage (1) is subjected to chemical -Mechanical polishing (chemical-mechanical polish, hereinafter referred to as C Μ P), followed by wet cleaning in HF solution and oxygen plasma ashing; (3): 3 days of exposure to the following stage (2) After atmospheric conditions: and (4) _ · Then the atmospheric exposure in the following stage (3), after exposure to electron beam radiation again under the conditions of the gnawing section (1). Figure 8 illustrates between 3600 and 3700 cm-1 The absorption at the wavelength increases, and the increase in the hydroxyl symbol in the film symbolizes the increase in the moisture absorption of the film. After the CMP and cleaning process in stage (2), the hydroxyl extension is particularly noticeable. However, this moisture Can be removed by re-exposure of the film to electron beam treatment, as in Displayed in 8. ^ 4 · Line booking (please read the precautions on the back to fill in this page) -25- A-? B7 3〇87〇9 5. Description of the invention (23 Example 8: Exposure to atmospheric environment and selectivity The FTIR results of the lightning ray after immersion in water *-~ The cured film was produced and cured after the wafers were produced according to the processes described in Examples 1, 2 and 3. Figure 9 compares the presence of oxygen at 425 1 hour of heat-hardening wafers at a temperature of ° C, and FTIR wafers hardened at a dose of 10,000 microcoulombs / cm 2 and an electron beam temperature of 20 ° C and exposed to atmospheric humidity for 7 days, FTIR Spectroscopy> The lack of electron beam hardened wafers at 3600-3700 (1 / cm) wavelength shows an increase in absorption. They show that, in contrast to thermally hardened films, they do not absorb moisture. Figure 10 (a) and (b) compare In the presence of argon, it is hardened with an electron beam at a dose of 10,000 microcoulomb / cm2 and a temperature of 400 ° C, and it is immersed in water with a temperature of 25Ό for 24 hours at various energy levels .. .................................... FTIR spectra of the film before and after. After immersion in water In the FTI R spectrum before and after the middle, the lack of visual difference shows that when immersed in water for 24 hours, the electron beam hardened film does not absorb moisture. Example 9: In nitrogen, argon, helium, and oxygen FTIR results of electron beam hardened film under ambient conditions. Wafers were generated and hardened according to the processes described in Examples 1, 2 and 3. Except that the film was in the presence of nitrogen, argon, helium, and oxygen, respectively, at 10,000 micrometers. The dose of coulomb / cm 2 and the temperature of 200 ° C are exposed to the energy of the electron beam. After these wafers were aged for 7 days by exposure to atmospheric moisture, FTIR analysis was performed. · A picture 11 shows all gases except helium at 3600-3700 (1 / cm) wave __ -26- This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) Read the back first, V notes, and write this page.) A7 B7 printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economics. 5. Description of the invention (a slight increase in the absorption of 24 advantages. Because of the & It hardens in the presence of oxygen without subsequent moisture absorption. Mechanically polished wafers are produced and hardened according to the process described in Example 4, and then polished according to the processes described in Examples 7 and 13. And cleaning. During cleaning after polishing, contaminants are removed from the surface of the film due to simple oxide etching in HF. This type of immersion typically convexly shows the low-density bonding wire in the electric propeller chamber, which needs to be covered The layer is deposited to smooth the bonding line. The thickness measurement of the CMP-treated film indicates that the electron beam hardened stone oxy-sinter material has an easy-to-control polishing rate, which is similar to the unmixed rate, and does not Will be at The cleaned film after polishing shows any areas with a high # engraving rate. Set Μ_11: a rear device that can be arbitrarily configured will be a 0.5-micron complementary agent from the Cypress Semiconductor Corporation. The semiconductor static random access memory can be arbitrarily configured post-process device wafers, coated twice according to the process described in Example 1, and then at uo, 2s〇, or 3 according to the procedure described in Example 4. 〇〇.〇 temperature, and 5000, 7500, and 10000 micro-coulombs / square centimeters of the hardening. Can be arbitrarily configured after the treatment of the full details are described in, for example, Cleeves (Cleeves) M. In the work, the International Electron Institute ’s technical report of the Very Large Integrated Circuit Technology Abstracts Proceedings No. 6 (1994).-'The thickness of the "double-layer coating" finally formed on the wafer is about 65. 〇 埃. In throwing -27 The paper standard is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -II II-· Reference-(please read the back, V note ^. ^ Written education) Ministry of Economic Affairs A7-B7 Printed by the Central Bureau of Standards Employees Consumer Cooperative Description of the invention (25) Please read the notes on the back 'After burning and drying the paper, the final formed wafer is ashed and then cleaned with HF' as explained in Examples 7 and 13. -TiW colloid layer is deposited directly on the polished SOG surface of the wafer. Then, before 45 (TC Tungsten chemical vapor deposition (hereinafter referred to as CVD W), the wafer is exposed to 60 (TC Rapid thermal anneal (rT a) for 1 minute. No peeling of the film or gas exposure was observed in the finally formed crystal circle. The electron beam hardened "double-layer coating" film is also set to 425. (: And 700 X: baked in an oven at a temperature of 30 minutes. The film shrinkage analysis of the baked film at 425X: temperature indicates that the thickness is 4% based on the thickness measured directly after rapid thermal annealing Shrinkage. No additional shrinkage occurs at temperatures as high as 70 ° C. Therefore, as can be seen from Example 11, the amount of film shrinkage is independent of temperature. Furthermore, the resulting wafer is crack-free and has good planarization.上 上! 1 2: Etched contact device wafer The Ministry of Economic Affairs, Central Bureau of Samples and Employee's Consumer Cooperative printed a traditional etched contact device wafer that will be 0 _ 5 micron complementary metal oxide semiconductor static random access memory, according to The procedure described in Example 11 was created to 'harden, polish, and clean, except for the simultaneous preparation of both single-coated and double-coated wafers. During the manufacturing steps required for the fabrication of all these devices' observed gas off or exposed film. complex 3 ... CMP wafer directly on the metal coating made of two layers ACCUglass® 311 s〇G a metal deposited directly, i.e., 'Ming' formed pattern Silicon On the circle, and electron beam hardening according to the conditions described in Example 4. The TE〇s of 9000 angstroms in the form of cVD 28 paper standard Guanjia standard (called A4i ^ x 297 Central Standards of the Ministry of Public Economy Printing by the Bureau ’s Consumer Labor Cooperation

AT B7 五、發明説明(26 ) 沈積至因而形成的SOG層上,然後使用配備有可從羅得 (Rodel)購得之IC 1000/SUBA 4抛光墊的伊佩克西方技術 (Ipec Westech)拋光機,在下列的條件下拋光:每平方英忖 7磅的晶圓壓力;110°F的晶圓抛光溫度:可從綠沛(Rippey) 購得之以130毫升/分鐘流動的SC 1 12漿液:每分鐘2 8轉的 壓盤(固定抛光墊)轉速;每分鐘28轉的載物台(固定晶圓) 轉速:185釐米的抛光位置:及2釐米/秒之速度下的5釐 米壓盤振盪。晶圓使用H F拋光及清潔,接著以氧電蒙灰 化。在SOG與TE0S層之間未見到附著性問題或其他不爲 人期待的交互作用。 爲了將S0G層和TE0S層之間的界面暴露至拋光應力,在 這個實例中所產生的晶圓接著在類似的條件下拋光。未觀 察到剝離或其他異常之處。 實—例14 :具有暴露之界面之變化的金屬上s〇g層數 實例1 3可在晶圓上使用—、二、或三層s 〇 g塗層而加以 重複°這些晶圓也顯示出優異平坦度,而沒有s〇G層的龜 裂。 實1 5 :覆蓋TEQS,形成變化之s〇G層數的晶圓 覆蓋TE0S的晶圓根據在實例1 3和1 4中所説明的製程而 產生及硬化’但具有使用約12〇〇〇埃之已攙雜TE〇s氧化物 介電物於主動裝置之上’ 5〇〇〇和1〇〇〇〇微庫侖/平方厘米之 劑量和9及1 5仟電子伏特之能量的例外之處。電子到達晶 圓表面所需要的能量據估算爲約1 2仟電子伏特。所選擇的 電子數能量値因此預期將電子置於TE〇s膜表面之内且進 -- -29- 本紙張尺度適用中國國家標準(CNS --- 裝 訂 線 < (諳先¾讀背面之注意事¾..蜞寫本X) 經濟部中央標準局員工消費合作社印製 Α7· "------------- Β7 五、發明説明(27 ) 入矽Ba圓自身中。然後將硬化的晶圓經過接觸蝕刻、接觸 填充(w充填物)和在實例η中所説明的局部互連形成步骑 而處理,並測試裝置及場起始祕和問極氧化物的qbd。 这些測試的細節說明於伍爾夫(w〇lf),"次^金屬氧化 物半導體場效電晶體”,第3章,極大型㈣f路紀元_ 處理(测年)中。場起始電壓測試的結果未指^通道電 晶體之電壓(Vts)上的偏热,/符批-丄 』7侷牙夕但顯不出P-通道電晶體之Vts 上的小偏#。然而,在15仟電子伏特之高能量下,p-通道 裝置I Vts的3 0毫伏特偏移與v t變化的允許範圍,即高達 約150毫伏特,相比較之下,仍然是小的。由於15〇〇〇仟電 子伏特I電子束能量超過1〇〇〇〇微庫侖/平方厘米的劑量増 加造成QBD的系統性劣化’其意指,閘極氧化物在這心 數値的電子束曝照期間可能變得受到損壞。 复1 6 :在多晏爲介電物之靜熊隨機存取命 憶體測試結構的特性AT B7 V. Description of the invention (26) Deposited onto the SOG layer thus formed, and then polished using Ipec Westech technology equipped with an IC 1000 / SUBA 4 polishing pad available from Rodel Machine, polish under the following conditions: wafer pressure of 7 pounds per square inch; wafer polishing temperature of 110 ° F: SC 1 12 slurry flowing at 130 ml / min, available from Rippey : Rotation speed of the platen (fixed polishing pad) at 28 rotations per minute; stage (fixed wafer) at 28 rotations per minute Rotational speed: 185 cm polishing position: and 5 cm platen at a speed of 2 cm / s oscillation. The wafer is polished and cleaned using H F and then ashed with oxygen. No adhesion problems or other unexpected interactions were seen between the SOG and TEOS layers. In order to expose the interface between the SOG layer and the TEOS layer to polishing stress, the wafer produced in this example was then polished under similar conditions. No peeling or other abnormalities were observed. Real Example 14: The number of sog layers on a metal with exposed interface changes Example 1 3 can be repeated on the wafer using-, two, or three layers of sog coating. These wafers also show Excellent flatness without cracking of the SOG layer. Real 15: Covering TEQS, forming wafers with varying number of SOG layers TEOS-covered wafers were produced and hardened according to the processes described in Examples 13 and 14, but with the use of about 12,000 angstroms The exception is the dosing of TE〇s oxide dielectrics on the active device with doses of 5,000 and 10,000 microcoulombs per square centimeter and energies of 9 and 15 thousand electron volts. The energy required for electrons to reach the surface of the wafer is estimated to be about 12 thousand electron volts. The selected electron number energy value is therefore expected to place the electrons within the surface of the TE〇s film and enter --- 29- This paper scale is applicable to the Chinese national standard (CNS --- gutter < (know first ¾ read the back Matters needing attention: 蜞 本本 X) Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs Α7 · " ------------- Β7 5. Description of the invention (27) into the silicon Ba circle itself .Then the hardened wafer is processed by contact etching, contact filling (w filler) and the local interconnect formation step described in Example η, and the device and the field start secretion and the Qbd of the oxide of the electrode are tested The details of these tests are described in Woolf, "" Secondary Metal Oxide Semiconductor Field-Effect Transistors ", Chapter 3, Very Large ㈣f 路 纪元 _ Processing (Dating). Field Start The results of the voltage test did not refer to the overheating of the voltage (Vts) of the channel transistors, / Fu Piao- 丄 "7 rounds but no small deviation # on the Vts of the P-channel transistors was shown. However, At a high energy of 15 thousand electron volts, the allowable range of the 30-mV offset and vt variation of the p-channel device I Vts is up to about 150 mV In particular, it is still relatively small. The dose increase of 15,000 volt I electron beam energy exceeds 10,000 microcoulombs per square centimeter resulting in systemic degradation of QBD ’, which means that The polar oxide may become damaged during the exposure of this number of electron beams. Complex 1 6: Test the characteristics of the structure of random access memorizer in the static bear which is a dielectric

Accuglass® S0G膜製成的”雙層塗層„根據在實例3中所 説明的程序,並在20(TC、1〇仟電子伏特、和1〇〇〇〇微庫侖 /平方厘米之條件下,產生及硬化至〇 5微米塗覆有多晶矽 之靜態隨機存取記憶(static Rand〇m Access Mem〇ry,下文 簡稱SRAM )測試結構上。然後藉由實例丨2之以傳統蝕刻 爲基礎的處理方法,或是實例1 1之可任意配置的後製程, 在塗覆有硬化SOG的結構中製作0.6微米接觸。 在後處理結構中,SOG特性在接觸金屬化之前,但在接 觸形成之後,於不同的退火溫度,即425。〇、600。(:、和 本紙張尺度適用中國國家樣準(CNS ) A4規格(210X297公;t ) 种衣ir,— ^ (請先閱讀背面,V注意事¾¼寫本頁} 一 五、發明説明(28 700 C下量取。矽化物阻抗因爲該低的溫度預估而不受 S 0 G製程影響。 1爲了 ·二由傳統的蝕刻製程形成通孔,將SOG層如在實例 1 3和1 4中所説明地覆蓋9000埃的TEOS Si〇2,然後根據在 只例1 J中所說明製程拋光掉。在這層介電轫中蝕刻出〇 7 通孔3通孔填充以毯狀W和説明於,例如,Η小島 (K〇J1ma)等人,,,使用於玻璃上旋轉之多重塗層的平坦化製 程極大型積體電路(1 988年6月),中的蝕刻掉處理進行。 如在,例如,安勒(Anner),"平面處理入門" 79-90( 1990 年)中所%明,含有蝕刻接觸之結構的電氣阻抗測試顯示 出,弘子束硬化S〇G層的接觸抗高於已攙雜再流動之1£〇5 Si〇2 ;ι電層的接觸阻抗。這大概是由於接觸蝕刻中大的過 度蝕刻而引起,該過度蝕刻將大部分的TiSi2自下層的氧化 物蝕刻掉。 "" 如在圖1 2中所圖示,閘極氧化物的QBD相當於具有蝕刻 接觸之已攙雜再流動之TE0S Si〇2,其意指,在電子速處 理期間,具有薄SOG層之晶圓對氧化物的損害小於具有 TEOS Si〇2氧化物的晶圓。電氣結果的摘述提供於表格2中 (請先閱讀背面-之注意事¾.也寫本頁) 裝· 訂 經濟部中央標準局員工消費合作杜印製 -31 - 各紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 五、發明説明(29 ) A-7 B7 經濟部中央橾準局員工消費合作社印製 控制 具有SOG的蚀刻型態 具有SOG的後處理型態 (700"C 退火) 具有SOG的後處理型態 (6〇〇\:退火) 具有SOG的後處理型態 (425"C 退火) 接觸型態 K) UJ N) Ό Ui 00 N+類 接觸阻抗(歐姆) N) UJ LA 35Ι* U) Os P+類 σν 00 斷路 ίο 自動對正(P+) 00 i'r 〇\ 自動對正(N+) 通過 ¥ 通過 通過 通過 自動對正接觸漏電 \y\ ON 矽化物阻抗 >5000 g 205 270 - 十 + 4XU 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐) ---------种衣------1T------^ I (請先閱靖背面之注意事¾#寫本頁) A7- B7 五、發明説明(30 ) 經濟部中央標準局員工消費合作社印製 复7 :用於多層介電物的電子束處理CVD TEOS 將具有1000埃至8000埃之間,較好從約1500埃至约3000 埃’之厚度的·一層TEOS膜在約350。(:至約450。(:的溫度和 約7至9托耳的壓力下,經由CVD沈積至多晶矽晶圓上。然 後在可攸電子視像公司購得的ElectronCureTM裝置中,在 氮或氬存在時,於約200°C至約25(TC之溫度和約1 〇毫托耳 至40毫托耳之壓力下,將該丁E〇s膜暴露至約5〇〇〇至約 10000微庫侖/平方厘米之劑量和約5至約1 5仟電子伏特之 能量的電子束輻射流量約丨〇分鐘。最終形成的膜是富含矽 、緻密的TEOS氧化物。 然後將矽酸鹽、磷矽酸鹽、及/或矽氧烷s〇G旋轉塗佈於 已硬化的TEOS晶圓上並加以硬化。選擇的S〇g型態和 S 0 G塗層的厚度視所想要的平坦化而定。可選擇地,如果 須要的話’介電物疊層可由CVD TEOS氧化物沈積完成, 或者另外’可將SOG留作爲層間介電物疊層中的最終層。 :超薄閘極氣化物的形成 在氧氣存在時,於約1 0至約200毫托耳的壓力和約25〇。〇 的/ja度^下,將多晶$夕晶.圓暴露至實例1 5的電子束處理條 件’持續一段足以成長想要之氧化物厚度的時間。結果是 一種均勻地緻密且均質的膜,該膜適用於微電子應用所需 要的進—步處理。 -33- 本紙張尺度it用中Hi]家標準(CNS ) A4規格(21Qx 297公慶 批衣-- (請先閱讀背面之注意事^,-'唭寫本頁) 、-=5Accuglass® S0G film "double-layer coating" according to the procedure described in Example 3, and under the conditions of 20 (TC, 10 thousand electron volts, and 10000 microcoulombs per square centimeter, Generated and hardened to a static random access memory (SRAM) test structure of polysilicon coated with 0.5 micron. Then, the conventional etching-based processing method of Example 丨 2 was used. , Or the post-process of Example 11 which can be arbitrarily configured, making a 0.6 micron contact in the structure coated with hardened SOG. In the post-processing structure, the SOG characteristics are different before the contact metallization, but after the contact is formed, the difference is different. The annealing temperature of 425.〇, 600. (:, and this paper scale are applicable to China National Standards (CNS) A4 specifications (210X297; t)) seed coat ir, — ^ (please read the back, V Cautions ¾¼ Write this page] Fifteen. Description of the invention (measured at 28 700 C. The silicide resistance is not affected by the S 0 G process because of this low temperature estimate. 1 In order to form the via hole by the traditional etching process, SOG layer as illustrated in Examples 13 and 14 TEOS Si〇2 covering 9000 Angstroms, and then polished off according to the process described in Example 1 J. In this layer of dielectric etched 7 holes 3 through holes filled with a blanket W and illustrated in, for example, Η 小島 (K〇J1ma) et al., The etching-out process in the very large-scale integrated circuit (June 1988) using multiple coatings rotating on glass was performed. As in, for example, Anler (Anner), " Introduction to Planar Processing " 79-90 (1990) shows that the electrical impedance test of structures with etched contacts shows that the contact resistance of the Hiroko beam hardened SOG layer is higher than Doped and reflowed 1 £ 〇5 Si〇2; ι contact resistance of the electrical layer. This is probably caused by a large over-etching in the contact etching, the over-etching will etch away most of the TiSi2 from the underlying oxide. &Quot; " As illustrated in FIG. 12, the QBD of the gate oxide is equivalent to the doped and reflowed TEOS Si〇2 with etched contacts, which means that during the rapid electron processing, it has a thin SOG layer. The damage of the wafer to the oxide is smaller than that of the wafer with TEOS Si02 oxide. A summary of the results is provided in Table 2 (please read the back page-the precautions ¾. Also write this page) Binding · Binding the Ministry of Economic Affairs Central Standards Bureau employee consumption cooperation du printing -31-each paper size applies to the Chinese national standards ( CNS) A4 specification (210X297 mm) V. Description of invention (29) A-7 B7 Central Ministry of Economic Affairs Employee Consumer Cooperative Printing and Controlling the etching type with SOG The post-processing type with SOG (700 " C Annealing ) Post-processing type with SOG (600 °: Annealing) Post-processing type with SOG (425 " C annealing) Contact type K) UJ N) Ό Ui 00 N + contact resistance (ohm) N) UJ LA 35Ι * U) Os P + class σν 00 Open circuit ο Automatic alignment (P +) 00 i'r 〇 \ Automatic alignment (N +) Pass ¥ Pass through automatic alignment contact leakage \ y \ ON Silicide impedance> 5000 g 205 270-Ten + 4XU This paper scale is applicable to Chinese National Standard (CNS) A4 specification (210X 297mm) --------- seed coat ------ 1T ------ ^ I (please read the notes on the back of Jing Jing ## to write this page) A7- B7 V. Description of Invention (30) Employees of Central Bureau of Standards, Ministry of Economic Affairs Fei Cooperative Printed Complex 7: Electron beam treatment CVD TEOS for multilayer dielectrics will have a thickness of between 1000 angstroms and 8000 angstroms, preferably from about 1500 angstroms to about 3000 angstroms, a layer of TEOS film at about 350 . (: Up to about 450. (: At a temperature of about 7 to 9 Torr, deposited on a polysilicon wafer by CVD. Then in the ElectronCureTM device purchased by Keyou Electronics, in the presence of nitrogen or argon , At a temperature of about 200 ° C to about 25 ° C and a pressure of about 10 mTorr to 40 mTorr, the Ding Eos film is exposed to about 5000 to about 10,000 microcoulombs / The dose of the square centimeter and the electron beam radiation flow rate of about 5 to about 15 thousand electron volts are about 10 minutes. The resulting film is rich in silicon and dense TEOS oxide. Then the silicate and phosphosilicate Salt, and / or silicone SG is spin-coated on the hardened TEOS wafer and hardened. The thickness of the selected S0g type and S0G coating depends on the desired flattening Alternatively, if necessary, the 'dielectric stack can be completed by CVD TEOS oxide deposition, or else the SOG can be left as the final layer in the interlayer dielectric stack .: Ultra-thin gate gasification formation In the presence of oxygen, at a pressure of about 10 to about 200 mTorr and about 25〇.〇 / ja degrees ^, the polycrystalline $ evening crystal. Exposure to the electron beam processing conditions of Example 15 continued for a period of time sufficient to grow the desired oxide thickness. The result is a uniformly dense and homogeneous film that is suitable for further processing required for microelectronic applications. -33- This paper standard it uses the Hi] home standard (CNS) A4 specification (21Qx 297 official approving clothes-(please read the notes on the back ^,-'don't write this page),-= 5

Claims (1)

2 4. 6. 輕濟部中夬榡準局負工消費合作社印製 7. •-種硬化基板上之介電材科的方法 ⑷將介電材料施加至該基板的—表面:万法及包含: (b)在足以將介電材科硬化成膜的條件之下 材料暴露至電子束輻射。 、琢a 1 根據申請專利範圍第1項之方法 酸鹽類、磷矽酸鹽類、矽氧烷類 ’昆合物製成。 根據申請專利範圍第2項之方法 路至该電子束輻射之前, '土彳成,孩矽氧烷以耳 兮二:馬準,具有從約2%至約9〇%的有機基, =有機基含有從則至約1〇個繼基,具有從約〇 族個碳的芳香族基’具有從約4至約10個硬的脂街 佚基,及其中的混合物。 根據申請專利範園第Η之方法,其中該介電材料在從 ’.·勺2 :&gt; C至約4 0 0。(:的溫度下加以硬化。 Τ據申請專利範圍第丨項之方法,其中該介電材料在從 約1 〇毫托耳至約2 0 0毫托耳的壓力下加以硬化。 根據申請專利範圍第丨項之方法,其中該基板在選自含 有氧、氬、氮、氦和其中之混合物之群體的氣體存在下 ’暴露至電子束輻射。 —種塗覆有至少一層根據申請專利範圍第i項之膜的基 板。 種含有根據申請專利範圍第7項之基板的微電子裝置 其中孩介電材料由々 磷矽氧烷類及其中 其中該介電材料在暴 ^---- \碕先閲|?»-背面[&lt;.注意事項严矣^) 訂 t ------ - 34 - 本紙法尺度家梂準(CNS「A4祕(210乂297公着) A8 B8 C8' D8 申請專利範圍 方==覆有化學氣相沈積材料之基板退火的方法,該 丨:):化學氣相沈積材料施加至該基板的表面上;及 足以將化學氣相沈積材料退火成膜的條件之下, 化學氣相沈積材料暴露至電子束輻射。 10. ·艮據申請專利範圍第9瑁之 &amp; 八万法,其中該化學氣相沈積 :t裳強化四乙基正石夕酸鹽、石夕燒屬氧化物 '硼 螂矽毆鹽玻璃、磷矽酸鹽玻璃、氮化物、無水物膜、氧 亂化物、由四乙基正㈣製成的料玻璃、或其中的混 合物。 η.根據申請專利範圍第9項之方法,其中該化學氣相沈積 材料在„有目乙基正石夕㉟鹽和氧或氣、石夕燒和可選擇性 1吏用〈-硼烷、磷烷、及氧化亞氮之混合物的氣體存在 下,施加至該基板。 12. —種塗覆有至少一層根據申請專利範圍第9項之膜的基 板。 13. —種含有根據申請專利範圍第丨2項之基板的微電子裝 置。 14_ 一種在基板上成長超薄膜氧化物或氮化物的方法,該方 法包含: 在氣體狀態之材料的存在下,且在足以使該材料離子 化並促成基板表面上之氧化或氮化反應的條件之下,將 基板的一表面暴露至電子束輻射&gt; 15.根據申請專利範圍第! 4項之方法,其中該基板由件化 本紙張尺度逋用中國國豕標牟(CNS ) A4現格(210 X 297公董) ^-- 1' (請先閎’讀背面之注意事項寫本瓦) 訂 線 經濟部中央標隼局負工消費合作社印製 -35-2 4. 6. Printed by the Consumer Cooperative of the Ministry of Light Industry of the Ministry of Light Industry 7. • A method of curing a dielectric material on a substrate ⑷ applying a dielectric material to the surface of the substrate: Wanfa and Including: (b) The material is exposed to electron beam radiation under conditions sufficient to harden the dielectric material into a film. , Zhuo a 1 According to the method of claim 1 of the scope of patent application, acid salts, phosphosilicates, siloxane compounds are made. According to the method of item 2 of the patent application scope, before the electron beam radiation, 'Tu Shicheng, children's silicones are two ears: Ma Zun, with an organic group from about 2% to about 90%, = organic The group contains from then to about 10 secondary groups, the aromatic group with from about 0 carbons to the group has from about 4 to about 10 hard lipid groups, and mixtures thereof. According to the method of patent application No. H, where the dielectric material ranges from &apos;. Spoon 2: &gt; C to about 400. (: It is hardened at a temperature. According to the method of item 丨 of the patent application range, the dielectric material is hardened under a pressure of from about 100 mTorr to about 200 mTorr. According to the patent application The method of item 丨, wherein the substrate is exposed to electron beam radiation in the presence of a gas selected from the group consisting of oxygen, argon, nitrogen, helium, and mixtures thereof-a species coated with at least one layer according to patent application scope i Substrate of the film of the item. A microelectronic device containing a substrate according to item 7 of the patent application in which the dielectric material is made of phosphorosiloxanes and in which the dielectric material is exposed ^ ---- \ 碕 先READ |? »-Back [&lt;. Precautions Yan Yi ^) Order t -------34-The standard of the paper standard (CNS" A4 secret (210 to 297 public) A8 B8 C8 'D8 Patent application scope == Method of annealing a substrate coated with chemical vapor deposition material, the 丨 :): The chemical vapor deposition material is applied to the surface of the substrate; and sufficient conditions to anneal the chemical vapor deposition material into a film Below, the chemical vapor deposition material is exposed to electron beam radiation. 10. · According to the 9th method of patent application, the 80,000 method, in which the chemical vapor deposition: t-strontium strengthened tetraethyl orthosilicate oxonate, shixi burned oxides' boron silicate glass, phosphorus Silicate glass, nitride, anhydrous film, oxygenated compound, frit glass made of tetraethyl n- (iv), or a mixture thereof. Η. The method according to item 9 of the patent application scope, wherein the chemical gas phase The deposited material is applied to the mixture of ‘eye mesh ethyl orthostone Xi’ salt and oxygen or gas, Shi Xiyaki, and optionally a mixture of <-borane, phosphane, and nitrous oxide. Substrate. 12. A substrate coated with at least one layer of the film according to item 9 of the patent application. 13. A microelectronic device containing a substrate according to item 丨 2 of the patent application scope. 14_ A method of growing an ultra-thin film oxide or nitride on a substrate, the method comprising: in the presence of a material in a gaseous state, and under conditions sufficient to ionize the material and promote oxidation or nitridation reactions on the surface of the substrate Next, expose one surface of the substrate to electron beam radiation &gt; 15. According to the patent application No. 1! The method of item 4, in which the substrate is made of a piece of paper, and the Chinese national standard (CNS) A4 is used (210 X 297 Gongdong) ^-1 '(please read the precautions on the back side first) W) Printed by the Ministry of Economics, Central Standard Falcon Bureau, Unemployment Consumer Cooperative-35- 申詩專利範圍 16鎵或矽製成。 據申5青專利範圍第1 4項之方法,其中兮好 产 體、货—. 共干邊材枓含有氣 亞氣、其中之反應產物或混合物 種塗復有至少一 基板 18’ —種含有根據申請專利範圍第1 7項之基板的微電子裝 置。 1艮據申請專利範圍第1項之方法,其中該基板是矽晶圓 ------裝II 广请先聞讀背面,-C-注意事項-?〜、寫本頁) .II— · 昇華之固體或蒸發之液體型式下的氧、氨、^、氧 層根據申請專利範圍第1 4項之膜的 17 -1T 經濟部中央標準局員工消費合作社印製 36- 本紙張尺度適用中國國家標準(CNS ) A4規格(2丨0X297公釐〉Shenshi's patent scope is made of 16 gallium or silicon. According to the method of item 14 in the scope of the application of the 5th patent, among them, the product and the goods are dry. The co-drying sapwood contains gas and sub-gas, and the reaction product or mixture is coated with at least one substrate 18′-containing A microelectronic device based on the substrate of claim 17 of the patent application. 1 Gen According to the method of item 1 of the patent application scope, where the substrate is a silicon wafer --- Mount II Please read the back first, -C-Notes-? ~, Write this page) .II— · The oxygen, ammonia, ^, and oxygen layers in the sublimated solid or vaporized liquid type are printed according to the 17-1T film of the patent application item 14 of the patent scope. 36-This paper size is suitable for China National Standard (CNS) A4 specification (2 丨 0X297mm)
TW85107802A 1996-05-23 1996-06-28 Electron-beam processed films for microelectronics structures TW308709B (en)

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