3〇〇§M.§bc/002 A7 __________B7 五、發明説明（丨） 技術範圍 本發明大致係有關於半導體記憶元件之製作方法，特 別是有關於在記憶胞之電容陣列上製作位元線之方法。 技術背景 由於極大規模集積半導體技術（VLSI，very-large scale integration)的緣故，晶片的電路密度已有顯 著的增加。建構於半導體基體其上與其中的迷你縮小化元 件構成了此些電路，其間係以極爲緊密接近的方式互相分 離，且其包裝密度亦已有顯著的增加。近來在微影成像 (photolithography)技術方面的進展，諸如相移光罩 (phase-shifting mask)，以及自動對準製程步驟 (self-aligned process)的進展，已進一步地降低了 半導體元件的尺寸並增加了電路的密度。此些發展導致特 大規模集積（ULSI, ultra large scale i n t e g r a t i ο η )的元件能以小於一微米的最小元件尺寸， 在晶片上製作超過一百萬個的電晶體。利用此類改進的製 程所製作的電路元件，由於其尺寸縮小的緣故，有些已經 遭遇到電氣特性上限制的問題。 經濟部中央標準局員工消費合作社印裂 n 1^1^1 ^^^1 m> I ^^^1 ^^^1 ^ m· m ^^^1 ^^^1^t .- (請先閱讀背面之注意事項再填寫本頁) 遭遇到電氣特性上限制問題的此類電路元件之中，有 一種是爲動態隨機存取記憶（DRAM，dynamic random-access memory)晶片上的儲存胞陣列。通常由單一金 屬氧化物半導體場效電晶體（MOS-FET，metal-0χide-s e m i c ο n d u c t 〇 r f i e 1 d - e f f e c t t r a n s i s t 〇 r) 與單 一電容所構成的此類個別DRAM儲存胞，已在電子工業中 本紙張尺度適用中國國家標準（CNS ) Λ4规格（210X2<J7公釐） 0553TWF.DOC/002 A7 B7 五、發明説明（) 被廣汎利用來儲存資料。單一DRAM的記億胞可以將一個 位元的資料以電荷的形態儲存於電容之中。由於記憶胞面 積減縮所造成的記憶胞電容量的減小’乃是DRAM能再增 加包裝密度的一個嚴重障礙。因此，記憶胞電容量降低的 問題必須予以解決，才能夠在半導體記憶元件中達成較高 的包裝密度。由於記憶胞電容量的減小非但減低了資料讀 出的能力，增加了記憶胞的軟錯記比率（soft error rate)，並且由於電阻性元件的操作的緣故因而在低電壓 動作期間消耗了超量的電力。 通常，在記憶胞面積約爲1.5 μιη2並採用一種常見的 二度空間堆疊電容胞架構的一種64 MB DRAM之中，縱然 使用諸如五氧化二鉬（Ta2〇5)的高介電係數材料，仍亦無 法獲得足夠的記憶胞電容量。因此，已有人提議一種具有 三度空間構造的堆疊電容來增加記憶胞的電容量。此類的 堆疊電容包含有’例如’雙堆疊、翼形、柱形、分散堆 疊、以及盒式構造等的電容。 習知DRAM的電谷陣列結樽通常使用埋置式位元線或 非埋置式位兀線。g使用埋置式位元線構造時，所提供的 位元線之形態乃是與記憶胞場效電晶體（FET)的位元線接 觸窗在垂直方向上互相接近’其記憶胞電容係以水平的形 態'形成於字元_位元_0。當使難_式位元線 構造時，深入的垂直接觸窗係通過—厚絕緣層到達記憶胞 而而關，謂賴驗㈣奸_上別日在位元線 的下方。此種非埋置式位元線的結構亦被稱爲「位元線下 n^— n^i 1^1 m ^^^1 ^m· .. m ^^^1 .HI ^^^1 ^^^1 ~0¾. ,-口 (請先閱讀背面之注意事項再填寫本頁) 濟 部 中 標 隼 局 Μ 工 消 費 Ϊ 本紙張尺度適用中國國家標準（CNS ) Λ4規格（21〇X29：^J'y''· A7 B7 3 G doc/002 五、發明説明（彡） 電谷」（capacitor-underbitline)或者「位元線在 電谷上」（bitline-〇ver-capacitor)的構造，其亦爲 本發明之主題。 後列的美國專利中揭示了相關的製程以及位元線的構 造··頒予Lage的美國專利第5,38 9,5 6 6號案，頒予Ch〇i 等人的美國專利第5,4 2 2,2 9 5號案，以及頒予Dennis〇n 的美國專利寧5, 40 1 ,68 1號案。不過，利用較少的光學 及餓刻步驟便可以改進此些習知技術的製程。多種此類習 矢口 S術方法皆需要實質上相當多會使製造程序更爲複雜且 胃貴：的製程步驟與/或平面結構。其他的製程方法則亦須 @賴控制蝕刻的進行到達一個預定的蝕刻深度，而這在半 導體製造的環境之中可能是相當難以控制的。此外，位元 線接觸窗開口時常會需要較大的製程誤差來避免位元線接 觸窗與字元線或電容極板發生短路的情形。再者，記憶胞 的尺寸也必準進一步地減小才能夠達成元件再縮小化的目 的。 對於發展出此些能夠將製程成本減至最低，且將半導 體元件的製作良率增至最高的電容與位元線製作方法而 W，這乃是一種挑戰。特別是，對於發展出能將光阻光罩 操作的次數減到最少，並仍提供最大製程誤差容許度以獲 得最大產品良率的方法而言，也是一種挑戰。 本發明$—目的係在於提供可以減少光學及蝕刻步驟 的一種製作位元線接觸窗的方法。 ^^1 ^^^1 ί ί —^ϋ ^^^1 ' i ^^^1 i n n^i - J. 身 、va *- (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局工消費合作社印製 本紙張尺度適财_家料（CNS) M規格 (21 OX 297公釐） 0553TWF.DOC/002 A7 B7 _ 五、發明説明（>) 本發明之另一目的係在於提供可以減低製程複雜度’ 並提供額外的程序誤差容許度，以減低位元線與字元線及 電極板發生短路情形的一種「位元線在電容上」之製作方 法。 本發明之又一目的係在於提供一種方法可供製作動態 隨機存取記憶（DRAM.)，其僅只使用三層複晶矽層以及具 有較高密度的位元線，但其成本較低，易於製造’且製作 良率亦可增加。 爲達成上述目的，本發明提供一種製作高密度記憶元 件位元線之方法。該方法首先在一基體10上的兩個分離 的轉移閘14，18之間提供一汲極區8，汲極區8之上的第 一氧化砂絕緣層2Q，22，汲極8上具有一複晶砍頂電極板 30的一電容，以及其因而形成的結構之上的一金屬間介 電質層。首先，在金屬間介電質層之中形成一位元線接觸 開口’其並終止於汲極上的頂電極板之處。接著，利用非 等向性的複晶矽蝕刻程序來除去汲極上的頂電極板。第 三，再於位元線開口的側壁上形成介電質間隔層40。間 隔層將頂電極板與位元線分隔開。間隔層亦容許使用較小 的位元線，因而使得所製成的記憶胞亦可以較小。第四’ 由間隔層所對正排列的位元線開口內被塡以金屬以便接觸 位元線。 更詳細而言，本發明提供了一種方法可供製作高密度 DRAM的位元線。此DRAM的製作只使用了三層的複晶矽 層。此方法首先在一基體10上的兩分離轉移閘14之間提 ____ 6 本紙張尺度適用中Hu家縣（CNS) M規格（2IGx 297公釐） —-------{ 裝------訂 •- (請先閱讀背面之注意事項再填窩本頁) 經濟部中央榡準局員工消費合作衽印製 0553TWF.DOC/002 A7 0553TWF.DOC/002 A7 經濟部中央標率局員工消費合作社印袋 B7 五、發明説明（夂） 供一個汲極區8。接著，再於汲極8，轉移閘的內部側 壁，以及頂閘電極表面上形成第一氧化矽絕緣層20， 22。儲存電極24係形成於源極4之上。接著再於包含儲存 電極24的整個基體表面上形成一電容介電質層26。 電容介電質層26以及第一絕緣層22之上至少形成一 第一複晶矽層30(頂極板）。此第一複晶矽層最好應被形 成於整個基體表面上。第一導電層30之上形成一金屬間 介電質層32。汲極8之上的第一金屬間介電質層32之中形 成一第一開口 38，曝露出汲極8上的第一複晶矽層30。第 一開口係由金屬間介電質層32的側壁38所界定。曝露出 來的第一複晶矽層30在第一開口內係經過非等向性蝕刻 處理，曝露出汲極8上的第一氧化矽絕緣層22。非等向性 蝕刻處理亦在第一開口內形成第一複晶矽層30的側壁。 在一個重要的步驟之中，在金屬間介電質層與第一導電層 的側壁上形成一介電質側壁間隔層，此介電質側壁間隔層 亦形成於第一絕緣層22之上，因而形成一第二開口 38A。 接著再於第二開口之內形成一位元線接觸塞5 0以便與汲 極接觸。最後，護層與金屬層被形成於此時的表面上，以 將電路中的亢件連接起來。 本發明較之習用技術提供了多種的優點。本發明僅只 使用三層的複晶矽層來界定一個DRAM記憶胞及位元線接 觸窗。本發明與習知技藝的製程相較之下減少了遮罩以及 蝕刻的步驟。此外，位元線接觸窗的四步驟製程可以顯著 地減少必須用來避免字元線（或電容頂電極板3G)與位元 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝· 訂 0553TWF.DOC/002 經濟部中央標準局員工消費合作社印製 A7 B7__ 五、發明説明（6 ) 線50之間發生短路的保護空間。與習知的DRAM製程相較 之下，本發明可以將記憶胞的面積減少達10至20%。本發 明的方法亦使用複晶矽層30來覆蓋除了汲極8之上，位元 線5 (3用以連接至汲極的位元線接觸區域以外的整個的晶 片。第三複晶矽層30(頂電極板）的此種地毯式覆蓋可以 顯著地減低DRAM的軟錯記比率。 圖式之簡單說明 依據本發明的一種半導體元件之特點與優點，以及依 據本發明而製作此種半導體元件製程的進一步細節，將於 後面配合參考所附圖式而進行的詳細說明之中變得更爲淸 楚而易於瞭解，而附圖之中，相當的參考標號係被用來標 相似的或對應的元件，區域以及部份等，其中： V 圖1至圖8以係爲截面圖，其分別顯示依據本發明而製 作一 DRAM的位元線之方法步驟。 較佳實施例之說明 本發明將配合參考所附圖式而加以詳細說明。本發明 提供一種製作記憶胞（例如，dram)的方法，其擁有具備 小尺寸的電容上位元線，只需要較少的光學步驟，並可以 因製程誤差容許度的增加而增進良率。目前在製造DRAM 記憶胞時’用以製作場氧化物（F0X，fie丨d oxide)與 場效電晶體結構的製程步驟，在此僅將只簡單地予以說 明’以便能夠較易於瞭解本發明。習於本技藝之士應可瞭 解，利用本寧施例的說明之中所未包含在內的額外製程步 驟，亦可以將其他型式的半導體元件包含於DRAM晶片之 __8 本紙張尺度適用中國國CNS〉M規格（^7〇><297公釐〉- ^^1 ml km m mf n^i. —a^i ^^^1 m n^i «m \J (請先閱讀背面之注意事項再填寫本頁) 0553TWF.DOC/002 A7 B7 五、發明説明（η ) 中。例如，N型基體中P井區以及CMOS電路皆可在其中製 成。另外亦應瞭解的是，附圖之中只顯現了應屬同時製作 形成於基體上的多重DRAM儲存記憶胞之中的一個。此 外’此等位元線亦可以應用於除了 DRAM晶片之外的其他 晶片形式之上。除此之外，此位元線亦可以被應用於諸如 SRAM，EPROM與E2PR0M的其他晶片形態之中。 應予瞭解的是基體10應可能包括一半導體晶圓，形成 於晶圓中的主動與被動元件，以及形成於晶圓表面上的各 層。「基體表面」一詞係指包含在一半導體晶圓之上的大 部份曝露各層，諸如矽表面，絕緣層與金屬線等。 如圖1中所顯示的，本發明方法之啓始步驟係在具有 場氧化物層1·2，以及在其上形成有FET元件的一基體上製 作一位元線。場氧化物層12係被形成於一半導體基體10 上以供界定主動元件區以及絕緣區。較佳的基體應由具有 (100)晶格指向的Ρ型單晶矽所構成。相對較厚的一層場 氧化物（FOX) 12環繞著主動元件區而形成，以便電性地 將該些區域絕緣。此場氧化物乃是利用一層厚氧化矽（墊 氧化物）與構成一種氧化阻障的一層更厚的氮化矽層，將 主動元件區加以遮罩而形成。矽基體接著再於一種氧化的 環境之中進行氧化，以形氧化物層12。其較佳的厚度應 在大約4,0 0 0至6,0 0 0 A的範圍內。 在將氮化矽阻障層與墊氧化物以常用的濕蝕刻程序除 去之後，接著再於主動元件區域之中形成半導體FET元 件。DRAM中最常用的元件是爲M0SFET。此元件係利用首 本纸張尺度適用中國國家標準（〔阳）八4規格（210/ 297公釐） (請先閣讀背面之注意事項再填寫本頁) 裝. 、νβ 經濟部中央標準局員工消費合作社印聚 經濟部中央標準局員工消費合作社印聚 廳002 五、發明説明（g ) 先將主動元件區予以熱氧化以形成一薄閘極氧化物13而 形成。就一3V的電源而言，其較佳的厚度應在大約75至 120 A之間。 一層適當的掺雜複晶矽層（亦即，第一複晶矽層），與 一絕緣層被沉積於基體10之上，且可以使用習知的微影 技術在複晶矽層中，以及由轉移閘14，18所構成的絕緣 層中形成所需圖形。此些步驟可以在主動元件區域內形成 MOSFET的轉移閘。如圖1中所顯示的，於基體表面上形 成有兩個轉移閘，其係設置於場氧化物區12之間。轉移 閘與氧化物12之間的第一主動區4(例如，源極），係被用 來與記憶胞電容達成電性連接的。轉移閘之間的區域，即 第二主動區8 (例如，汲極），則是用來電性地連接位元 線的。其他的轉移閘則可以形成於基體上的其他位置。轉 移閘可爲用以將MOSFET閘電極電性地連接至DRAM晶片上 適當週邊電路的字元線。接著即形成N通道MOSFET的淡 摻雜源極-汲極4A，8A，此通常是利用通過轉移閘14， 18與場氧化物12之間植入N型離子物種而形成，諸如植入 砷或磷。例如，一種典型的植入物可爲磷P31，其劑量 (dose)大約在1E13至1E14原子/cm2之間，且其植入 能量約在30至80 KeV之間。 在形成淡摻雜的源極/汲極4A，8A之後，側壁間隔層 16，17即可形成於轉移閘14，18的側壁上。面朝向汲極 8 (位元線）的此些側壁間隔層17被稱爲內側壁間隔層。 此些側壁間隔層16，17最好是利用沉積一層低溫氧化3〇〇§M.§bc / 002 A7 __________B7 V. Description of the invention (丨) Technical scope The present invention generally relates to the manufacturing method of semiconductor memory devices, in particular to the production of bit lines on the capacitor array of memory cells method. Technical Background Due to very large-scale integration semiconductor technology (VLSI), the circuit density of wafers has increased significantly. The miniaturized components built on the semiconductor substrate and these constitute the circuits, which are separated from each other in a very close manner, and the packaging density has also increased significantly. Recent advances in photolithography technology, such as phase-shifting masks and self-aligned processes, have further reduced the size of semiconductor devices and Increased circuit density. These developments have led to ultra large scale (ULSI, ultra large scale int e g r a t i o η) devices that can produce more than one million transistors on a wafer with a minimum device size of less than one micron. Some of the circuit components manufactured using such improved processes have encountered problems with limited electrical characteristics due to their reduced size. Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs printed n 1 ^ 1 ^ 1 ^^^ 1 m > I ^^^ 1 ^^^ 1 ^ m · m ^^^ 1 ^^^ 1 ^ t .- (please first Read the precautions on the back and then fill out this page. One of the circuit elements that encounters electrical limitations is a storage cell array on a dynamic random-access memory (DRAM) chip. Such individual DRAM storage cells, usually composed of a single metal oxide semiconductor field effect transistor (MOS-FET, metal-0χide-semic ο nduct 〇rfie 1 d-effecttransist 〇r) and a single capacitor, are already in the electronics industry Nakamoto paper scale is applicable to Chinese National Standard (CNS) Λ4 specification (210X2 < J7mm) 0553TWF.DOC / 002 A7 B7 V. Description of invention () is widely used to store data. One billion DRAM cell can store one bit of data in the capacitor in the form of charge. The reduction in the memory cell's electrical capacity due to the reduction in the area of the memory cell is a serious obstacle for DRAM to increase the packing density. Therefore, the problem of reduced memory cell capacitance must be solved to achieve a higher packing density in semiconductor memory devices. The reduction in the capacitance of the memory cell not only reduces the ability to read data, but also increases the soft error rate of the memory cell (soft error rate), and due to the operation of the resistive element, it consumes more The amount of electricity. In general, in a 64 MB DRAM with a memory cell area of about 1.5 μm2 and a common two-dimensional space stacked capacitor cell architecture, even if a high dielectric constant material such as molybdenum pentoxide (Ta205) is used, It is also unable to obtain sufficient memory cell electrical capacity. Therefore, some people have proposed a stacked capacitor with a three-dimensional spatial structure to increase the capacitance of the memory cell. Such stacked capacitors include, for example, double-stacked, wing-shaped, cylindrical, distributed stacked, and box-shaped capacitors. The valley array structure of the conventional DRAM generally uses buried bit lines or non-buried bit lines. gWhen using the embedded bit line structure, the form of the provided bit line is close to each other in the vertical direction with the bit line contact window of the memory cell field effect transistor (FET). The memory cell capacitance is horizontal The form of 'is formed in character_bit_0. When the difficult-to-bit line structure is formed, the deep vertical contact window is closed by reaching the memory cell through a thick insulating layer, which is said to be under the bit line. This non-embedded bit line structure is also known as "n ^-n ^ i 1 ^ 1 m ^^^ 1 ^ m · .. m ^^^ 1 .HI ^^^ 1 ^ ^^ 1 ~ 0¾., -Port (please read the precautions on the back before filling in this page) The Ministry of Economic Affairs won the bid for Falcon Bureau Μ Industrial Consumption Ϊ This paper scale is applicable to the Chinese National Standard (CNS) Λ4 specifications (21〇X29: ^ J 'y' '· A7 B7 3 G doc / 002 V. Description of the invention (彡) electric valley (capacitor-underbitline) or "bitline on the electric valley" (bitline-〇ver-capacitor) structure, which also It is the subject of the present invention. The following US patents disclose the related processes and the structure of the bit lines. US Patent No. 5,38 9,5 6 6 issued to Lage, issued to Ch〇i et al. U.S. Patent No. 5,4 2 2,2 9 5 and U.S. Patent Ning 5,40 1,68 1 issued to Dennis〇n. However, this can be improved by using fewer optical and etched steps Process of these conventional techniques. A variety of such conventional methods require a substantial number of manufacturing processes that are more complicated and expensive: process steps and / or planar structures. Other process methods also require @ 赖Controlling the progress of etching to a predetermined etch depth, which can be quite difficult to control in semiconductor manufacturing environments. In addition, bit line contact window openings often require large process errors to avoid bit line contact windows There is a short circuit with the word line or capacitor plate. Furthermore, the size of the memory cell must be further reduced to achieve the purpose of reducing the size of the device. For the development of these, the process cost can be minimized, And it is a challenge to increase the manufacturing yield of semiconductor devices to the highest capacitance and bit line manufacturing method. In particular, for the development of a method that can minimize the number of photoresist mask operations, and still provide The method of maximum process error tolerance is also a challenge. The purpose of the present invention is to provide a method for manufacturing a bit line contact window that can reduce the optical and etching steps. ^^ 1 ^^ ^ 1 ί ί — ^ ϋ ^^^ 1 'i ^^^ 1 inn ^ i-J. Body, va *-(please read the precautions on the back before filling in this page) Ministry of Economic Affairs Central Standards Bureau Bureau of Industry and Consumption The size of the paper printed by the company is appropriate._Home Material (CNS) M Specification (21 OX 297 mm) 0553TWF.DOC / 002 A7 B7 _ V. Description of the invention (>) Another object of the invention is to provide a reduction Process complexity 'and provide additional tolerance for program errors, to reduce the bit line and word line and electrode plate short circuit situation of a "bit line on the capacitor" manufacturing method. Another object of the present invention is to provide a method for making dynamic random access memory (DRAM), which uses only three polycrystalline silicon layers and bit lines with higher density, but its cost is lower and it is easy Manufacturing 'and manufacturing yield can also be increased. In order to achieve the above object, the present invention provides a method for manufacturing bit lines of high-density memory elements. The method first provides a drain region 8 between two separate transfer gates 14, 18 on a substrate 10, and a first oxide sand insulating layer 2Q, 22 on the drain region 8 with a drain electrode 8 The polycrystal cuts a capacitor of the top electrode plate 30 and an intermetal dielectric layer above the structure formed thereby. First, a bit line contact opening is formed in the intermetal dielectric layer and terminates at the top electrode plate on the drain. Next, an anisotropic polycrystalline silicon etching process is used to remove the top electrode plate on the drain. Third, a dielectric spacer layer 40 is formed on the sidewall of the bit line opening. The spacer layer separates the top electrode plate from the bit line. The spacer layer also allows the use of smaller bit lines, thus making the memory cells made smaller. The fourth 'bit line opening aligned by the spacer layer is covered with metal in order to contact the bit line. In more detail, the present invention provides a method for making bit lines of high-density DRAM. This DRAM is fabricated using only three polysilicon layers. This method first lifts between two separation transfer gates 14 on a substrate 10 ____ 6 The paper size is applicable to the Hujia County (CNS) M specification (2IGx 297 mm) —------ {装- ----- Order •-(Please read the precautions on the back before filling the nest page) Printed by the Ministry of Economic Affairs Bureau of Central Bureau of Consumer Affairs 0553TWF.DOC / 002 A7 0553TWF.DOC / 002 A7 Central Standard of the Ministry of Economy Printed bag B7 of the employee consumer cooperative of the Bureau. V. Description of invention (夂) Provide a drain area 8. Next, the first silicon oxide insulating layers 20, 22 are formed on the drain electrode 8, the inner side wall of the transfer gate, and the surface of the top gate electrode. The storage electrode 24 is formed on the source 4. Then, a capacitor dielectric layer 26 is formed on the entire substrate surface including the storage electrode 24. At least a first polycrystalline silicon layer 30 (top plate) is formed on the capacitor dielectric layer 26 and the first insulating layer 22. This first polycrystalline silicon layer should preferably be formed on the entire substrate surface. An intermetal dielectric layer 32 is formed on the first conductive layer 30. A first opening 38 is formed in the first intermetal dielectric layer 32 above the drain 8 to expose the first polycrystalline silicon layer 30 on the drain 8. The first opening is defined by the sidewall 38 of the inter-metal dielectric layer 32. The exposed first polycrystalline silicon layer 30 undergoes anisotropic etching in the first opening, exposing the first silicon oxide insulating layer 22 on the drain electrode 8. The anisotropic etching process also forms the sidewalls of the first polycrystalline silicon layer 30 in the first opening. In an important step, a dielectric sidewall spacer is formed on the sidewalls of the intermetal dielectric layer and the first conductive layer, the dielectric sidewall spacer is also formed on the first insulating layer 22, Thus, a second opening 38A is formed. Then, a bit line contact plug 50 is formed in the second opening to make contact with the drain. Finally, a protective layer and a metal layer are formed on the surface at this time to connect the active parts in the circuit. The present invention provides various advantages over conventional techniques. The present invention only uses three polysilicon layers to define a DRAM memory cell and bit line contact window. Compared with the prior art process, the present invention reduces the mask and etching steps. In addition, the four-step process of the bit line contact window can significantly reduce the need to avoid the character line (or capacitor top electrode plate 3G) and bit paper size. The Chinese National Standard (CNS) Λ4 specification (210X 297 mm ) (Please read the precautions on the back before filling out this page) Binding · Order 0553TWF.DOC / 002 A7 B7__ printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (6) Protection space for short circuit between lines 50 . Compared with the conventional DRAM manufacturing process, the present invention can reduce the memory cell area by 10 to 20%. The method of the present invention also uses a polycrystalline silicon layer 30 to cover the entire wafer except for the bit line 5 (3 for connecting to the bit line contact area of the drain. The third polycrystalline silicon layer Such a carpet covering of 30 (top electrode plate) can significantly reduce the DRAM soft-misrecord ratio. The simple description of the drawings illustrates the characteristics and advantages of a semiconductor device according to the present invention and the manufacture of such a semiconductor device according to the present invention Further details of the manufacturing process will become more clear and easy to understand in the detailed description that follows with reference to the attached drawings, and in the drawings, corresponding reference numbers are used to mark similar or corresponding The components, regions, parts, etc., of which: V Figures 1 to 8 are cross-sectional views showing the method steps of making a DRAM bit line according to the present invention. Description of the preferred embodiments Detailed description will be made with reference to the attached drawings. The present invention provides a method for manufacturing a memory cell (for example, a dram), which has a capacitor upper line with a small size and requires fewer optical steps. The yield can be improved due to the increase in the tolerance of the process error. At present, when manufacturing DRAM memory cells, the process steps used to fabricate field oxide (FOX) and field effect transistor structures are only described here. Briefly explain 'in order to make it easier to understand the present invention. Those skilled in the art should understand that other types of semiconductor devices can also be used by using additional process steps not included in the description of the Benning embodiment Included in the DRAM chip __8 This paper standard is applicable to China ’s CNS> M specifications (^ 7〇 > < 297mm>-^^ 1 ml km m mf n ^ i. —A ^ i ^^^ 1 mn ^ i «m \ J (Please read the precautions on the back before filling in this page) 0553TWF.DOC / 002 A7 B7 5. In the description of invention (η). For example, the P-well area and CMOS circuit in the N-type substrate can be It is also made. In addition, it should be understood that only one of the multiple DRAM storage cells formed on the substrate is shown in the drawing. In addition, this bit line can also be used in addition to DRAM Other than the wafer form. In addition to this, this bit line also It can be applied to other chip forms such as SRAM, EPROM and E2PROM. It should be understood that the substrate 10 should possibly include a semiconductor wafer, active and passive components formed in the wafer, and formed on the wafer surface The various layers. The term "substrate surface" refers to the most exposed layers contained on a semiconductor wafer, such as silicon surfaces, insulating layers and metal lines. As shown in Figure 1, the method of the present invention The initial step is to fabricate a bit line on a substrate having a field oxide layer 1.2 and FET elements formed thereon. The field oxide layer 12 is formed on a semiconductor substrate 10 for defining active elements Area and insulation area. The preferred substrate should be made of P-type single crystal silicon with (100) lattice orientation. A relatively thick layer of field oxide (FOX) 12 is formed around the active device area to electrically insulate these areas. This field oxide is formed by using a thick layer of silicon oxide (pad oxide) and a thicker layer of silicon nitride to form an oxidation barrier to mask the active device area. The silicon substrate is then oxidized in an oxidizing environment to form the oxide layer 12. The preferred thickness should be in the range of about 4,00 to 6,0 0 0 A. After removing the silicon nitride barrier layer and the pad oxide by a common wet etching process, a semiconductor FET element is then formed in the active element area. The most commonly used component in DRAM is the MOSFET. This element is based on the first paper standard applicable to the Chinese national standard ([Yang] 84 specifications (210/297 mm) (please read the precautions on the back before filling this page). Νβ Central Standards Bureau of the Ministry of Economic Affairs Employee Consumption Cooperative Printing and Congregation Department, Employee Cooperative Printing and Congregation Office 002, Central Bureau of Standards, Ministry of Economic Affairs V. Invention Description (g) First, the active component area is thermally oxidized to form a thin gate oxide 13. For a 3V power supply, the preferred thickness should be between about 75 and 120 A. An appropriate doped polycrystalline silicon layer (ie, the first polycrystalline silicon layer), and an insulating layer are deposited on the substrate 10, and can be formed in the polycrystalline silicon layer using conventional lithography techniques, and A desired pattern is formed in the insulating layer composed of transfer gates 14, 18. These steps can form the transfer gate of the MOSFET in the active device area. As shown in FIG. 1, two transfer gates are formed on the surface of the substrate, which are disposed between the field oxide regions 12. The first active region 4 (e.g., source) between the transfer gate and the oxide 12 is used to electrically connect the memory cell capacitor. The area between the transfer gates, the second active area 8 (for example, the drain), is used to electrically connect the bit lines. Other transfer gates can be formed at other locations on the substrate. The transfer gate may be a word line used to electrically connect the MOSFET gate electrode to appropriate peripheral circuits on the DRAM chip. Next, the lightly doped source-drain 4A, 8A of the N-channel MOSFET is formed. This is usually formed by implanting N-type ion species between the transfer gates 14, 18 and the field oxide 12, such as arsenic or phosphorus. For example, a typical implant may be phosphorus P31, whose dose is about 1E13 to 1E14 atoms / cm2, and its implantation energy is about 30 to 80 KeV. After the lightly doped source / drain electrodes 4A, 8A are formed, the sidewall spacers 16, 17 can be formed on the sidewalls of the transfer gates 14, 18. These sidewall spacers 17 facing the drain 8 (bit line) are called inner sidewall spacers. These sidewall spacers 16, 17 are preferably deposited by depositing a low temperature oxidation
In HI In (m « ml- - · 、vd (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 0553TWF.DOC/002 A7 ___ B7 五、發明説明（巧） 矽，並再進行非等向性回蝕刻到達矽層表面而形成。例 如，氧化矽層可以是利用四乙氧基矽烷（TEOS， tetraethoxysi lane)在溫度約爲650至900 °C範圍進 行化學氣相沉積，並再於一低壓活性離子蝕刻器內進行回 蝕刻而形成的氧化矽層。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 至少有兩種方法可以形成源極/汲極區4，8。首先， M0SFET的源極/汲極區4，8可以利用N型離子物種，諸如 砷（As75)，在間隔層16，17之間植入，以便完成源極/ 汲極區4，8。其植入通常是利用透過厚度約爲2 0 0至300 A的薄層氧化矽層而完成，以便將植入不均（implant channeling)的情形減至最低程度，並保護免受金屬與 其他雜質所污染。典型的植入劑量應在大約1E15至2E16 原子/cm2之間，且其植入能量應約在20至70 KeV之間。 N +區8最好是利用砷或磷植入所形成，其典型劑量應在大 約1E15至1E16原子/cm2之間，且最好爲大約5E15原子 /cm2，而其植入能量則約在20至70 KeV之間。其他的區 域在此源極/汲極離子植入的期間皆被遮蔽起來。第二種 方法則是，N +區4最好是利用如圖2中所顯示的，由後續 形成的複晶矽層24將雜質擴散出來而摻雜形成。 本實施例的其餘部份係特別與本發明之前述目的有 關，其係有關於具有小尺寸並更適於產製位元線的三層複 晶矽層DRAM之製作。 如圖1中所顯示的，第一絕緣層20，22至少形成於汲 極8，轉移閘的內側壁17，以及頂閘電極表面之上。第一 11 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210 X 29?公釐） 0553TWF.DOC/002 Α7 Β7 經濟部中央標準局員工消費合作社印裝 五、發明説明（丨) 絕緣層20，22可由氧化矽所構成，諸如沉積的氧化砂。 第一絕緣層20，22可有具有大約1,000至2,〇〇〇 A範圍 之間的厚度。第一絕緣層內在源極區4上的開口最好係利 用習知的微影與乾蝕刻技術加以界定。 如圖2中所顯示的，儲存電極24係形成於源極4 ’轉 移閘的外側壁，以及頂閘電極表面之上。儲存電極24構 成了到達汲極4的一種電性連接。在此時的基體表面上’ 儲存電極24可以利用對順帶同時進行摻雜的導電性複晶 矽層進行成像而構成。複晶矽層被保留下來覆蓋源極4， 外側壁16，以及頂轉移閘表面18的部份，以便因而形成 儲存電極24。儲存電極24的厚度約在2,000至6,000 A 的範圍之間。儲存電極24可具有大約5E20至5E21原子 /cm3範圍之間的雜質濃度，且最好應約爲1E21原子 /cm3。此外，儲存電極24可以利用數種技術予以增強， 以便增加其表面面積。例如，一種半球形晶粒複晶砂 (HSG , hemispherical grain po 1 y s i 1 i con)層可 於頒予Dennison的美國專利第5 ,401, 681號案中所描述 的儲存電極之上形成。此外，N +區4最好是利用如圖2中 所顯示的，由複晶矽層24將雜質擴散出來而摻雜形成。In HI In (m «ml--·, vd (please read the precautions on the back before filling out this page) This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 0553TWF.DOC / 002 A7 ___ B7 5. Description of the invention (Qiao) Silicon is formed by anisotropic etch back to the surface of the silicon layer. For example, the silicon oxide layer can be made of TEOS (tetraethoxysi lane) at a temperature of about 650 to The silicon oxide layer formed by chemical vapor deposition in the range of 900 ° C and then etched back in a low-pressure active ion etchant. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economy This page) There are at least two ways to form the source / drain regions 4, 8. First, the source / drain regions 4, 8 of the MOSFET can use N-type ion species, such as arsenic (As75), in the spacer layer 16 , 17 implanted in order to complete the source / drain regions 4, 8. Its implantation is usually done by using a thin silicon oxide layer with a thickness of about 200 to 300 A, in order to uneven implantation (Implant channeling) to a minimum, and Protect from contamination by metals and other impurities. The typical implantation dose should be between about 1E15 to 2E16 atoms / cm2, and the implantation energy should be between about 20 to 70 KeV. N + zone 8 is best used For arsenic or phosphorus implantation, the typical dose should be between about 1E15 to 1E16 atoms / cm2, and preferably about 5E15 atoms / cm2, and the implantation energy is about 20 to 70 KeV. Others The region is masked during the source / drain ion implantation. The second method is that the N + region 4 is preferably made of the subsequently formed polycrystalline silicon layer 24 as shown in FIG. 2 Impurities are diffused out and doped to form. The rest of this embodiment is particularly related to the aforementioned object of the present invention, which relates to a three-layer polycrystalline silicon DRAM with a small size and more suitable for producing bit lines As shown in FIG. 1, the first insulating layers 20, 22 are formed at least on the drain electrode 8, the inner sidewall 17 of the transfer gate, and the surface of the top gate electrode. The first 11 paper scales are in accordance with Chinese national standards (CNS) Λ4 specification (210 X 29? Mm) 0553TWF.DOC / 002 Α7 Β7 Central Ministry of Economic Affairs Printed by the Quasi-Council Staff Consumer Cooperative V. Description of the invention (丨) The insulating layers 20, 22 may be composed of silicon oxide, such as deposited oxide sand. The first insulating layers 20, 22 may have about 1,000 to 2,000 A The thickness between the range. The opening in the first insulating layer on the source region 4 is preferably defined using conventional lithography and dry etching techniques. As shown in FIG. 2, the storage electrode 24 is formed on the source 4 'The outer side wall of the transfer gate and the surface of the top gate electrode. The storage electrode 24 constitutes an electrical connection to the drain 4. The storage electrode 24 on the surface of the substrate at this time can be formed by imaging a conductive polycrystalline silicon layer doped along with the band. The polycrystalline silicon layer is retained to cover the source 4, the outer sidewall 16, and the portion of the top transfer gate surface 18 to thereby form the storage electrode 24. The thickness of the storage electrode 24 is approximately in the range of 2,000 to 6,000 A. The storage electrode 24 may have an impurity concentration in the range of approximately 5E20 to 5E21 atoms / cm3, and should preferably be approximately 1E21 atoms / cm3. In addition, the storage electrode 24 can be enhanced using several techniques to increase its surface area. For example, a layer of hemispherical grain polycrystalline sand (HSG, hemispherical grain po 1 y s i 1 i con) can be formed on the storage electrode described in US Patent No. 5,401, 681 issued to Dennison. In addition, the N + region 4 is preferably formed by doping by diffusion of impurities from the polycrystalline silicon layer 24 as shown in FIG. 2.
如圖3中所顯示的，儲存電極24之上再行沉積一電容 介電質層26。介電質層26的材料可以爲具有高介電常 數，並爲連續且無任何針孔的任何合適材料。符合條件的 介電質層26可由氮化矽，氧化物/氮化物/氧化物（〇N〇) 膜，五氧化二鉅（Ta2(h)，以及氧化矽材料所構成。就3V . 12 本紙張尺度適用中國國家標準（CNS ) Λ4規格（2IOX297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝. 經濟部中央標準局員工消費合作社印製 3060¾¾17°0^002 · a7 ___B7___ 五、發明説明（1丨） 的電源而言，符合條件的介電質層26最好具有約在45至 60 A之間的等效氧化物厚度。 接著參考圖4，形成一頂電極板3G以覆蓋介電質層。 要達成此覆蓋可以利用在基體表面上形成一第一導電層 30。第一導電層30可由矽化鎢，或經摻雜的複晶矽材料 所構成。第一導電層最好是以複晶矽，利用LPCVD (low pressure chemical vapor deposition，低壓化學 氣相沉積）反應器，在大約5 50至6 50 °C溫度範圍的製程 所製作形成。複晶矽層可爲摻雜N +型，利用離子植入， 例如，利用砷離子，以約20至80 KeV之間的植入能量進 行植入，且植入劑量大約爲1E15至1E16原子/cm2之間。 另外一種方式，複晶矽層亦可以利用順帶同時進行的程 序，在複晶矽沉積時進行摻雜。第一導電層30的厚度最 好約在1，0 0 0至2,00Ό A的範圍之間。第一導電層的雜 質濃度可以大約在1E21至5E22原子/cm3之間，且最好約 爲1E22原子/ cm3。 在本發明中，第三複晶矽層30 (頂電極板）最好除了 在汲極8之上供位元線5G連接至汲極的位元接觸區之外， 亦應覆蓋整個的晶片。第三複晶矽層30的此種地毯式覆 蓋可以顯著地減低軟錯記比率。 如圖4中所顯示的，第一導電層30之上形成一金屬間 介電質層32。金屬間介電質層32最好是由硼磷矽玻璃 (BPSG， borophosilicate glass)，或未摻雜的 13 n- in i^i— m ^^^1 -i^n 一"' • . u? 、vd (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 0553TWF.DOC/002 A7 B7 五、發明説明（D) TEOS (氧化矽）所構成，並具有大約5,000至1 0,000 A 範圍之間的厚度。 接著，在汲極8之上於金屬間介電質層32中形成第一 開口 38，曝露出汲極8之上的第一導電層30。第一開口係 由金屬間介電質層32的側壁38所界定。如同圖4之中所顯 示的，第一開口在第一金屬間介電質層中的形成，包含了 形成具有開口 37的一第一遮蔽層（resist layer) 34，透過開口 37而非等向性地蝕刻第一金屬間介電質 層，並再將第一遮蔽層除去。第一金屬間介電質層中第一 開口 38的開口尺寸係在設計準則（design rules)可 以容許的範圍內，且其深度約在5,0 0 0至1 0,000 A的範 圍之間。 如圖5中所顯示的，在第一開口 38內所曝露出來的第 一導電層30以一次非等向性蝕刻程序將之除去。非等向 性蝕刻的程序會曝露出汲極8之上的第一絕緣層32。非等 向性蝕刻的程序亦會在第一導電層30中於第一開口內形 成側壁。非等向性蝕刻的程序可以爲一種乾複晶矽蝕刻程 序，具有針對氧化矽上複晶矽的高度選擇性。非等向性蝕 刻的程序最好是爲使用包含有反應劑的氯化物（CL)，諸 如CF2-Cl2的一種乾蝕刻程序。 如圖6中所顯示的，介電質側壁間隔層40係形成於金 屬間介電質層32以及第一導電層30的側壁上。側壁間隔 層40至少局部地界定了一第二開口 38 A。側壁間隔層40 可以利用在金屬間介電質層32 ’第一開口內的第一導電 ' 14 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公嫠） (請先閲讀背面之注意事項再填寫本頁) 裝· -m 經濟部中央標準局員工消費合作社印製 0553TWF.DOC/002 A 7 0553TWF.DOC/002 A 7 經濟部中央標準局員工消費合作社印製 五、發明説明（丨> ) 層，以及第一絕緣層32上沉積氧化物或氮化物的一介電 質層而形成。接著’通過第一開口內的第一導電層’介電 質層與第一絕緣層經過非等向性蝕刻而曝露出汲極8 ’並 因而形成了第二開口 38A(亦即’位元線接觸開口）。此種 蝕刻程序界定了金屬間介電質層以及第一導電層30側壁 上的介電質側壁間隔層40。間隔層40最好應由氮化物所 構成，並應具有大約4 0 0至60G A範圍之間的寬度’且最 好約爲5 0 0 A寬。 如圖7中所顯示的，位元線接觸塞50係被形成於接觸 到汲極的第二開口 38A之中。位元線接觸塞50最好係由鎢 或鋁所構成。位元線接觸窗可以利用在第二開口 38A之內 以及在金屬間介電質層之上沉積一導電層而形成。金屬間 介電質層上的導電層接著再進行成像。 如圖8中所顯示的，沉積一護層54並進行成像以便提 供一個向下對著位元線接觸塞50的一個接觸開口。此護 層最好是由硼磷矽玻璃（BPSG)所構成。數元線的材料56 被沉積下來並進行成像以便提供所需要的數元線（例如， 經過成像的金屬線）。 因此，本發明提供了一種方法，可以僅只使用三層的 複晶矽層14，24，30便製成DRAM記憶胞。本發明與諸如 四層複晶矽層的DRAM製程的習知技藝製程相較之下，減 少了遮罩以及蝕刻的步驟。與習知的四層複晶矽層的 DRAM記憶胞製程方法相較之下，本發明去除了兩次微影 步驟，兩次RIE蝕刻步驟，以及位元線複晶矽模組。此 15 ^^^1 ml dn —^n nn mi ^^^1 In ml il^i ^^^1 lJ - 一 i (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X2S»7公釐） .DOC/002 A7 五、發明説明（丨f) 外，位元線接觸窗的四步驟製程可以顯著地減少必須用來 避免字元線（或電容頂電極板）與位元線之間發生短路的 保護空間。這可以容許DRAM記憶胞的尺寸得以進一步地 縮小。 本發明的方法亦使用複晶矽層30 (頂電極板）來覆蓋 在汲極8之上，除了位元線50用以連接至汲極的位元接觸 區以外的整個晶片。此種地毯式覆蓋可以顯著地減低軟錯 記比率。 雖然附圖中所顯示的是一種堆疊式電容，但如同習於 本技藝之士所可以瞭解的，本發明的位元線製作方法亦可 以適用於任何型式的電容，諸如堆疊與柱形電容。 雖然本發明已參考所附圖式依據較佳之實施例而進行 說明描述如上，但習於本技藝之士應可瞭解的是，其各種 的細節之變化皆可以輕易地進行而仍不偏離於本發明之精 神範疇之外。 Γ Γ " 批衣 訂 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標隼局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X2W公釐）As shown in FIG. 3, a capacitor dielectric layer 26 is further deposited on the storage electrode 24. The material of the dielectric layer 26 may be any suitable material having a high dielectric constant and being continuous without any pinholes. Eligible dielectric layer 26 may be composed of silicon nitride, oxide / nitride / oxide (〇N〇) film, pentoxide (Ta2 (h), and silicon oxide material. 3V. 12 books The paper scale is applicable to the Chinese National Standard (CNS) Λ4 specification (2IOX297mm) (please read the precautions on the back before filling in this page). Printed by the Ministry of Economic Affairs Central Standards Bureau staff consumer cooperative printed 3060¾¾17 ° 0 ^ 002 · a7 ___B7___ 5 2. Description of the invention (1 丨) For the power supply, the qualified dielectric layer 26 preferably has an equivalent oxide thickness between about 45 and 60 A. Next, referring to FIG. 4, a top electrode plate 3G is formed to Covering the dielectric layer. To achieve this coverage, a first conductive layer 30 can be formed on the surface of the substrate. The first conductive layer 30 can be made of tungsten silicide or doped polycrystalline silicon material. The first conductive layer is the most Fortunately, it is made of polycrystalline silicon using a LPCVD (low pressure chemical vapor deposition) reactor at a temperature range of about 5 50 to 6 50 ° C. The polycrystalline silicon layer can be doped N + type, using ion implantation, example For example, using arsenic ions, the implantation energy is between about 20 and 80 KeV, and the implantation dose is about 1E15 to 1E16 atoms / cm2. In another way, the polycrystalline silicon layer can also be used simultaneously The procedure to be performed is doping during the deposition of polycrystalline silicon. The thickness of the first conductive layer 30 is preferably in the range of approximately 1,000 to 2,00Ό A. The impurity concentration of the first conductive layer may be approximately 1E21 to 5E22 atoms / cm3, and preferably about 1E22 atoms / cm3. In the present invention, the third polycrystalline silicon layer 30 (top electrode plate) is preferably provided on the drain 8 above the bit line 5G The bit contact area connected to the drain should also cover the entire wafer. This carpet coverage of the third polycrystalline silicon layer 30 can significantly reduce the soft miss rate. As shown in FIG. 4, An inter-metal dielectric layer 32 is formed on a conductive layer 30. The inter-metal dielectric layer 32 is preferably made of borophosphosilicate glass (BPSG) or undoped 13 n-in i ^ i — M ^^^ 1 -i ^ n 一 " '•. U?, Vd (please read the precautions on the back before filling this page) The paper size is suitable Made with China National Standard (CNS) A4 specification (210X 297mm) 0553TWF.DOC / 002 A7 B7 5. Invention description (D) TEOS (silicon oxide), and has a thickness in the range of about 5,000 to 10,000 A Next, a first opening 38 is formed in the intermetal dielectric layer 32 above the drain 8 to expose the first conductive layer 30 above the drain 8. The first opening is defined by the sidewall 38 of the intermetal dielectric layer 32. As shown in FIG. 4, the formation of the first opening in the first intermetal dielectric layer includes forming a first resist layer 34 having an opening 37 through the opening 37 rather than isotropically The first intermetal dielectric layer is etched, and then the first shielding layer is removed. The opening size of the first opening 38 in the first intermetal dielectric layer is within the allowable range of design rules and its depth is approximately in the range of 5,000 to 10,000 A. As shown in FIG. 5, the first conductive layer 30 exposed in the first opening 38 is removed by an anisotropic etching process. The anisotropic etching process will expose the first insulating layer 32 above the drain 8. The anisotropic etching process also forms sidewalls in the first opening in the first conductive layer 30. The anisotropic etching process may be a dry polycrystalline silicon etching process, which has a high selectivity for polycrystalline silicon on silicon oxide. The anisotropic etching process is preferably a dry etching process using a chloride (CL) containing a reactant, such as CF2-Cl2. As shown in FIG. 6, the dielectric sidewall spacer 40 is formed on the sidewalls of the inter-metal dielectric layer 32 and the first conductive layer 30. The sidewall spacer 40 at least partially defines a second opening 38A. The sidewall spacer 40 can be used in the inter-metal dielectric layer 32 'the first conductivity in the first opening' 14 This paper size is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297 gong) (please read the notes on the back first (Fill in this page again) Installed -m Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 0553TWF.DOC / 002 A 7 0553TWF.DOC / 002 A 7 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of Invention (丨 >) Layer, and a dielectric layer of oxide or nitride deposited on the first insulating layer 32 is formed. Then, the dielectric layer and the first insulating layer are exposed to the drain electrode 8 by anisotropic etching through the "first conductive layer in the first opening" and thus a second opening 38A (ie, a bit line) is formed Contact opening). This etching process defines the intermetal dielectric layer and the dielectric sidewall spacer 40 on the sidewalls of the first conductive layer 30. The spacer layer 40 should preferably be composed of nitride and should have a width in the range of about 400 to 60 G A and preferably about 500 A wide. As shown in FIG. 7, the bit line contact plug 50 is formed in the second opening 38A that contacts the drain. The bit line contact plug 50 is preferably made of tungsten or aluminum. The bit line contact window can be formed by depositing a conductive layer within the second opening 38A and above the intermetal dielectric layer. The conductive layer on the intermetal dielectric layer is then imaged. As shown in Fig. 8, a protective layer 54 is deposited and imaged to provide a contact opening downwardly facing the bit line contact plug 50. The protective layer is preferably made of borophosphosilicate glass (BPSG). The material 56 of the digit line is deposited and imaged in order to provide the required digit line (for example, an imaged metal line). Therefore, the present invention provides a method by which only three polysilicon layers 14, 24, and 30 can be used to form a DRAM memory cell. Compared with the prior art process such as the four-layer polycrystalline silicon layer DRAM process, the present invention reduces the masking and etching steps. Compared with the conventional four-layer polycrystalline silicon layer DRAM memory cell manufacturing method, the present invention eliminates two lithography steps, two RIE etching steps, and bit line polycrystalline silicon modules. This 15 ^^^ 1 ml dn — ^ n nn mi ^^^ 1 In ml il ^ i ^^^ 1 lJ-Yi (please read the precautions on the back before filling this page) This paper size is applicable to Chinese national standards (CNS) Λ4 specification (210X2S »7mm). DOC / 002 A7 V. Invention description (丨 f) In addition, the four-step process of the bit line contact window can significantly reduce the need to avoid the character line (or capacitor Protective space where a short circuit occurs between the top electrode plate and the bit line. This allows the size of the DRAM memory cell to be further reduced. The method of the present invention also uses a polycrystalline silicon layer 30 (top electrode plate) to cover the entire wafer except for the bit contact area of the bit line 50 used to connect to the drain. This carpet covering can significantly reduce the soft miss rate. Although the drawing shows a stacked capacitor, as can be understood by those skilled in the art, the bit line fabrication method of the present invention can also be applied to any type of capacitor, such as stacked and cylindrical capacitors. Although the present invention has been described and described above with reference to the accompanying drawings according to the preferred embodiments, those skilled in the art should understand that various changes in their details can be easily carried out without departing from this. Out of the spirit of invention. Γ Γ " Approval of clothing (please read the precautions on the back before filling out this page) Printed by the Employee Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs This paper standard is applicable to the Chinese National Standard (CNS) A4 specification (210X2W mm)