經濟部令央揉率局貝工消费合作杜印*. 咖672 A7 B7 五、發明说明（） 本發明你鼷於一種載醍附著晶片之方法及構造，主要 為一種可供晶片之陣列接脚良好連接之載體構造，且於·晶 片與載鳢结合後，更為一種缩入於戰體中之型式，更僅需 於外層接脚處經以錫凸塊及導罨膠銜接形成多雇堆叠立鳢 構造者》 按現今己見的積體踅路外包裝之方式上，大部份為如 第四A、B圖之側視圖及俯視圈所示.fe將積體電路（8 〇)之輸入/輸出各式接脚（8 1)分佈於周邊位置，而 經接脚（8 1)以表面黏著（SMT)或焊接方式與電路 > 板（7 0)上之迺路連接者，而為達缩小體積之包裝型態 ，即有採用如第五A、B圖所示，為直接令積體霍路晶片 (8 2 )直接黏箸於電路板（7 0 )上，而直接排列於晶 片（82)周邊位置之接觸區以金線（83)(或鋁線） 打線至電路板（70)上，再以外覆保護® (90)予以 保護住，據以免除晶Η (82)外包裝産生之佔用面積問 題，獲致缩小積體電路佔用霣路板之現象，然由上述型式 之稹醱霣路的型態可知，無論是晶片之打線區或是外包裝 之接脑均為分佈在晶片或外包裝之周邊位置上，如此，在 晶片之接脚數量不斷增加下，不僅造成外包裝之面積亦箱 一併増加（以在周邊位置容纳更多接脚），而導致積鳗霣 路佔用面積増加之外，更有造成内部金線或鋁線之長度增 加之缺點（金線或鋁線長度超過3〜4mm時，邸影鬱導 ®性及機械性能），故而現今欲解決上述限制下，即有所 本紙張尺度適用中國國家標準（CMS ) Α4規格（210X 297公犛> < .1裝-------訂-----f 線 (請先Μ讀背面之注意事項再填寫本頁) 經濟部中央梂準為Λ工消费合作社印«. A7 ___B7_ 五、發明说明（） »将晶片之输入/输出黏集中在特定匾域或是分敗在晶Η 各值Ε域上，例如現今值人霣腥使用之接脚數量离達3. 0 0脚數之中央處理單元，即在外包裝底面形成陣列式接脚 (PGA).,以逹到解決其接脚數量、金線（鋁線）長度 及佔用面積之問題，然而此等非排列在周邊位置之晶片接 脚，邸導致無法如第四圖之表面鈷著技術（SMT)方式 實施，亦因其打線匾為分佈在晶片各健部份，使晶片各打 線匾連接金線（或鋁線）至第五Β圖所示之電路板（7 0 )上，邸因無法確保各金線不致相互接觸短路之情況，實 施上更有相當困難度的情況下，致使此類接胞!型式之積^體 電路晶片之安裝方面缺乏彈性及良好的適用性，即有再予 改進之必要β 本發明人鑑於現有晶Η未能大量使用於電路板上之缺 點乃經悉心地試驗與研究並一本鍥而不捨之發明精神，终 創作出一種可解決前述限制之可供各式晶片直接附著於電 路板上之方法及構造。 本發明之主要目的在於提供一種載體附著晶片之方法 及構造，主要為蓮用載體本身為多層之特性，将多層式載 體上形成相通而不同寬度大小之缺口，而可令晶片直接黏 著於底層之缺口内，而與載體底面相互貼接之晶片各打線 匾則可經錫凸塊與載醱迴路連接，或利用膠直接黏阽銜接 ,並使晶片表面内刨之打線區則可再以金線（或鋁線）穿 遇載體之缺口而打線至其他位置上，此等结合方式上，可 本纸張尺度適用中國國家橾準（CNS ) Α4規格（2ΙΟΧ 297公犛） ^---------1裝------·訂-----(線 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央揉準局貝工消费合作社印裝 A7 B7__ 五、發明説明（) 速到相E連接位在晶片任何位置之输入/輪出端黏，逹到 與晶片最佳的配合。 本發明之次一目的在於提供一種載體附着晶Η之方法 及構造，可令載體同時形成有散熱孔、散熱黏或散熱面之 型態，以提供晶片適當的散熱效果》 本發明之又一目的在於提供一種載體附著晶片之方法 及構造，其多層式載體可與晶片各输入/輸出Ε域之對應 距雄缩短，使打線之距離縮短，免除打综過長之顧盧。 本發明之再一目的在於提供一種載體附著晶片之方法 f 及構造，以多層式載體與晶Μ结合後，晶K為一種埋入載 體内之型態，故可使多數載體呈上、下多®堆疊形成多晶 Η立體構造，獲致空間之有效利用》 本發明之更一目的在於提供一種載體附著晶片之方法 及構造，於同一載體上更可透過前逑相同方式安裝其他晶 片於其中，如配合阻抗匹配線路或去雜訊迺路，而形成一 模组式構迪，蓮用具相當彈性。 為使 貴審査委員能進一步瞭解本發明之结構，特勘 及其他目的，茲 附以圖式詳細說明如后： (一）·圖式部份： 第一A、B、C圖：係本發明之其一實施例示意圖。 第二圔：係本發明之另一實施例剖面BL· 第三圃：傜本發明之第三實施例剖面Ββ 第四A、 Β圖：傣傳统電路板以SMT方式附著積體電路 本紙張尺度適；中國國家標聿（CNS ) A4現格（210X 297公聲） ;---------f I裝------訂-----(線 (請先閱讀背面之注$項再填寫本芡) 五、發明说明（） A7 B7 Μ濟部中夬橾率局貝工消费合作杜印袋 之示意圖。 第五 ：A 、 B圈 傜 習 男 1晶 ,片 直 接打 结 1 !接 霣 路 板 之示 Μ :麵 (二 ) • 圖號 部 〇 份 % • (1 0 ) 多層 載 體 (1 1 ) 上 m 板 (1 2 ) 中層 板 (1 3 ) 下 描 板 (1 1 1 )( 1 2 1 ) ( 1 3 1 ) 缺 P (1 2 2 )接 點 (2 0 ) 晶 片 (2 1 ) 接觭 區 (3 0 ) 金 综 ( 或 € 丨線 ) 1 (4 0 ) 錫凸 塊 ( 5 0 ) 接 點 1 1 (6 0 ) 貫孔 (7 0 ) 霣 路 板 (8 0 ) 積體 電 路 (8 1 ) 接 脚 (8 2 ) 晶片 (8 3 ) 金 線 (9 0 ) 保護 m 如 第 —A .、 B 、 C 圔 所 示 ，係 為 以 多 層 載 髖 ( 1 0 ) (如 多 層 電路 板 ) 配 合 〇〇 卑 一 晶 片（ 2 0 ) 之 组 合 剖 面 圈 、 俯視 m 及 佃視 圖 % 而 在 第 一 A 鼷之 组 合 剖 面 圈 中 可 清 楚 看 出， 該 多 層載 體 ( 1 0 ) ( 可 為玻 璃 m 維 X 陶 瓷 X 環 氣 樹 脂等 之 有 機材 料 或 具 散 热 金 屬 芯之 有 按 混 合 材 料 ) 之 之 各 層板 除 了 形成 有 不 同 且 相 互 隔 開之 導 電 迺 路 外 t 上 % 中 X 下層 板 ( 1 1 ) ( 1 3 ) 更 分別 形 成 有 上 、 下 貫 通 之 上 、中 % 下 層缺 口 ( 1 1 1 ) ( 12 1 ) ( 1 3 1 ) 9 而 各 層缺 P ( 1 1 1 ) ( 1 3 1 )亦 分 別 設 為 不 同 開 孔 大 小 ^ I裝-------訂-----(線 (請先聞讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標牟（CNS ) Α4規格（210X 297公犛） 經濟部中央標準局貞工消费合作社印装 A7 _^_ B7_ 五、發明说明（） ，在此例中，下層缺口 （131)寬度最大，而依次為上 層缺口 （111)及中層缺口 （121).而中層板（1 2)廚應於缺口 （121)的底面外圍，且位在該下層觖 口 （131)内樹之位置上卽分別形成有可為均勻分佈之 接點（122) ,而中層板（1 2)對應於缺口 （1 21 )的頂面外困且位在上層缺口 （111)之内倒位置上， 亦分別形成可供打線之接點（1 23),亦即為在中雇板 (12)之頂、底面之對應於上/下S缺口 （111)( 1 3 1)内側部位形成可供與晶片連接之多‘数接點（1 .2 丨1 2) (123)，故可在該下庖缺口 （131)中容置晶 Η (20)進入，該晶片（20)邸經黏著方式结合於中 雇板（12)之底面上（如第一C臑之佃視匾），此時， 而中層板（12)與晶片（20)相互阽接之位置上（第 一C祖晶Η (20)之外框及内倒虛線框間之區域），即 ♦ 以其各接點（122)偽與晶Η (20)之相應接栋黏（ 2 1)對應之情況下，邸可透過在晶片（20)之各接觸 點（2 1)附著錫凸塊後，邸可在前述晶片與中層板相互 黏著之際而一併形成電性連接，而晶片（20)近中央上 方之其他接觸點，可配合第一Β圖所示，則可直接經焊接 金線（30)(或鋁線）方式穿過中®板（12)之中雇 缺口 （12 1)而與位在中層板（12)頂面之各接觸點 (1 2 3 )連接β 而前述多層載髅（1〇)兩舾形成有可供鍍銅之貫孔 •Ί - 本紙張尺度適用中國國家標率（CNS ) Α4規格（2丨297公犛） --------f I裝------訂-----(線 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央橾率局負工消费合作社印装 298672 A7 B7 五、發明说明（） (60)及可供多層堆層使用之接黏（50)及錫凸塊（ 40),而以上述多層載體（10)與晶Η (20)相互 間之组合蘭係及配線鼷傜可知，本發明主要即有效運用多 β載體（10)形成不同高低層次之缺口 （1 11)〜（ 1 3 1),據以形成可供埋入晶片（20)、及直接利用 中層板（12)底面及頂面之區域供分別结合晶片（2 0 )外倒及内倒接《匾之導霣連接.此舉，不僅可使晶片（ 20)與多層載體（1〇)可融合成一體之外，更有效地 解決晶片（20)散佈於不同位置衍生之配線困擾及覷盧 丨1 〇 而前述僅以配合單一晶片（20)為例說明，同理， 亦可如第二圖所示，在同一載體（10)上形成多數類似 之階梯式缺口，達到埋入多數晶片（20)於其中，供容 置/功能方面之«充，或設置晶Η (20)相願的周邊電 路晶Μ ,達到模组化之效果。 此外，上述第一、二圖經埋入晶Η (20)之多層載 鳢（10)的外表面更為呈一平整型態，更有便於模组化 上下堆叠之效果，亦邸如第三圖所示，可於各値載體（1 〇>間欲相互連接之外突接點（50)或錫凸塊（40) 位置上經覆蓋導霣膠（41)即可簡單地相互黏合成一立 體型式，達到晶Μ立體配置效果，而各值載體（10)之 間相應之鍍鏑貫孔（6 0>則可視需要供做為焊接導醴以 形成外接的接脚使用，而為達適當散熱效果，*亦可直接在 本紙張尺度適用中國國家標準（CNS ) Μ規格（2丨ΟΧ 297公釐） ---------1裝-----^--訂-----(線 (請先閲讀背面之注意事項再填寫本頁) A7 __B7 _ 五、發明说明（) 載驩上形成鍍箱之散熱孔、败熱塊或散熱平面，更可適當 提昇晶片之散熱能力。 故以前述對本發明之說明可知，具有如下優點： ⑴其多®階梯式缺口之載體設計，可適用於接®不同位置之 晶片使用，達到較佳的適用性β ⑵其載艨之特殊設計，使晶Η打線的距離结短，可解決傳统 打線距離之顧麽，達到較佳的導笛效果。 ⑶可在載體上設計散熱孔、散熱塊及散熱面.使晶Η具有較 佳的散熱能力The Ministry of Economic Affairs, the Ministry of Economic Affairs, Bureau of Industry and Commerce, Du Yin *. Coffee 672 A7 B7 V. Description of the invention () The method and structure of the invention is to attach a wafer to a wafer, which is mainly an array pin for wafers A well-connected carrier structure, and after the chip is combined with the carrier, it is a type of shrinking into the war body, and it only needs to be connected with tin bumps and conductive glue at the outer layer pins to form a multi-employment stack According to the current packaging method of integrated circuit, most of them are shown in the side view and top view of the fourth A and B diagrams. The input of the integrated circuit (8 〇) / Output various pins (8 1) are distributed in the peripheral position, and the pins (8 1) are connected to the circuit & the circuit on the board (70) by surface adhesion (SMT) or soldering method, and are The packaging type that achieves a reduced volume is used as shown in Figures 5A and B. The integrated Hollow chip (8 2) is directly adhered to the circuit board (7 0) and arranged directly on the chip (82) The contact area of the surrounding position is wired with gold wire (83) (or aluminum wire) to the circuit board (70), and then covered with protection ® (90) To protect it, in order to avoid the problem of the occupied area caused by the outer packaging of the crystal Η (82), resulting in the phenomenon of shrinking the integrated circuit to occupy the road board. However, from the type of the above-mentioned type, it can be seen that whether it is a chip The bonding area of the wire bonding area or the outer packaging is distributed on the peripheral position of the chip or the outer packaging. Thus, with the increasing number of pins of the chip, not only the area of the outer packaging but also the box is increased (in the peripheral position (Accommodating more pins), which leads to the increase of the occupied area of the eel road and the disadvantage of increasing the length of the internal gold wire or aluminum wire (when the length of the gold wire or aluminum wire exceeds 3 ~ 4mm, Di Yingyu guide And mechanical properties), so now if you want to solve the above restrictions, there are some paper standards applicable to the Chinese National Standard (CMS) Α4 specification (210X 297 male yak > < .1 installed ------- order- --- f line (please read the precautions on the back before filling in this page) The Central Ministry of Economic Affairs prints for Λ 工 consumer cooperatives «. A7 ___B7_ V. Description of invention ()» Concentrate the input / output of the chip on The specific plaque field may be defeated by each value of crystal Η In the field, for example, the number of pins used by people who are currently in use is as large as 3. 0 0 pin central processing unit, that is, forming array pins (PGA) on the bottom of the outer package. In order to solve the number of pins, The length of the gold wire (aluminum wire) and the occupied area, however, these chip pins that are not arranged in the surrounding position, cannot be implemented as shown in the surface cobalt technology (SMT) method of the fourth figure, because the wire plaque is Distribute in the healthy part of the chip, make the wire plaque of the chip connect the gold wire (or aluminum wire) to the circuit board (7 0) shown in the fifth B, because Di cannot ensure that the gold wires will not contact each other and short circuit. In the case of more difficult implementation, this type of integration is lacking! The mounting of the integrated circuit chip of the type lacks flexibility and good applicability, that is, there is a need for further improvement. Η The shortcomings of not being able to use a large number of circuit boards are carefully tested and researched and a persistent spirit of invention, and finally created a method and structure that can solve the aforementioned limitations and can be directly attached to various circuit boards . The main purpose of the present invention is to provide a method and structure for attaching a carrier to a wafer, mainly because the lotus carrier itself is a multi-layer feature, forming a multi-layer carrier with a gap of different widths and sizes, so that the wafer can be directly attached to the bottom layer In the notch, the wire bonding plaques of the wafer that are attached to the bottom surface of the carrier can be connected to the load-bearing circuit via tin bumps, or directly bonded by glue, and the wire bonding area in the chip surface can then be gold wire. (Or aluminum wire) meet the gap of the carrier and hit the wire to another position. In these combinations, the paper size can be applied to the Chinese National Standard (CNS) Α4 specification (2ΙOX 297 male yak) ^ ----- ---- 1 outfit ------ ordering --- (line (please read the precautions on the back before filling in this page) Printed A7 B7__ by Beigong Consumer Cooperative, Central Bureau of Economic Development, Ministry of Economic Affairs Description of the invention () The input / wheel output end of the position where the phase E connection is located at any position of the wafer is sticky to achieve the best fit with the wafer. The next object of the present invention is to provide a method and structure for the carrier to attach the crystal H The carrier is formed with heat dissipation holes and heat dissipation at the same time The shape of the adhesive or heat dissipation surface to provide the appropriate heat dissipation effect of the chip. Another object of the present invention is to provide a method and structure for attaching the carrier to the chip. The multi-layer carrier can be corresponding to the corresponding input / output E domain of the chip. Shortening, shortening the distance between the bonding wires, and avoiding the need for excessively long harnessing. Another object of the present invention is to provide a method f and structure for attaching a carrier to a wafer. After combining a multi-layered carrier with a crystal M, the crystal K is a buried The shape into the carrier, so that most of the carriers can be stacked up and down to form a polycrystalline Η three-dimensional structure, resulting in effective use of space. "Another object of the present invention is to provide a method and structure of the carrier attached to the wafer, in On the same carrier, other chips can be installed in the same way in the same way, such as matching impedance matching lines or de-noising channels, to form a modular structure, the lotus equipment is quite flexible. To enable your review committee to further understand The structure, special survey and other purposes of the present invention are attached with drawings to explain in detail as follows: (1) · Drawing part: The first A, B and C drawings: it is the invention Schematic diagram of one embodiment. Second 圔: It is another embodiment of the present invention. Section BL · Third Garden: 傜 The third embodiment of the present invention, section Ββ Fourth A, Β 图: Dai traditional circuit board attached by SMT The size of the integrated circuit book is suitable; the Chinese national standard (CNS) A4 is now available (210X 297 public voice); --------- f I installed ------ ordered ----- ( Line (please read the $ item on the back and then fill in the text) Fifth, the description of the invention () A7 B7 The schematic diagram of the Du Yin bag of the Beigong Consumer Cooperation of the Ministry of Economic Affairs of the Ministry of Economic Affairs. Fifth: A, B circle study Male 1 crystal, piece directly knotted 1! Indication of road board M: surface (2) • 0% of drawing number part • (1 0) multi-layer carrier (1 1) on m-board (1 2) mid-layer board ( 1 3) Lower drawing board (1 1 1) (1 2 1) (1 3 1) P missing (1 2 2) contact (2 0) chip (2 1) contact area (3 0) gold hedging (or €丨 Line) 1 (4 0) Tin bump (5 0) Contact 1 1 (6 0) Through hole (7 0) Engraved board (8 0) Integrated circuit (8 1) Pin ( 8 2) Chip (8 3) gold wire (9 0) protection m As shown in Sections -A., B and C, it is a multi-layered hip (1 0) (such as a multi-layer circuit board). The combined profile circle, top view m and tenant view% of the wafer (20) can be clearly seen in the combined profile circle of the first A reel, the multilayer carrier (10) (may be glass m dimension X ceramic X ring gas In addition to organic materials such as resin or metal cores with heat dissipation, each layer of the board is formed with different and separated conductive channels t upper% middle X lower layer board (1 1) (1 3) There are upper and lower through upper and middle% lower layer gaps (1 1 1) (12 1) (1 3 1) 9 and each layer lacks P (1 1 1) (1 3 1) are also set to different hole sizes ^ I installed ------- order ----- (line (please read the precautions on the back and then fill in this page) This paper size is applicable to China National Standard Mou (CNS) Α4 specification (210X 297 male yak ) Central Ministry of Economy The quasi-bureau Zhengong Consumer Cooperative printed A7 _ ^ _ B7_ 5. Description of the invention (). In this example, the width of the lower gap (131) is the largest, followed by the upper gap (111) and the middle gap (121). The board (12) should be located on the periphery of the bottom surface of the notch (121), and located at the position of the tree in the lower layer of the mouth (131). There are separately formed contacts (122) that can be evenly distributed, and the middle layer ( 1 2) The top surface corresponding to the gap (1 21) is trapped on the outside and is located in the upper position of the gap (111). It also forms a connection point (1 23) for wire bonding, that is, the middle employment board (12) The top and bottom surface corresponding to the upper / lower S notch (111) (1 3 1) The inner part of the formation of a number of contacts available for connection to the chip (1.2 丨 1 2) (123), so The crystal H (20) can be accommodated in the lower gap (131), and the chip (20) is bonded to the bottom surface of the middle employment board (12) by means of adhesion (such as the first plaque of the first C) At this time, the position where the middle layer (12) and the wafer (20) are connected to each other (the area between the outer frame of the first C ancestor crystal H (20) and the inner broken line frame), that is Point (122) In the case where the corresponding bonding pads (2 1) of the crystal H (20) correspond to each other, after the tin bumps are attached to the contact points (21) of the wafer (20), the di When they are adhered to each other, they form an electrical connection together, and the other contact points of the chip (20) near the center can be matched with the first figure B, and can be directly soldered to the gold wire (30) (or aluminum wire) Passing the gap (12 1) in the middle ® board (12) and connecting with the contact points (1 2 3) located on the top surface of the middle board (12) β is formed and the two-layer cross-bearing (1〇) is formed There are through holes for copper plating • Ί-This paper scale is applicable to China National Standard (CNS) Α4 specifications (2 丨 297 g) -------- f I installed ------ order- ---- (Line (please read the precautions on the back before filling this page) Printed 298672 A7 B7 by the Consumer Labor Cooperative of the Central Bureau of the Ministry of Economic Affairs V. Invention description () (60) and available for multi-layer stacking The bonding (50) and the tin bump (40), and the combination of the above-mentioned multilayer carrier (10) and the crystal H (20) between the blue system and wiring is known, the present invention is mainly to effectively use multiple beta carriers ( 10) Formation is not High and low level gaps (1 11) ~ (1 3 1), according to which the area for embedding the wafer (20) and the bottom surface and top surface of the intermediate layer (12) can be directly used for combining with the wafer (20) Inverted and inverted connection of "Plaque's guide connection. This not only allows the chip (20) and the multilayer carrier (10) to be integrated into one body, but also effectively solves the problem of the chip (20) spreading in different positions. Wiring trouble and 觑 卢 丨 10. The foregoing is only explained with a single chip (20) as an example. Similarly, as shown in the second figure, many similar stepped gaps can be formed on the same carrier (10) to achieve Most of the chips (20) are embedded in them for storage / function aspects, or the desired peripheral circuit crystal M of the crystal H (20) is provided to achieve the effect of modularization. In addition, the outer surface of the multi-layered snakehead (10) embedded in the crystal H (20) in the above first and second figures is more flat, and it is more convenient for modularization to stack up and down, and it is also like the third As shown in the figure, it can be easily bonded to each other by covering the guide glue (41) at the position of the external contact (50) or the tin bump (40) between the various carriers (10). The three-dimensional type achieves the three-dimensional configuration effect of the crystal M, and the corresponding dysprosium-plated through holes (6 0>) between the value carriers (10) can be used as welding guides to form external pins as needed, to achieve appropriate The heat dissipation effect, * can also be directly applied to the Chinese national standard (CNS) Μ specifications (2 丨 ΟΧ 297mm) on this paper scale --------- 1 installed ----- ^-order-- --- (Wire (please read the precautions on the back before filling in this page) A7 __B7 _ V. Description of invention () The heat dissipation holes, heat failure blocks or heat dissipation planes formed on the platen of the carrier are more suitable for upgrading the chip The heat dissipation capacity. Therefore, the foregoing description of the present invention shows that it has the following advantages: (1) its multi-stepped notch carrier design can be applied to connect different Use the placed chip to achieve better applicability β ⑵The special design of its carrier makes the distance between the bonding wires of the crystal H shorter, which can solve the problem of the distance between traditional wires and achieve a better guide flute effect. ⑶Can be used in the carrier Design heat dissipation holes, heat dissipation blocks and heat dissipation surfaces, so that crystal H has better heat dissipation capacity
' V ⑷在載體上更可容纳其他周邊霄路或晶片，達到模組化之優 黏》 ⑸晶片為一種埋入載體内部之設計，更提供便於直接堆《成 立體多晶片構造，達到擴充及空間有效利用β ---------1 1裝------訂-----1 線 (請先Μ讀背面之注$項再填寫本頁) 經濟部中央揉率局I工消费合作杜印¾ 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公犛）'V ⑷ can also accommodate other peripheral roads or chips on the carrier, to achieve the excellent adhesion of modularization. ⑸ The chip is a design embedded in the carrier, and it is more convenient to directly stack the "multi-chip structure of the body, to achieve expansion and Effective use of space β --------- 1 1 set ------ order ----- 1 line (please read the $ item on the back and then fill in this page) Central Ministry of Economic Affairs Bureau I Industry and Consumer Cooperation Du Yin ¾ This paper standard is applicable to China National Standard (CNS) Α4 specification (210Χ 297 g)