29?i^7 A7 A7 _ B7_ 五、發明説明（i ) 本案係一種形成金屬矽化物接面之方法，尤指一種於 低溫形成金屬矽化物接面之方法。 於積體電路淺接面之製程中，對接面深度的要求有愈 來愈淺之趨勢’於這種要求下，如果以太高的溫度來製造 淺接面，則易產生高溫擴散，使得接面擴散太深。習知常 見用以製造淺接面有二種方法，第一種是利用低能量的離 子佈植機，佈植低能量（例如1〜2kev或5G0ev與200ev) 之B +離子於矽基座中，以製成淺接面；由於此種方法之佈 植劑量不能太高（一般爲lXl015cnT1)，故其片電阻不可 能太低，對操作速度有影響，且低能量的佈植機非常少 見，再加上此方法於退火後所引發之缺陷必須於高溫下 (約在800〜850 °C左右）才能消除，故而以低能量佈植機 製造淺接面之方法無法低溫化。 經濟部中央揉準局負工消費合作社印裝 (請先閩讀背面之注意事項再填寫本頁) 第二種方法是用預先佈植矽或鍺將矽基座打成非晶 態，再將硼離子佈植於矽基座中，此方法隨著EOR(end of range)缺陷與硼離子的相對位置而可能對硼離子擴 散產生增進或延遲之現象，且E0R缺陷對接面特性也有不 良影響，更重要的是，此方法於佈植退火後所產生之缺 陷，亦必須要於高溫下（約爲800〜901TC)才能消除，故 此方法亦無法達成低溫化之要求。 本案之主要目的在提供一於低溫形成金屬矽化物接面 之方法，俾得良好特性之接面。 本案係一種於低溫形成矽化物接面之方法，其步驟包 括：a)形成一鈷層於一已定義出元件區之矽基板上；b)形 1 本紙張尺度適用中國國家樑準（CNS ) A4规格（210X297公釐） 經濟部中央標準局負工消费合作社印製 A7 __B7 ____ 五、發明説明（2 ) 成一保護金屬層於該鈷金屬層上；俾防止鈷之氧化；c)佈 植摻雜質至該元件區之鈷層，佈植能量以不致於將該摻雜 質打入該矽基板內爲限；d)實施第一次退火，俾於該元區 形成CoSi ; e)除去未形成CoSi之鈷層；f)於600 °C以下 之溫度實施第二次退火，俾形成CoSi2，並使該摻雜質被 推入與活化至該矽基板內，而形成特性良好之接面。 當然，本案於步驟（a)之前更包括下列步驟：g)沈積 —層Si〇2於一矽基板上；h)利用光學蝕刻技術於該矽基 板上定義出一元件區。 以一實施例而言，其中，該步驟（b)中之保護金屬層 爲非晶矽（α-Si)層；步驟（c)中之摻雜質係BF2+ ;步騾 (a)中之鈷層厚度爲1〇〇〜500A，而步驟（f)中之退火溫 度爲5 5 0 °C。 當然，步驟（e)係以草酸、硝酸、磷酸及硫酸之混合 溶液除去該Co金屬；步驟（c)中之佈植能量以不至於將該 摻雜質打入該矽基板內爲限，例如70kev。 本案得藉下列圖式及詳細說明，俾得一深入了解。 第一圖：係本案方法步驟之一較佳實施例示意圖。 第二圖：係本案之退火溫度與漏電流密度之一較佳實 施例曲線圖。 第三圖：係本案之退火溫度與正向理想因子之一較佳 實施例曲線圖。 茲舉一較佳實施例而爲本案之詳細說明：請參閱圖 一，圖一（a)包括： 3 本纸張尺度適用中國國家橾準（CNS ) A4规格（210X297公釐） | ~裝----：丨-1訂-----d線 (請先閲f面之注意事項再填寫本頁) 2dnS7 ^_ 五、發明説明（3 ) 1)沈積一層二氧化矽（Si02)ll於一矽基板10之上； 圖一（b )包括： 2 )利用光學蝕刻技術形成一元件區1 2 ; 圖一（c)包括： 3) 蒸鍍約300A厚之鈷金屬層13於矽基板10之上’俾 做爲離子佈植障礙層，並於Co 1 3之上蒸鍍一層約50A厚 之非晶砂（a-Si)14，該a-Si 14可防止鈷13於形成砂 化物之過程中氧化；其後再以ITM法（Impantation through Metal)佈植BF2 +離子於鈷層13內，佈植能量 以可將BF2+打入Co 13中’但不穿入Si 10內爲限，以 7 0 k e v爲例，佈植劑量以1 X 1 0 1 6 (高劑量）爲例； 圖一（d)包括： 4) 於450 °C實施第一次退火30分鐘，俾於元件區12 形成鈷矽化物（CoSi)15 ; 圖一（e )包括： 5) 以溶液體積比5 : 3 : 1 : 1之草酸、硝酸、磷酸及 硫酸，於40°C除去未形成鈷矽化物之鈷層； 經濟部中央梂準局WC工消费合作社印«. -A------订 (請先《讀背*之注意事項再填寫本X) ' 6) 於550 °C之低溫，以30分鐘之時間，施行第二次退 火，以形成低阻値之金屬矽化物CoSi2 16,來做爲形成 淺接面之電極板，並可將BF2 +推入與活化（dr ive and activation)於砂基板10內，俾形成特性良好之接面。29? I ^ 7 A7 A7 _ B7_ V. Description of the Invention (i) This case is a method of forming a metal silicide junction, especially a method of forming a metal silicide junction at a low temperature. In the manufacturing process of shallow junctions of integrated circuits, the requirements for the depth of the junction have become increasingly shallow. Under this requirement, if the shallow junction is manufactured at a too high temperature, high temperature diffusion is likely to occur, making the junction The spread is too deep. There are two common methods for manufacturing shallow junctions. The first is to use a low energy ion implanter to implant B + ions of low energy (such as 1 ~ 2kev or 5G0ev and 200ev) in a silicon susceptor. In order to make a shallow junction; because the implantation dose of this method cannot be too high (generally lXl015cnT1), the sheet resistance cannot be too low, which affects the operating speed, and low-energy implanters are very rare. In addition, the defects caused by this method after annealing must be eliminated at high temperatures (about 800 ~ 850 ° C), so the method of making shallow junctions with low energy implanters cannot be lowered. Printed by the Consumer Labor Cooperative of the Central Bureau of Economic Development of the Ministry of Economic Affairs (please read the precautions on the back before filling in this page) The second method is to use pre-planted silicon or germanium to make the silicon base into an amorphous state, and then Boron ions are implanted in the silicon pedestal. This method may cause the phenomenon of promoting or delaying the diffusion of boron ions with the relative position of EOR (end of range) defects and boron ions, and E0R defects also have an adverse effect on the interface characteristics. More importantly, the defects generated by this method after planting annealing must also be eliminated at high temperatures (approximately 800 ~ 901TC), so this method cannot meet the requirements of low temperature. The main purpose of this case is to provide a method for forming a metal silicide junction at a low temperature to obtain a junction with good characteristics. This case is a method for forming a silicide junction at a low temperature. The steps include: a) forming a cobalt layer on a silicon substrate with a defined device area; b) form 1 This paper size is applicable to China National Standards (CNS) A4 size (210X297 mm) A7 __B7 ____ printed by the Consumer Labor Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of invention (2) Form a protective metal layer on the cobalt metal layer; to prevent the oxidation of cobalt; c) planting and doping Impurities are deposited on the cobalt layer of the device region, and the implantation energy is limited so as not to drive the dopant into the silicon substrate; d) performing the first annealing to form CoSi in the meta region; e) removing Forming a cobalt layer of CoSi; f) performing a second annealing at a temperature below 600 ° C to form CoSi2, and the dopant is pushed and activated into the silicon substrate to form a junction with good characteristics. Of course, this step further includes the following steps before step (a): g) depositing a layer of Si〇2 on a silicon substrate; h) using optical etching technology to define a device area on the silicon substrate. In an embodiment, wherein the protective metal layer in step (b) is an amorphous silicon (α-Si) layer; the dopant in step (c) is BF2 +; the cobalt in step mule (a) The layer thickness is 100 ~ 500A, and the annealing temperature in step (f) is 5 50 ° C. Of course, step (e) is to remove the Co metal with a mixed solution of oxalic acid, nitric acid, phosphoric acid, and sulfuric acid; the implantation energy in step (c) is not limited to driving the dopant into the silicon substrate, for example 70kev. In this case, the following diagrams and detailed explanations can be used to gain an in-depth understanding. The first figure is a schematic diagram of a preferred embodiment of the method steps in this case. The second figure is a graph of a preferred embodiment of annealing temperature and leakage current density in this case. The third figure is a graph of the preferred embodiment of the annealing temperature and positive ideal factor in this case. Here is a preferred embodiment for a detailed description of the case: Please refer to Figure 1, Figure 1 (a) includes: 3 This paper size is applicable to China National Standard (CNS) A4 specification (210X297mm) | ~ installed- ---: 丨 -1 order ----- d line (please read the precautions on the f side before filling in this page) 2dnS7 ^ _ V. Description of the invention (3) 1) Deposit a layer of silicon dioxide (Si02) ll On a silicon substrate 10; Figure 1 (b) includes: 2) forming an element region 12 using optical etching technology; Figure 1 (c) includes: 3) vapor-depositing a cobalt metal layer 13 with a thickness of about 300A on the silicon substrate 10 on top of it as a barrier layer for ion implantation, and a layer of amorphous sand (a-Si) 14 with a thickness of about 50A is evaporated on Co 1 3, the a-Si 14 can prevent cobalt 13 from forming sand It is oxidized during the process; after that, BF2 + ions are implanted into the cobalt layer 13 by the ITM method (Impantation through Metal). The implantation energy is limited to the ability to drive BF2 + into Co 13 but not into Si 10, Taking 70 kev as an example, the implantation dose is 1 X 1 0 16 (high dose) as an example; Figure 1 (d) includes: 4) The first annealing is carried out at 450 ° C for 30 minutes, in the component area 12 Formation of Cobalt Silicide (CoSi) 15 Figure 1 (e) includes: 5) Oxalic acid, nitric acid, phosphoric acid and sulfuric acid at a volume ratio of 5: 3: 1: 1: 1 to remove the cobalt layer that has not formed cobalt silicide at 40 ° C; Printed by WC Industrial Consumer Cooperative «.-A ------ Order (please read" Notes on the back * first and then fill in this X ") '6) At a low temperature of 550 ° C for 30 minutes, perform the second Secondary annealing to form a low-resistance metal silicide CoSi2 16, as a shallow junction electrode plate, and can push and activate BF2 + in the sand substrate 10 to form characteristics Good interface.
請參閱第二圖及第三圖，其爲本案較佳實施例之退火 溫度與漏電流、正向理想因子（η)之曲線圖，由圖二及圖 三中可以看出，以Co爲佈植障礙層，高劑量的摻雜（IX 4 本纸張尺度適用中國國家橾準（CNS ) A4规格（210X297公* ) A7 B7 五、發明説明（ο l〇i6cm2)、7〇kev佈植能量，於550 °c之低溫退火後所 得之接面，其漏電流密度小於3nA/cm2、正向理想因子η 小於1.01，接面深度約爲，同樣符合一般於高溫 下所得之接面特性標準》 綜上所述，本案以鈷金屬做爲離子佈植障礙層，再選 擇適當的離子佈植劑量及佈植能量，利用鈷矽化物形成時 對佈植雜質推入與活化（driven & activation)的效 果，以及矽化物形成時點缺陷注入矽基板中對佈植缺陷增 進消除效果之性質，而可於600 °C以下之低溫形成特性良 好接面，而有利於低溫淺接面之製造。 本案得由熟悉本技藝之人士任施匠思而爲諸般修飾， 然皆不脫如附申請專利範圍所欲保護者。 (請先《讀背ά之注再填寫本頁) 鯉濟部中央揉準局負工消费合作社印製 5 本紙張尺度遑用中國國家橾準（CNS ) Α4规格（210Χ297公釐）Please refer to the second and third figures, which are the graphs of annealing temperature, leakage current, and forward ideality factor (η) in the preferred embodiment of this case. As can be seen from FIGS. 2 and 3, Co is used as the cloth Implant barrier layer, high-dose doping (IX 4 This paper scale is applicable to China National Standard (CNS) A4 specification (210X297 g *)) A7 B7 5. Description of the invention (ο l〇i6cm2), 7〇kev planting energy , The junction obtained after annealing at a low temperature of 550 ° c has a leakage current density of less than 3nA / cm2, a positive ideal factor η of less than 1.01, and a junction depth of about, which also meets the general junction characteristics standards obtained at high temperatures. In summary, in this case, cobalt metal was used as the ion implantation barrier layer, and then the appropriate ion implantation dose and implantation energy were selected, and the implanted impurities were driven and activated during the formation of cobalt silicide (driven & activation) The effect of implantation of point defects into the silicon substrate during the formation of silicide to improve the elimination effect of implant defects, and can form good junctions at low temperatures below 600 ° C, which is conducive to the manufacture of shallow junctions at low temperatures. By someone familiar with this skill Shi Ren is a carpenter who makes all kinds of modifications, but they are all as good as those who want to protect the scope of the patent application. (Please read the note of the back and then fill out this page). The size of the paper is made using the Chinese National Standard (CNS) Α4 specification (210Χ297mm)