經濟部中央標準局員工消費合作社印製 206462 A7 B7 五、發明説明（） 發明領域： 本發明與一種金氧半（Μ 0 S)電晶禮之製程有關’特别 是一種利用穿透閘極氣化房之深離子佈植以提昇金氧半 電晶體性能之方法。 發明背景： 一般在金氧半（M〇S)電晶體之四個接點中，源極與基 材通常接地，讓整個M〇S電晶體之操作由閘極電壓與没 極電壓來主導，閘極電壓將主導整個電晶體之開關狀態， 而汲極電壓則決定當電晶體處於開之狀態時流經；及極、通 道和源極之電流。以N Μ〇S而言’當加於閘極之電歷：不 大時，由汲極流經通道之汲極電流將與閘極電壓成正比之 關係，在此情況下汲極電流將隨著汲極電蜃之增強而增大 直至汲極電流達绝和爲止’此時之；及極電I稱绝和及.極電 壓，此時不論施加於汲極之電壓有多大’只要汲極電壓大 於飽和汲極電磬’汲極電流將爲定値’反轉層寬度減爲 零，此處稱爲夹止點。在夹止點之飽和電壓保持不變之原 因亦即由源極至夾止點之載子數和由；及極到源極的電说 維持不變。在此飽和區間下之汲極電壓很高使得閘極電麼 在接近汲極之附近的部份被抵消（π e u t「a丨i z e d )，使通道接 近汲極之反轉層消失。 本紙張尺度適用中國國家揉準（CNS )八4規格（2丨0X 297公釐） ^、1TΜ (請先閱讀背面之注意事項再填寫本頁) A7Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 206462 A7 B7 V. Description of the invention () Field of the invention: The present invention is related to a process of gold oxide semi-oxide (Μ0S) electro-crystal ceremonies', especially a method using penetrating gate gas The method of deep ion implantation in the chemical room to improve the performance of metal oxide semi-transistors. Background of the Invention: Generally, in the four contacts of the metal oxide semi-oxide (MOS) transistor, the source electrode and the substrate are usually grounded, so that the operation of the entire MOS transistor is dominated by the gate voltage and the electrode voltage, The gate voltage will dominate the switching state of the entire transistor, while the drain voltage determines the current flowing through the transistor when it is on; and the current of the pole, channel, and source. In terms of N MOS, when the electric calendar applied to the gate is not large, the drain current flowing from the drain through the channel will be proportional to the gate voltage. In this case, the drain current will follow With the enhancement of the drain electrode mirage, it increases until the drain current reaches the limit. At this time; and the pole electrode I is called the limit and the pole voltage, at this time no matter how large the voltage applied to the drain is. The voltage is greater than the saturation drain electrode. The drain current will be reduced to zero for the fixed value, which is called the pinch point. The reason why the saturation voltage at the pinch point remains unchanged is the number and origin of carriers from the source to the pinch point; and the electrode-to-source electrode theory remains unchanged. In this saturation interval, the drain voltage is very high, so that the gate electrode near the drain is cancelled (π eut "a 丨 ized"), so that the inversion layer of the channel close to the drain disappears. Applicable to the Chinese National Kneading (CNS) 8.4 specifications (2 丨 0X 297mm) ^, 1TM (please read the precautions on the back before filling this page) A7
五、發明説明（） 經濟部中央標隼局員工消費合作社印裝 短通道元件中及極電壓增加會產生短通道效應，例如 產生臨界電壓降低，較大之次臨界電流（subthreshold current)和發生抵穿（punchthr〇ugh)效應，抵穿效應之產 生主要是因爲元件之尺寸縮小，汲極與源極之空乏區邊緣 越來越靠近而產生，一但發生抵穿效應產生之電流則次臨 界濃幅參數（SUbthreshold swing parameter ; St)將增 加。一艘而言，MOS利用離子佈植碉於矽與二氧化矽界 面以增如通道之摻雜濃度來調整臨界電壓。通道摻雜分佈 影響元件之性能甚鉅，通道離子佈植由—個淺離子佈植與 一深離子佈植組成，淺離子佈植決定臨界電壓之大小，深 離子佈植則防止抵穿（punchthrough)效應，降低通道之表 面掺雜哀度及同時於汲、源極接面深度附近保持足夠之摻 雜’農度了以私·昇元件之電泥及防止抵穿（punchthrough) 電流之發生。但是傳統之製程中需經過數道熱處理之裎 序’因此離子佈植常因熱處理之情形而擴散而破壌原有之 捧雜離子；農度分佈’尤其是形成場氧化層之製程其溫度約 爲1 0 0 0 且經歷較長之時間。 發明目的及概述： 本發明之主要目的爲提供一種利用深離子佈植 (deep ion implantation)穿透閘極氡化層之製裎以增進金 氧半電晶體之性能。 本發明之主要目的爲利用深離子佈植（d e e p i ο η 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） --------------I---丁 (請先閱讀背面之注意事項再填寫本頁) ^^C4〇2 A7 B7 經濟部中央標準局員工消費合作杜印製 五、發明説明（) implantation)穿透閘極氧化層用以增進汲極之鉋和電 流。 利用深離子佈植（deep ion implantation)穿透閘極氧 化層防止短通道效應及降低通道表面之掺雜濃度，本發明 之方法能同時在基底接面深度附近保持足夠高澴度之摻 雜並降低通道表面之掺雜濃度以提昇汲極之鉋和電流及 防止抵穿（punchthrough)電流。本發明之製程包含：形成 場氧化層於基板上，離子植入用以調鳖臨界電壓 (threshold voltage)，植入離子爲二氧化胡（BF2)離子劑 量爲 3.2E12-3.6E12 atoms/cm2，植入能量爲 70KeV， 熱生長二氧化矽層於基板與場氡化之上，二氧化矽層將作 爲閘極氧化層，接著爲進行穿透閘極氧化層之深離子佈埴 (deep ion implantation)，上述之深離子佈植以能量爲 180keV，劑量爲3.5E12atoms/cm2t^l離子，沈積複晶 矽於二氧化矽層之上，以微影與蝕刻技術形成閘極，閘極 結構作爲自我校準罩幕進行離子植入，離子源爲磷，主要 是作爲防止熱載子效應之輕微掺雜汲極（LDD)結構，下一 步驟爲沈積二氡化矽層於閘極 '基板之上，以非等向性蝕 刻上迷之二氧化矽層形成側壁間隙（side wall spacer)， 最後進行摻雜區之泼摻雜形成汲極與源極完成本發明之 深離子佈植（deep ion implantation)穿透閘極氡化層之金 乳半電晶體。 私衣 、1τ (請先閱讀背面之注意事項再填寫本頁〕 本紙張尺度適用中國國家棣準（CNS) Α4規格（210χ297公釐） 經濟部中央標準局員工消費合作社印製 A7 __B7 五、發明説明（） 圖式簡單説明： V岸一圈爲本發明之NM0S形成第一二氧化石夕層、氣化石夕 I及定義第一光阻之截面圖。 第二圖爲本發明之NMOS第一次離子植入之截面圖° '第三圖爲本發明之NMOS形成場氧化層及第二次離子植 \之載面圖。 ，第四圖爲本發明之NMOS形成第二二氧化矽層及深離子 植入之截面圖。 •第五圖爲本發明之NMOS形成閘極結構之截面圖。 '第六圖爲本發明之NMOS形成摻雜區之截面圖。 .第七圖爲本發明與傳統法之電流-電壓曲線圖（圖示之數 據爲0_45微米之SRAM製程之電流-電磬曲線’曲線 爲傳統之方法，曲線7 〇 2爲本發明之方法）。 第八圖爲本發明之CMOS形成第一二氧化矽層、氬化石夕 層及第一光阻之截面圖。 V第九圖爲本發明之CMOS形成N丼區域之截面圖。 、，第十圖爲本發明之CMOS形成通道阻絶（channel stop)之 截面圖。 ，第十一圖爲本發明之CMOS形成場氡化層與臨界電壓調 整之離子植入之截面圖。 ’第十二圖爲本發明之CMOS形成閘極氡化層與深離子植 入之截面圖。 '第十三圖爲本發明之CMOS形成閘極結構之截面圖。 本纸張尺度適用中國國家標準（CMS ) A4規格（2丨0X297公釐） t------ΐτ-------.it (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（） ^第十四圈爲本發明之CMOS形成NMOS元件摻雜區之截 面圈。 v第十五圖爲本發明之CMOS形成pm〇S元件摻雜區之截 面囷。 發明詳麵説明： 本發明之方法利用深離子佈植（d e e p i ο π i m p丨a n t a t i ο η ) 穿透閉極氧化層防止短通道效應降低通道表面之摻雜；農 度’本發明方法之金氧半電晶禮（MOSFET)之深離子佈植 可避免受到形成場氧化層時高溫熱處理之影響，同時本發 明ι方法能同時在基底接面附近保持足夠高；農度之摻雜 ^昇没極之絶和電流及防止抵穿（punchthrough)電流。本 發明之製裎將後述如下： 參閱第一圖’本發明之較佳實施例爲利用晶面爲< 1〇〇〉之P型單晶發半導體爲基板（subst「ate)2。將基板 2置於造管含氧環境中將基板之表面形成一厚度約爲數 百埃之第一二氧化矽層4，接著上述之第一二氧化矽層4 之上以化學氣相沈積形成氮化碎層6厚度約爲1 〇 Q Q _ 2000埃之間，然後以微影技術將第一光阻8形成於氣化 石夕層之上。接著以蝕刻技術蝕刻氮化矽層6與第一二氧 化珍層4，此蝕刻後之結構將作爲製作場氡化層之罩幕， 以崎離子對整個基板達行第一次植入用以做通道阻絶，如 ▲-------玎------線 (請先閲讀背面之注意事項再填寫本頁) 6 經濟部中央標準局員Η消費合作社印製 . A7 —-!______B7 五、發明説明（） 第二圖所示。 參閱第三圖，去除第一光阻8後將基板置於高溫瀘之 中以溼式氧化法進行場氧化層1 0之成長並將第一次植入 之磷雜子驅入基板2内，完成場氧化層1〇之製作後以溼 蝕刻去除氮化矽層6,下一步驟爲第二次離子植入用以調 整臨界電壓（threshold voltage),植入離子爲二氧化堋 (巳F2)離子劍量爲3.2E12-3.6E12 atoms/cm:，植入能量 爲 70KeV 。 如第四圖所示，以溼蝕刻技術將第一二氧化矽層4 去除後，沈積第二二氧化矽層12於基板2與場氧化層10 之上厚度爲90-1 20埃，此第二二氧化矽層1 2將作爲閘極 氡化層12。接著爲進行穿透閘極氧化層12之深離子佈植 (deep ion implantation)，上述之深離子佈植以能量爲 180keV，劑量爲3.5E12atoms/cm2之袖離子，其他適合 之三價離子亦可作爲此深離子佈植之離子源。 如第五圖所示，形成厚度约2000-3000埃之複晶矽 1 4於第二二氧化矽層1 2之上，進行第三次離子埴入以降 低複晶矽1 4之電阻，或是沈積已摻雜之複晶矽層（i η situ-doped polysilicon)於第二二氧化·δ夕層12之上。進行 第二次微影及定義第二光阻形成於複晶矽1 4之上，以蝕 刻技術形成閘極1 4，之後以硫酸或其他方法去除第二光 本紙張尺度it财關家縣（CNS ) Α4規格（21Qx297公釐） ^二衣------1Τ-------^ (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局舅工消費合作社印製 A7 ____ B7__ 五、發明説明（ 阻0 參閲第六S，以閘極14結構作爲罩幕進杵 π A 1丁弟四次離 子植入，離子源爲磷，劑量約爲1E13 atoms/Cm2主要 作爲防止熱載子效應之輕微摻雜汲極（LDD)結構16 ， 一步驟爲沈積第三二氧化矽層18於閘極、基板2 興場氧 化層1 0之上，以非等向性蝕刻蝕刻上述之第=- ^ 層18形成側壁間隙（3丨〇16以3丨丨3口306〇18，最後途；^_^ 疋订擇·雜 區之濃摻雜形成汲極20輿源極22完成本發明之深離子 佈植（deep ion implantation)穿透閘極氧化層之金氧半電 晶體。 參閲表一及第七圖’第七圈爲本發明與傳統方法之電 流（丨）-電壓（V)曲線圏，圖示之數據爲〇_45微米之SRAM 製程之電流-電壓曲線，Vg表示電晶體操作之電壓，本發 明之閘極氧化層厚度爲90埃，深離子佈植濃度爲3 5E1 2 atoms/cm2，植入能量18〇 KeV。於閘極偏壓^下，曲 線701A爲傳统方法之實驗數據，曲線7〇2A爲本發明方 法之實驗數據；於閘極偏壓4\/下，曲線7〇1日爲傳統方 法之實驗數據，曲線702B爲本發明方法之實驗數據；於 閉極偏墨3.3V下’曲線701C爲傳统方法之實驗數據， 曲線702C爲本發明方法之實驗數據；於閘極偏壓2Vt , 曲線701D爲傳统方法之實驗數據，曲線7〇2〇爲本發明 方法之實驗數據；於閘極偏| 1VT，曲線7〇iE爲傳统 本紙張尺度逋用中國國家標準（CNsT^i721〇_;297公17 (請先閲讀背面之注意事項再填寫本頁) •丨裝· 訂 五、發明説明（) 方法t實驗數據，曲線702E爲本發明方法之實驗數據， 由第七圈知本發明之方法在栢同之閘極偏壓下產生較高 足汲極電流，本發明之方法中深離子佈植於場氧化層形成 疋後進行，故深離子佈植不受到形成場氧化之高溫熱影響 (约爲1000 ·〇；’ 110分鐘）而擴散影窨臨界電壓調整之佈 植及表面通道之離子佈植。如表一爲用〇45微米之SRAM 製程於傳統方法與本發明之比較’以不同離子佈植（vt|/丨） 得到之臨界電壓（Vt)、漏電流（|0ff)、飽和電流（|dsat)與 次臨界擺幅（subthreshold swing)之結果，從表一中可知 本發明至少可將鉋和電流提昇。 (請先閲讀背面之注意事項再填寫本頁) •棄· 、-口 經濟部中央標準局員工消費合作杜印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐) 經濟部中央標準局員工消費合作社印製 A7 ____ B7 五、發明説明（） 表一 臨界電1 調整離子 佈植能量 與濃度 臨界電 壓（V) 漏電流 (pA/UM) 飽:fO電 流 (uA/um) 次臨界擺 幅 (mA/d ec) 傳統 方法 70KeV 2.6E1 2 atoms/cm 2 0.58 0.11 (3.3V) 288.7 (3.3V) 89 0.14 (5V) 539 (5V) 本發 明之 方法 70KeV 3.2E1 2 atoms/cm 2 0.52 0.52 (3.3V) 336.7 (3.3V) 85.4 17 % 1.01 (5V) 6 10.4 (5V) 13 % 本發 明之 方法 70KeV 3.6E1 2 atoms/cm2 0.57 0.178 (3.3V) 319.6 (3.3V) 86.8 11 % 0.295 (5V) 588.8 (5V) 9.2 % 装------1T-------0 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X 297公釐） 經濟部中央標準局員工消費合作杜印製 A7 B7 五、發明説明（） 由表一及第七圖，在操作電廢:爲5V時飽和電流增加 1 3 %，操作電壓爲3.3 V時鲍和電流增加1 7 %，其次本 發明之次臨界擺幅亦有些微降低，而臨界電壓則只降低 0.0 6 V，關閉態漏電流貝"I維持於合理範圍之内。本發明之 製程中若將深離子佈植於場氧化層形成後植入，接著再實 施臨界電壓調整之離子植入、形成閘極氧化層，其餘步驟 與第一實施例栢同亦能提昇Μ〇S之性能，飽和電流則有 6 %增加，次臨界擺幅亦有些微改善，而臨界電壓降低 0.0 3 V，漏電流維持於1 p A / u m以下。 本發明之方法亦可以應用於CMOS之製作，製程將 由下述： 本發明將以N井CMOS作爲説明，同理本發明之方 法亦能使用於P井或雙井M〇S之製作。參閲第八圖，本 發明之較佳實施例爲利用晶面爲< 1 0 0 >之P型單晶矽 半導體爲基板30。將基板30之表面形成一厚度約爲數百 埃之第一二氧化矽層32，接著上述之第一二氧化矽層32 之上以化學氣相沈積形成氮化矽層3 4，然後以微影技術 將第一光阻3 6形成於氮化矽層3 4之上。接著以蝕刻技 術蝕刻氮化矽層3 4，此蝕刻後之結構將作爲製作場氧化 層之罩幕，如第九圖所示接著定義第二光阻38曝露出欲 製作P Μ 0 S區域以磷離子對整個基板進行第一次植入，劑 量約爲1Ε12-1Ε13 atoms/cm2，形成Ν丼區域39。如第 十圖所示，除去第二光阻38後以微影曝光形成第三光阻 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） --------------ΐτ------i (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作杜印製 A7 * B7 五、發明説明（） 40於N井區域39之上，接著以第二次離子植入形成通道 阻絶4 2。 如第十一圖所示，完成通道阻絶42後去除第三光阻 4 0 ，將晶片置於高溫環境中以溼式氧化法將未被氮化矽 層34覆蓋區域進行場氧化層44之製作，之後去除氮化矽 層34與第一二氧化矽層32。以三價之硼或適合之三價離 子進行第三次離子植入，此第三次離子植入是用以調整臨 界電墨，劍量約爲1E12atoms/cm2，能量數十KeV之間。 參閲第十二圖，於基板20上形成第二二氧化矽層 46，之後形成第四光阻48於N丼區域39之上，以硼實 施第四次離子植入，此第四次離子植入爲深離子植入，將 穿透閘極氧化層深入基板，上述之深離子佈植以能量爲 180keV，劑量爲3.5E12atoms/cm2之蝴離子，其他適合 之三價離子亦可作爲此深離子佈植之離子源，完成深離子 佈植後去除第四光阻4 8。 如第十三圖所示，沈積複晶石夕層5 0於閘極氧化層4 6 之上，以蝕刻技術進行第五次離子植入以降低複晶矽5 0 之電阻，或是沈積已掺雜之複晶石夕層（insitu-doped polysil icon)於閘極氧化層46之上。進行微影及定義第五 光阻形成於複晶矽之上，以蝕刻技術形成閘極5 0，之後 以硫酸或其他方法去除第五光阻， 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） --------------ir------4 (請先閱讀背面之注意事項再填寫本頁) A7 B7 ' 五、發明説明（） 參閱第十四圈，定義第六光阻52於N丼區域39之 上，以離子植入NMOS元件主動區形成作爲防止熱載子 效應之輕微摻雜汲極（LDD)結構54 ，下一步驟爲沈積第 三二氧化矽層於閘極50、基板20與場氣化層44之上， 接者以非等向性蝕刻技術蝕刻上述之第三二氧化矽層形 成側壁間味（s i d e w a丨丨s p a c e r) 5 6，最後進行捧雜區之濃 摻雜形成汲極58n與源極60n。如第十五圖所示，下一步 驟爲製作PM〇S之摻雜區，首先去除第六光阻52然後形 成第七光阻62暴露出N井區域39，以閘極50爲罩幕進 行離子植入PMOS元件形成摻雜區之汲極58p與源極 60p 。最後完成本發明之深離子佈植（deep ion implantation)穿透閘極氧化層之互補式金氧半電晶體 (CMOS)。 衣發明以較佳實抱例説明如上，而熟悉此領域技藝 者，在不脱離本發明之精神範圍内，當可作些許更動潤 飾，如本發明以N井C Μ〇S做爲實施例之説明，而P并與 雙井Μ〇S亦適用本發明之方法，其專利保護範圍更當視 後附之申請專利範圍及其等同領域而定。 1裝 訂 各 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標隼局員工消費合作杜印製 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公釐）5. Description of the invention () The increase in the voltage of the short-channel components printed in the printed short-channel components of the Central Standard Falcon Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs will produce short-channel effects, such as the reduction of the critical voltage, the larger subthreshold current and the offset. The punchthrough effect is due to the reduction in the size of the device. The edges of the drain and drain regions of the drain and source are getting closer and closer. Once the punchthrough effect occurs, the current is subcritically concentrated. The amplitude parameter (SUbthreshold swing parameter; St) will increase. For one vessel, MOS uses ion implantation on the interface between silicon and silicon dioxide to increase the channel doping concentration to adjust the threshold voltage. The channel doping distribution affects the performance of the device. The channel ion implantation consists of a shallow ion implantation and a deep ion implantation. The shallow ion implantation determines the size of the critical voltage, and the deep ion implantation prevents punchthrough. ) Effect, reduce the surface doping level of the channel and at the same time maintain sufficient doping near the depth of the sink and source junctions to increase the electro-clay of the device and prevent punchthrough current. However, the traditional process requires several heat treatment sequences. Therefore, ion implantation often diffuses due to the heat treatment and breaks the original ions; the agricultural distribution is especially the temperature of the process of forming the field oxide layer. It is 1 0 0 0 and it takes a long time. Object and Summary of the Invention: The main object of the present invention is to provide a method of using deep ion implantation to penetrate the gate radonization layer to improve the performance of metal oxide semi-transistors. The main purpose of the present invention is to use deep ion implantation (deepi ο η This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -------------- I- --Ding (please read the precautions on the back before filling in this page) ^^ C4〇2 A7 B7 Employee's consumer cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs Du Printed V. Description of invention () implantation) through the gate oxide layer Promote the dip plan and current. Deep ion implantation is used to penetrate the gate oxide layer to prevent short channel effects and reduce the doping concentration of the channel surface. The method of the present invention can simultaneously maintain a sufficiently high doping concentration near the substrate junction depth. The doping concentration on the surface of the channel is reduced to increase the planing current of the drain and prevent punchthrough current. The process of the present invention includes: forming a field oxide layer on the substrate, ion implantation to adjust the turtle threshold voltage, the implanted ion is BF2 ion dose is 3.2E12-3.6E12 atoms / cm2, The implantation energy is 70KeV, and the silicon dioxide layer is thermally grown on the substrate and the field radonization. The silicon dioxide layer will serve as the gate oxide layer, followed by deep ion implantation through the gate oxide layer. ), The above-mentioned deep ion implantation uses an energy of 180keV, a dose of 3.5E12atoms / cm2t ^ l ions, deposits polycrystalline silicon on the silicon dioxide layer, and forms the gate by lithography and etching technology. The gate structure serves as the self The calibration mask is used for ion implantation. The ion source is phosphorus, which is mainly used as a lightly doped drain (LDD) structure to prevent the hot carrier effect. The next step is to deposit a radon silicon layer on the gate 'substrate. The side wall spacer is formed by anisotropically etched silicon dioxide layer, and finally doping region is doped to form the drain and source to complete the deep ion implantation of the present invention. Penetrating the gate radon layer Gold milk semi-electric crystals. Private clothing, 1τ (please read the precautions on the back before filling in this page) This paper size is applicable to China National Standards (CNS) Α4 specifications (210 × 297 mm) Printed by the Ministry of Economic Affairs Central Standards Bureau employee consumer cooperatives A7 __B7 V. Inventions Description () Brief description of the diagram: A circle on the V bank is a cross-sectional view of the NMOS of the present invention forming a first dioxide layer, a gasification layer I and defining a first photoresist. The second figure is the first NMOS of the present invention Cross-sectional view of secondary ion implantation ° 'The third image is the NMOS forming field oxide layer of the present invention and the second ion implantation \. The fourth image is the NMOS forming second silicon dioxide layer of the present invention and Cross-sectional view of deep ion implantation. • The fifth figure is the cross-sectional view of the NMOS forming gate structure of the present invention. The sixth figure is the cross-sectional view of the NMOS forming doped region of the present invention. The seventh figure is the invention and The current-voltage curve of the traditional method (the data shown in the figure is the current-electric curve of the SRAM process of 0_45 microns). The curve is the traditional method, and the curve 702 is the method of the invention. The eighth figure is the invention CMOS forms the first silicon dioxide layer, argon fossil The cross-sectional view of the layer and the first photoresist. V. The ninth figure is the cross-sectional view of the CMOS forming N-region of the present invention. The tenth figure is the cross-sectional view of the CMOS forming the channel stop of the present invention., Figure 11 is a cross-sectional view of a field radon layer formed by CMOS and ion implantation with threshold voltage adjustment in the present invention. 'Figure 12 is a cross-sectional view of a gate radon layer formed by CMOS and deep ion implantation of the present invention 'Thirteenth picture is a cross-sectional view of the CMOS gate structure of the present invention. This paper scale is applicable to the Chinese National Standard (CMS) A4 specification (2 丨 0X297mm) t ------ lτ --- ----.it (Please read the precautions on the back before filling in this page) A7 B7 printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention () ^ The 14th circle is the CMOS formed NMOS device of the invention Cross-section circle of the doped region. V Figure 15 is a cross-sectional view of the CMOS forming the doped region of the PMOS device of the present invention. Detailed description of the invention: The method of the present invention uses deep ion implantation (deep ο π imp 丨 antati ο η) penetrating the closed-pole oxide layer to prevent short channel effects and reduce the doping of the channel surface Miscellaneous; Nongdu 'deep ion implantation of the metal oxide semi-electric crystal (MOSFET) of the method of the present invention can avoid the influence of high temperature heat treatment when forming the field oxide layer, and the method of the present invention can simultaneously maintain sufficient near the substrate junction High; the doping of the agriculture ^ the sum of the current and the penetration current (punchthrough) to prevent punching (punchthrough) current. The manufacturing method of the present invention will be described below: Refer to the first figure 'the preferred embodiment of the present invention is to use the crystal plane as < 100〇> The P-type single crystal semiconductor is a substrate (subst "ate" 2). The substrate 2 is placed in a tube-forming oxygen-containing environment to form a first silicon dioxide layer 4 with a thickness of about several hundred angstroms on the surface of the substrate, and then formed by chemical vapor deposition on the above first silicon dioxide layer 4 The thickness of the nitrided broken layer 6 is between about 100 angstroms and 2,000 angstroms, and then the first photoresist 8 is formed on the gasification layer by lithography. Next, the silicon nitride layer 6 and the first precious oxide layer 4 are etched by an etching technique. The etched structure will be used as a mask for manufacturing the radon layer, and the entire substrate is implanted with ions for the first time. Do channel blocking, such as ▲ ------- 玎 ------ line (please read the precautions on the back before filling in this page) 6 Printed by the Consumer Cooperative, a member of the Central Standards Bureau of the Ministry of Economy. A7 —- ! ______ B7 V. Description of invention () As shown in the second figure. Referring to the third figure, after removing the first photoresist 8, the substrate is placed in a high-temperature dew to grow the field oxide layer 10 by wet oxidation and drive the first implanted phosphorus impurities into the substrate 2, After the production of the field oxide layer 10 is completed, the silicon nitride layer 6 is removed by wet etching. The next step is the second ion implantation to adjust the threshold voltage, and the implanted ion is dioxide (巳 F2) The amount of ion sword is 3.2E12-3.6E12 atoms / cm :, and the implantation energy is 70KeV. As shown in the fourth figure, after the first silicon dioxide layer 4 is removed by wet etching technology, a second silicon dioxide layer 12 is deposited on the substrate 2 and the field oxide layer 10 with a thickness of 90-1 20 Angstroms. The silicon dioxide layer 12 will serve as the gate radon layer 12. Next, for deep ion implantation through the gate oxide layer 12, the above deep ion implantation uses sleeve ions with an energy of 180 keV and a dose of 3.5E12 atoms / cm2, and other suitable trivalent ions can also be used. As an ion source for this deep ion implantation. As shown in the fifth figure, forming polycrystalline silicon 14 with a thickness of about 2000-3000 angstroms on the second silicon dioxide layer 12 for the third ion implantation to reduce the resistance of the polycrystalline silicon 14 or It is to deposit a doped polycrystalline silicon layer (i η situ-doped polysilicon) on the second dioxide · δ evening layer 12. Perform the second photolithography and define the second photoresist formed on the polycrystalline silicon 14 to form the gate 14 by etching technology, and then use sulfuric acid or other methods to remove the second photo paper. CNS) Α4 specification (21Qx297mm) ^ Second ------ 1Τ ------- ^ (Please read the precautions on the back before filling out this page) Printed by Uncle Consumer Cooperatives, Central Standards Bureau, Ministry of Economic Affairs System A7 ____ B7__ V. Description of the invention (Resistance 0 Refer to the sixth S, use the gate 14 structure as a mask to enter the pestle π A 1 Ding Di four ion implantation, ion source is phosphorus, the dose is about 1E13 atoms / Cm2 Mainly used as a lightly doped drain (LDD) structure 16 to prevent the hot carrier effect, one step is to deposit a third silicon dioxide layer 18 on the gate and substrate 2 and the field oxide layer 10, with anisotropy Etching the above-mentioned first =-^ layer 18 to form a side wall gap (3 ~ 〇16 to 3 ~ 丨 3 port 306〇18, the last way; ^ _ ^ 碋 定 · Dense doping of the impurity region to form the drain 20 source The electrode 22 completes the deep ion implantation of the present invention (deep ion implantation) through the metal oxide semi-transistor of the gate oxide layer. Refer to Table 1 and the seventh figure. The current (丨) -voltage (V) curve of the present invention and the traditional method, the data shown in the figure is the current-voltage curve of the SRAM process of 0_45 microns, Vg represents the voltage of the transistor operation, the gate oxidation of the present invention The thickness of the layer is 90 angstroms, the concentration of deep ion implantation is 3 5E1 2 atoms / cm2, and the implantation energy is 18〇KeV. Under the gate bias voltage, curve 701A is the experimental data of the traditional method, and curve 7〇2A is the invention The experimental data of the method; under the gate bias voltage of 4 \ /, the curve 701 is the experimental data of the traditional method, and the curve 702B is the experimental data of the method of the present invention; under the closed pole bias ink 3.3V, the curve 701C is the traditional Experimental data of the method, curve 702C is the experimental data of the method of the present invention; at the gate bias voltage of 2Vt, curve 701D is the experimental data of the traditional method, and curve 7020 is the experimental data of the method of the present invention; at the gate bias | 1VT ， Curve 7〇iE is the traditional paper standard using the Chinese national standard (CNsT ^ i721〇_; 297 public 17 (please read the precautions on the back before filling out this page) • 丨 installation · order five, invention description () method t Experimental data, curve 702E is the method of the present invention Experimental data, from the seventh circle, it is known that the method of the present invention generates a high foot-drain current under the gate bias of Baitong. In the method of the present invention, deep ions are implanted in the field oxide layer to form a squat, so the deep ions The implantation is not affected by the high temperature heat of the formation field oxidation (approximately 1000 · 〇; '110 minutes) while the diffusion shadow is adjusted by critical voltage adjustment and ion implantation of the surface channel. Comparison of the SRAM process with the traditional method and the present invention 'critical voltage (Vt), leakage current (| 0ff), saturation current (| dsat) and sub-critical swing (subthreshold) obtained by different ion implantation (vt | / 丨) As a result of swing), it can be seen from Table 1 that the present invention can at least increase the planer and current. (Please read the precautions on the back before filling out this page) • Discarded ·,-The Ministry of Economy Central Standards Bureau employee consumption cooperation du printed this paper standard is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) Central Ministry of Economic Affairs Printed by the Bureau of Standards and Staff Consumer Cooperative A7 ____ B7 V. Description of invention () Table 1 Critical current 1 Adjust ion implantation energy and concentration critical voltage (V) Leakage current (pA / UM) Saturation: fO current (uA / um) times Critical swing (mA / d ec) Conventional method 70KeV 2.6E1 2 atoms / cm 2 0.58 0.11 (3.3V) 288.7 (3.3V) 89 0.14 (5V) 539 (5V) 70KeV 3.2E1 2 atoms / cm 2 0.52 0.52 (3.3V) 336.7 (3.3V) 85.4 17% 1.01 (5V) 6 10.4 (5V) 13% The method of the invention 70KeV 3.6E1 2 atoms / cm2 0.57 0.178 (3.3V) 319.6 (3.3V) 86.8 11 % 0.295 (5V) 588.8 (5V) 9.2% Pack ------ 1T ------- 0 (please read the precautions on the back before filling this page) This paper size is applicable to China National Standard Falcon (CNS ) A4 specification (210X 297 mm) A7 B7 printed by the consumer cooperation of the Central Standards Bureau of the Ministry of Economic Affairs V. Description of invention () By Figures 1 and 7 show the waste electricity during operation: the saturation current increases by 13% at 5V, and the current and the current increases by 17% at 3.3V. Secondly, the second critical swing of the present invention also decreases slightly, and the critical The voltage is only reduced by 0.0 6 V, and the off-state leakage current is kept within a reasonable range. In the process of the present invention, if deep ions are implanted in the field oxide layer after formation and implantation, then ion implantation with threshold voltage adjustment is performed to form a gate oxide layer, and the remaining steps can be improved as in the first embodiment. For the performance of 〇S, the saturation current is increased by 6%, the sub-critical swing is also slightly improved, and the critical voltage is reduced by 0.0 3 V, and the leakage current is maintained below 1 p A / um. The method of the present invention can also be applied to the production of CMOS. The manufacturing process will be described as follows: The present invention will use N-well CMOS as an illustration. Similarly, the method of the present invention can also be used for the production of P-well or dual-well MOS. Referring to the eighth figure, a preferred embodiment of the present invention uses a P-type single crystal silicon semiconductor having a crystal plane of < 100 0 > as the substrate 30. A first silicon dioxide layer 32 with a thickness of about several hundred angstroms is formed on the surface of the substrate 30, and then a silicon nitride layer 34 is formed on the first silicon dioxide layer 32 by chemical vapor deposition The shadow technique forms the first photoresist 36 on the silicon nitride layer 34. Then, the silicon nitride layer 34 is etched by an etching technique. The etched structure will be used as a mask for manufacturing a field oxide layer. As shown in the ninth figure, a second photoresist 38 is defined to expose the P MOS region to be formed. Phosphorus ions are implanted into the entire substrate for the first time at a dose of about 1E12-1E13 atoms / cm2 to form an N-region 39. As shown in the tenth figure, after removing the second photoresist 38, the third photoresist is formed by lithography exposure. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297mm) --------- ----- Ιτ ------ i (Please read the notes on the back before filling in this page) A7 * B7 du printed by the consumer cooperation of the Central Standards Bureau of the Ministry of Economic Affairs V. Description of invention () 40 in Well N Above the area 39, a second ion implantation is then used to form a channel blocker 42. As shown in the eleventh figure, after the channel block 42 is completed, the third photoresist 40 is removed, the wafer is placed in a high temperature environment, and the area not covered by the silicon nitride layer 34 is subjected to the field oxide layer 44 by wet oxidation. After fabrication, the silicon nitride layer 34 and the first silicon dioxide layer 32 are removed. Perform the third ion implantation with trivalent boron or suitable trivalent ions. This third ion implantation is used to adjust the critical electro-ink. The amount of sword is about 1E12atoms / cm2, and the energy is between tens of KeV. Referring to FIG. 12, a second silicon dioxide layer 46 is formed on the substrate 20, and then a fourth photoresist 48 is formed on the N-region 39, and boron is used for the fourth ion implantation. The implantation is deep ion implantation, which penetrates the gate oxide layer deep into the substrate. The above deep ion implantation uses butterfly ions with an energy of 180keV and a dose of 3.5E12 atoms / cm2. Other suitable trivalent ions can also be used as this depth. The ion source of ion implantation, after the completion of deep ion implantation, remove the fourth photoresist 48. As shown in Figure 13, deposit the polycrystalline night layer 50 on the gate oxide layer 46, and use the etching technique for the fifth ion implantation to reduce the resistance of the polycrystalline silicon 50, or deposit An insitu-doped polysilicon layer (insitu-doped polysil icon) is above the gate oxide layer 46. Perform lithography and define the fifth photoresist formed on the polysilicon, use the etching technique to form the gate 50, and then use sulfuric acid or other methods to remove the fifth photoresist. This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) -------------- ir ------ 4 (Please read the precautions on the back before filling in this page) A7 B7 'V. Description of invention () See In the fourteenth circle, the sixth photoresist 52 is defined on the NTO region 39, and the ion implanted active region of the NMOS device is used to form a lightly doped drain (LDD) structure 54 to prevent hot carrier effects. The next step is A third silicon dioxide layer is deposited on the gate 50, the substrate 20 and the field vaporization layer 44, and then the third silicon dioxide layer is etched by anisotropic etching technology to form a side wall smell ) 5 6. Finally, dopant regions are heavily doped to form drain 58n and source 60n. As shown in Figure 15, the next step is to fabricate a doped region of PMOS. First remove the sixth photoresist 52 and then form a seventh photoresist 62 to expose the N-well region 39, using the gate 50 as a mask The ion implanted PMOS device forms the drain 58p and source 60p of the doped region. Finally, the complementary metal oxide semi-transistor (CMOS) with deep ion implantation penetrating the gate oxide layer of the present invention is completed. The invention of clothing is described above with a better example, and those skilled in the art can make some changes and modifications without departing from the spirit of the invention. For example, the invention uses N Well C Μ〇S as an example. Note that P and Shuangjing MOS are also applicable to the method of the present invention, and the scope of patent protection depends on the scope of the attached patent application and its equivalent fields. 1 Binding each (please read the precautions on the back before filling out this page) The Ministry of Economic Affairs Central Standard Falcon Bureau employee consumption cooperation du printing This paper standard is applicable to China National Standard (CNS) Α4 specification (210Χ 297 mm)