Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics CorpfiledCriticalUnited Microelectronics Corp
Priority to TW84101757ApriorityCriticalpatent/TW276363B/en
Application grantedgrantedCritical
Publication of TW276363BpublicationCriticalpatent/TW276363B/en
A fabricating method for multi-level mask read only memory comprises the steps of: supplying one silicon substrate with first conductivity, in which there forms buried bit lines with second conductivity, and there forms gate stack structure with word lines on silicon substrate surface; forming one oxide layer on the surface of silicon substrate and word line; forming sidewall spacer on two sides of those word lines; coating photoresist to make memory cell element programmed as OFF expose sidewall spacer on its two sides; make cell element programmed as half-ON expose sidewall spacer on its one side; make cell element programmed as ON expose sidewall spacer on its two sides be covered; removing all exposed sidewall spacer, then removing photoresist; and with the first conductivity ion performing slant ion implantation programming.
TW84101757A1995-02-251995-02-25Fabricating method for multi-level mask read only memory
TW276363B
(en)