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Application filed by United Microelectronics CorpfiledCriticalUnited Microelectronics Corp
Priority to TW83111984ApriorityCriticalpatent/TW270222B/en
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Publication of TW270222BpublicationCriticalpatent/TW270222B/en
Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits
(AREA)
Element Separation
(AREA)
Abstract
A latch-up preventing method for semiconductor device comprises: covering photoresist on silicon surface; performing well ditch photoresist for forming photoresist indentation with respect to each well edge part; etching ditch for forming trench on each well edge; filling trench with high-conductivity material; by the high-conductivity material surrounding each well edge forming electron stoppable structure.
TW83111984A1994-12-211994-12-21Latch-up preventing method for semiconductor device
TW270222B
(en)
A method for forming a power semiconductor as in figure 5 having a substrate (2), a voltage sustaining epitaxial layer (1) with at least a trench (52), a doped region (5a) adjacent and surrounding the trench.