TW268140B - Process for lightly doped drain with shallow trench and device thereof - Google Patents

Abstract

A process of lightly doped drain with shallow trench comprises: forming pad oxide and Si3N4 in sequence on silicon substrate; via one field mask to define active region, and via one field oxide to grow one field oxide; via one mask exposing, developing and etching Si3N4, making Si3N4 form trench with length L, in which the L value is sum of device gate width and two times subsequent sidewall spacer width; forming sidewall spacer around gate edge; removing pad oxide, then growing one gate oxide through thermal oxidization; depositing one polysilicon layer doped by impurity with high concentration; etching back to proper polysilicon thickness under Si3N4 surface to form device gate, and removing polysilicon left on field oxide; removing Si3N4, and forming source/drain with high concentration by impurity ion implantation with high concentration; forming metal silicide on gate and source/drain with high concentration to decrease its impedance; removing sidewall spacer, and with metal silicide and field oxide as etching mask etching silicon substrate to form one shallow trench; performing large-angle-tilt low-concentration impurity ion implantation to form lightly doped drain/drain; and through one thermal oxidization making inner edge of shallow trench grow one oxide and cover the whole chip with one dielectric layer; by shallow trench preventing depletion region of high-concentration source/drain expand into horizontal direction so as to achieve the effect of preventing punch through phenomena generate.

Description

26S140 A7 V. Description of the invention ('—1 Background of the invention; 1 1! Μ When the size of the field effect transistor element is smaller, the effective channel (ch an ne 1) becomes shorter so that the electrons are accelerated by the electric field between the source and the drain Exceed the energy barrier between silicon and oxygen * back-bu 1 layer (--- generally 3 · 2e V) 9 This electron is called thermoelectric 5t meaning t -1 son 0 These hot electrons are very easy to jump to the gate oxidation Eyebrow 9 Part of the hot electrons will be lost, Ψ til I * Most of the electrons will be captured by some defects of the original gate oxide layer such as interface traps x? 1 l 1 1% h (I nter fa ce T ra ps) • Or when the drain 1 gate is connected to a high voltage, the interface between the drain and the channel is prone to cumulative collapse (Αν a 1 an che Br ea kd ί 1 I i 0 W η), which makes it easy for electrons to obtain high energy and form heat. Electrons • When these c 1 hot electrons are captured by the oxide layer Catching will cause adverse effects on the operation of the components, such as the threshold voltage (vt) increases the unnecessary gate current formed by hot electrons 1 | * The breakdown voltage of the drain interface decreases Gm (Tr an SC on duct an ce) Change 1 to set smaller and reduce the working life of the device, etc. • 1 I * In general, to prevent the generation of hot electrons, some device structure changes are made to 1 1 to avoid the formation of a high electric field at the interface between the source / drain and the channel. 1 1 pole (Li gh t 1 y Dope d Dr ai η LDD) structure t which is mainly through N, line / P * source / drain and drain pole by low concentration N- / p- source / drain Separated by 1 I open t without generating high electric field around N * / source / drain to achieve the effect of suppressing the generation of 1 1 heating electrons • t 1 is produced but the distance between the source and the drain is very small due to the smaller component size 9 Then when \ I Jiji Drainage The higher, the drain depletion area of the drain (D ep 1 eti on L ay er) will expand with the 1 1 I clip Ψ until the drain depletion area of the drain is connected to the source drain area. The rapid rise of the pole current 9 means that the source and the drain are broken down (Pu nc h- Thro 1 1 elimination * ik Ug h) phenomenon, especially when the LDD process is below 0.5 micron t This phenomenon is more 1 | 3 1 1 268140 A7 268140 A7 Five, the description of invention () can not be avoided 'the value of the drain electrode ® is called the breakdown current · (Punch Through Voltage) · and the breakdown voltage value is related to the channel length and the resistance of the wonderful substrate The value (ie, the surface impurity concentration of the silicon substrate) is related, so some people use a breakdown-resistant ion implantation to increase the near-surface impurity concentration of the wonderful substrate, so that the empty region of the drain is not easy to expand as the drain current should increase. In order to avoid the breakdown phenomenon, it is very easy to make the threshold of the component (Threshold Volta ge) different height is not easy to control. Of course, there are various methods to improve the breakdown of the NM〇S LDD in the conventional technology. A few representative examples will be briefly described as follows: 1. A P ♦ Pocket structure is provided, as shown in FIG. 1 • There is a factory-like pocket around the N- / N ♦ source / drain Wrap it up, so that the empty depletion regions of the source and the drain will be limited to the p-bag region 'so that the source and drain depletion regions are not easily accessible' to avoid the occurrence of breakdown phenomena. The spatial location of the source / drain is shown in FIG. 2. The source / drain S / D is located in the same plane as the gate 22, and the source / drain S / D is separated from the gate 22 by the LDD part. Open, by the special spatial configuration of the source / drain S / D, the depleted area is not easy to expand laterally and connect with the 鲥, so as to avoid the effect of the breakdown phenomenon. 3. Form a structure with a recessed gate As shown in # 3. First, a groove is formed, and then a gate oxide layer 21 is grown by thermal oxidation, and filled with polycrystalline silicon as the idle electrode 2, and then the source / drain S / D is formed on both sides of the groove. The structure of the idle connection of the groove is also achieved by preventing the source / drain S / D of the empty depletion region from being easily contacted by the oxide shield 21 to prevent the breakdown phenomenon. Four. Change I: the wall spacer ( Spa cer) to adjust the source / drain and polycrystalline silicon gates to be green and one. • Above various ways to improve the breakdown voltage of NMOS LDD-4 («First« Read the back * the ii * matters and then the dumb book 1 > . Installed. The surname of the surname t is the t-fold list «ΛΧ-consumption contains a thorium seal« 1 · ·-J / — y ', * · 1 · -3 f 4.-t distance etc. A7 268140 V. Description of the invention () The method is not limited by the complicated process, that is, it is limited by the improvement effect, making it unsuitable for production. Therefore, it is necessary to propose a method for increasing the breakdown voltage and a method that is simple for the production process and improves the effectiveness of the general effect. Its device · | Summary of invention: |

The main purpose of the present invention is to provide an LDD manufacturing method and device with shallow grooves, which is simple and suitable for Dong production. The present invention is mainly to form shallow grooves around the gate and implant low-impurity impurities at a large angle Into the shallow groove to form a low-doped source / drain structure. The source and drain are separated by the structure of the shallow groove LDD (Lightly Doped Drain) to improve the breakdown through V〇i tage) and the effect of simplifying the process · Description of the drawings 5 Figure 1 is a cross-sectional view of the P * pocket LDD structure · Figure 2 is a cross-sectional view of the LDD structure with the source / drain increased position · Figure 3 is a groove Cross-sectional view of the LDD structure of the gate · Figure 4 A-4M is a cross-sectional view of the main process structure according to the first preferred embodiment of the present invention · Figure 5 A_ 5 D is a main process according to the second preferred embodiment of the present invention

Structure section icon number part: silicon substrate ... pad oxide layer ... silicon nitride ... field oxide layer ... 10 11 12 13 high concentration source / drain ... 41 metal silicide ......... 51 Shallow grooves ......... 61 Low concentration source / drain (LDD). 42 5 — 268140 A7 Ministry of Economic Affairs Associated employees' consumption includes social printing * · > J «« y · ** — · > Λ— V. Description of invention () Side wall spacer ____23 CVD oxide layer ........ 71 Gate Oxide layer ... 21 Polycrystalline silicon layer ... 31 Gate ......... 32 In order to make your examination committee more clear about the technical means of the present invention and its effect, Zuo The first preferred embodiment will be described in detail with reference to the drawings. First, please refer to FIG. 4A. A pad oxide layer 11 is grown on the silicon substrate 10 by thermal oxidation, and a silicon nitride layer 12 is deposited. The pad oxide layer 11 The role is to prevent the difference in coefficient of thermal expansion between the silicon substrate 10 and the silicon nitride 12 is very easy to produce lattice defects. Then through a field of light. Mask exposure development to define the active region (electronic region) where electronic components are placed, After the photoresist is removed, the field region is oxidized to grow a thick field oxide layer 13 as the electrical isolation of the active region • This field oxidation step, also known as Local Oxidation of Silicone L0C0S, uses silicon nitride 12 as an oxidation mask to produce a selective oxidation effect on the silicon substrate 10. Then, it is exposed through a photomask, The silicon nitride 12 is developed and etched to form a groove with a length L. The value of L is generally designed as the sum of the width of the device gate (commonly referred to as the line width) and the width of the spacers on both sides. For example, the process of 0.35 microns, the width of the edge spacer is about 0.1-0. 15 microns, then this L value is 0.35 + 2X0.1 = 0.55 microns, as shown in Figure 4B. Then, in the kryptonized silicon On the periphery of 12, the phoenix partition carving 23 is formed, which is generally achieved by first depositing a dielectric eyebrow and then borrowing the etching back (Etching Back) technique, and the material of the wall partition 23 may be an oxide, as shown in FIG. 4C — 6 — (please read the precautions on the back and then fill in this page) {Read first «Read the iit kite item on the back and then write this page > Then _-装 · 訂 _ 线 ίΓΝ '?) Ψ 4 (2 \ 0 y M7 cm) 82. 9. 6,000 268140 A7

5. Description of the invention () shown • Next, the pad oxide layer 11 is removed and then thermally oxidized to grow a gate oxide layer 21 of good quality, as shown in FIG. 4D. Then, it is deposited on the entire wafer surface by CVD method -Fujing Miao Shield 31 is doped with a high concentration of impurities. This doping method can be achieved by in_Sit u Doping, impurity diffusion or engraving to reduce the impedance of the Fu Jing 31 layer, such as As shown in Figure 4E • Then, the wafer is subjected to chemical-mechanical polishing (Chem i ca 1 Meehan i ca 丨 Po 1 i sh i ng, c Μ P) to grind it to the appropriate polycrystalline silicon layer below the surface of the vaporized Miao 12 3i thickness to form the idler electrode 32 '. The appropriate residual thickness is about 1500-2500 angstroms, and the residual polysilicon is located on the field oxide layer 13 as shown in FIG. 4F. ▼ · Read I at X back

I Binding and then 'remove silicon nitride 12 and pad oxide layer 11 with an etching gas or etching solution with a high selective etching rate ratio of silicon nitride to polycrystalline silicon and silicon nitride to oxide, as shown in FIG. 4G • High-concentration N ♦ Impurity carvings are implanted to form a high-concentration source / drain 41. The side wall partitions 23 have the function of blocking the carvings so that the high-wave source / drain 41 is separated from the sink pole 32 by an appropriate distance. , As shown in FIG. 4 Η. Then, Co-sputtered method is used to selectively deposit TiSU or WSiss on the silicon-containing material, so that a layer of metal silicide 51 is sintered on the high-wave source / drain electrode 41 and the prism electrode 32 to It further reduces its impedance and increases the operation speed of the device. This step is a selective deposition formed by self-alignment, so no mask is needed, as shown in Figure 4I. The side wall spacers 23 are removed, as shown in FIG. 4J. Then, using the metal silicide 51 and the field radon layer 13 as an etching mask, the silicon substrate 10 is etched into a shallow groove 61 with a depth of about less than or Equal to the depth of the high-concentration source / drain 41, generally about -7 %

A

Produce 268140 A7 carp department Chinese shellfish;

X Consumption V. Description of the invention (1 Island I is about 0.1-0.15 micron 9 as shown in Figure 4 Κ • '1 Next »for large angle N- impurity ion implantation, the angle is about 30 to 45 degrees η First, between M 1 1 and t can form a low-doped source / drain (LDD) 42, and the L nq read back Jq 1 DD structure also separates the gate 32 from the high-concentration source / drain 4 1 9 Fig. 4, shown at 1 1 L • Afterwards, P is thermally oxidized to grow the shallow recess 61-oxidation for insulation \ re | 1 layer and covered with a CVD oxide M 71 to complete the present invention with shallow groove L% This 1 1 DD device Qian 1 | By circle 4 Μ It is shown that when the high wave source / drain is coupled with an appropriate pressure drop I r, the depleted area is expanded vertically 9 in the horizontal direction due to the shallow groove installation I 61 The internal oxide barrier is not easy to expand, so the empty region of the source 41 is not easy 1 1 and the drain 41 are empty Dysprosium 9 is connected to each other to achieve the effect of improving the breakdown voltage 1 1 9 and the present invention still retains the characteristics of general LDD »such as suppressing the production of thermal electrons 1 | Health etc. • At the same time t the process of the present invention is not known Complicated 9 product formulation | manufacturing cycle and product yield has not deteriorated 9 so it is-* suitable for the production process of the director 1 1 9 has great industrial use value • 1 1 The following will introduce the second most according to the present invention The preferred embodiment 9 is still dominated by N 1 — Μ 0 S. First, after the local silicon oxidation (L 0 C 0 line 1 S) on the silicon substrate 10, the active region is defined and the field oxide layer 13 is formed. It is thermally oxidized to 1 1 I long oxide layer 21 and Shenji _1 polycrystalline silicon with high impurity concentration doping. This 1 doping method has been described in the first preferred embodiment. Jun 1: Exposure t Development and etching of polycrystalline silicon and gate oxidation 21 Formation of gate 32 > Re-sink 1 |: Use a dielectric eyebrow and borrow etching technology to form a side wall on the periphery of gate 32 1 I • Isolation 23 t as shown in FIG. 5 A • 1 1 1 1 — 8 — 1 1 The paper size is suitable for China® • Home · Rubble Accuracy (r〇V2) (1)

I. Description of the invention () {«Precautions on the back of Mtr and then write this page) Then 1 is implanted with a high concentration of N + impurities to form a high concentration source / drain 41, then the side wall spacer 23 It still has the function of blocking ion implantation, so that the gate 32 is separated from the high-concentration source / drain, as shown in FIG. 5B. • Then * still the same as the previous embodiment, the TiSi2 or WSi2 etc. are used by the Co-sputtered method The metal silicide 51 is only selectively deposited on the gate 32 and the high-concentration source / drain 41 to reduce its impedance, that is, as shown in FIG. 5C. Afterwards * the side wall spacer 23 is removed and the metal silicide 51 and The field oxide layer 13 is used as an etching mask to etch a shallow groove 61 on the silicon substrate 10, as shown in FIG. 5D, its depth is about less than or equal to the depth of the high concentration source / drain 41, generally about 0.1-0.5 microns Left and right • The last remaining process is the same as the previous embodiment, that is, the formation of a low-doped source / drain (LDD) 42, and a CVD oxide layer 71, etc. The preferred embodiment clearly shows that the process of the second preferred embodiment is simpler and more practical, and has been checked by relevant hand magazines and periodicals. At present, the industry has not found the use of the same technical means as the present invention *, so the application for a patent is filed according to law. -9 — This paper is available in 8B home tf »(CNS> A < say grid (210 X 297m 82. 9. 6,000

Claims (1)

268140 Sixth, the Chinese patent range m ii ^ fft ^ t, quasi tortoise Ax " fr included as a printed V u ,, 4 ------ lτ ------ A -------- ----- (1 * Mir back first ^ 11 *? ^ Then Jflx table ί> ___ I_I__ ^ ^ ld 1 ^ ^ ^ ^ ^ ^ forming ploidy; the low degree is \ crystal square silicon and silicon wave drop Do a source of oxidation and crystallographic height to level the water level of the mixed water zone: thick compound the physical and chemical building in the past: the field makes the oxygen of the wide layer of silicon and the area * including silicon one, polarization., Crystal on The low-level silicon field depleted encapsulates the silicon and oxygen of the silicon layer of the silicon gate oxygen layer and the chemical effect of the chemical element. The power of the gold is in the form of oxygen. And, the nitrogen element is crystallized as oxygen. , With the one-layer normal layer engraved as., The long complex field-shaped silicon groove into the long-pull systemic chemical erosion value: under the physical composition, it is a concave plant formation on the complex \ D oxygen production and L and separation The complex is reflected by the source of the ultra-gold gold astronomer D, and the remaining soil of the oxygen-proof floor is drawn with an internal degree, which is now apparent, and the thermal quality of the wall is high, and the quality groove is engraved. The shape is fixed, the wide side of the trench is doped with silicon to remove the source and the recessed high-strike groove sequence, and then the optical groove is formed again. Combine and measure the substrate level, shallow., Stop the concave cover., The exposed layer of concentrated nitrogen, thick concentrated base} Make the eyebrow resistance against the shallow glazing layer L. Miao low-D electricity is connected to the bottom area of the luminosity of the knee with oxygen engraving., And the wall will be a D-oxygen medium groove with a base field oxygen-a long side electrode pad and an eroded gas electrode., Side cover angle L Hot one concave, one kind of silicon, one gate, one gate, one gate, one gate, one gate, one gate, one gate, one gate, one gate, one gate, one gate, one gate Zhang scale applies " Chinese National Standard TtWS (210X297mm) 268140 A8 B8 C8 VI. Patent application scope II. The LD technology with shallow grooves described in the first item of the patent application scope is completed, and The material of the dielectric layer can be oxide or nitride * 3. A method of producing LDD with shallow grooves according to the first item of the scope of the patent application, wherein the impurity doping method of polycrystalline silicon can be ion implantation In-Situ Doping or Impurity Diffusion, etc. 4. A method of producing LDD with shallow grooves as described in item 1 of the patent application The etching back of the polycrystalline silicon layer can be achieved by chemical-mechanical polishing (CMP). 5. A method of producing LDD with shallow grooves according to the first item of the scope of the patent application, in which metal silicide is the choice It does not require any light emerald, the metal silicide is only formed on the gate and the high concentration source / drain * 6. According to the LD with a shallow groove as described in the first item of the patent application Describe the deep groove in the shallow groove. Fan Qiduli, the deep special law, please apply for extreme D, Yi Yi, seven sources, concentration is higher than or equal to (please read "Precautions on the back and then fill this page") • L. Order, >;#殈 済 / | * 芈 局 ^, Work: «Fee. ^^ The groove of the DL printed by the company has a kind or material nitrogen or material oxygen is a material layer & 0 medium The method described in D 2 includes silicon-containing encapsulated nitrogen, and the method of forming D-oxygen D pad L. The grooves are formed in a concave sequence with a base silicon on the stack. Yuehuo. It is determined that the field of oxygen will be covered by the light layer. The patent should be patented Ε Α8 Β8 C8 (please read the notes on the back first. \ * Ί (拎 先 Mitw · 面 之; 1 ± Gu Xiangzai? Ί * .Ι) ___I_ Zha Zhiqi's etched dip slice to D etched gas D into L and thrown into a sub-low as \ crystal side L erosion, L plant's mechanical shape departed to be a son of a flat return The layering of the tank machine is a layered mixing tank. The tank is separated from the concave by the chemical tank; the chemical compound is mixed into the concave and the reoxygen concave is a shallow layer of oxygen. In order to expand the chemical W concentrated silicon field, the low-level depleted people have electricity to have available tools, oxygen and high genus and chemical space effect tools, available hybrids, closed silicon, and gold-shaped oxygen. Fang or one crystal at a time and become a complex .. The erosion of one of the poles is a heavy material and a complex. The formation / depletion of the layer P1 of the formation and production description layer. The source of the ultra-gold astonite is like the Do item shield 1 of the Institute of Physics and Electricity. U Eight silicon-one hot shadows, and carved grooves thickly penetrate the eight partitions. The eight silicon it crystals are shown by the edge \ source, the etched and concave high hit the second wall and wait for the second crystal-S to surround and form the source Degree of bottom., Shallow., Blocking the edge, silicon enclosure complex In Fanzhong JI light shape thick off base concentration Huadian entered the specialty with the advantages of Daliqi compound, the peripheral height of the oxygen hood and the wall will be special. The planting method is to mat the optical pole. The side mask angle L is hot and concave. The law court may apply for the removal of one. The big {one superficial and large-scale application of artefacts is now based on the D to the meridian, engraved into the resistance and carved the meridian to borrow and expand the D according to the D, · D •. 1 Ninety-one 1 --- ~ ^ 1¾¾ ZTE «Η- 局 β 工-« fr 合 tru 印 V A8 B8 C8 6. The patent application of the Chinese Patent Application Group (CMP) method is reached. 2. A method of L DD with shallow grooves as described in item 8 of the patent application, in which the metal silicide is a selective deposition, so there is no need Any photodiode is needed, the metal silicide is only formed on the gate and high concentration source / Above the drain. 3. According to the DD method with shallow grooves described in item 8 of the patent scope, where the depth of the shallow groove is about less than or equal to the depth of the high concentration source / drain. 4. According to A method for producing L DD with shallow grooves as described in item 8 of the patent application scope, in which the dielectric layer material can be radon or nitride or first M it back i Meaning ψ% year% L The combination of the above two * 15. An LDD device with stack grooves, including: an active region and a field oxide layer are formed on a silicon substrate; the active region contains a high concentration source / drain Gate, low-doped source / drain 'gate oxide layer and polycrystalline silicon gate doped with high concentration of impurities, and the low-doped source / drain is located in the polycrystalline silicon gate by large-angle ion implantation Formed by shallow grooves on the periphery; metal silicides are formed on the polysilicon gate and high concentration source / drain; an oxide layer is grown in the shallow grooves on the periphery of the polysilicon gate by hot oxygen; A dielectric layer covers the above-mentioned field oxide layer, metal silicide, and shallow grooves; the shallow grooves are used to block the expansion of the empty region of the high concentration source / drain in the horizontal direction * to prevent breakdown phenomena Efficacy · — 1 3 — A8 Βδ C8 ^ _-_ VI. Patent application ffl 16. The LDD device with shallow grooves according to item 15 of the scope of the patent application, where the depth of the shallow grooves is about less than Or equal to the depth of the high concentration source / drain The LDD device with shallow grooves, wherein the metal silicide is TiSi2 $ WSi2, etc. 18. Eighteen LDD devices with shallow grooves according to the fifteenth item of the patent application scope * where the dielectric layer can be It is an oxide or a krypton compound or a combination of the two. * 19. An LDD device with shallow grooves as described in item 15 of the patent scope, where the LDD structure is an NMOS, PM 0S or CMOS device. (Please read the precautions on the back before filling in the nest page) V. 4 Order I. Too W >? 疥 m tiMB B «V14at (TNS1