TW254013B - Single rail up-down pass transistor logic - Google Patents

Abstract

A single rail up-down pass transistor logic used for executing a logic operation, which outputs the result of executing the logic operation with a set of input variable to a set of output variable by use of a set of control variable, includes: - a first mixed pass transistor circuit consisting of multi-PMOS transistors and multi-NMOS field effect transistors, whose input end is the reference level of the single rail up-down pass transistor logic, through the set of control variable to gate-control the field effect transistor, outputting a set of first middle variable; - a NMOS pass transistor circuit consisting of multi-NMOS field effect transistors, whose input end is the set of input variable, through the set of control variable to gate-control the field effect transistor, outputting a set of second middle variable and constituting a set of pre-output variable with the first middle variable; - multi-up output buffer whose input end is the set of pre-output variable and output end is the set of output variable, used for raising the logic high level of the set of pre-output variable to the reference high level of the single rail up-down pass transistor logic.