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Priority to TW83110898ApriorityCriticalpatent/TW251384B/en
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Publication of TW251384BpublicationCriticalpatent/TW251384B/en
A process of planarized trench device isolation includes: - forming a mask layer on a substrate, and by etching defining pattern, exposing the area destined to be formed as active area on substrate; - etching the area uncovered by mask layer on substrate to form trench; - forming a thin oxide layer on the bottom and sidewall of the trench; - implanting a dopant into the substrate under the trench to form a channel stop region; - forming a TEOS layer covering the thin oxide layer and the mask layer to fill the trench; - forming a metal layer on the TEOS layer; - removing the metal layer; - through the crack and pit etching to remove the mask layer and the part of the TEOS located on the top of the mask layer; - forming a insulating filler to fill up the crack and pit in the trench, completing the planarized trench device isolation.
TW83110898A1994-11-231994-11-23Process of IC planarized trench isolation
TW251384B
(en)
A method for isolating an active region of an MOS semiconductor device using a planarized refill layer which is not substantially overpolished and an MOS device fabricated thereby