TW243552B - Fabricating method for flash EEPROM - Google Patents

Fabricating method for flash EEPROM

Info

Publication number
TW243552B
TW243552B TW82111055A TW82111055A TW243552B TW 243552 B TW243552 B TW 243552B TW 82111055 A TW82111055 A TW 82111055A TW 82111055 A TW82111055 A TW 82111055A TW 243552 B TW243552 B TW 243552B
Authority
TW
Taiwan
Prior art keywords
polysilicon
conductive
mask
doping
dopant
Prior art date
Application number
TW82111055A
Other languages
Chinese (zh)
Inventor
Yeun-Ding Horng
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to TW82111055A priority Critical patent/TW243552B/en
Application granted granted Critical
Publication of TW243552B publication Critical patent/TW243552B/en

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Abstract

A fabricating method for flash EEPROM with high electron tunneling efficiency includes: 1. growing one gate oxide on the first conductive semiconductor or the first conductive well area, and defining the source/drain region through tunneling oxide mask, then implanting the second conductive dopant ion with high density to form buried the second conductive area; 2. doping the first polysilicon, and doping dopant, then etching through mask, making the first polysilicon overlay only on the buried second conductive area and connect with the buried second conductive area in short circuit, then removing mask; 3. growing one polysilicon oxide through thermal oxidization and making the interface between the first polysilicon and polysilicon oxidization form many needle protuberance, then depositing the second polysilicon and doping dopant and through mask etching to form floating gate, then implanting the second conductive dopant ion with high density to from source/drain region; 4. depositing one intermediate insulating layer as the electric separation between two polysilicon, and depositing the third polysilicon, doping dopant and through mask etching to form control gate.
TW82111055A 1993-12-28 1993-12-28 Fabricating method for flash EEPROM TW243552B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW82111055A TW243552B (en) 1993-12-28 1993-12-28 Fabricating method for flash EEPROM

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW82111055A TW243552B (en) 1993-12-28 1993-12-28 Fabricating method for flash EEPROM

Publications (1)

Publication Number Publication Date
TW243552B true TW243552B (en) 1995-03-21

Family

ID=51401027

Family Applications (1)

Application Number Title Priority Date Filing Date
TW82111055A TW243552B (en) 1993-12-28 1993-12-28 Fabricating method for flash EEPROM

Country Status (1)

Country Link
TW (1) TW243552B (en)

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