TW226482B - High-capacitance stacked capacitor of dram cell - Google Patents
High-capacitance stacked capacitor of dram cellInfo
- Publication number
- TW226482B TW226482B TW82105916A TW82105916A TW226482B TW 226482 B TW226482 B TW 226482B TW 82105916 A TW82105916 A TW 82105916A TW 82105916 A TW82105916 A TW 82105916A TW 226482 B TW226482 B TW 226482B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- poly
- etching
- covering
- oxide layer
- Prior art date
Links
Landscapes
- Semiconductor Memories (AREA)
Abstract
A process for producing high-capacitance stacked capacitor of dram cellwhich comprises: the step of on a base or an area sequentially growing a gate oxide layer,precipitating first poly layer/oxide layer/second poly layer/silicon nitridelayer/another oxide layer; the step of implementing bit-line mask/covering photo resistor to undergoetching of the oxide layer, silicon nitride layer and the second poly layer; the step of implementing sedimentation/etching of silicon nitride to formthe second poly side wall; the step of etching the oxide layer beneath the second poly layer andetching the first poly layer; the step of implementing source/drain area ion implantation; the step of chemical gas phase sedimentation to form an oxide layer andetching the layer to form a first poly layer side wall; the step of etching to remove the silicon nitride layer side wall of theouter circumference of the second poly layer and the top of the siliconnitride layer; the step of covering poly via mask/loading photo resistor/etching to formthe poly via; the step of precipitating/doping/masking/loading photo resistor/etchingthe third poly layer to enable the third poly layer contacting the secondpoly layer to form the bottom electrode of the stacked capacitor; the step of covering a dielectric layer on the third poly layer; the step of precipitating/doping/masking/loading photo resistor/etching thefourth poly layer; and the step of covering a sheath layer and etching to form a bit line contactwindow.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW82105916A TW226482B (en) | 1993-07-26 | 1993-07-26 | High-capacitance stacked capacitor of dram cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW82105916A TW226482B (en) | 1993-07-26 | 1993-07-26 | High-capacitance stacked capacitor of dram cell |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW226482B true TW226482B (en) | 1994-07-11 |
Family
ID=51348389
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW82105916A TW226482B (en) | 1993-07-26 | 1993-07-26 | High-capacitance stacked capacitor of dram cell |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TW226482B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7893911B2 (en) | 2005-05-16 | 2011-02-22 | Au Optronics Corp. | Display panel and driving method thereof |
-
1993
- 1993-07-26 TW TW82105916A patent/TW226482B/en active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7893911B2 (en) | 2005-05-16 | 2011-02-22 | Au Optronics Corp. | Display panel and driving method thereof |
| US8542174B2 (en) | 2005-05-16 | 2013-09-24 | Au Optronics Corp. | Display panel and driving method thereof |
| US8542173B2 (en) | 2005-05-16 | 2013-09-24 | Au Optronics Corp. | Display panel and driving method thereof |
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