TW219989B - A screen refreshing method which is independent of resolution - Google Patents

Abstract

A screen refreshing controller which can store pixel data by linear addresses and use row addresses and sequential memory retrieval to receive row pixel data from the storage device and sequentially output the data to be used in signal memory; the controller is comprised of the following: (1) a first counter to count the output pixel number of the pixel data from the memory's sequential output; (2) a second counter to address next row of pixel data which is to be transferred into sequential storage and fetch memory; (3) a time pulse generator circuit, which increases the second counter once when the first counter is in the range of its lower half row; (4) a fetch retrieval pointer generation device which indicates that when the first counter is on the upper half, the lower half pixel data of the second counter in the storage device must be transferred into lower half of the sequential fetch and retrieval memory; and when the first counter is on the lower half, the upper half pixel data of the second counter in the storage device must be transferred into upper half of the sequential fetch and retrieval memory; and (5) a screen refresh request generator device which generates a request signal when the first counter reaches every half row range to transfer the fetch retrieval pointer to the half row of the second counter to transfer into sequential storage retrieval memory.

Description

218339

V. Description of the invention The Ministry of Economic Affairs and the Central Standards Bureau staff and employees. Du Yinzheng 1 shows a traditional holographic display system. The display system 10 is used to display an image on the CRT 12. The pixel data to be displayed on the image display 12 is stored on the neck display memory 14. In the conventional display system 10, the display memory 14 is composed of dynamic random access memory (DRAM). composition. When the host computer system 16 prepares to update the pixel data in the dynamic random access memory 14, the host computer system 16 receives the address from the address bus 15 and the multiplexer 18 On the dynamic random access memory 14. The pixel data of the updated dynamic random access memory generated by the host computer system 16 is sent to the random access port 20 of the dynamic access memory 14 via the bus 30. The access control signal is sent to the memory controller line 7 through the control line 8 to generate various control signals such as CAS, RAS, etc., and sent to the dynamic access memory 14 through the line 9. For completing a screen update operation, The updated address is sent by the drawing controller 22 to the dynamic access memory 14 via the E-stream 17 and the multiplexer 18. The pixel data to be transferred to the Yingmu 12 during the Yingmu update operation is updated by the dynamic The random access port 20 of the random access memory is read out and sent to the shift register 24 via the bus 30. The shift register 24 is used as a parallel-to-serial converter (Parallel-to-serial converter). After that, a digital-to-analog converter (DAC) is used to convert the digital The pixel data is converted into an analog signal, and then the timing control to the shift register 24 is performed by the video timing signal generated by the Graphic Coutroller 22, and by The signal line 19 is servo-served to the shift register 24. The drawing circle controller 22 uses the confluence (please read Jibei's precautions # 瑱 写 this page) to install-line · original paper " Bibi (CHS) T butterfly grid (210; < 297 public; jf) 61. 2. 20,000 219039 Λ 6 116 The Ministry of Economic Affairs ’standard and the β-worker ’s cooperation in cooperation with Du. V. Description of invention () Row 11 is It is connected to the host computer system 16, and it also generates at least a vertical synchronization signal (VSYNC), a horizontal synchronization signal (HSYNC), a horizontal and vertical blanking signal (Horizontal and Vertical Blanking Signal). The display system 10 of these signals has a serious drawback by serving the signal line 21 to the digital display 12 and the digital-to-analog converter 26. The display system 10 of FIG. The main problem is that the medical streaming system 30 Suka broadcast host computer system 16 is randomly accessed; [Fu 20 accesses data to update the pixel data in the display screen and the update screen operation must also send data through this port To Yingmu 12 〇 Obviously, when the resolution of Yingmu is increased, the time it takes to complete the update and update is also increased. When the time required to update Yingmu reaches a certain level, the host computer The system 6 will not be able to gain control of the bus 30 and the random access port 20 to complete the update operation of the display memory. This conflict is due to the occasional use of the random access port 20 and the bus 30. This result reduces the overall operating efficiency of the display system. One solution to such conflicts is to use video random access memory ( VRAM) replaces the simple dynamic random access memory to implement the on-screen display memory. Gu 2 shows a 256KM video random access memory ⑽. The video random access memory 4 in cell 2 contains a dynamic random access memory 42. It has 512 rows and 512 columns. The video random access memory 40 also has a random access port 44 and a sequential access port 45. Video access memory 40 also includes a broadcast sequential access memory (SAM) 46, which is temporarily shifted The memory and output pixel data sequentially through the sequential input / output port 4g. A complete row of data in the video access memory 42 can be passed through the message (please read first. This page) Binding-Binding-Line.

219239 AGH 6 The Ministry of Economic Affairs, the central standard, ^ industrial and consumer cooperation cooperation Du Du. V. Description of invention () Line 47 A, 47B and transfer transfer gate to the serial access memory 46, this transfer operation is called Read data transfer (Read Data Transfer, RDT) o When a read data transfer operation is completed, a whole row of pixel data on the dynamic random access memory 42 is transferred to the sequential access memory 46. In order to access the pixel data in the memory 46 sequentially, the input / output port (I / O Port) 49 can be sequentially moved out. This action is completed by one of the internal #sequence counter 4S. This counter (Serinal Counter) receives a sequential time squint (SC) as its time squint input, and the sequential counter rushes with each time of the sequential squint. The pixel data at different positions is output from the memory 46 by sequential access. On the other hand, the sequential counter 48 can be counted by the outside world (that is, given its starting position index), so that it refers to any position in the sequential access memory boat 46 as the starting round of pixel data position. Here In the operation of the chess game, the data is sequentially read from the position pointed to by the index to the sequential access memory. For example, TMS 4 2 0 2 5 0 video random access manufactured by Texas Instruments The memory operation mode is similar to the video random access memory 40 in FIG. 2. The video 3 shows a video display system 10. The system 10 in FIG. 3 is the same as the system in the surrounding 1. 10 〇 The difference is that the video display memory is implemented by the video random access memory 40 instead of the dynamic random access memory 14 used in sleepy 1 〇 In addition, the parallel to sequential conversion The device was also removed. In the system 10 of K3, the display memory update operation is transferred from the host computer system 16 via the bus 47 to the random access port 44 of the video random access memory 40. On the other hand , The completion of the update operation of Yingmu is sequentially outputted by the order of #FU; 1 阜 45 # and sent to digital to analog transfer (please pay attention to the first and tNotes # fill this page) Τ This paper standard is in use as Home Standards (CNS) TM regulations (210x297 g; in 81. 2. 20,000 V. Description of invention ()), on 26, it is updated with a signal converted into an analogue to Yingmu 12. The display system 10 In the above, the sequential clock used on the broadcast sequence 45 in the video random access memory 雅 40 is generated by the Emin controller 22 and sent to the signal via the signal line 48. In short, In the system 10 of Min 3, the update operation of the display memory and the update operation of the display memory are performed by different access ports and different buses, so that the two processing procedures are independent of each other. Therefore, , The conflict caused by occasionally accessing random port 20 and bus 30 in violation of the two types of operations in FIG. 1 It can be solved θ. However, the system 1 of 囷 3 implies another problem, that is, the memory space of the video random access memory 40 cannot be used very efficiently. The following example will illustrate this One problem. Here, consider the example where the resolution of Dengmu 12 is 900 selection lines and i 152 pixels on each trace line. The pixels on each selection line of the display screen are sequentially marked as 〇 , 1, ... 1151 〇 and each selected line is sequentially marked as i, .. 9000. A memory array composed of 256KM video random access memory is used to store a frame The format of the 900 * 1152 pixel data is shown in the solid choke. The memory space of 4A is engraved into two memory banks (Bank), which are respectively marked as memory bank 1 and memory bank 2. Each memory group contains four memory arrays. The memory arrays in memory group 1 are labeled VRAM0, VRAM1, VRAM2, and VRAM3. Similarly, the memory arrays in memory group 2 are also marked as VRAMO, VRAM1, VRAM2, and VRAM. Each memory array is 29 * 29 The significance is that it has 512 columns and each column has 512 row positions. Each row position of each column can have 210339 Λ 6 Π 6 printed by cooperation with the CX Industrial Consumers of the Central Bureau of the Ministry of Economic Affairs. V. Description of the invention () Put data of one pixel. In Fig. 4A, 512 rows on each memory array are marked as 0, 1, 511. In this memory arrangement, video random access Each column on the memory VRAMO, VRAM1, VRAM2 and VRAM3 is used to store the pixel data in each scan line on the display. Also in the 4A, the 512 row positions on each memory array are Marked as 0, 1,... 511 〇 Chewi twelve pixels on the selected line 1 on the trace line 〇, 1, ... 1151, is stored in the circle 4A memory skull array of its arrangement It is as follows, every fourth pixel starting from 0, that is, showing the 0,4,8 on the scan line i of the twilight frame ---- 1148 pixels occupy the first memory of the memory group 1 The row position of column 0 of volume array VRAM0 is 0, l, .. 287 and every fourth pixel starting from l is displayed on the first, fifth, 9th, ____ 1 of scan line 1 The 149 pixel dots occupy the row positions 0, 1, ---- 287 of the second memory array VRAM1 of the memory group 1 in column 0. Similarly, the fourth pixel starting from 2 is the second, 6,6,10, ... 1150 pixels on the scan edge 1 of the display screen frame occupying the third memory array of memory group 1. The row position of column 0 of VRAM2 is 0, 1 .... 287. Finally, it shows that the scan line of the fluorescent frame is on the 3rd, 7th, U ----- 1151 pixels occupy the row position 0,1, column 0 of the fourth memory array VRAM3 of the memory group 1 ... 287 on the same arrangement method, showing that the first, second, and fourth memory arrays on the scan line 2 of the firefly field frame occupied the first memory array VRAM of memory group 1. The row position of column 1 is 0, 1,... 287. On the other hand, the 1st, 5th, 9th, ... 1149 pixels on the scanning line 2 of the display frame of the screen display occupy the row position 0,1, column 1 of the second memory array VRAM1 of the memory group 1. . 287, the rest are all in this way · Line · This "Zhang Scale Xiao uses China National Standards (CNS) T4 specifications (210x297 public 81. 2. 20,000 V. Invention description () push. Therefore, the display shows twilight The pixel data on scan lines 1, ... 512 of the axis respectively occupy the row positions of columns 0, 1,... 511 of each memory array VRAMO, VRAM1, VRAM2, VRAM3 of memory dice group 1. , 1,... _287 on the display and the scan line 513, 514,... 900 of the pixel data on the display screen are the same as the arrangement method of the memory group 1, which respectively occupy each of the memory group 2 Memory arrays VRAMO, VRAM1, VRAM2, VRAM3 Column 0,1, ... 387, row position 0,1.287. For example, display the pixel data on the scan line 513 of the screen frame is stored in the memory Each memory array VRAMO, VRAM1, VRAM2, VRAM3 of the group 2 is listed on the first row. The pixel is the first memory array VRAM0 stored in the memory group 2 like The row position in the column is 0,1. .287, the 1,5,9__1149 pixels are stored in the row position 0,1, of column 0 of the second memory array VRAM1 of the memory group 2. .... 287, etc. As such, arranging the pixel data in this way in 囡 4A, there will be 50.6% of the space in the video random access memory that is not used to the memory of 4A. The process of transferring the pixel data in the volume to Flicker 12 in Figure 3 is as follows. When the Flicker display is scanning 1, the memory group 1 is divided into each memory array VRAM0, VRAM1, VRAM2 during the vertical blanking period, The data in row 0 of VRAM3 is transferred to the sequential access memory 46 (field 2) by a read row data transfer operation. Then, the data on the sequential access memory 46 is changed from position 0,1, _ .287 According to the bit-by-bit format, the data is transferred to the screen through the sequential access and the horizontal blanking period after the scan line 1 is displayed on the video display device. 〇, the data in row 1 of VKAM1, VRAM2, VRAM3 is also transferred to the sequential access memory 46 (囷 2) by a row reading data transfer operation So stored in Xuan 218338 Λ 6 1 \ 6 V. Description of invention The Ministry of Economic Affairs 兮 央 桴 半 and employee consumption 銆 · Cooperative printed order access memory 46 (囷 2) in the Ο, 1,... 287 position The data is subsequently transferred to the screen in sequence to update the second scan line on the monitor screen. Then, the trace lines 3, 4,... 512 of the monitor screen are also updated in this way. Therefore, it is processed in this way until the scanning line 513 of the fluorescent display must be updated. At this point, the data in the rows of each memory array VRAMO, VKAM1, VRAM2, VRAM3 of the memory group 2 is read by reading The row data transfer operation is transferred to its sequential access memory 46 (囷 2), and during the subsequent display period from the position 0 ,; L ,. The display scan lines 514, 515, ... 900 are also updated in the same way as above. On the other hand, if the video random access memory has the ability to split row Trausfter Operation, Then the pixel data can be stored in the memory array using a more special arrangement method. A video random access memory 60 with the ability to divide and transfer is randomly selected in the Min 5 video. The access memory 60 includes a memory array, that is, dynamic random access memory 62, which in the example has 512 columns and fl2 rows. The row position is marked at the top of Gate 5. The video random access memory 60 includes a random access port 64, by which pixel data can be stored in the dynamic random access memory 62. Video Random Access Memory 60 to a spread order with unique transfer capability; (Fu 65〇 Therefore, the standby sequence 65 can perform traditional read data conversion operations and split transfer operations. In operation, the access sequence is still in order. The action of 66 is the same as-single 1 shift ^ register unit. The addressing method of any row in the dynamic memory memory number 62 is to add the Tv-row address to the complex Address register 127 to complete. This paper-shaped + class national standard (CNS) «M specifications (210x297 public phantom S1- 2. 20,000 (please read the back and pay attention to Bian Xiang Sun hard to write wooden pages) installation · order-line, V. Description of the invention () The transfer gates 67 and 68 are simultaneously sent to enable the addressing of a row. 2 The entire row of 51 pixel data can be transferred to the sequential access memory 60. The pixel data is The sequential access memory 66 starts from the row position 〇 and synchronizes with the sequential counter 74 to sequentially send out through the sequential input and output port 73. The sent pixel data is displayed on the signal line 75. The sequential counting device 74 The function 60 is the same as the above-mentioned method in that it sequentially refers to each row position in the sequential access memory 62 , In order to send the data pointed to that position to the input and output 73. On the column transfer operation, the sequential access memory 66 is divided into two halves 66A and 66B. The lower column 66A contains the bit position Printed as 〇, χ ......... 225 Ministry of Economic Affairs Central Standards Bureau β 工 消 t Cooperative, and the first half row 66B contains the bit positions of 256, 257,... 511〇 in the example of the branch transfer , Only one of the transfer gates 67 and 6S will be enabled so that only the video random access memory hip 6 is the upper half row or lower half row of the row addressed by the row address register 127 Is transferred, and it is also transferred to the upper half or lower half of the sequential access memory 66. The branch transfer operation utilizes the index index (Tap) that is created in the transfer control delay circuit 71 (Tap P〇iuter) assisted to complete. When a separate transfer cycle is initiated from S, in the sequential access memory 66 is referenced by the index (that is, the upper half or lower half of the column) will refer to the content of the half column by The row address register 127 of the dynamic random access memory ya 62 is relative to the half row of data Instead, it is worth noting that the sequential access memory is regarded as a different shift register unit in this operation, so when the data is read out sequentially from half of the rows, the new The data can be transferred to the other half of the row without disturbing the action of the half row that is outputting the data in sequence. Another index is provided by the outside world (given by the outside world during the split transfer cycle). By Germany 81.2 . 20,000 (please read the "5" /. T 意 事 ## difficulty writing wooden pages first). The size of the paper is based on the Chinese η home rubbing (CNS) V4 specification (210x29 · / public;! T) 219339 A 6 l \ 6 V. Description of invention () The TMS44C251 produced by the State Instrument Company of the Central Standards Bureau of the Ministry of Shu, 51. The TMS44C251 produced by the State Instrument Company is an example of a video random access memory hip 60 with a transfer capability. Like the video random access memory 40 of FIG. 3, the sequence counter 74 has an input for receiving the starting position indicator when the sequential access memory 66 is sequentially output. With this index, the sequential access memory 66 will The pixel data can be sequentially moved out of the position described by this indicator. Therefore, the sequential output operation of the sequential access memory 66 can be controlled until some pixel data is not read. The serial input and output control circuit 76 that must be described in the Gu5 is also subject to enemies. This line accepts an input signal, labeled SE, which is used to control the enable or suppression of the input and output line 73. Therefore, the sequential output of the video random access memory 60 can be selectively turned on and off. 5B is shown when using the 256κ * 4 video random access memory 60 (囷 6) which can perform the column transfer operation. , A display with a resolution of usztQOO, a special arrangement structure where the pixel data of each scan line is stored in a memory array. In this example, only one memory group consisting of 4 memory arrays is used. When used, they are marked as VRAM0, VRAM1 'VRAM2 and VRAM3. As mentioned above, the scan lines on the display screen are marked as 1, 2, ... 900' and the line position on each scan line is marked as 〇, 1 ----- 1151 〇 The columns in the video random access memory are marked as ○, 1, .511 'and the row position on each column is marked as 〇 > 1 ,. . 511 ○ The columns on each memory array VRAMO, VRAM1, VRAM2, VRAM3 are scored into two halves. The lower half of the row on each array, that is, the position at 〇, 1’255 is used to store and display the odd-numbered scan lines of the glowing twilight ’.

Ministry of Economic Affairs Central Standards and β Industry Consumer Cooperation Du Yin 3i 21SS39 A fi ________H6___ V. Description of invention () 1024 pixel data. The upper half of the column, that is, located at 256, 257, ... The si position is used to store the first 1024 pixel data displayed on the even-numbered selective trace of Yingmu. The storage method of pixel data is now described as follows . The data of the first 1024 pixels on the display of Twilight's scan line 1 are stored in the memory array VRAM〇, VRAM1, VRAM2, VRAM3, column 0, row position 0, 2, ... 255. As mentioned earlier, every fourth pixel starting from 0, that is, the 〇, 4, 8, ... 1〇2〇 pixels are stored in the first memory array VRAM0 row 〇 Location 〇, 1 ----- 255. Similarly, every fourth pixel starting from 1, that is, the first, fifth, ninth, iOZl pixel is stored in the row 0 of the second memory hip array VRAM1. ... 255. And the fourth pixel starting from 2, namely 2, 6, 10, ... i 〇2 2 pixels are stored in the third memory array VRAM2 row 0 row position, 1, 255. Finally, every fourth pixel starting from 3, that is, the 3rd, 7th, and 11th, 1024 pixels are stored in the row 0 of the fourth memory array VRAM3 column 0, 1, ... 255. The rest of the odd scan lines 3,5, ... that display 2048 are ... The first 1024 image data on the 899 are also the same as the arrangement of the selected trace 1 and are placed in four memory arrays VRAMO, VRAM1, VRAM2, The VRAM3 line position is 0,1, .. • 255. In other words, the first 1024 pixels of the odd scan lines occupy the four memory arrays VRAMO, VRAM1, VRAM2, and VRAM3, columns 0, 1, ____ 449, the lower half column position. Display the last 128 pixel data of its odd scan lines on the screen, that is, the 1024th, 1025th, ---- 1151th pixel is stored in the lower part of the memory array VRAM0, VRAM1, VRAM2, VRAM3 511 , 510, ____454 (please read the precautions and fill in the 7Ϊ page first) Binding-Thread · Line · This paper is used in the standard (S) standard (CNS) specifications (210x297 public goods) 81. 2. 2〇 (〇 () q 210239 Λ (i Η 6 Printed by the Employee Consumer Cooperative of the Bureau of Standards and Economics of the Ministry of Economic Affairs. Fifth, the description of invention () in the first half. Shows the first scanning line No. 1024, 1028 on the screen , ... 1148 pixels are stored on the first memory array VRAM0, column 511, row position 256, 257, ... 289. The first scan line on the display screen is displayed on the first 1025, 1029 .... 1149 pixels are stored in the row position 256, 257, ---- 289 of column 511 of the second memory array VRAM1. The 1026 and 1030 of the first scan line on the display screen are displayed. , ... 1150 pixels are stored in row 511, row 256, 257, ... 289 of column 511 of the third memory array VRAM2. Finally, Yen shows the first scanning line 1027, 1031 of Yingmu ,: 1151 pixels It is stored in the row position 256, 257,... 289 of the column 511 of the fourth memory array VRAM3. In the same way, the data of the last 128 pixels of the third scan line on the display screen is displayed. It is stored in the row position of 32 consecutive pixels after the last 128 pixels of the first selection line, that is, the row position 290, 2911 ... 321. Therefore, the selection line 1, 3, 5, on the display screen is displayed. The last 128 pixels of 7, 9, 11, 13, and 15 are stored in the upper half of the row 511 of the memory array VRAMO, VRAM1, VRAM2, VRAM3. The last 128 pixels of 21, 23, 25, 27, 29, 31 are stored in the upper half of the row 510 of the memory array VRAMO, VRAM1, VRAM2, VRAM3. Therefore, according to this arrangement, the display screen The 128 pixels after each odd scan line on the twilight are stored in the column 511 of the memory arrays VRAMO, VRAM1, VRAM2, and VRAM3 into the column 454, and only the upper half of the row position is used until the display screen is displayed. The storage method of the pixel data on the even-numbered scanning line on Mushang will be described as follows. The pixel points 0, 1, ... 1023 of the display on the scanning line on the display are displayed (Please read the note back and grandchild Bian write code page) This paper side with the Chinese national standard scale Bi (CHS) T4 specifications (210x297 male dragon) S1. 2. 20,000 219339

V. Description of the invention () The first line selection method of the same display screen is stored in the four memory number arrays VRAMO, VRAMl, VRAM2, VRAM3. The row position 256, 257, ·· 511 in the journal 〇. In other words, the 0,4,8, ---- 1020 pixels on the display scan line 2 are stored in the row position 256, 257, ____ 511 of the first memory array VRAMO. The first, fifth, ninth, ... on the display trace line 2 · 1021 pixels are stored in the row position 256, 257, ____511 of the second memory array VRAM1 column 〇. The 2,6,10 pixels on the display screen selection trace 2 are stored at the row positions 256,257, ... 511 of the third memory array VRAM2 column. Finally, The 3,7,11, ... 1023 pixels on the scan line 2 of the Dengmu display are stored in the row positions 256, 257, ... 511 of column 0 of the fourth memory array VRAM3. Therefore, in the same way, the first 1024 pixels of the even scan lines 2, 4, 6, ·. 900 on Yingmu are displayed in the rows of the four memory arrays VRAMO, VRAM1, VRAM2, VRAM3. On positions 256, 257, ____ 511. In other words, the first 1024 pixels of the even-numbered scan lines occupy the columns of the four memory arrays VRAMO, VRAM1, VRAM2, and VRAM3. The position of the upper half column of i ....... 499 is displayed. The data of the last 128 pixels of its even scan lines on Yingmu, namely the 1024th, 1025th, and 1151st pixels are stored in the lower part of the memory array VRam〇, VRAM1, VRAM2, VRAM3 511 , 510 ..... 454 in the lower half. The 1024, 11028, ---- 1148 pixels of the second scan line on the display screen are stored in the first memory array VRAM0. The test department is accurate and the employee consumer cooperative printed 511. Line position 〇, 1, ---- 31 on 〇 and display the second scan line on the image 1025, 1029, ... 1149 pixels are stored in the second memory 51 2. 20 , 〇〇〇 paper »Standard use in a S family standard (CNS) T4 specifications (210x297 public foot) Λ 6 Π Γ» ^ 13339 V. Description of the invention () Row position of column 511 of the body array VRAM1 ο, 1. .... 31 on. On the display screen, the 10th, 25th, and 10th of the second stroke line on the display screen.... 1149 pixels are stored in the row position of the column 511 of the second memory array VRAM1. 1 ____31 is displayed separately. The 1026, 1030, ... 1150 pixels of the second selected line on the screen are stored at the row position of the column 511 of the third memory array VRAM2 ° »1 ... 31 finally. The 1027, 1031,-1151 pixels of the second scan line on the second display of Ying Shiying were stored in the row position of the column 511 of the fourth memory array VRAM3. In the same way, the data of the last 128 pixels of the fourth selected line on Yong Shi Ying Mu is stored in the row position of 32 rows after the last 128 pixels of the second scan line, that is, the row Positions 32, 33,... _ 63 on 〇 Therefore, the last 128 pixels of the scan lines 2, 4, 6, 8, 8, 10, 12, 14, 16 on the display screen are placed on the memory array In the lower half of the column 511 of VRAMO, VRAM1, VRAM2, VRAM3. In addition, it is shown that the last 128 pixels of the 18,20,22,24,26,28,30,32 traces on the screen are stored in the memory array VRAM〇, VRAM1, VRAM1 'VRAM2, VRAM3 column 510 In the lower half. Therefore, according to this arrangement, it is shown that 128 pixels after each even scan line on the board are stored in the column 511 of the memory array VRAMO, VRAM1, VRAM2, VRAM3 to the column 454, and only these columns are used Of the lower half of the row. The screen update operation is an example that differs from the previous example 4A. For the pixel data of the display line 1 of the display screen, a branch transfer operation is performed to transfer the dynamic random access memory 6 2 (囷 5) The lower half of the row 0 is transferred into the sequential access memory 66 (圏 5). Therefore, after this transfer operation, the lower half of the sequential access memory 66 (囏 5) is stored and owned_this paper In the scale border, "ϋ Sample Standard (CNS)> M Specification (2〗 0x29 · / Male; a;) ——————- 81. 2. 20,000 Pack ·,? Τ- line. Jing Shu The Ministry of Economic Affairs and Standardization of β-Works & Co .; Co. Du Printed 2ieas9 Λ (ί η (ί The Ministry of Economic Affairs of the Ministry of Economic Affairs and Industry Bureau A Co-operation of Co., Ltd. Du Printed ¾. Fifth, the description of the invention () before the scan line 1 1024 pixel data 0 When the pixel data in this half row is sequentially output from the serial port, another branch transfer operation is performed to store the row 511 of dynamic random access memory 6 2 (囷 5) The pixel data of the upper half of the row is transferred into the sequential access memory 66 (囷 5). In this way, the sequential access memory contains the last 128 pixel data of the scan line 1. Therefore, the following After the pixel data of the row is output by the sequential access memory 66 (囷 5), the sequential counter index can be set to point to the starting position of the last 128 pixel data of the scanning line 1 in the sequential access memory 66 The last 128 pixel data of the scan line 1 on the display screen is output from the sequential port-sequentially. After displaying the trace line 1 on the display screen of the display screen, a horizontal speed occurs without a cycle. At this time, the dynamic random storage The pixel data of the upper half of the row 0 of the memory 62 (囫 5) (this position contains the data of the first 1024 pixels of the scan line 2 showing the twilight) is transferred to the sequential access by the row transfer operation In the upper half of the memory 66 (囷 5), the sequential counter index is set to the first pixel position of the pixel data in the upper half of the row, and then the memory is sequentially accessed from this address sequentially (囷 5) Output through the serial port. When this scan line pixel data is sequentially output in the upper half of the sequential access memory, a branch transfer operation is performed to transfer the dynamic random access memory 62 (囷 5 ) Pixels in the lower half of column 511 Move to the sequential access memory 66 (Solid 5), so the sequential access memory contains the last 12 8 data of the display screen scan line 2. Once again, at the top of the display screen scan line £ After the 1024 pixel data is moved out, the sequential counter index is set to point to the starting position of the last 128 pixel data of the selected trace 2 in the sequential access memory 66. Then, the last 128 of the scan line 2 The data is moved out in sequence (please wli? Pay attention to the apples and then hang out the wooden pages). Install, line, and use the Chinese National Standards (CNS) V4 regulations (210X297) for the paper size. 81. 2 . 20,000 V. Description of the invention () ο This process is to repeat the operation continuously so that all the scan lines of the display are very clear. The video random access memory used according to the 5B arrangement Body 60 (囷 6) does not waste space. However, the new operations shown in the history of Teng Mu are quite complicated. When the display has an odd number of unfolds or its horizontal drunk resolution is not divisible by 32, its complexity also increases. For the aforementioned reasons, the purpose of the present invention is to provide a display system so that it can more fully and efficiently use memory resources. Another object of the present invention is to provide a video display system, the architecture of which will be unimpeded With regard to the resolution of the display used, the further object of the present invention is to provide a video display system which can use any resolution of resolution and will not be accompanied by a more complicated circuit to complete the image update 〇 Highlights of the present invention: The present invention is applied to a video headset system, which can effectively use the space of the display memory of the fluorescent display and its strategy is to use the resolution of the fluorescent display without change. In other words, it can be used for display screens of various resolutions. The display system of the present invention utilizes a special type of video random access memory, which can perform a so-called split transfer operation. In the split transfer operation, any half of the data in the video random access memory skeleton row can be transferred to the sequential access memory, and it will not be taken to the # sequential access memory ship The operation of the other half of the row of data output on the order of the order Λ 6 Π 6 ^ 19339 V. Description of the invention () This type of video random access memory sequential access memory can be regarded as composed of two half rows = Success, and it has an index to indicate which half of the two halves. In the action of split transfer, the dynamic random access memory in the video random access memory is relative to the index The referred half-row data is transferred to the sequential access memory relative to the half-row pointed to by the retrieval index. When such video random access memory is used, it can now transfer The pixel data on each scanning line in the display is stored in the dynamic random access memory on the video random access memory in a manner that one scanning line is continuously followed by another scanning line. Once again, 4 video random access memories are used, and the data at the pixels 0,4,8, ____ are stored in the first video random access memory; the pixels are at 15,9, ____The data at the location is placed in the second video random access memory ... etc. 〇So 'the first and all other video random access memory all the storage space can be filled Used in portions. For example, a screen display device has 128 scan edges (the standard is 1,2 ----- 1280) and each scan line has 1,600 pixels (marked as 0, 1, · · 1599). At the time, the pixel at the position of 0'4,8, ... 1596 on the scan line is stored in the row position of the dynamic random access memory column in the first memory array. ___ 399. The pixels on the scanning line 2 of the fluorescent display can be continuously stored in the remaining unused space in row 0 and the dynamic random access memory row 1 in the first memory array. In other words, the pixels on the scanning line 2 of the fluorescent display at positions 0, 4, 8, ... 444 are stored in the first memory array row 0 of 400, ---- 511 Line position. The scanning line of the fluorescent display is 2 copies of the paper, and the standard is used in the B B & H standard (CNS) T4 specification (210X297 g *) ......................... .... ^ ..... 玎 ·· f Please read it back and forth .- < .- > ± Issue ¾ and then shingle the shingle) Ministry of Economic Affairs Bureau of Standards κχ 工 消 作 合作 DU Printed 81. 2. 20,000 Λ 6 η β 219339 5. Description of the invention () The data of the pixels located at 448,452, ---- 1596 are stored in the dynamic random access memory of the first memory array Column 1, 〇, 2 8 7 row position 〇 and display the pixel data on the twilight scan line 3, is placed in the first memory array row 1 288 ---- -511 row The position and the row position of 0 to 275 in column 2 and the pixel data on the remaining scan lines are also arranged in this way. The strategy for storing pixel data in this way is called the linear address arrangement structure of birds 0Comparing linear address arrangement with other strategies for storing pixel data, it has the advantage of not wasting any memory space on the video random access memory. In the display system of the present invention, the display memory Sister's update action This is done through a random access port on the video random access memory. The update operation is performed by a sequential port with split transfer capability. In the split transfer action, the video random access memory One half of the data in the addressed row is transferred to its location in the sequential access memory relative to the half. For example, if a video random access memory has 512 row positions for storing pixel data and is labeled as 0, i ... 511, and the sequential access memory also has 512 positions and labeled For ο,〗,... _511 〇 For one-way transfer, if you want to transfer the data in the lower half of the video random access memory, it will be located at Ο, 1 ... 255 The pixel data on the image is transferred to the sequential access memory at 0, 1, ... 255. Similarly, the one-line transfer is to transfer the data in the upper half of the video random access memory. That is to transfer the pixel data at the position of 256,25 B ..... 511 | The sequential access memory is located at the position of 256,257, ---- 511. Ministry ί quasi-consumption system This standard is used in the national standard (CNS) T4 regulation (210x297 g; it)

Outfit-line-81. 2. 20,000 Λ β Μ 6

91 QO OQ 5. Description of the invention () The display system of the present invention includes a unique update controller. This update controller has the first counter, which is used to count and store the memory in sequential access. The location of valid pixel data or the number of pixels that have been used in the memory is taken sequentially. The second counter is used to count the row position on the dynamic random access memory of the video random access memory. The first counter sets its initial value island at the end of the vertical return interval. The popular guanidines are counted by frame and can be up to the total number of pixels in a row of video random access memory. For example, the sequential time eye is synchronized to the sequential time eye of the servo-to-video random access memory. The second counter is at least also set at the end of the vertical return interval and the initial value is 0. The first counter is Normal counting is at the lower half of its counting pitch circle; in other words, before the midpoint of its counting pitch plane has been reached or not exceeded, the second counter is incremented once. For example, for a 512 * 512 video random access memory, the second counter is incremented every time the first counter counts to 127. In addition, the controller has an index generator for alternately pointing to sequential storage Take the top half or bottom half of the memory. When the first counter counts positively in the lower half of its count section, the index is triggered to refer to the upper half of the access memory. Furthermore, when the first counter counts positively in the upper half of its count, the index is triggered to access the lower half of the memory sequentially. In order to complete these actions, the bit of the highest position of the first counter is inverted, and the result is the input of the index address of the random access memory of the persuasion video, to create a random access random access memory. Introductory index of the body 〇61. 2. 20,000 (please read the back-to-back precautions first and then write the wood π hard). Installed and printed. Printed by the β-Consumer Cooperative Society of the Central Standards Bureau of the Ministry of Economic Affairs ^ 19939 V. After the description of the invention The controller includes at least one update request generator for starting a transfer period. The update request is generated between the vertical display selection period. The device initiates a branch transfer action to transfer the video randomized for the second counter. Access the pixel data of each half of the row of memory. When the first counter counts positively, the pixel data of each row on the random access memory of the video included in the sequential access memory of its count is high. At half time, a branch transfer operation occurs to convert the pixel data of the lower half of the column to which the second counter is addressed in the video random access memory. Similarly, when the first counter counts positively In the count video random access memory, each of the low-half rows of pixel data included in the broadcast access memory, a one-text branch transfer operation occurs to transfer the video random access memory. The pixel data in the upper half of the row addressed by the second counter in the example. For example, for a 512 * 512 recognized random access memory, when the first counter counts to 2560, one point is transferred to the transfer action. The pixel data of the lower half of the column addressed (ie, the row position is at 〇, i, 2.... 255). When the first counter counts to 512, the column transfer action transfers the column addressed to The higher half column of pixel data (that is, the row position is at 256511). In addition, when the update request generator is heard in the vertical return area, it also generates at least a request signal to start a read column transfer pass period, making the video random The pixel information in the first row of the dynamic random access memory of the access memory is sufficient to be transferred into the memory of the sequential access memory (please read the back and forth precautions #code writing wooden page first)装 · Order_ Line · Ministry of Economic Affairs Bureau is: Gongxiao 1Ϊ-Cooperative seal 31 8]. 2, 20,000 219339 Λ 6 Μ 6 V. Description of invention () Brief description of the closed style: Park 1 shows a traditional full-image selective scanning head display system and Its display memory is implemented using dynamic random access memory. Circle 2 shows a video random access memory (VRam) with sequential ports. Figure 3 shows a traditional hologram scan. The display system's display memory is implemented using the video 2 random access memory of 囷 2; 4A; a special pixel data arrangement structure using the video 2 random access memory of 雖 2 is illustrated. 5 shows a video random access memory with split transfer capability. Circuit 5B illustrates a special pixel data arrangement structure using the video random access memory of FIG. 5. The display shown in FIG. 6 is the root cause. An example of a holographic selective display system invented and embodied. Wei 7 illustrates the arrangement structure of pixel data in the video random access memory in FIG. 6. Wei 8 shows a complete The address generator circuit in the display system shown in Figure 9 shows a user The index generator circuit is in the address generator circuit of Fig. 8. Gu 10 illustrates the sequence transfer and read sequence transfer operations on the video random access memory of Cell 6 ® 11 illustrates the pixel data arrangement structure of a system containing two sets of video random access memory. Field 12 shows an exchange line used in the memory group of the address generator circuit of the 囷 b 〇61 · 2. 20,000 0 (please read f and lg.-Note_if wooden page first) Printed by the Ministry of Economic Affairs, Central Standard Workers' Union, Cooperative Society 219339 Λ 6 Η6 Printed by the Ministry of Economic Affairs, Pyongyang Purchasing Bureau β Industrial Consumer Cooperatives. Fifth, Invention Description () 車 13 depicts a modified line of address counters to enable the invention It can also be used in the case of interlaced scanning (Interlaced scanning) and two display buffers (Double Buffer). Detailed description of the invention: Fig. 6 shows an example of a holographic scanning neck display system 10 " embodied in the light of the invention. The difference between the system 10 in the cell 6 and the system 10 in the cell 3 is that the frame Butter in the system 10 is implemented using a video with separate transfer capabilities to access the memory 60 with money Instead of using the video random access memory 40 in the non-sequential transfer capability 3, in addition to the system 6 in the 6 system, the system includes a refresh controller circuit 700 in the system 6 in the 6 In ", the address of the screen update action is generated by the line of the Twilight update controller 70, and is sent to the multiplexer 18 via the bus 79. The correct Twilight update is completed, and the Twilight update controller 70 sends an update request signal to the memory controller circuit 7 via the line 6. In contrast, in the system 10 'of the loop 3, the address for the update operation of the fluorescent light is generated by the graphics controller 22. In the system 10 " of Wai 6, the update operation of the display memory enters the video random access memory 60 by writing data through the random access port 64 and the pixel data update operation reads the pixel data through the sequential port 65 〇As seen above, the use of video random access memory 60 with split transfer capability and the update controller circuit 70 enables the display system 10 of "囷 6" to be used very efficiently. The memory of the random access memory 60 is elegant, and it also makes the system 10's "Flicker Update" action unrelated to the resolution of the Flicker 12 used in the system.

T This paper standard is used in the 8 national standard iMCNS) TM specifications (210x29 · / public; «:) 81. 2. 20,000 219339 Λ fi Π 6 printed by the Ministry of Economic Affairs 4 quasi-bureau ex Gongxiao 1Ϊ 'cooperative

5. Description of the invention () When using a video random access memory capable of performing separate transfer operations, the pixel data in the video random access memory can be stored in a linear address arrangement. The arrangement in this way is depicted in Figure 7. In the structure described in this article, the video random access memory 60 which can provide serial transfer using solid 5 is used. The video random access memory 60 The row is marked as 〇, work, •, 511〇 and stored in the video random access memory 60 is each row or scan line on a fluorescent display, and it is marked as 1, 2, .._ 〇 As depicted in Fig. 7, the pixel data on each scan line is placed in a manner similar to the previous scan line. When the pixel data on the scanning line cannot be stored in the entire width of the video random access memory 60, the part which is not enough to store is stored in the next scanning line. For example, the video random access memory is the 60th row. It stores the pixel data of the first scan line and the first part of scan line 2 on the fluorescent display. The remaining pixel data on the trace line 2 is not stored. Placed in row 1 of video random access memory 60. In addition, immediately after the remaining part of the scan line 2 is the pixel data on the scan line 3, and the placement of the pixel data on the remaining scan lines is the same. The following will be described in detail 8- The function of the flash update controller circuit 70 is 0. When the video random access memory 60 (囷 6) stores data in a linear address mode, this controller is used to assist in displaying the update action of the flash video. The device contains a "Dirty Counter" (Dirty Counter) that has been used, which has an output terminal 102, a time input 104 and a reset input 106. The reset input 106 violates the VDISP signal via a line 108. Therefore, " the used pixel counter " 100 is cleared during the vertical blanking interval (that is, reset to Lin 0). This VDISP will be discussed in more detail in the ensuing discussion (please read it first) Back to seven precautions and then write this page) Install & Line. The paper size is based on the Chinese 漸 楳 擳 (CNS) τ4 specifications (2) 〇χ297 public release) SJ. 2. 20,000 -24.BB3B V. Description of the invention () Μ 6 The printed signal is at least connected to the memory controller 7 (囷 6) in cooperation with the Ministry of Standards and Laboratories ’β-consumer cooperation to determine whether the _ split transfer or read transfer should be occur. The input glands of the time gland are connected by line 110 to a sequential time frame. This sequential time line is generated by the drawing controller 22 (閖 6), and it is synchronized with the video of the holographic scan CRT 12 (囷 6). Take the output of pixel data on the serial port of memory 60 (¾6). Therefore, the " pixel counter " 100 that has been used all the time is initialized to zero during the vertical blanking period, and increases in sequence with the advent of the eye as the sequential eyes appear during the vertical display period. And when it counts to the maximum line position included in the video random access memory 60 (囷 6), the " already used pixel counter " 100 returns to zero and has to be calculated again. For example, for a video random access memory 60 with 512 line positions, the " pixel counter used " 100 is counted from 0 to 5n and then returns to 0 again in order. Counting. The refresh controller 70 has at least one column address counter like the pixel counter " 100 which has been used. The column address counter 112 has a time gland input 114, a reset input 116 and an output 118. The reset input lie is connected to the VDISP signal at least via line 120. Therefore, the column address counter i 12 is reset (ie set to 0) during the vertical blanking interval and the output 118 reaches the address multiplexer 18 (fixed 6) via line 122 and line 79, so it can be This address is sent to the video random access memory 60 (囷 6). The time input 114 of the row address counter U2 is connected to a time generator circuit 125 via line 124. The time generator circuit 125 The purpose is to generate a time signal when the " pixel counter encountered " 100 positive value counts during the lower half of its counting factor. In the example, the time-eye generation line includes a combination line 140 and a register 130. The line is generated on line 24 (please read first-back to seven notes for writing a wooden page in the field) Install-line-this For paper size, use the Chinese National Standard (CNS) Ή specification (210X297 male dragon) S1. 2. 20,000 219339 Λ fi Μ 6 5. Description of the invention () When the Ministry of Economic Affairs is approved by the central government and the company is cooperating with the du printing The gland signal is connected to the Q output 128 of the register 130. The register 130 also has a momentary Saka input 132, which is connected to the broadcast sequence via line 2 34, β capture gland (SC) or other control signal. The device 130 also has a D input 136 connected to the first combined line 140 via line 138. The first combined circuit 140 is connected via line 142 to the " already used pixel counter, _JL00 output 1〇2. With the first combination circuit 140, when the pixel counter " 100〇 that has been used is positively counted in the lower half of its counting difficulty, then a lug is output to line 138— 夂. In the first combination circuit 140, you can use the ANJ) gate or the inverting gate to output the individual bits of the "counter pixel counter" that has been used or the results of the inverting must be ANDed with each other to achieve this. begging. For example, suppose that the condition for setting the register 130 is that when the " pixel counter that has been used all over " 100 counts to 127, in the first combination circuit 140, the lower seven The result of the inversion of the bit and the higher two bits can be ANDed with each other. This means that a logic 1 can be determined every time when the "counter has been used" · 100 counter Generated several times and only once 0 is between the vertical blanking period of the video, a favorite is to reset the register by resetting the register 135 through the line 121 servo into the register 130. Screen update control The device 170 has at least one update request generator circuit 170 for initiating a transfer period. The update request generator circuit 170 includes a second combination circuit 144, a register 150 and an OR gate 160. The interconnection of these components will now be described in detail as follows. The second combination circuit 144 is The line 146 is connected to the output terminal 102 of the used pixel counter " 100. The second combination line 144 is counted by the pixel counter " used to meet the lower half of its counting range And the upper half (please read the precautions on the outside to write wooden pages first) Binding · Order _ Line. This paper is used in the standard β B home «Rate (CNS) A 4 specifications (210X29 · / Public) S1 2. 20,000 213333 Printed by the Ministry of Economic Affairs of the Ministry of Education and printed by the CX Industrial Consumer Cooperatives. 5. The last position of the invention description () will be edited once for each output. For example, the second combination circuit 144 is used when ; The pixel counter that has been used " output count 1 when counting from 100 to 255 and 511. To meet this requirement, the implementation of the second combination circuit 144 will soon be " The pixel counter that has been used " 1 The lower 8 bits of 〇〇 are connected to each other by AND gate Reach of. This circuit will generate a pixel with the length of a time period when the pixel counter that has been used is counted to 255 or 511. The output of the second combined circuit 144 is via line 148 The D input 152 connected to the register 150. The register 150 has a Q output 154 and a momentary input 156. At this time, the input signal is connected to a signal time signal via the control line 134. With this arrangement In this way, when the pixel counter n 100 that has been used counts to 255 and 511, the second combination circuit 144 outputs a series 1 and stores it in the temporary storage 150. Otherwise, when the counter counts to another number, the temporary register 150 stores a selection display, and the temporary register 150 will delay the output of the second combined circuit 144. Therefore, when " the pixel counter that has been used, counts up to 256 and 0, a late 1 is generated by the output terminal of the register 150. As with the register 130, the reset signal is transmitted to the reset input 151 of the register 150 through the control line 121, and the register 15 is pushed to reset to the edit level 0 during the vertical blanking interval ○ The Q output 154 of the register 150 is servoed from the line 158 to an OR gate 160. The VR signal (vertical foldback signal) is input to the OR gate 160 via the line 166. The output of the OR gate is the update request signal. This signal is servoed to the memory controller line 7 via line 168 and line 6 for initiating a transfer operation cycle (a split transfer operation cycle or a read transfer operation cycle). (Please read first-note The content of the project is ergonomic wood sheets) The 5fc scale of the paper is used in China's sleepy quasi (CNS) Ή specification (2 丨 0X297 male dragon) 81. 2. 20,000 Λ (Ϊ Η 6 Beta Workers of the Ministry of Economic Affairs, Central Standards Bureau Cooperation Du Yinnu V. Description of the invention (). The firefly update address generator circuit 70 has at least one tap pointer generator circuit 172, and it is depicted in Fig. 9. In the example, The most significant bit of the used pixel counter " 100 (囷 8) is servoed to an inverter 188 through line 186. The output of inverter 188 is servoed to an AND idle 194 through line 190 〇This AND idle 194 accepts the VDISP signal as its other input signal at least through line 192. In the operation of drawing the indicator line 172, the highest position of the pixel calculator " 100 (囷 8) that has been used throughout Of the bits are sent into the outgoing index line 172 by line 186 and they are processed The result is sent from the output terminal 196 of the generator. In order, the output line 196 of the index generator is sent to the input terminal of the video random access memory 60 through the multiplexer 18 (¾6) , U is used as the index of demand in the transfer operation of the video random access memory 60 during the update operation of Yingmu. When " the used pixel counter " is a positive value counted in sequential access memory In the upper half of the pixel data in 66 (囷 5), the “" pixel counter that has been used, the bit charge at the highest position of i 〇〇 (圍 g) is set only to the edit 1 0. Therefore, the index is taken The value is based on whether the "used pixel counter" is positively counted in the upper half or lower half of the count, and the highest position bit is sent through the inverting gate. In the example, the index generator 172 is designed to capture a output from its output line 1963 to its output line 1963, which means that it refers to the lower half of the sequential access memory 66 (囷 5). When you want to refer to accessing the upper half of the memory 66 in sequence, what is the example? A filter is on its output line 196. This line 196 is the bit at the highest position of the index address. The remaining bits on the index address are always set to the index (please first Inter-back notes: fill in the wooden page) The standard of this paper uses the Chinese National Standard (CNS) Τ4 specification (210X297 Minister) 81. 2. 20,000 219389 A 6 Π 6 Ministry of Economic Affairs, Central Bureau of Economic Development, A Gongxiao & Co .; Print 5. Description of the invention () The VDISP signal is servoed to the AND gate 194 via line 192. Its use is to set the index to be edited when the vertical speed is not cycled. The purpose of this arrangement is when the read column is transferred. Occurring during the vertical encounter period, the index index address can be kept as late. The operation sequence of the index index between the entire vertical masking interval will now be described in more detail in the updated bits in the next 8-8 The operation procedure of the address generator circuit 70 is now described in FIG. 10 together. Figure 10 describes the relationship between certain video timing signals. First, a vertical blanking interval occurs on the VDISP signal. Therefore, " the used pixel counter · _100, the column address counter 112, and the registers 130, and 150 are reset to the later version. Next, still in the vertical blank period interval, a Miao Chong presents Jiang on the VR signal to initiate the vertical return of the electronic surplus in the fluorescent display. And at this time, it also intends to complete a Read Data Traversing action instead of a Split Row Traversing action. Therefore, by closing 16R, the update request generator can generate an update request. In addition, the VDISP signal as shown in Fig. 6 must also be connected to the memory control circuit 7 so that it can generate a good control timing to the control signal input terminal of the video random access memory 60 (囷 6) to indicate one The sequence of actions for the read column transfer sequence will occur instead of a sub-column transfer operation. Further, the index must be kept in the late sequence 0 more desirably during the read column transfer operation by the AND gate 194 in the surrounding 9 » The retrieval index is kept in the edit 0. The update request signal is then served to the memory controller circuit 7 (circle 6) in order to properly request that it must generate a refresh update operation period (as before). According to the state of the VDISP signal, at this time, the memory limb control li circuit 70 will trigger the sequence of the first-reading transfer action) (please read " 背 而 的 注解 # 锅 写 这 页） Standard (CNS) T4 specification (2) 0 × 297 g; ¢) S1. 2. 20,000 219 S39 Λ 6 Π 6 Printed by the β Bureau of Consumer Industry Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs V. Invention description () After the transfer operation , Dynamic random access in video random access memory (VRAM) (peripheral 5) The row in the memory 62. The entire row of pixel data is transferred into the backup access memory 66 (囲 5). After the vertical masking area, there is the Sakura signal on the HDISP signal. This is the electron gun in the display shown in the screen is scanning from top to bottom one by one line by line. The eye will be generated in a way that is in violation of these signals in sequence. When the video random access memory accepts this sequence of eyes, the pixel data will be taken from the memory 66 one by one 66 (囷 5 ) Move out. In addition, the "used pixel counter" "100〇 will also follow the eye of each #sequence. In this way, the" used pixel counter "100 It indicates that the pixel data in the sequential access memory 66 (圏 5) has been removed. Between " pixel counters that have been used all over " 100 are positive when counting a time in the lower half of it, the first combining circuit 140 generates an output of the edit i. This output is at the next eye The impulse is loaded into the scratchpad 130 when it arrives. As the state of the register 130 changes, the column address counter 112 changes from 0 to 10. Therefore, the column address currently accepted by Frame Buffer 60 (Lan 5) is the column 1. When the " pixel counter that has been used " 100 is counted to the last position of the lower half of the sequential access memory 66 (圊 5), the sequential access memory 66 is indicated ( The pixel data of the lower half of 5) has been removed from the meeting. At this point, the sequential access to the lower half of the memory 66 (囷 5) can load the pixel data contained in the lower half of the next row of the dynamic random access memory 雅 6 2 (Solid 5). When the pixel counter 100 that has been used has counted to this value, the first combination of the poor road 144 sends a filter 10. This output is for the next time (please read the back and seven notes Erguo writes wooden pages). Lines. The paper size is used in beta Η family standard JMCNS) TM specifications (2 丨 0x297 male dragon) 81. 2. 20,000

Λ 6 Π G 213939 V. Description of the invention () When it arrives, it is input into the register 150. The combination of the output value of the register 150 (now logic 1) and the VR signal gate generates a selection 1, which prints out an update request to the memory controller circuit 7 (sleepy 6). In addition, the VDISP signal shown in Fig. 6 is also connected to at least the memory controller line 7 (Sleep 6), and it indicates that the branch transfer operation should occur instead of the one-read row transfer operation. However, which half of the data needs to be transferred in a branch transfer operation depends on the address of the index index sent to the video random access memory. The highest bit of the pixel counter that has been used · 100 The current value is set 1 (that is, the pixel counter " 100 that has been used has been counted to 256), so the index generator circuit 172 (囷 9) generates an output of set 0. At this point, the index refers to the lower half of the sequential access memory 66 (solid 5), so it indicates that the column transfer operation should occur in the row that is dynamically addressed with the brown access memory 62 (Min 5) Lower half. Therefore, the pixel data of the lower half of row 1 of the dynamic random access memory 62 (囷 5) is transferred into the lower half of the sequential access memory 66 (FIG. 5). At the same time, the video access memory 66 (Fi 5) still continuously removes the pixel data stored in the upper half of it, that is, the pixel data of the upper half of the original dynamic random access memory row. Obviously, sequential access to the memory 66 (fixed 5) will remove all the pixel data located on the first scan line of the display screen 12 (around 6). At this point, the remaining pixel data of the sequential access memory 66 (囷 5) must also be sequentially removed, but these must be displayed on the second trace line of the display 12 (BJ6). However, Before removing the remaining data contained in the sequential access memory 66 (field 5), a horizontal masking interval will occur first. In this section, the electron gun in the display will be installed by the first article

219939 Λ 6 η 6 Central Standard of the Ministry of Economic Affairs and CX Gongxiaot Cooperative Du Printed 5. Description of the invention () The unfolded scanning line ® to the beginning of the second scanning line is between the horizontal blanking interval, in order The favor is suppressed so that no pixel data is moved out of the sequential access memory 66 (solid 5). Finally, the data in the sequential memory 66 (囷 5) is moved to the last position of its upper half ( That is, the last pixel of the dynamic random access memory row 0). In the illustration, for a 512 * 512 video random access memory 60 (圏 6), this is relative to the sequential access memory 66 (FIG. 5) The position of line 511 at the same time, &quot; the used pixel counter &quot; counts to 511. Therefore, the highest bit of &quot; the used pixel counter &quot; 100 is next At the same time when the sequential time (eye 9) is set to logic 00, at the same time, the second combination circuit 144 sends a selection 1 at this time, and it is stored in the temporary memory 150 at the same time as the next sequential eye. Scratchpad 150 and OR gate 160, and Dengmu update request generator 170 output a series 1 as before Generally, this update request signal is sent to the memory controller circuit 7 and a branch transfer operation is initiated. However, the row address counter still refers to row 1 of the video random access memory 6 (囷 6), so the row 1 Any half of the pixel data will be transferred to the sequential access memory 60 (囷 5). However, during this time, the index generator circuit 172 (circle 9) outputs a logic 1 (by virtue of the fact that the most significant bit of the pixel counter &quot; 100〇 being used is currently zero) ’ To the upper half of the list. Therefore, the column transfer operation shifts the pixel data of the upper half of the mobile random access memory row 1 into the upper half of the sequential access memory 66 (囷 5). At the same time, the pixel counter "100" that has been used returns to 0 for recounting, and the pixel data is also moved out of the lower half of the access memory. As mentioned earlier, the sequential access to the memory at this time is to include the paper standard and use the Chinese National Standard (CNS) T4 regulation (210x297 mm) 20,000 (Please read 3 * first and pay attention Matter #Cutting to write a wooden page) installed-line · 2133S9 Λ 6 Π 6 The Ministry of Economic Affairs 揮 央 桴 准 和 κχ 工 消 tv · Cooperative cooperative print ¾ V. Description of invention () The lower half of the dynamic random access memory row 1 Pixel data. Obviously, both of the aforementioned separate transfer operations will be repeated once when the &quot; pixel counter &quot; 100 encountered is counted to 255 and 5 lJL, respectively. Therefore, two column transfer operations will occur for each row. First, when #order access memory skeleton 66 (囷 5) starts to move out of the upper half of the pixel data, the video random access memory 60 (Solid 6) The lower half of the pixel data in the next row is transferred to the lower half of the sequential access memory 66 (囷 5). Then, when the sequential access memory 66 (囷 5) starts to move out For half-row pixel data, the upper half of the current row of video random access memory 60 (囷 6) is transferred to sequential access memory 66 (囷 5). The processing procedure is repeated repeatedly until all the scanning lines on the display screen are scanned. At this time, a vertical speed interval will appear in the VDISP signal again. The read column transfer operation will also occur in this area again. As such, the entire update process of Yingmu is repeatedly completed in accordance with this strategy. Now the topic described in the discussion topic 11 is transferred. A 11 ^ 244280 flexible screen display device 12 (囷 6) uses 256K * 4 video random access memory 雅 60 (囷 6) for the twilight pixel storage arrangement structure 20 is shown in the close The 0 pixel data in Gonggong are stored in four memory arrays, and are respectively marked as VRAO, VRM1, VRM2, and VRAM3. This arrangement method also uses the linear address arrangement structure as shown in FIG. 7. In this example In the middle, the total number of pixels of the fluorescent display 12 (due to 6) exceeds the number of positions contained in a memory array group. Therefore, as shown in FIG. 11, the memory arrays of the two groups must be used, marked as BANK1 and BANK2 〇So, in the last column 511 of Group 1, the pixel capital paper scale is used in "A Home Sample Standard (CNS) A 4 regulations (2 丨 0X297; a :) 20,000 (please first> 1? Contrary to the precautions, please fill out this page) Order-line, 5. The description of the invention () is the same as the part 0 of the first column of group 2. In other words, trace line 1, (please pay attention to the precautions before writing wooden pages) 2. The pixel data on 819 is placed in the memory array of group 1 in a linear arrangement in. The data of the first 256 pixels of the 820th scan line is also stored in at least the last row of group 1. After the 820th scan line, 1024 pixel data will be placed in the group 2 row. From then on, the scan edge 821 to 1024 pixel data is still continuously stored in the group 2 memory in a linear arrangement On the array. As mentioned above, the column address counter 112 (囷 8) is used to count and address the video to access the columns in the memory 60 (fixed 6). When using 256 * 4 video random access memory 60 to form a set of memory arrays, the row address counter 112 (fixed 8) only needs 9 bits. However, when two sets of memory arrays are used, 10 bits are required. At this time, the highest bit is used to select the correct memory array group, that is, group 1 or group 2. This can be sent by the 10th bit of the stele and the signal of its encounter This is done by means of the chip selection signal to the video random access memory 60 (囡 6) of each group. An example of a group selector circuit 12 is enclosed in the gate 12. Reference 12 now, a bank selector circuit (Bank Se tec tor) line 210 will be approved by the Central Ministry of Economic Affairs. Cooperative printing is described in more detail below. As shown in Figure 2, a modified address counter 212 is divided into two parts, the high position bit 212A and the low position bit 212B. The low-order bit 212B is used as previously described to address a row in the video random access memory 6 (閖 6). The high position bit 212A is servoed into the group selector circuit 21 by line 214. The high position bit 212A is input to a decoder 216 via line 214, and the solution is 81. 2. 20,000 paper "• Standard Free Use Chinese National Standardization (CNS) T4 Specification (210x297) 219339 Ministry of Economic Affairs Central Bureau of Accreditation Printed by the Negative Workers Cooperative Society 5. Description of the invention () The decoder bit 212A causes the binary obligate to enter a different type. Based on this, each single individual output line 218-1. .... 21β-Ν was convinced to the input enable line of the video random access memory 6 (囷 6) (marked as RAS in 囷 12) to enable a specific memory group Accept row address. For example, an address counter 212 has 13 bits and is designed to support 512 * 512 video random access memory, so it has four additional high-position bits 212A 〇These bits 212A can be used to select one of the 16 video random access memory groups to allow them to accept the row address. The completion of this strategy is to enter the high-order bits into a fresh In the encoder 216, each single individual output line after its obstruction, 218_2,... 21816, is relative to the group signal RAS [ I], RAS [2] ...... RAS [16] 〇When there are only two memory array groups, only one bit 212A is required. 〇Clearly, each group is not selected late The video random access memory hip 60 (囷 6) must not only inhibit it from accepting column address check-in, but also the output of the #sequence access memory in these memories should be suppressed at least 0 for this purpose A more complicated arrangement circuit is necessary to make sure that when the last row of pixel data of the group's sequential access memory has completed the sequential output, the sequential output of the group can be suppressed. Some repetitive circuits 250-1, ... 250-Ν are individually connected to a single detection line 218-1, ... 218-Ν, these circuits are ready to complete such work. Relative to each decoded output line 218-1, ... 218 is checked into line 251-1 ... 251-Ν, each group of lines 250-1 ... ... 250-Ν is designed to control the sequential output of each set of video random access memory 60 (Min 6). For example, for each set of lines 250-1, ... .250 paper size, use Zhongwei® Home Palm Standard (CNS) * P4 specifications (210X297 g; tt) 81. 2. 20,000 warp? ^ Ministry of Central Affairs Bureau sc Gongxiao <\ ·· Cooperative printed Λ 6 Π6 V. Description of invention () -N each has an output 248-1 ..... 248_Ν, that is, it is servoed to its related Sequentially enabled input (SE) of video random access memory 60 (solid 6) of a group. This SE input controls the sequential output of video random access memory 60 (closed 6) of each group. The operation of lines 251-1 and 251-2 will now be discussed below, from which it can be analogized to all lines winter 250-1, ... 250-N. The lowest position solution% is checked into an AND gate 226-1 via line 218-1. This output line 218-1 is relative to the first group of memory arrays, and when the first group of memory arrays is When it is late, this line is the output of Liner 1. This condition is the case when none of the bits in 212A is equal to 1. The output of the cascade circuit 222 is sent to the AND gate via line 224-1 The other input of 226-1. The combination circuit 222 ANDs all the bits of the "pixel counter that has been used" "100. Therefore, when the" pixel counter that has been used "counts to the last point of its count range, this The combination circuit outputs a selection 1 to line 224. In other words, when the sequential access memory 66 (¾ 5) has output to its last pixel data, line 224 outputs the selection 1 to 0. This is specific It is determined that when the sequential access memory 66 (Sleep 5) is output to the last pixel data, the AND gate 226-1 can only output a serial 10 circuit 250-1 with the second AND 228-1 combination circuit The inverse of the output of 222 is servoed to the input terminal of the AND gate 228-1 at least via the line 224-1. The other input terminal of the AND gate 228-1 is the Q detection 244-1 of the register 24 〇-1 by The return path is 234-1. Therefore, when the "used pixel counter &quot; 100 is not counted to the last pixel of the sequential access memory 66 (囷 5) and the register 240-1 has been set to the desired threshold, the gate 228 -1 only published a collection of 1 〇 (please read first. Read the back notes &amp; 肀 项 # pot qiao wood page) installation · line. This paper is sufficient for easy use in the s B family home (CHS) regulations tM210x297 male dragon) 81. 2. 20,000 218939 Λ (5 Π 6 Central Standard of the Ministry of Economic Affairs ^; cx industrial and consumer cooperation in cooperation with Du printed five. Invention description () Two AND idle outputs 226-1, 228-1 respectively Serve from lines 230-1 and 232-1 to an OR gate 236-1. When one of the two AND gates 226-1 and 228-1 outputs the edit 1, the OR gate outputs a edit 1 ⑽ The output of gate 236-i is servoed to D output 242-1 of register 240-1 via line 238-1. Temporary register 240-1 has a guanidine input 246.1 and a Q output 244-1. Q (inverted) output 245-1, and a set input 247-1. When guanidine input 244-1 is connected by line 252 to a sequential clock or other control signal. Therefore, the storage of temporary register 240-1 is Also synchronized with &quot; Already used pixel counter &quot; 10000Q The output 244-1 is input to the 228-Q through the recovery channel 2344. The output 245-1 is through the sequential performance of servoing to the group 1 via 248-1.) Except the register 240-1 has a setting In addition to the input 247-1, the remaining registers 240 -2, 240-3, ... 24〇-N are respectively a reset input 247-1,247-3, ... 247-N 〇 Line 250 The operation of -1 is now explained as follows. Initially, during the period of the vertical speed of the VDISp signal, the register 2504 is set to edit 1, and the remaining registers 250-2, ... 250-N are Both are reset to the edit 0. At this time, the quotient position bit 212A of the column address counter 212 is also reset to at least the edit 0. This means that the pixel data of the group 1 to be accessed (Tian 0 is therefore, After the vertical blanking period, the register 24 0-1 is set as the editing register and the remaining registers 240-2 ... 240_1 &lt; are reset to the register 0, and the register 240-1 will also be maintained at the output of Lin Ji 1. Therefore, SEU] is equivalent to Fan Ji 〇 [2], ..... SE [N] is equivalent to Lu Ji 1 〇SE [1] The sequential output of the memory array (囷 11) of the enablement group i, and during this period, the sequential output of the other groups of records is prohibited Able (disable) 〇 (please read the precautions to be filled out by Sun before filling this page). Binding-binding-line. This paper is used in the B country «quasi (CNS) T4 specification (2 丨 0x297 public; it) 81. 2. 20,000 21S939 Λ 6 W 6 Printed by the β-Work Consumers' Co-op of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention () As mentioned above, the column address counter 212 is output from the sequential access memory 66 (Min 5). The lower half of the pixel data of each row of random access memory 60 (囷 6) is incremented once. Therefore, when sequentially accessing the lower half of the last row of pixel data of the video random access memory 60 (囷 6) of the output group 1 of the memory 66 (fixed 5), the row address counter 212 It was swayed once. At this point, the low-order bit 212B of the row address is addressed to row 0 and the selection circuit for each group of memory is now selected to video random access memory 2 (Sleepy 11). Therefore, decode The device 216 outputs a selection 1 on line 2182, and the remaining unhardened lines 218-1, 218-3, 218-4, ... 218-N are output as a series. At this time, the sequential access memory also continuously outputs image data sequentially and the pixel data is sequentially output. When the sequential access memory 66 (囷 5) is sequentially detected to its last pixel data , &Quot; The count of pixels that have been used • _i〇〇 has also counted to the last point of its count. All the bits of the counter are now the value of Liner 2, which causes the combinational circuit 222 to output a Liner 10 in the AND gate 226-1, and a Liner 2 on line. Buckle up and line 218 -1 is a logic 0 input. Therefore, the AND gate 2264 is an output of the logic 0, and the result is servoed to the input terminal of the OR gate 2364 via the line 230-1. In the above, the inverting output of the combination circuit 222 (this value is equal to the editing 〇) and the Q output of the register 240-1 (the value is the editing υ is the two input values for this gate. 228-1 also outputs at least one filter 0 to the shutter 236 1. Therefore, the 0R gate 236-1 outputs a filter 0 to the 1) input terminal of the register 24〇1, and is temporarily stored and entered at the next time. In the scratchpad 24〇_1 (that is, store a serial number into the scratchpad). After that, the gate will accept the logic input of the scratchpad.

81. 2. 20,000 (Please call ^ Backwards before filling in the wooden page) Binding · Order-Line_

Ο 1 a QQQ A. · Jl. W V. · 1 iJ A 6 Π 6 Printed by the Cooperative Society of the Central Committee of the Ministry of Economic Affairs, “XIX Gongxiao”, the description of the invention () is output to its input terminal, so 228-1 The output of the can no longer set the register 24〇-1 to logic 1. At this time, only the AND gate 226-1 can set the register 240-1 to the selection 10, and this only occurs when the high position bit 212A of the current address counter 212 is selected to the group 1 (圏 11) (i.e. All output is Lin 0) and "the used pixel counter" 100 counts to the last time when it outputs data sequentially. At the same time, line 218-2 carries a Lin 1. The output of line 218-2 and the combined circuit 222 via line 224-2 is servoed to the two-round input of AND gate 226-2 of line 250-2. Therefore, AND gate 226-2 outputs a logic 1 and another Q in register 240-2 detects that 244-2 is a logic 0 output (described above), and AND gate 228-2 is a logic 1 0 output. The outputs of the two AND 226-2 and 228-2 are the input signals of an OR gate 236-2, respectively, so it produces a result of the filter] to the D input 242-2 of the register 240-2. When reaching the next moment, the register 240-2 is set to the value of this filter 1, and this state is maintained until the high bit 212A of the column address counter 212 changes state and "has been used The pixel counter &quot; 100 is counted to its last pixel. This is done by the AND gate 228-2, so one input of the gate 1 comes from the Q output 2442 of the register 24〇-2 And another late 1 input comes from the inverted result of the output of the combining circuit 222. As the register 240-2 is set to YA1, the first 0 is detected on line 24 8-2, which is the SE [2] signal. Therefore, when the column address counter 212 counts to When its relatively different memory group (that is, bit 212A changes state) and sequential access memory 66 (Sleep 5) has been output to its last pixel, it is in SE [1], SE [2],... In SE [N], there will be a #sequence enable signal outputting an edited value. At a time, only one SE signal will send out a logic value, and the rest of the SE signals are all completed (please read the back And the precautions are to write wooden pages) This paper uses the Chinese National Standard (CNS) V4 regulations (2) 〇x297 male dragon) S1. 2. 20,000 213339 Λ β It fi

The Ministry of Economic Affairs, the Ministry of Economic Affairs, the quasi-industry quasi- β-consumer cooperation, Du Yin M. V. Invention description (1) Output 1 Therefore, the sequential output of different groups of video random access memory 6 (囷 6) can be alternated It has been selected to be at least. The update controller circuit 70 can be modified at least to be used in the example with dual display memory and interleaved display. The dual display memory is Use two separate display memories to store the pixel data on yingmu repeatedly. Therefore, when the pixel data on the first yingmu display memory is only displayed on the display 12 (囷 6), The central processing unit (CPU) 16 (® 6) can supplement the latest pixel data in the second screen display memory. On the first screen, the data in the display memory is displayed up to the screen display 12 (囷 6 ) After that, the second block of flash memory that has been supplemented with pixel data by the central processing unit 16 (囷 6) and then output pixel data on the fluorescent display 12 (囷 6). At this time, the first piece of memory in the display area can be accessed by the central processing unit 16 (囷 6) to update the data in the memory 0. According to this strategy of alternately displaying the pixel data in the display memory, The central processing unit 16 (Circumference 6) can alternately fill the next image to be displayed on the neck display memory skeleton that is not currently outputting pixel data without disturbing the display action of another display memory. Dual display One example of a typical application of memory is the computer's animated simulation. The interlaced scanning method is a visualization technology that displays the pixels on the memory skull with a low scanning frequency. The data is alternately placed in the screen to produce an image without flashing the display screen. For example, the scan lines on the monitor screen are marked from 1 to the last scan line. These scans At this moment, the line is divided into two shadow surfaces (Field), namely the idol shadow surface and the odd shadow surface. The idol image surface is marked with an even number of scans. The paper size is easy to use Chinese Η home sample standard (CNS) T4 specification (210Χ297 male dragon) 81. 2. 20,000 (please read '1.? ¾ wood pages) binding, thread. ^ 19939

Λ 6 Η G The Ministry of Economic Affairs standard and R Gongxiao's cooperative cooperative printed five. The description of invention () line, and the singular shadow surface is composed of scanning lines marked as odd numbers. In the action of Qimu update, The odd and even shadows are shown on the cheeks. The alternate scanning method has a lower scanning frequency, so the production cost will be lower. However, it is not suitable for the display method with a higher unfolding degree, because the flicker phenomenon is more obvious. Produce poor visual effects. One line 260 is used to support dual flash memory and interlaced scanning mode, and it is shown in FIG. 13. Line 260 includes a column address counter 262 for correction, which includes an eye input 266, which is entangled to an external source via line 268. As previously mentioned, the way the eye is generated is The method of making the clock 114 similar to the column address counter 112 of FIG. 8 is that in addition, the column address counter 262 also has a load signal input 261 ′ which is connected to a plant signal via line 264 ( LOAD Sngnal) 〇Here, the plant signal 261 is provided to replace the reset signal (ie, the reset input 116 of the 8-column address counter 112). The column address counter 262 further includes an input 271, which It is through line 272 that an input value is accepted. Therefore, the corrected column address counter 262 is designed to load the value present on line 272 into the counter when the load signal on line 264 is triggered. This loaded value is used as the initial value counted by the column address counter 262. For example, the input signal is a VDISP signal, so that the input signal is triggered when it is in the vertical blanking interval. Connected to the input terminal 271 by line 2672 is a multiplexer The round-off signal of 270. In the example, this multiplexer accepts a one-bit late selection control signal via line 280. By selecting the state of the control signal from this, the multiplexer selects (please read first-back) Note that the curtain item is harder to write the wooden page). Binding_ Line-This paper scale is used in China ffl Jiayu standard (CNS) Τ 4 specifications (210x297 public goods) 81. 2. 20,000 219933

Λ 6 UG The Ministry of Economic Affairs, the Central Bureau of Economics and Trade, β-work elimination, cooperation, du printing. V. Description of invention () Select the value of line 274 or line 276 to the output terminal 0. It is the output of the base address register (Base Address Registor) 278-1 and 278-2 respectively. These registers store the starting address of the first row of the individual display memory or screen. Of course, it also stores the local memory group address. For example, in the interleaved scanning method, the temporary register 278-1 stores the first column address of the odd image plane, and the temporary register 278-2 does the first column address of the idol plane. On the other hand, in the example of dual display memory, the register 278-1 stores the first row address of the first block of display memory, and the register 278_2 stores the second block of display memory The first row of addresses. Obviously, with the ease of drawing the sleepy controller 22 (Wai 6), the same path 260 can be used in the example of double display memory and interlaced description method. The selection control bit of the multiplexer 270 is generated by a 101 gate 282. The 0R gate 282 accepts the video input signal input via the line 286 and the display memory via the line 284, respectively The body switching control signal. Therefore, the circuit 26 can rely on the operation of the update address generator circuit 70. The chess mode supports the interleaved scanning method and the example of dual display memory. The operation method of the circuit 260 will now be confined to under. In the example of the dual display memory, when it shows that the data in the first display memory is on the screen, an adequate signal is generated on line 284. On the other hand, in the interleaved mode In the ground sweeping method, if it is allowed to display the color image in the singular image surface, a sudden signal is generated on line 286. Both signals come from the controller 22 (closed 6). For example, when displaying the content of the first block of "Yi Yisao", "_Lian Ji" is input to line 284. Another Yu Xianxian (please note the matter first, fill in the wooden page) install, line-81. 2. 20,000 213339

Λ Γ. Η G Printed by the Ministry of Economic Affairs # 准 ^ β 工 消 # Cooperative Society V. Description of invention () When the content of the phantom screen is shown, a screening 〇 is sent to line 286 for inspection at gate 282 The output is input to the multiplexer 270 through the line 280, which selects one of the two base address registers 278-1, 278-2 as an output. In the illustration, for the selection of the singular image plane or the first block of display memory, the basic address register 278-1 is selected to assume that the output of the multiplexer 27 is at the same time. It also occurs on the edge 264. The violation causes the column address counter to wear in the value selected by the multiplexer, that is, the value sent to line 272. Since then, this address has been used for the row address of the video random access memory 60 (囲 6) during the update operation. In the case of dual display memory, the first display memory The image is displayed in the middle of the screen after the first block of display memory is displayed. When it wants to display the pixel data in the first block of display memory II, it is a signal (i.e. a selection 1) It is generated on line 284 to select the column address in the second register 278-2. On the other hand, in the interlaced scanning mode, after the odd shadow surface has been displayed, the second chime update needs to be completed, and the typical idol surface must follow the strange shadow surface (of course, After the display of the idol image, the parity surface must be displayed). At this time, an immediate signal (i.e., Echo 1) is generated on line 286 to select the second register 278-2 Column address. Once again, a plant signal is also simultaneously generated on line 264 so as to put the output value of this multiplexer 270 into the column address register 2 62 as the base address. In addition, in the dual screen In the first twilight display memory, usually to achieve a better visual stool effect, the switch of the display skull usually occurs during the vertical masking period. The alternate display of the Qibao shadow surface is also usually in the vertical dimming cycle. Generate these signals 〇 (please read ^ the notes before filling in the wooden page)

T This paper size is used in the middle 8 «Home Standard Bi (CNS) Τ4 specifications (210x297 male dragon) S1. 2. 20,000

Λ 6 It G 218389 V. Description of the invention () In short, the present invention is applied to the holographic scanning display system, which can be used very efficiently in the space of the display memory and is not related to the glow The resolution update strategy has been described in detail before. Finally, the above embodiment uses W as an example to illustrate the present invention, not to limit the present invention. Without departing from the spirit and scope of the present invention, those who are familiar with this technique can rely on it. The various modifications, modifications and applications that should be made should be included in the scope of the present invention. (Please read the back and the precautions #fill in the wooden page first). Packing--ΓΓ- line. Printed by the Central Bureau of Bureau of the Ministry of Economic Affairs, ΧΧ 工 消 浀 cooperatives 81- 2. 20,000

Claims (1)

… Month &quot; said, positive—Supplement Η 2 213939 VII. The reasons for the application for re-examination are as follows: April 14th of the following year ’s guest book review opinion, amending the patent application for patent application patent solidity: The pixel data is stored in a linear address in the servicing bank that is addressed by the row address and is stored in a sequence in the video memory received by the proud memory device-the entire row of pixel information S (II) video memory Use, the above-mentioned remaining control device is like two daggers, and it is used to count the first counter mentioned above in the lower half of its range. The second double-number generating device is used for Indicate the second count in the storage device when the half is counted relative to the first count. The second count in the half device is addressed by the second count in the storage device t. The half of the pixel data must be transferred. Entering people and accessing them in sequence ^ Itui counts to i every counter produced by ϊίίίίΙ ϊ: ϊ ;; l «Two Counts« Addressing. Column === 219339 2. As stated in item-of the patent claim SI-sheng ⑴-combinational circuit has-fine _ the above-mentioned first counter ^ · all the bits are combined together; (2)-the scratchpad is It is generated by 1 Si :: two temporary storage f-the output is a knot] on the i-th counter counts to the lower half of its range. Uj: used to increment the above column address counter. In the controller described in the item τ, the update of the firefly 3. If the patent application is applied, the first request generator device includes: (1) A combined circuit has an AND gate to divide the first counter above into the highest bit All other bits except the element are intertwined with each other; (2)-The temporary register is connected to the above-mentioned combined circuit. The above-mentioned temporary register is counted by the first counter above to the upper half of its festival. Part or the above ^ -th count H is generated when the count reaches the lower half of its profile-request output to start a branch transfer operation. ΙίίίίΞΪΓ-The index of the controller described in the item-AND gate connects the inverse result of the highest output bit in the first counter to a vertical display signal to generate an index for use as the first When a counter counts to the upper half of its range, it refers to the lower half of an addressed column, and when the first counter above counts to the lower half of its range, the indicator produced Refers to the upper half of a column addressed, and during the vertical blanking period of the vertical display signal described above, the result of suppressing the complementation of the highest bit of the first counter mentioned above is suppressed. 219939 5. The video memory as described in the first paragraph of the patent application model is made up of a memory module, and the above-mentioned linear storage of pixel data is performed by a memory group. When storing to another group, the above-mentioned controller further includes: a memory group selection device so that when the current memory group has completely output the pixel data of the last row, it is captured by the first With the help of the third counter, it can be used in the next sequence in the next memory group to send the data in the next sequence output operation 0 6. As described in the controller described in item 5 of the patent application park The memory group selection device includes: a decoder device that uses the above-mentioned second counter to divide the high-order part into two parts for enabling proper video memory group, and the rest The address bits are sent to the input 0 of the available video memory. 7. The second counter described in the controller described in the first item of the patent application includes a load Device to load a specific The base address goes into the second counter mentioned above. A 4 (210 X 297 X centimeters) -4-219339 8. The counter described in the controller described in item 7 of the patent application can be applied to the pixel data of the image surface of the alternating scanning head display Switching between the pixel data display of the odd shadow plane and the loading device described in the second counter mentioned above alternately plant the base address of the odd and even data shadow plane during the vertical blanking period into the second counter mentioned above In 〇9. As described in the seventh section of the patent application, the counter in the controller can be used to switch between the two memories when the dual memory is displayed. It is the second. The planting device described in the counter alternately features one head display body after the head display and loads the base address of the other head display after the head display into the second counter above. 10. Video The display system includes: (1) an arbitrary unfolding head-display device; (2)-the video driver circuit is connected to the above-mentioned driver display device; (3)-the Yingmu update controller is connected to In the above-mentioned Zhuxun actuator circuit, its Wu is in a linear position Storing pixel data in its own storage that can be addressed using row addresses and has a sequential access memory for receiving a whole row of pixel data from the storage device and sequentially-outputting video memory For use, the above controller includes: U) The first counter is used to count the number of pixels that have been output when sequentially accessing the memory to sequentially output pixel data; (b) The second counter is based on the above The first counter is incremented once in the lower half of its range to address the pixel data of the next row in the storage device; A 4 (210 X 297 mm) binding line 21S93S (C) An index generation device is It is used to indicate that the lower half of the pixel data in the storage device that is addressed by the second counter above must be transferred into the sequential access memory when the counter is counted in the upper half of its order relative to the first estimated counter. In the lower half, and when the first counter counts in the lower half of its order, the pixel data in the upper half of the row addressed by the second counter in the storage device must be transferred Into the upper half of the sequential access memory; (d)-The device for generating the update request is between the first counter and each of its half columns, and a request signal is generated to convert the above 5 丨Take the pointer to the second counter address and transfer the half-row into the sequential access memory. 11. An output pixel data method is used to store the pixel data at a linear address when it has a usable row. In the address-addressed storage and with a sequential access memory for receiving a whole row of pixel data from the memory device and sequentially-used in the output video memory, the above methods include the following Steps: (1) Counting the number of pixels that have been output when the pixel data is sequentially output in the sequential access to the German body; (2) When counting to the position of the lower half of the sequential access memory Increment the address counter once to address the next row of data in the storage device to be transferred to the sequential access memory; (3) when the count is fixed in the upper half of the sequential access memory, Transfer storage device The pixel data of the lower half of the row addressed to enter the lower half row of the sequential access memory, and when the count is fixed in the position of the upper half of the row, the pixel data of the upper half of the addressed row is transferred into the sequence Access memory in the upper half of the memory row 4 (210 X 297 mm)