1J 邾中央樣準局8工消费合作杜印製 Α6 Β6 五、發明説明（1 ) 本發明是有鬭於一種靜態記億體（Static Memory)的記億 單元（Cell),且特別是有閿於一種以字元線（Word Line)控制 的N-型電晶體當作拉高（puU-uP)負載裝置的靜態隨機存取 記億體（SRAM)之記億單元。 随箸電子業及資訊業之發達，SRAM已經是一種廣被採 用的稹體電路（1C)零件。第1圖所示便是一種習知六値電 晶體的SRAM記億單元之電路示意圖，此種記億單元包括兩 匍交叉铒接的拉低（Pull-down)電晶體24、26、兩個拉高負載 電晶體12、14、以及兩掴通行（pass)電晶體16、22。電晶 體24、26、16和22是N型金颶氣化物半導體（NM0S)，而負 載電晶體12和14則是P型金屬«化物半導體（PM0S)。負載 電晶鼸12的源棰（Source)與電晶體24的汲榷（Drain)連接於一 共同節點18,共同節點18經由通行電晶體16連接到一位元 線（Bit Line) BL ;負載電晶膿14的源棰與霄晶體26的汲棰連 接於另一共同節點20,共同節點20經由通行電晶體22連接 到另一位元線瓦。共同節點18控制18晶髏14和26的控制閘 極，而共同節點20則控制霄晶體12和24的控制閘極，因而 使共同節點18和20所儲存的數據會保持在互為反相，也就 是若共同節點18是高轚位.共同節點20則為低電位；共同 節黠18是低電位，共同節點20則為高電位。負載電晶體12 和14也可以用高霣阻的電阻器取代，同樣當作拉高負載元 件。通行霣晶體16和22的控制閘極都是由一宇元線WL所控 制，用來當作記億單元的謓/寫開關，在讀取操作時，字 元線WL通上高電位的信號，使通行電晶體16和22均導通， -3 - (請先閲讀背面之注意事項卉塡寫本頁) ,vs 丁 % 本紙張尺度適用中國國家標準（CNS)甲4规格（210 X 297公釐） 82.3. 40,000 5 經袍部中央標準局R工消费合作社印製 212847 A 6 B6 五、發明説明（2 ) 位元線BL和E便可謓取共同節點18和20所儲存的數據。在 寫入操作時，將適當的位元線BL或[強制為接地，即可改 變SRAM記億單元的狀態，亦卽共同節點18和20中的一値電 壓升高，而另一値刖霣壓降低，數據即經由通行電晶體16 、22寫入記億單元中。 上述使用CMOS (互補式金屬氣化物半導髓）電晶體對 的SRAM ,以P型電晶驩當作交叉耦接的N型電晶體之負載 ，雖然此種電路的消耗功率較低，但是卻需要有摻雜井（ Doped Well)以形成互補式霉晶醱對。因此會增加記億單元的 尺寸，且增加裝置（Device )製造的複雜性。為了縮減記億 單元的尺寸，有人提出以高霣阻的聚矽（Poly silicon)拉高負 載來取代上述的P型負載電晶髓，雖然這種N型記億單元 比CMOS記億單元的尺寸小，但是使用高電阻聚矽卻也增加 製程的後雜性，而且導致晶圖（Wafer)製造的循環時間（Cycle ΤίΒβ)增長。再者，使用高電阻聚矽也會提高消耗功率，因 此並非是一棰優良的解決之道。 在目前SRAM製造廠商正面臨全球空前未有的激烈競争 下，如何使1C的尺寸更小，製程更簡單，裂造成本更低， 且消耗功率較低，乃是攸蘭競争力的一大課題。本發明主 要便是針對此一課題，而發展出一種新穎的SRAM記億單元 〇 緣此，本發明的一主要目的是提供一種靜態記億體的 記億單元，其傜以字元線控制的N型電晶體當作拉离負載 元件，以便使記億單元的尺寸更小，製程更簡單，因此製 -4 - (請先閲讀背面之注意事項再塡寫本頁) 丨裝. .11- .線· 本紙張尺度適用中國國家標準（CNS)甲4規格（210 X 297公犛） 82.3. 40.000 A6 B6 紙濟部中央標準局员工消費合作社印製 五、發明説明（3 ) 造成本更低，而且仍保有低消耗功率的優點。 本發明的另一目的是提供一種靜態記億體的記億單元 ,其記億單元電路全部是使用NMOS電晶體。 依照本發明，一種靜態記德體的記憶單元，適於連接 一字元線、第一和第二位元線以及第一和第二霣壓位準， 該靜態記億體的記億單元包括： 第一和第二MOS電晶體，每一電晶體均具有一源榷、汲 極和控制閘極； 第三和第四MOS電晶體，毎一電晶體均具有一源棰、汲 極和控制閘搔，且其控制閛極均連接到該字元線； 用來將第一和第三MOS電晶體串接於該第一和第二電應 位準之間，且將第一和第三MOS電晶體連接於一第一共同節 點的装置； 用來將第二和第四MOS電晶鱧串接於該第一和第二霣壓 位準之間，且将第二和第四NOS電晶體連接於一第二共同節 點的裝置； 用來將該第一共同節點連接到該第二MOS電晶體的控制 閛極之裝置； 用來将該第二共同節點連接到該第一 M0S1S晶體的控制 閘極之装置； 一第五MOS電晶龌具有一源極、汲棰和控制閘極，且將 該第一位元線連接到該第一共同節點，該第五MOS®晶驩的 控制閛極被連接到該字元線；以及 一第六MOS®晶醭具有一源極、汲極和控制閘極，且將 -5 - (請先閱讀背面之注意事Ifi再項寫本頁) 裝. 線. 本紙張尺度適用中國國家標準（CNS)甲4規格（21ϋ X 297公犛） 82.3. 40,000 ^12841 5 8 -- = 部中央標準局R工消费合作社印製 五、發明説明（4 ) 該第二位元線連接到該第二共同節點，該第六MOS®晶體的 控制閘極被連接到該字元線。 為讓本發明之上述和其他目的、持擻和優點能更明顯 ，下文特舉一較佳實施例，並配合所附圖式，作詳细說明 如下： 圈式之簡單說明： 第1圖是習知一種SRAM記憶單元的電路圖；以及 第2圖是依照本發明，一種SRAM記億單元的霣路圈。 現請參照第2圖，依照本發明的一較佳實施例，一種 SRAM記億單元包括六個加強型的N型霣晶體62、64、66、 72、74和76。其與習知者之最大相異處是：負載電晶體62 、64是使用與其他電晶體相同型式的霄晶體，例如都是N 型電晶髖，而且負載電晶體62、64的控制閘極是建接到字 元線WL,而不是連接到共同節點70、68。共同節黏68仍控 制驅動（Drive)電晶臁的控制閘極；共同節點70仍控制驅動 霣晶龌的控制閘極。依照此種架構，由於所有的罨晶髏都 是相同型式的（例如N型電晶匾），所以可以使記億單元 的尺寸縮小，而且將拉高負載電晶體62、64的控制闌極連 接於字元線，也更進一步簡化«路。因此本發明可以達成 缩減記億單元的尺寸，簡化製程，降低成本等等功效，而 且也同樣具有低消耗功率的優點。本記德單元的讀/寫是 利用字元線WL促動負載霜晶體62、64以及通行霣晶體66、 72同時導通，來進行共同節點68、70所儲存互為反相數據 的讀取或寫入。 -6 - ------------------------裝------TT------線 {請先閲讀背面之注意事項再塡寫本頁) 本紙張尺度適用中團國家標準（CNS)甲4規格（210 X 297公犛） 82.3. 40,000 1) II» 部 中 央 樣 準 局 员 工 消 費 合 作 杜 印 製 21284 Αί； B6 五、發明説明（5 第2國所 、64 ,且其控 元的正確運作 晶體74、76以 ，當本記億單 體62和64都不 限電暖，所以 不導通的驅動 持儲存高電壓 然在較極端的 成非常小，而 ，甚至是空乏 克服驅動電晶 擇的狀態下若 Standby)電流也 是保持負載（ 億單元的待命 睡限漏電流予 動電晶體74、 示的記億單元的一値 制閘極被連接到字元 ，負載霉晶體62和64 及通行電晶驩66、72 元未被選擇時，字元 導通，由於負載電晶 負載電晶體的次臨限 霜晶髏74或76之次海 的共同節點68或72之 情況，負載電晶體62 變成純（Native)裝置（ (Depletion)裝置，以便 體74、76的次臨限漏 有較高的負載供應電 會較离。因此，在未 62、64 )的供應電流 電流，而再相對地將 以縮減。要達到此一 76的臨限電壓，或者 當字元線被選擇時，通行電晶 釀62、64偽同時被導通，而通行電 的霣晶釀尺寸比應作適當的設計， 負載霣晶黼可以有肋於記億單元中 -7 - 持點是使用船观晶體62 線WL。為了確保記億單 可以作成具有比驅動電 低的臨限（Threshold)電壓 線是OFF,導致負載電晶 體62、64具有較低的臨 (Subthreshold)電流會大於 限漏電流，因而足以維 電位能持绩被儲存。雖 、64的臨限電歷可以作 亦即具有零臨限電壓） 具有大的次臨限電流來 電流，然而，在未被選 流，那麽装置的待命（ 被選擇的狀態下，最好 為小霣流，以便縮減記 驅動電晶體74、76的次 目的，可以藉由提高驅 利用更佳的製程來達成 體66、72以及負載霄晶 晶鼸和負載霄晶膿之間 以便在操作期間，拉高 儲存高電壓的共同節點 ------------------------裝------.玎------0 (請先閲讀背面之注意事項再塡寫本頁) 本紙張尺度適用中國國家樣準（CNS)甲4規格（210 X 29V公犛） H2.3. 40.000 11 Ε部中央標準局R工消费合作杜印« 21-B47 A6 B6 五、發明説明（6 ) 的電位之拉昇，因而增進記億體的記億單元穗定性。通常 一 SRAM記億單元的設計是以下列的方式予以最佳化：通行 霣晶髏要作的儘可能的窄和短；驅動電晶體要作的足夠長 ，以便有助於記億單元經由通行電晶體至位元線，以最快 的速度被寫入數據和謓取其狀態；而負載電晶體則是具有 最小的寬度和足夠的長度，以便記億單元在寫入狀態時可 以切換。 為了證實本發明的功效，本發明人曾以下列的裝置尺 寸進行模擬： 負載電晶體（62、64 ) 寬/長=0.8 / 2.0 通行電晶體（66、72 ) 寬/長=0.6 / 0.8 驅動電晶體（74、76 > 寬/長=2.0 / 0.6 其他裝置的參數則遵照本申請人新的0.6α磡程。基於SPICE 的模擬結果顯示本發明可以非常正常地工作，進一步證實 了本發明之可行性。吾人應瞭解上述的尺寸參數僅用來當 作例子，而非用以限定本發明，每一裝置的最佳霣晶體尺 寸都需視所用的製程參數和佈局（Layout )規則而定。 依照本發明的一持點，字元線控制的拉高負載電晶髏 ，應用於SRAM記億單元中係非常有利的，其可以使記憶單 元的所有電晶體都是NM0S裝置，而且在記億單元中不需要 任何額外的互連線，因而簡化電路設計和製程。在未被選 擇的狀態下，字元線控制的拉高負載電晶體偽當作實質上 不導通的裝置，因而縮減記億單元的待命電流，降低消耗 功率。在被S擇的狀態下，拉高電晶體的控制閘極電位變 -8 - 本紙張又度適用中國國家標準（CNS)甲4规格（21ϋ X 297公釐） 82.3. 40,000 (請先閱讀背面之注意事項再塡寫本頁) 裝. .ΪΤ. .線. 13 15 部 t 央 樣 準 工 消 费 合 作 杜 印 製 212847 A 6 B6 五、發明説明（7 ) 為高霣壓，使較高 而有助於提昇記億 操作期間記億單元 含單一種型式的電 減記億單元的尺寸 薄膜電晶體，也可 置，亦卽負載電晶 Polycrystalline Silicon 單元的尺寸。 雖然本發明已 以限定本發明，任 精神和範圍内，當 保護範圍當視後附 的的負載供應電流送至儲存節點上，因 單元中儲存高電壓的節點之霉位，改菩 的穩定性。由於本發明的記億單元只包 晶體（例如是N型電晶體），故可以縮 。再者，全特性的（Fully Characterized) NMOS 以用來當作該字元線控制的拉高負載裝 體62和64可被作在一多結晶矽薄膜（ Thin Film)上，以便更進一步地縮減記憧 以一較佳實施例掲露如上，然其並非用 何熟習此項技藝者，在不脱離本發明之 可作些許之更動與潤飾，因此本發明之 之申請專利範圍所界定者為準。 (請先閲讀背面之注意事項再項寫本頁) .裝. 訂. 本紙張凡度適用t國國家標準（CNS)中4规格（21U X 297公釐） 82.3. 40,0001J Pi Central Provincial Bureau of Standards, Industrial Engineering, Consumer Cooperation, Co., Ltd. A6 Β6. V. Description of the invention (1) The present invention is a cell that records a static memory (Static Memory), and in particular has a shortcoming. In an N-type transistor controlled by a word line (Word Line), it is used as a static random access memory (SRAM) memory cell of a puU-uP load device. With the development of the electronic industry and the information industry, SRAM is already a widely used elementary circuit (1C) component. Figure 1 is a schematic diagram of a conventional SRAM memory cell with six-value transistors. Such a memory cell includes two pull-down transistors 24, 26, two Pull up the load transistors 12, 14 and the two slap pass transistors 16, 22. The transistors 24, 26, 16 and 22 are N-type gold hurricane gas semiconductors (NMOS), while the load transistors 12 and 14 are P-type metal semiconductor compounds (PMOS). The source transistor (Source) of the load transistor 12 and the drain of the transistor 24 are connected to a common node 18, and the common node 18 is connected to a bit line BL via the pass transistor 16; The source of the crystal pus 14 and the drain of the crystal 26 are connected to another common node 20, and the common node 20 is connected to another bit line tile via a pass transistor 22. The common node 18 controls the control gates of the 18 crystals 14 and 26, while the common node 20 controls the control gates of the crystals 12 and 24, so that the data stored in the common nodes 18 and 20 will remain in reverse phase with each other. That is, if the common node 18 is high, the common node 20 is low potential; the common node 18 is low potential, and the common node 20 is high potential. The load transistors 12 and 14 can also be replaced with high-resistance resistors, which also act as high-load elements. The control gates of the pass-through crystals 16 and 22 are controlled by a Yuyuan line WL, which is used as a writing / writing switch for the billion unit. During the reading operation, the word line WL is connected to a high potential signal , Make both pass transistors 16 and 22 conductive, -3-(please read the notes on the back of Huicheng to write this page first), vs Ding% This paper scale is applicable to China National Standard (CNS) A 4 specifications (210 X 297 ) 82.3. 40,000 5 Printed 212847 A 6 B6 by R Industry and Consumer Cooperative of Central Bureau of Standards of the Ministry of Economic Development 5. Description of invention (2) Bit lines BL and E can retrieve the data stored in common nodes 18 and 20. During the write operation, the appropriate bit line BL or [forced to ground, can change the state of the SRAM memory cell, and the voltage in one of the common nodes 18 and 20 rises, while the other one rises. When the voltage drops, the data is written into the billion unit via the pass transistors 16 and 22. The above SRAM using CMOS (Complementary Metal Vaporized Semiconductor) transistor pairs uses P-type transistors as the load of cross-coupled N-type transistors. Although the power consumption of this circuit is low, it does Doped wells are required to form complementary mildew crystal pairs. Therefore, the size of the billion-unit is increased, and the manufacturing complexity of the device is increased. In order to reduce the size of billion-element cells, it has been proposed to replace the above-mentioned P-type load electric crystal with high-resistance polysilicon (Poly silicon) to increase the load. Small, but the use of high-resistance polysilicon also increases the complexity of the process, and leads to an increase in the cycle time (Cycle ΤίΒβ) of wafer manufacturing. Furthermore, the use of high-resistance polysilicon also increases power consumption, so it is not a good solution. At present, SRAM manufacturers are facing unprecedented fierce competition in the world. How to make the size of 1C smaller, the process simpler, the cost of cracking lower, and the power consumption lower, is a major issue for Oran's competitiveness . The present invention is mainly aimed at this subject, and developed a novel SRAM billion memory cell. Therefore, a main object of the present invention is to provide a static billion memory cell, which is controlled by the word line The N-type transistor is used as a pull-off load element, so that the size of the billion-element unit is smaller and the process is simpler, so the system is -4-(please read the precautions on the back before writing this page). . Line · This paper scale is applicable to China National Standard (CNS) Grade A 4 (210 X 297 male) 82.3. 40.000 A6 B6 Printed by the Employee Consumer Cooperative of the Central Standardization Bureau of the Ministry of Paper Economy 5. The invention description (3) results in a lower cost , And still retain the advantages of low power consumption. Another object of the present invention is to provide a static billion-memory-memory unit, all of which use NMOS transistors. According to the present invention, a memory unit of a static German font is suitable for connecting a word line, first and second bit lines, and first and second high pressure levels. : The first and second MOS transistors, each of which has a source, drain, and control gate; the third and fourth MOS transistors, each of which has a source, drain, and control Gate, and its control electrode is connected to the word line; used to connect the first and third MOS transistor in series between the first and second electrical response level, and the first and third A device for connecting the MOS transistor to a first common node; used to connect the second and fourth MOS transistors in series between the first and second pressure levels, and to connect the second and fourth NOS A device for connecting the crystal to a second common node; a device for connecting the first common node to the control pole of the second MOS transistor; a device for connecting the second common node to the first MOS 1S crystal A device for controlling the gate; a fifth MOS transistor has a source, drain and control gate, and the first The element line is connected to the first common node, the control gate of the fifth MOS® crystal is connected to the word line; and a sixth MOS® crystal has a source, a drain, and a control gate, and Put -5-(Please read the notes on the back of Ifi before writing this page). Thread. The paper size is applicable to China National Standard (CNS) A 4 specifications (21ϋ X 297 male yak) 82.3. 40,000 ^ 12841 5 8 -= Printed by the Ministry of Standards, Bureau of Industry and Consumer Cooperatives V. Description of the invention (4) The second bit line is connected to the second common node, and the control gate of the sixth MOS® crystal is connected to the character line. In order to make the above and other objects, advantages and advantages of the present invention more obvious, a preferred embodiment is described below in conjunction with the attached drawings, which are described in detail as follows: A brief description of the circle type: Figure 1 is A circuit diagram of an SRAM memory cell is known; and FIG. 2 is an illustration of an SRAM memory cell in accordance with the present invention. Referring now to FIG. 2, in accordance with a preferred embodiment of the present invention, a SRAM memory cell includes six enhanced N-type yin crystals 62, 64, 66, 72, 74, and 76. The biggest difference between them and the conventional ones is that the load transistors 62 and 64 use the same type of crystals as other transistors, such as N-type transistors, and the control gates of the load transistors 62 and 64. It is built to connect to the word line WL, not to the common nodes 70 and 68. The common joint 68 still controls the control gate of the drive transistor; the common node 70 still controls the control gate of the drive Jing Jingqiang. According to this architecture, since all the crystal skeletons are of the same type (for example, N-type electric crystal plaque), the size of the billion unit can be reduced, and the control poles of the pull-up transistors 62 and 64 are connected. The character line also further simplifies the «road. Therefore, the present invention can achieve the effect of reducing the size of the billion-element unit, simplifying the manufacturing process, reducing the cost and so on, and also has the advantages of low power consumption. The read / write of the Bende cell is to use the word line WL to actuate the load frost crystals 62, 64 and the pass-through crystals 66, 72 to conduct at the same time to read or store the mutually inverted data stored in the common nodes 68, 70 or Write. -6------------------------- installed ------ TT ------ line {please read the notes on the back first (This page will be written on this page again) This paper scale is applicable to the China National Standards (CNS) A 4 specifications (210 X 297 male) 82.3. 40,000 1) II »Ministry of Central Bureau of Standards and Practitioners, consumer cooperation, duprint 21284 Αί; B6 Five 3. Description of the invention (5 second country office, 64, and the correct operation of its control elements, crystals 74, 76, when the notebook unit 62 and 64 are not limited to electric heating, so the non-conductive drive maintains a high voltage storage. In the extreme extreme, the current is very small, and even in the state where the exhaustion overcomes the selection of the driving circuit, the current is also to maintain the load (100 million units of standby sleep limit leakage current to the dynamic transistor 74, shown one of the 100 million units) When the gate is connected to the character, and the load mold crystals 62 and 64 and the pass transistors 66 and 72 are not selected, the character is turned on, due to the load transistor's secondary threshold frost crystal skeleton 74 or In the case of the common node 68 or 72 in the sub-sea of 76, the load transistor 62 becomes a native device (Depletion) device, so that the secondary threshold leakage of the body 74, 76 Higher load power supply will be farther away. Therefore, the supply current in the 62, 64) will be relatively reduced. To reach this threshold voltage of 76, or when the word line is selected, The pass electric crystals 62 and 64 are simultaneously turned on at the same time, and the size ratio of the pass electric crystals should be properly designed. The load crystals can be ribbed in the unit of -7 million-the holding point is the use of the ship watch crystal 62 Line WL. In order to ensure that the billing unit can be made to have a lower threshold voltage than the drive (Threshold) voltage line is OFF, resulting in the load transistor 62, 64 has a lower threshold (Subthreshold) current will be greater than the limit leakage current, which is sufficient The dimensional potential can be stored. Although the 64-year threshold can be used as a zero-threshold voltage, it has a large sub-threshold current. However, if the current is not selected, then the device is on standby (being In the selected state, it is better to be a small fan, so as to reduce the secondary purpose of driving the transistors 74, 76, and the body 66, 72 and the load crystals and the load can be achieved by improving the drive using a better process. Between crystal pus in order to operate Between the time, the common node of pulling high and storing high voltage ------------------------ installed ------. 玎 ------ 0 (Please read the precautions on the back before writing this page) This paper scale is applicable to China National Standards (CNS) Grade 4 (210 X 29V male yak) H2.3. 40.000 11 Central Bureau of Standards R Industrial and Consumer Cooperation Du Yin «21-B47 A6 B6 Fifth, the description of the invention (6) The electric potential is raised, thus improving the qualitative of the billion unit of the billion unit. Generally, the design of a SRAM billion cell is optimized in the following ways: the passing skull should be made as narrow and short as possible; the driving transistor must be made long enough to help the billion cell pass through The transistor to the bit line is written with data and its state at the fastest speed; and the load transistor has the smallest width and sufficient length so that the billion unit can be switched during the writing state. In order to verify the effectiveness of the present invention, the inventors have simulated with the following device sizes: load transistors (62, 64) width / length = 0.8 / 2.0 pass transistors (66,72) width / length = 0.6 / 0.8 drive Transistor (74, 76> width / length = 2.0 / 0.6 The parameters of other devices follow the applicant ’s new 0.6α process. The simulation results based on SPICE show that the present invention can work very normally, further confirming the present invention Feasibility. I should understand that the above size parameters are only used as examples, not to limit the present invention. The optimal size of each device depends on the process parameters and layout rules used. According to one aspect of the present invention, the high load transistors controlled by the word line are very useful in SRAM memory cells, which can make all the transistors of the memory cell be NMOS devices, and There is no need for any extra interconnection in the 100 million cell, which simplifies the circuit design and manufacturing process. In the unselected state, the word line controlled pull-up load transistor is assumed to be a substantially non-conductive device, so The standby current of 100 million units is reduced, and the power consumption is reduced. In the state of being selected, the control gate potential of the high transistor is changed to -8-this paper is again applicable to the Chinese National Standard (CNS) A 4 specifications (21ϋ X 297 mm) 82.3. 40,000 (Please read the precautions on the back before writing this page) Installed ... ΪΤ .. 线. 13 15 parts t Central sample quasi-industrial consumer cooperation du print 212847 A 6 B6 V. Description of invention (7) For the high pressure, it is higher and helps to increase the size of the billion-element unit during the billion-element operation. The size of the thin-film transistor contains a single type of electrically reduced billion-element unit. It can also be placed and loaded with polycrystalline silicon. The size of the unit. Although the present invention has been limited to the present invention, within the spirit and scope, when the protection range is considered as the supply current of the attached load is sent to the storage node, due to the mold position of the node storing high voltage in the unit, The stability of the bodhisattva. Since the billion unit of the present invention only contains a crystal (for example, an N-type transistor), it can be reduced. Furthermore, a fully characterized (Fully Characterized) NMOS is used to control the word line Pull negative The bodies 62 and 64 can be made on a thin film of polycrystalline silicon (Thin Film) to further reduce the use of a preferred embodiment, as described above, but it is not used by those skilled in the art. Some changes and modifications can be made without the invention, so the scope of the patent application of the invention is defined. (Please read the precautions on the back before writing this page). Install. Order. Applicable to 4 specifications (21U X 297mm) in the National Standards (CNS) of country t 82.3. 40,000