,037^ ,037^ 經濟部中央標準局员工消费合作社印¾ A6, 037 ^, 037 ^ Printed by the Employees Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs ¾ A6
BG 五、發明説明（f) 本發明偽為一種資料缓衝裝置，主要為以環狀缓衝器 配合一個二對一多工器、一計數器及一比較器構成分時多 工資料缓衝，據此降低傳統平行資料缓衝架構所需之大型 多工器構造，達到降低積髏電路佔用面積及電路佈局複雜 性者。 按現今積體電路使用極為頻繁，且其架構亦朝箸縮小 …. · - - . 、 髏積、障JH雜度及便於製造等方面改進，而對於欲達成 資料迅速進出之方式下所採用之資料缓衝器（buffer)，即 為改進資料處理速度之不二法門，而現今對於分時多工架 構之資料缓衝方式上，槪為採用平行缓衝方式，以下茲舉 - ........... ...... ....... 一應用在乘法器上之資科缓衝器的實例加以説明，為此可 配合參看第四圖所示，即以一位址解碼器（5 1 )予待寫 入資料之位址解碼，而使各組被乘數及乘數等不同資料（ DATA)分別儲存於上、下兩以多數暫存器所組成之缓 衝器（6 0) (7 0)内（圖中傜以八膣暫存器（A 1 ) 〜（A8) ( B 1 )〜(B8)為例），該上、下兩組缓 衝器（6 0 ) (7 0)之輸出端即分別經多工器（6 1 ) (7 1 )做分時多工選擇，依序蔣上、下缓衝器（6 〇 ) (7 0)其中各値暫存器之資料依序送入乘法蓮算單元（ 80)予以運算後，而依序由輸出端（Dout)送出各 組資料之蓮算结果者。 然以前述據以達成資料缓衝之架構而論，於多 器後方即需R置多工器，以達到多工選取不同資料者，而 本纸張又度適用中园囷家標準（CNS) T4規格（210 x 297公货） 81.9.20,000 -----1-------------------•-装--,^1. Ι.ΤΓ線 {請先«讀背面之注6事項再塡寫本頁) C： 0874^ A6 B6 經濟部中央標準局员工消费合作社印¾ 五、發明説明（·>〇 以上述圖示中，卽因暫存器設為上、下各別為八組之十六 位元構造，故多工器亦需為8對1之十六位元多工器為之 ，惟上述規格之多X-器^-編，其電路佈局原本ΕΠΜ十Jt複 ... ^ ^1*1 ·"''' 雜，更相當佔用積髏電路面稹者，若前述多工器切換數置 相對增加時，亦使其複雜度及佔用晶片之現象更形哮g , 此等現象不僅造成積體電路體積無法縮小外，更有違現今 之趨勢，確有加以改良之必要。 本發明人鑑於傳统資料缓衝架構之缺點乃經悉心地試 驗與研究並一本鍥而不捨之登明精神，终發明出一種可降 低多工器使用量而可具體降低其複雜度及可縮小實際佔用 晶Η面13之資料緩iii装置，主要將豪m .器..室接.形.成二 環形緩衝器，而環形缓衝器之_出端即直接送出資料..，面. 僅需於其f入端位置觅置衣小型多工器及用以決定 資料寫入環形缓衝器位置之計數器及位址比較器，即/可砍 序使資料分別寫入至各脑暫存器及依序送出至資/料.，..逹到 資料缓衝效果，而其間所採用之结構即免除傳統.資料緩衝 器所需使用之大型多工器，擭致缩小體積及降低積體電路 佈局複雜度者。 為使 貴審査委員能進一步瞭解本發明之結構，持勸 及其他目的，玆 附以圖式詳細說明如后： (—)·圖式部份： 第一圖：偽本發明之實施例方塊圖。 第二圖：係本發明寫入資料至缓蔺器之時序圖。 ~ 4 - <請先Mift背面之注Φ?事項再填寫本頁) i装· 訂· 線. 本纸張尺度a用中as家櫺準（CNS)甲4現格（210 X 297公货） 81,9.20,000 經濟部中央標準局KK工消費合作社印製 ^〇Β'ί Α6 _Β6_ 五、發明説明（$ ) 第三圖：係蓮算單元之實施例圖。 第四圖：偽習知蓮用於乘法器之資料缓衝器方塊 (二）·圖號部份： (10) (20)環形缓衝器（11) (21)多工器 (12) (22)位址比較器（30)計數器 (40)蓮算單元 （51)位址解碼器 (60) (70)缓衝器 （61) (71)多工器 (8 0 )蓮算單元 如第一圖所示，亦為本發明應用於乘法運算單元上之 資料缓衝溝造，於乘法蓮算單元（4 0 )之兩輸入端所在 位1上分別設以本發明之資料缝衝装置，該資料·缓衝装置 偽以多組可由正反器構成之暫存器（A1)〜（A8)( B 1 )〜（B 8 )相互串接後，再於最前端位置串接一 2 對1多工器（1 1 ) ( 1 2 >溝成一環形缓衝器（1 0 ) ，兩多工器（11) (.12)之其一輸入端（A )為最後 端暫存器（A8) ( B 8 )回送者，其另一輸入端（B) 則與資料匯流排（D A T A )連接，以供輸入資料，而位 址匯流排（A D D )所送入之位址訊號，即以其一高位址 線與兩多工器（1 1) (2 1)之致能端（EN)連接， 以供資料選擇性地寫入至其一環形缓衝器（1 0) (2 0 )内，位址訊號之低位址線則分別經位址比較器（1 2 ) (2 2)及一計數器（3 0)所構成之位址解碼器而與兩 多工器（1 1 ) ( 2 1 )之選擇端點（S )連接，該兩位 本纸張又度適用中國S家標準（CNS)甲4規格（210 X 297公：$ ) 81.9.20,000 -------------------------裝---^1 ----------·φ (坩先閲請背面之注念事項再塡寫本頁) 經濟部中央標準居與工消费合作社印製 :0374^ a6 _B6_ 五、發明説明（士） 址比較器（12) (2 2)之其一比較輸入端則與一計數 器（30)輸出端連接，該計數器（30)為同步於前述 環形缓衝器（10)之時脈訊號而同步計數，且其計數值 更相等於各組琛形缓衝器（10) (20)之暫存器數置 者，俥可由計數器之數值辨別資料寫入欲環形缓衝器（1 0) (20)之實際位址。 而其位址解碼之動作上，即如第二圖之時序圖所示， 相應於環形缓衝器之時脈（CLK)，即令計數器産生由 0至7之循環計數動作（係以八痼暫存器為例），而當低 位址線之值為3時，卽經位址端（ADD)輸入之資料經 比較器（1 2 ) ( 2 2 )而與計數器（3 0 )之計數值核BG 5. Description of the invention (f) The present invention is a kind of data buffering device. It mainly consists of a ring buffer combined with a two-to-one multiplexer, a counter and a comparator to form a time-sharing multiplexed data buffer. Accordingly, the structure of the large multiplexer required by the conventional parallel data buffer architecture is reduced, and the area occupied by the integrated circuit and the complexity of the circuit layout are reduced. According to the current use of integrated circuits is extremely frequent, and its structure has also shrunk towards….---., Cross-section, barrier JH complexity and ease of manufacturing, etc., and the method used to achieve rapid data entry and exit Data buffer (buffer), is the only way to improve the data processing speed, and nowadays for the data buffering method of the time-sharing multiplexing structure, the parallel buffering method is adopted, the following are -... ....... ...... ....... An example of a resource buffer applied to a multiplier is explained. For this purpose, please refer to the fourth figure, which means An address decoder (5 1) decodes the address of the data to be written, so that each group of multiplicands and multipliers and other different data (DATA) are stored in the upper and lower two composed of the majority of temporary memory In the buffer (6 0) (7 0) (in the figure, take the eight-fold register (A 1) ~ (A8) (B 1) ~ (B8) as an example), the upper and lower two groups of buffers The output terminals of the device (6 0) (7 0) are time-division multiplexed respectively selected by the multiplexer (6 1) (7 1), and the upper and lower buffers (6 〇) (7 0) in sequence The data in each value register is sent in order After input into the multiplication lotus calculation unit (80) for operation, the lotus calculation results of each group of data are sent out from the output terminal (Dout) in sequence. However, based on the aforementioned structure to achieve data buffering, a multiplexer is required after the multiplexer to achieve multiplexing to select different data, and this paper is also applicable to the Zhongyuan Family Standard (CNS) T4 specifications (210 x 297 public goods) 81.9.20,000 ----- 1 ------------------- • -installed-, ^ 1. Ι.ΤΓ line {Please first «read note 6 on the back and then write this page) C: 0874 ^ A6 B6 Printed by the Employees’ Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy ¾ V. Description of Invention (· > The memory is set to eight groups of sixteen-bit structures, so the multiplexer also needs to be an eight-to-one sixteen-bit multiplexer, but multiple X-devices of the above specifications ^- The circuit layout of the original ΠΠ 十 Jt complex ... ^ ^ 1 * 1 " '' 'Miscellaneous, more occupying the surface of the integrated circuit, if the number of the multiplexer switching is relatively increased, it also makes The complexity and the phenomenon of occupying chips are even worse. These phenomena not only cause the volume of the integrated circuit to be reduced, but also violate the current trend, and there is indeed a need for improvement. The inventors have considered the traditional data buffer architecture Disadvantages are carefully Experience and research combined with a persevering spirit, finally invented a device that can reduce the use of multiplexers and can specifically reduce its complexity and can reduce the actual data occupied by the crystal surface iii iii device, mainly will m. Device .. room connection. Formed into two ring buffers, and the _ output end of the ring buffer directly sends data .., surface. Only need to find a small multiplexer at its f input end and use A counter and an address comparator that determine the position of the data to be written into the ring buffer, ie / can be cut so that the data can be written to each brain register and sent to the data / material sequentially .... to the data buffer Effect, and the structure adopted in the meantime eliminates the traditional. The large multiplexer required for data buffers reduces the size and complexity of the integrated circuit layout. To enable your reviewers to further understand the structure of the present invention For persuasion and other purposes, here is a detailed description with the drawings as follows: (—) · The part of the drawings: the first picture: a block diagram of an embodiment of the pseudo invention. The second picture: the invention writes data to Timing diagram of the retarder. ~ 4-< Please note Φ? (Fill in this page again) i Pack · Order · Thread. The paper size a is used as a home frame standard (CNS) A 4 present grid (210 X 297 public goods) 81,9.20,000 KK Industrial Consumption, Central Bureau of Standards, Ministry of Economic Affairs Printed by the cooperative ^ 〇Β'ί Α6 _Β6_ V. Description of the invention ($) The third figure: the figure of the embodiment of the lotus arithmetic unit. Figure 4: Data buffer block used by Pseudo Xizhilian for multiplier (2) · Part of figure number: (10) (20) Ring buffer (11) (21) Multiplexer (12) (22) Address comparator (30) counter (40) lotus unit (51) address decoder (60) (70) buffer (61) (71) multiplexer (80) lotus unit as shown in the first figure As shown, it is also the data buffer trench of the present invention applied to the multiplication unit. The data slitting device of the present invention is provided on the bit 1 of the two input terminals of the multiplication lotus unit (40), the data · The buffer device is pseudo-multiple sets of temporary registers (A1) ~ (A8) (B 1) ~ (B 8) which can be composed of flip-flops, and they are connected in series with each other, then in series at the foremost position, 2 to 1 more The working device (1 1) (1 2 > grooves into a circular buffer (1 0), and one of the input terminals (A) of the two multiplexers (11) (.12) is the last-end register (A8) (B 8) For the sender, the other input terminal (B) is connected to the data bus (DATA) for inputting data, and the address signal sent by the address bus (ADD) is the first one. The high address line is connected to the enable terminal (EN) of two multiplexers (1 1) (2 1) To allow data to be selectively written into one of its ring buffers (1 0) (2 0), and the lower address lines of the address signal pass through address comparators (1 2) (2 2) and An address decoder composed of a counter (3 0) is connected to the selection endpoints (S) of two multiplexers (1 1) (2 1). CNS) A 4 specifications (210 X 297 male: $) 81.9.20,000 ------------------------- installed --- ^ 1 --- ------- · φ (Please read the notes on the back of the crucible before writing this page) Printed by the Central Standard Housing and Industrial and Consumer Cooperative of the Ministry of Economic Affairs: 0374 ^ a6 _B6_ V. Description of Invention (Shi) Address Comparison A comparison input terminal of the device (12) (2 2) is connected to the output terminal of a counter (30), the counter (30) is synchronized with the clock signal of the ring buffer (10) and counts synchronously, and The count value is more equal to the number of registers of each group of Chen-shaped buffers (10) (20), so that the actual value written into the ring buffer (1 0) (20) can be identified by the value of the counter The address decoding action, as shown in the timing diagram of the second figure, corresponds to the ring The clock (CLK) of the buffer causes the counter to generate a cycle counting action from 0 to 7 (using the eighth register as an example), and when the value of the lower address line is 3, it passes through the address end ( ADD) The input data is compared with the count value of the counter (3 0) through the comparator (1 2) (2 2)
對，當計數器（3 0 )計數至相同於位址訊號之值為3時 ，始令比較器（12) (22)輸出（Comp Ο / P )為高電位，據以使多工器（1 1 ) ( 2 1 )切換至B輸 入端位置，始令外界資料可寫入至環形缓衝器（10)相 應於該計數器（3 0)數值所代表之暫存器（第3痼暫存 器）上，達到令相應於位址訊號之資料可經由前述之位址 解碼構造而存入對瞜之暫存器内，依此方式，即令各項待 蓮算之資料可依序儲人環形缓衝器（10) (20)内， 而該環形缓衝器（10) (20)後方之輸出端位置可直 接與後方之乘法蓮算單元.（40)連接，經環形缓衝器（ 10) (20)後端依序送出上、下兩資料後，即可由蓮 算單元（4 0)據以蓮算而依序送出各组蓮算結果β -6- 本纸張又度適用中國园家標準（CNS)甲4现格（210 X 297公釐） 81.9.20,000 ------------------------_裝|_·—.---tr------^ * (請先《访背面之注+?事項再塡寫本頁> £06742 A6 _B6_ 五、發明説明（1) 此外，該乘法蓮算單元（40)之實施方式，亦可採 用一種移位累加之構造，使之配置前述裝置下，達到較佳 使用效果，可參看第三圖所示，邸以兩组分別為右移及左 移暫存器分別做乘數及披乘數之移位，再經加法器及暫存 器所構成之累加構造完成。 是以，由前述本發明之資料缓衝之結構觀之，即免除 傳统平行資料缓衝方式所需之大型多工器構造，轉而以環 狀缓衝架構配合位在輸入端位置之小型多工器、計數器及 比較器構成位址解碼作用，確為一可降低晶片佔用面積及 降低積體電路佈局複雜度之新穎資料缓衝装置。 {»先閲請背面之注+?事項再塡寫本頁) -.装· .線. 經濟部中央標準/¾員工消费合作社印製 本纸張尺度適用中as家標準（CNS〉甲4現格（210 X 297公货） 81.9.20,000Yes, when the counter (3 0) counts to the same value as the address signal is 3, the comparator (12) (22) output (Comp Ο / P) is set to a high potential, so that the multiplexer (1 1) (2 1) Switch to the B input terminal position, so that external data can be written to the ring buffer (10) corresponding to the register represented by the value of the counter (30) (the third register) ) To achieve that the data corresponding to the address signal can be stored in the temporary register through the aforementioned address decoding structure. In this way, the data to be calculated can be stored in a ring buffer in sequence. In the punch (10) (20), and the output position of the rear of the circular buffer (10) (20) can be directly connected to the rear multiplying unit. (40), through the circular buffer (10) (20) After the upper and lower data are sent in sequence at the back end, the lotus calculation unit (40) can sequentially send the results of each lotus calculation according to the lotus calculation β -6- This paper is also suitable for Chinese gardeners Standard (CNS) Grade A 4 (210 X 297 mm) 81.9.20,000 ------------------------_ install | _ · -.- --tr ------ ^ * (Please "Note on the back of the interview +? Matters before writing this page> £ 0 6742 A6 _B6_ V. Description of the invention (1) In addition, the implementation of the multiplying lotus unit (40) can also adopt a shift-accumulate structure, which can be configured under the aforementioned device to achieve better use effect. As shown in the three figures, Di uses two sets of right-shift and left-shift registers to shift the multiplier and multiplier, respectively, and then completes the accumulation structure formed by the adder and the register. The aforementioned structure view of the data buffer of the present invention is to eliminate the large-scale multiplexer structure required by the traditional parallel data buffer mode, and instead use a ring buffer structure to cooperate with the small multiplexer and counter at the input end And the comparator constitutes the address decoding function, which is indeed a novel data buffer device that can reduce the chip footprint and the complexity of the integrated circuit layout. {»Please read the note on the back +? Matters and then write this page)- .Package · .Line. Central Standard of the Ministry of Economic Affairs / ¾ Employee Consumer Cooperative Printed Paper Scale Applies to the Chinese Standard (CNS> A4 cash (210 X 297 public goods) 81.9.20,000