TW202425267A - Capacitor coupling package structure - Google Patents

Capacitor coupling package structure Download PDF

Info

Publication number
TW202425267A
TW202425267A TW111147287A TW111147287A TW202425267A TW 202425267 A TW202425267 A TW 202425267A TW 111147287 A TW111147287 A TW 111147287A TW 111147287 A TW111147287 A TW 111147287A TW 202425267 A TW202425267 A TW 202425267A
Authority
TW
Taiwan
Prior art keywords
lead frame
signal output
signal input
capacitive coupling
plate
Prior art date
Application number
TW111147287A
Other languages
Chinese (zh)
Other versions
TWI843323B (en
Inventor
又法 王
Original Assignee
新加坡商光寶科技新加坡私人有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 新加坡商光寶科技新加坡私人有限公司 filed Critical 新加坡商光寶科技新加坡私人有限公司
Priority to TW111147287A priority Critical patent/TWI843323B/en
Application granted granted Critical
Publication of TWI843323B publication Critical patent/TWI843323B/en
Publication of TW202425267A publication Critical patent/TW202425267A/en

Links

Images

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Microwave Amplifiers (AREA)

Abstract

A capacitor coupling package structure is provided. The capacitor coupling package structure includes a first leadframe, a second leadframe, a plurality of transmitter modules, and a plurality of receiver modules. The second leadframe corresponds to and is aligned with the first leadframe, and a gap is formed therebetween. The plurality of transmitter modules are correspondingly disposed on a first surface of the first leadframe or a second surface of the second leadframe. The plurality of receiver modules are correspondingly disposed on a first surface of the first leadframe or a second surface of the second leadframe. A first signal output pole and a second signal output pole of the transmitter module, and a first signal input pole and a second signal input pole of the receiver module are spaced apart at a predetermined distance respectively through floating leads.

Description

電容耦合封裝結構Capacitively coupled package structure

本發明涉及一種電容耦合封裝結構,特別是涉及一種通過懸浮支架分離設置的多信號通道電容耦合封裝結構。The present invention relates to a capacitive coupling packaging structure, and in particular to a multi-signal channel capacitive coupling packaging structure which is separately arranged by a suspension bracket.

現有電容耦合(capacitive coupling)技術主要將電容器設置於晶片上(on-chip),然而電容器的金屬導體之間的距離不能過大(一般必須小於16 μm),且當電容器設置於晶片上時,晶片的整體面積亦會隨之增加,致使相關產品會具有較大體積。此外,晶片上電容器的隔離電壓也會受限於晶片主體材料(例如二氧化矽)的厚度,因此不易符合特定應用領域的隔離要求。The existing capacitive coupling technology mainly places capacitors on-chip. However, the distance between the metal conductors of the capacitor cannot be too large (generally must be less than 16 μm), and when the capacitor is placed on the chip, the overall area of the chip will also increase, resulting in a larger volume for the related products. In addition, the isolation voltage of the capacitor on the chip is also limited by the thickness of the chip's main material (such as silicon dioxide), so it is not easy to meet the isolation requirements of specific application areas.

故,如何通過結構設計的改良,以使整體電容耦合封裝結構能夠微型化,來克服上述的缺陷,已成為該項事業所欲解決的重要課題之一。Therefore, how to improve the structural design so that the overall capacitor coupling package structure can be miniaturized to overcome the above-mentioned defects has become one of the important issues that the industry wants to solve.

本發明所要解決的技術問題在於,針對現有技術的不足提供一種多信號通道電容耦合封裝結構。The technical problem to be solved by the present invention is to provide a multi-signal channel capacitive coupling packaging structure in view of the shortcomings of the prior art.

為了解決上述的技術問題,本發明所採用的其中一技術方案是提供一種電容耦合封裝結構,其包括一第一引線架、一第二引線架、多個傳送器模組、以及多個接收器模組。第二引線架對應並對準第一引線架,且第一引線架與第二引線架之間具有一間隙。多個傳送器模組分別設置於第一引線架的一第一表面上或第二引線架的一第二表面上。每一傳送器模組包括一傳送器、一信號輸入引腳、一第一信號輸出極板及一第二信號輸出極板。傳送器的一輸入端電性連接信號輸入引腳,傳送器的一輸出端分別電性連接第一信號輸出極板及第二信號輸出極板。多個接收器模組分別設置於第一引線架的第一表面上或第二引線架的第二表面上。每一接收器模組包括一接收器、一信號輸出引腳、一第一信號輸入極板及一第二信號輸入極板。接收器的一輸入端分別電性連接第一信號輸入極板及第二信號輸入極板,接收器的一輸出端電性連接信號輸出引腳。多個接收器模組分別對應多個傳送器模組。第一信號輸入極板、第二信號輸入極板、第一信號輸出極板及第二信號輸出極板分別通過多個懸浮支架分離設置。當任一傳送器模組設置於第一引線架的第一表面上或第二引線架的第二表面上時,任一傳送器模組的對應接收器模組設置於第二引線架的第二表面上或第一引線架的第一表面上。In order to solve the above-mentioned technical problems, one of the technical solutions adopted by the present invention is to provide a capacitive coupling package structure, which includes a first lead frame, a second lead frame, a plurality of transmitter modules, and a plurality of receiver modules. The second lead frame corresponds to and is aligned with the first lead frame, and there is a gap between the first lead frame and the second lead frame. The plurality of transmitter modules are respectively arranged on a first surface of the first lead frame or a second surface of the second lead frame. Each transmitter module includes a transmitter, a signal input pin, a first signal output pole plate and a second signal output pole plate. An input end of the transmitter is electrically connected to the signal input pin, and an output end of the transmitter is electrically connected to the first signal output pole plate and the second signal output pole plate, respectively. A plurality of receiver modules are respectively arranged on the first surface of the first lead frame or the second surface of the second lead frame. Each receiver module includes a receiver, a signal output pin, a first signal input pole plate and a second signal input pole plate. An input end of the receiver is electrically connected to the first signal input pole plate and the second signal input pole plate, and an output end of the receiver is electrically connected to the signal output pin. A plurality of receiver modules correspond to a plurality of transmitter modules respectively. The first signal input pole plate, the second signal input pole plate, the first signal output pole plate and the second signal output pole plate are respectively separately arranged through a plurality of suspension brackets. When any transmitter module is disposed on the first surface of the first lead frame or the second surface of the second lead frame, the corresponding receiver module of any transmitter module is disposed on the second surface of the second lead frame or the first surface of the first lead frame.

本發明的其中一有益效果在於,本發明所提供的電容耦合封裝結構,其能通過“第一引線架與所述第二引線架之間具有一間隙”、“第一信號輸入極板、第二信號輸入極板、第一信號輸出極板及第二信號輸出極板分別通過懸浮支架分離設置”、“當任一傳送器模組設置於第一引線架的第一表面上或第二引線架的第二表面上時,任一傳送器模組的對應接收器模組設置於第二引線架的第二表面上或第一引線架的第一表面上” 以及“多個傳送器模組可以不全部設置於第一引線架的第一表面上或第二引線架的第二表面上”的技術方案,不僅提供了多信號通道電容耦合還可提升電容耦合封裝結構製備靈活性及有效減小體積,並可通過調整間隙的距離使整體電容值得以調整。One of the beneficial effects of the present invention is that the capacitive coupling package structure provided by the present invention can be realized by "a gap between the first lead frame and the second lead frame", "the first signal input plate, the second signal input plate, the first signal output plate and the second signal output plate are separately arranged through the suspension bracket", "when any transmitter module is arranged on the first surface of the first lead frame or the second surface of the second lead frame, the corresponding receiver module of any transmitter module is arranged on the second surface of the second lead frame or the first surface of the first lead frame" As well as the technical solution of "multiple transmitter modules may not all be arranged on the first surface of the first lead frame or the second surface of the second lead frame", it not only provides multi-signal channel capacitive coupling but also improves the flexibility of capacitive coupling packaging structure preparation and effectively reduces the volume, and the overall capacitance value can be adjusted by adjusting the distance of the gap.

更進一步來說,本發明所提供的電容耦合封裝結構,傳送器模組還包括至少一功能性半導體元件,至少一功能性半導體元件電性連接於信號輸入引腳與傳送器的輸入端之間,及/或接收器模組還包括至少一功能性半導體元件,至少一功能性半導體元件電性連接於接收器的輸出端與信號輸出引腳之間,可以在有限的結構空間中達到輸出信號的控制。Furthermore, in the capacitive coupling package structure provided by the present invention, the transmitter module further includes at least one functional semiconductor element, at least one functional semiconductor element is electrically connected between the signal input pin and the input end of the transmitter, and/or the receiver module further includes at least one functional semiconductor element, at least one functional semiconductor element is electrically connected between the output end of the receiver and the signal output pin, so that the control of the output signal can be achieved in a limited structural space.

為使能更進一步瞭解本發明的特徵及技術內容,請參閱以下有關本發明的詳細說明與圖式,然而所提供的圖式僅用於提供參考與說明,並非用來對本發明加以限制。To further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are only used for reference and description and are not used to limit the present invention.

以下是通過特定的具體實施例來說明本發明所公開有關“電容耦合封裝結構”的實施方式,本領域技術人員可由本說明書所公開的內容瞭解本發明的優點與效果。本發明可通過其他不同的具體實施例加以施行或應用,本說明書中的各項細節也可基於不同觀點與應用,在不背離本發明的構思下進行各種修改與變更。另外,本發明的附圖僅為簡單示意說明,並非依實際尺寸的描繪,事先聲明。以下的實施方式將進一步詳細說明本發明的相關技術內容,但所公開的內容並非用以限制本發明的保護範圍。另外,本文中所使用的術語“或”,應視實際情況可能包括相關聯的列出項目中的任一個或者多個的組合。The following is an explanation of the implementation of the "capacitive coupling packaging structure" disclosed in the present invention through specific concrete embodiments. Technical personnel in this field can understand the advantages and effects of the present invention from the contents disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed in various ways based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only simple schematic illustrations and are not depicted according to actual sizes. Please note in advance. The following implementation will further explain the relevant technical contents of the present invention in detail, but the disclosed contents are not intended to limit the scope of protection of the present invention. In addition, the term "or" used herein may include any one or more combinations of the associated listed items as appropriate.

[第一實施例][First embodiment]

參閱圖1至圖7所示,本發明第一實施例提供一種電容耦合封裝結構,其包括:一第一引線架1、一第二引線架2、多個傳送器模組3、多個接收器模組4以及一間隔物(封裝體5)。1 to 7 , the first embodiment of the present invention provides a capacitive coupling package structure, which includes: a first lead frame 1, a second lead frame 2, a plurality of transmitter modules 3, a plurality of receiver modules 4 and a spacer (package body 5).

具體來說,第一引線架1與第二引線架2可以具有相同的尺寸,且可由相同的材料製成,但本發明不限於此。此外,在電容耦合封裝結構中,第一引線架1與第二引線架2相互對應並對準,且第一引線架1與第二引線架2之間具有一間隙d,也就是說,第一引線架1可以平行設置在第二引線架2的正上方。在一較佳實施例中,間隙d的距離可以為50 μm至600 μm。值得注意的是,間隙d的距離可以根據實際應用進行調整,進而使整體電容值得以調整。Specifically, the first lead frame 1 and the second lead frame 2 may have the same size and may be made of the same material, but the present invention is not limited thereto. In addition, in the capacitive coupling package structure, the first lead frame 1 and the second lead frame 2 correspond to and align with each other, and there is a gap d between the first lead frame 1 and the second lead frame 2, that is, the first lead frame 1 may be arranged in parallel directly above the second lead frame 2. In a preferred embodiment, the distance of the gap d may be 50 μm to 600 μm. It is worth noting that the distance of the gap d may be adjusted according to the actual application, thereby adjusting the overall capacitance value.

多個傳送器模組3可以分別設置於第一引線架1的第一表面11或第二引線架2的第二表面21,多個接收器模組4可以對應分別設置於第二引線架2的第二表面21或第一引線架1的第一表面11,且多個傳送器模組3及多個接收器模組4都可以通過固晶(die-attach)的方式固定於第一引線架1或第二引線架2。舉例來說,如圖1至圖3所示,傳送器模組3及接收器模組4可以各具有3個,但本發明不限於此。3個傳送器模組3可以皆設置於第一引線架1且3個接收器模組4可以皆設置於第二引線架2(如圖1所示);3個傳送器模組3中的2個傳送器模組3設置於第一引線架1,另1個傳送器模組3設置於第二引線架2,且3個接收器模組4中的2個接收器模組4設置於第二引線架2,另1個接收器模組4設置於第一引線架1(如圖2所示);或3個傳送器模組3中的1個傳送器模組3設置於第一引線架1,另2個傳送器模組3設置於第二引線架2,且3個接收器模組4中的1個接收器模組4設置於第二引線架2,另2個接收器模組4設置於第一引線架1(如圖3所示)。The plurality of transmitter modules 3 may be disposed on the first surface 11 of the first lead frame 1 or the second surface 21 of the second lead frame 2, respectively. The plurality of receiver modules 4 may be disposed on the second surface 21 of the second lead frame 2 or the first surface 11 of the first lead frame 1, respectively, and the plurality of transmitter modules 3 and the plurality of receiver modules 4 may be fixed to the first lead frame 1 or the second lead frame 2 by die-attach. For example, as shown in FIGS. 1 to 3 , the number of transmitter modules 3 and the number of receiver modules 4 may be three, but the present invention is not limited thereto. The three transmitter modules 3 may all be arranged on the first lead frame 1 and the three receiver modules 4 may all be arranged on the second lead frame 2 (as shown in FIG. 1 ); two of the three transmitter modules 3 may be arranged on the first lead frame 1 and the other one of the transmitter modules 3 may be arranged on the second lead frame 2, and two of the three receiver modules 4 may be arranged on the second lead frame 2 and the other one of the receiver modules 4 may be arranged on the first lead frame 1 (as shown in FIG. 2 ); or one of the three transmitter modules 3 may be arranged on the first lead frame 1 and the other two of the transmitter modules 3 may be arranged on the second lead frame 2, and one of the three receiver modules 4 may be arranged on the second lead frame 2 and the other two of the receiver modules 4 may be arranged on the first lead frame 1 (as shown in FIG. 3 ).

傳送器模組3可以分別包含具有傳送信號的晶片。每一傳送器模組3可包括傳送器31、信號輸入引腳32、第一信號輸出極板33及第二信號輸出極板34。傳送器31的輸入端電性連接信號輸入引腳32,傳送器31的輸出端分別電性連接第一信號輸出極板33及第二信號輸出極板34。值得注意的是,傳送器模組3的各個組件可以由相同的導電材料製成,但本發明不限於此。The transmitter module 3 may include chips with transmission signals. Each transmitter module 3 may include a transmitter 31, a signal input pin 32, a first signal output plate 33, and a second signal output plate 34. The input end of the transmitter 31 is electrically connected to the signal input pin 32, and the output end of the transmitter 31 is electrically connected to the first signal output plate 33 and the second signal output plate 34. It is worth noting that each component of the transmitter module 3 may be made of the same conductive material, but the present invention is not limited thereto.

接收器模組4可以含具有接收信號的晶片。每一接收器模組4可包括接收器41、信號輸出引腳42、第一信號輸入極板43及第二信號輸入極板44,接收器41的輸入端分別電性連接第一信號輸入極板43及第二信號輸入極板44,接收器41的輸出端電性連接信號輸出引腳42。值得注意的是,接收器模組4的各個組件可以由相同的導電材料製成,但本發明不限於此。The receiver module 4 may include a chip having a receiving signal. Each receiver module 4 may include a receiver 41, a signal output pin 42, a first signal input plate 43, and a second signal input plate 44. The input end of the receiver 41 is electrically connected to the first signal input plate 43 and the second signal input plate 44, respectively, and the output end of the receiver 41 is electrically connected to the signal output pin 42. It is worth noting that each component of the receiver module 4 may be made of the same conductive material, but the present invention is not limited thereto.

在本發明中,傳送器31可以包含高頻傳送器晶片,且是以差分形式進行信號處理的傳送器晶片。在本發明中,使用差分形式進行信號處理可以使得電容耦合封裝結構符合共模拒斥(common mode rejection,CMR)的需求。因此,由信號輸入引腳32傳送至傳送器31的信號會以差分形式被分別傳送至第一信號輸出極板33以及第二信號輸出極板34,用以與接收器模組4的第一信號輸入極板43及第二信號輸入極板44產生兩個物理鏈接(physical link),而兩個物理鏈接形成一個信號通道(channel)。每一信號通道中的傳送器31及接收器41通過第一信號輸出極板33、第二信號輸出極板34、第一信號輸入極板43及第二信號輸入極板44所形成的電容而彼此電性絕緣(galvanically isolated/DC isolated),而高頻信號則可以藉由電容耦合而通過電容所形成之阻礙(barrier)。In the present invention, the transmitter 31 may include a high-frequency transmitter chip, and is a transmitter chip that performs signal processing in a differential form. In the present invention, using a differential form to perform signal processing can make the capacitive coupling package structure meet the requirements of common mode rejection (CMR). Therefore, the signal transmitted from the signal input pin 32 to the transmitter 31 will be transmitted to the first signal output plate 33 and the second signal output plate 34 in a differential form, respectively, to generate two physical links with the first signal input plate 43 and the second signal input plate 44 of the receiver module 4, and the two physical links form a signal channel. The transmitter 31 and the receiver 41 in each signal channel are galvanically isolated/DC isolated from each other through the capacitor formed by the first signal output plate 33, the second signal output plate 34, the first signal input plate 43 and the second signal input plate 44, and the high-frequency signal can pass through the barrier formed by the capacitor through capacitive coupling.

間隔物設置於第一引線架1及第二引線架2的間隙d,換言之,本實施例的間隔物可以為一封裝體5,封裝體5包覆第一引線架1及第二引線架2,且封裝體5填充充實於間隙d。封裝體5可以由模塑膠所形成,也可由模塑膠混合絕緣材料所形成,使得第一引線架1與第二引線架2彼此電性隔離,但本發明的封裝體5的絕緣材料可以根據實際需求進行調整。在一較佳實施例,封裝體5可以由環氧樹脂或矽氧樹脂所形成。The spacer is disposed in the gap d between the first lead frame 1 and the second lead frame 2. In other words, the spacer of the present embodiment can be a package 5, which covers the first lead frame 1 and the second lead frame 2, and the package 5 fills the gap d. The package 5 can be formed by molding glue, or by molding glue mixed with insulating materials, so that the first lead frame 1 and the second lead frame 2 are electrically isolated from each other, but the insulating material of the package 5 of the present invention can be adjusted according to actual needs. In a preferred embodiment, the package 5 can be formed by epoxy resin or silicone resin.

更進一步,第一引線架1的第一表面11與第二引線架2的第二表面21可以朝向相同方向或不同方向。舉例來說,在一實施例中,如圖4所示,第一表面11與第二表面21朝向相同方向,亦即,傳送器模組3與接收器模組4分別設置在第一引線架1的上表面(第一表面11)及第二引線架2的上表面(第二表面21)。在另一實施例中,如圖5所示,第一表面11與第二表面21朝向不同方向,亦即,傳送器模組3與接收器模組4分別設置在第一引線架1的下表面(第一表面11)及第二引線架2的上表面(第二表面21),或者,傳送器模組3與接收器模組4分別設置在第一引線架1的上表面(第一表面11)及第二引線架2的下表面(第二表面21)。值得注意的是,第一引線架1的第一表面11與第二引線架2的第二表面21的設置可以根據實際應用進行調整,本發明不限於此。Furthermore, the first surface 11 of the first lead frame 1 and the second surface 21 of the second lead frame 2 may face the same direction or different directions. For example, in one embodiment, as shown in FIG. 4 , the first surface 11 and the second surface 21 face the same direction, that is, the transmitter module 3 and the receiver module 4 are respectively disposed on the upper surface (first surface 11) of the first lead frame 1 and the upper surface (second surface 21) of the second lead frame 2. In another embodiment, as shown in FIG. 5 , the first surface 11 and the second surface 21 face different directions, that is, the transmitter module 3 and the receiver module 4 are respectively disposed on the lower surface (first surface 11) of the first lead frame 1 and the upper surface (second surface 21) of the second lead frame 2, or the transmitter module 3 and the receiver module 4 are respectively disposed on the upper surface (first surface 11) of the first lead frame 1 and the lower surface (second surface 21) of the second lead frame 2. It is worth noting that the arrangement of the first surface 11 of the first lead frame 1 and the second surface 21 of the second lead frame 2 can be adjusted according to actual applications, and the present invention is not limited thereto.

值得一提的是,本發明的電容耦合封裝結構還可以包括至少一功能性半導體元件E。在一實施例中,功能性半導體元件E可以電性連接於信號輸入引腳32與傳送器31的輸入端之間。在另一實施例中,如圖6及圖7所示,功能性半導體元件E可以電性連接於接收器41的輸出端與信號輸出引腳42之間。在又一實施例中,功能性半導體元件E可以為2個,其中一個功能性半導體元件E電性連接於信號輸入引腳32與傳送器31的輸入端之間,另一功能性半導體元件E電性連接於接收器41的輸出端與信號輸出引腳42之間。此外,功能性半導體元件E可以根據實際應用擇用,舉例來說,功能性半導體元件E可以為絕緣柵雙極電晶體(Insulated Gate Bipolar Transistor,IGBT)、數位類比轉換器電路(Digital to analog converter,DAC)或類比數位轉換器電路(Analog to Digital converter,ADC)等。It is worth mentioning that the capacitive coupling package structure of the present invention may further include at least one functional semiconductor element E. In one embodiment, the functional semiconductor element E may be electrically connected between the signal input pin 32 and the input end of the transmitter 31. In another embodiment, as shown in FIG6 and FIG7 , the functional semiconductor element E may be electrically connected between the output end of the receiver 41 and the signal output pin 42. In yet another embodiment, there may be two functional semiconductor elements E, one of which is electrically connected between the signal input pin 32 and the input end of the transmitter 31, and the other functional semiconductor element E is electrically connected between the output end of the receiver 41 and the signal output pin 42. In addition, the functional semiconductor element E can be selected according to the actual application. For example, the functional semiconductor element E can be an insulated gate bipolar transistor (IGBT), a digital to analog converter circuit (DAC), or an analog to digital converter circuit (ADC).

進一步,如圖6所示,功能性半導體元件E可以集成設置於接收器模組4,接收器模組4檢測來自傳送器31的調制高頻信號後可對其進行解調,使其恢復為傳輸控制信號以輸出至功能性半導體元件E。另一方面,如圖7所示,功能性半導體元件E也可以不與接收器模組4集成設置,亦即接收器模組4與功能性半導體元件E是分開的獨立結構,接收器模組4檢測來自傳送器31的調制高頻信號後可對其進行解調,使其恢復為傳輸控制信號再將控制信號輸出至功能性半導體元件E。Furthermore, as shown in FIG6 , the functional semiconductor element E can be integrated in the receiver module 4. After the receiver module 4 detects the modulated high-frequency signal from the transmitter 31, it can demodulate it and restore it to a transmission control signal to output to the functional semiconductor element E. On the other hand, as shown in FIG7 , the functional semiconductor element E can also be not integrated with the receiver module 4, that is, the receiver module 4 and the functional semiconductor element E are separate independent structures. After the receiver module 4 detects the modulated high-frequency signal from the transmitter 31, it can demodulate it and restore it to a transmission control signal and then output the control signal to the functional semiconductor element E.

更進一步,在本實施例中,如圖8所示,3個傳送器模組3設置於第一引線架1的第一表面11,3個接收器模組4對應設置於第二引線架2的第二表面21,以形成具有3個通道(即第一通道、第二通道及第三通道)的多信號通道電容耦合封裝結構。本實施例中,3個傳送器模組3可以集成於一個IC 晶片,同樣地,3個接收器模組4 可以集成於一個IC 晶片,減少成本以及封裝的尺寸。進行封裝時第一引線架1的第一表面11與所述第二引線架2的第二表面21朝向相同方向,平移第一引線架1或第二引線架2,則3個通道個別的第一信號輸出極板33(即圖8上半部所示之C1+、C2+及C3+;C1+、C2+及C3+是物理上相互不連接的,各自獨立的極板 )、第二信號輸出極板34(即圖8上半部所示之C1-、C2-及C3-; C1-、C2-及C3-是物理上相互不連接的,各自獨立的極板)、第一信號輸入極板43(即圖8下半部所示之C1+、C2+及C3+;C1+、C2+及C3+是物理上相互不連接的,各自獨立的極板。)及第二信號輸入極板44(即圖8下半部所示之C1-、C2-及C3-;C1-、C2-及C3-是物理上相互不連接的,各自獨立的極板)可以分別通過對應的懸浮支架FL(floating lead)懸浮設置於封裝體5,且第一信號輸出極板33與第一信號輸入極板43彼此對準,第二信號輸出極板34與第二信號輸入極板44彼此對準。此外,第一引線架1可以通過多個彼此分離的第一引腳12設置於封裝體5,第二引線架2可以通過多個彼此分離的第二引腳22設置於封裝體5,且第一引線架1與第二引線架2於封裝體5中相互對應並對準。在一實施例中,如圖8所示,當第一信號輸出極板33、第二信號輸出極板34、第一信號輸入極板43及第二信號輸入極板44分別通過對應的懸浮支架FL懸浮設置於封裝體5時,懸浮支架FL在投影面上的投影可以平行於多個第一引腳12及多個第二引腳22。也就是說,如圖8所示,第一信號輸出極板33及第二信號輸出極板34沿第一引線架1的一長度方向排列,第一信號輸入極板43及第二信號輸入極板44沿第二引線架2的一長度方向排列。在一較佳實施例,任一個懸浮支架FL在投影面上的投影對應於其所對應的相鄰的兩個第一引腳12之間的一中心線或其所對應的相鄰的兩個第二引腳22之間的一中心線,也就是說,自本發明的電容耦合封裝結構的上方觀察時,懸浮支架FL是設置在相鄰的兩個第一引腳12的間隔距離的中點或相鄰的兩個第二引腳22的間隔距離的中點。Furthermore, in this embodiment, as shown in FIG8 , three transmitter modules 3 are disposed on the first surface 11 of the first lead frame 1, and three receiver modules 4 are correspondingly disposed on the second surface 21 of the second lead frame 2, so as to form a multi-signal channel capacitive coupling package structure having three channels (i.e., a first channel, a second channel, and a third channel). In this embodiment, the three transmitter modules 3 can be integrated into one IC chip, and similarly, the three receiver modules 4 can be integrated into one IC chip, thereby reducing the cost and the size of the package. During packaging, the first surface 11 of the first lead frame 1 and the second surface 21 of the second lead frame 2 face the same direction. By translating the first lead frame 1 or the second lead frame 2, the first signal output plates 33 (i.e., C1+, C2+, and C3+ shown in the upper half of FIG. 8; C1+, C2+, and C3+ are physically not connected to each other and are independent plates) and the second signal output plates 34 (i.e., C1-, C2-, and C3- shown in the upper half of FIG. 8; C1-, C2- and C3- are physically not connected to each other and are independent poles), the first signal input pole plate 43 (i.e., C1+, C2+ and C3+ shown in the lower half of FIG. 8; C1+, C2+ and C3+ are physically not connected to each other and are independent poles) and the second signal input pole plate 44 (i.e., C1-, C2- and C3- shown in the lower half of FIG. 8; C1-, C2- and C3- are physically not connected to each other and are independent poles) can be suspended on the package body 5 through corresponding suspension brackets FL (floating lead), and the first signal output pole plate 33 is aligned with the first signal input pole plate 43, and the second signal output pole plate 34 is aligned with the second signal input pole plate 44. In addition, the first lead frame 1 can be disposed on the package body 5 through a plurality of first leads 12 separated from each other, and the second lead frame 2 can be disposed on the package body 5 through a plurality of second leads 22 separated from each other, and the first lead frame 1 and the second lead frame 2 correspond to and align with each other in the package body 5. In one embodiment, as shown in FIG8 , when the first signal output electrode 33, the second signal output electrode 34, the first signal input electrode 43, and the second signal input electrode 44 are suspended on the package body 5 through corresponding suspension brackets FL, respectively, the projection of the suspension bracket FL on the projection plane can be parallel to the plurality of first leads 12 and the plurality of second leads 22. That is, as shown in FIG8 , the first signal output electrode 33 and the second signal output electrode 34 are arranged along a length direction of the first lead frame 1, and the first signal input electrode 43 and the second signal input electrode 44 are arranged along a length direction of the second lead frame 2. In a preferred embodiment, the projection of any suspension bracket FL on the projection plane corresponds to a center line between two adjacent first pins 12 corresponding thereto or a center line between two adjacent second pins 22 corresponding thereto, that is, when the capacitive coupling package structure of the present invention is observed from above, the suspension bracket FL is disposed at the midpoint of the spacing distance between two adjacent first pins 12 or the midpoint of the spacing distance between two adjacent second pins 22.

然而,上述所舉的例子只是其中一可行的實施例而並非用以限定本發明。However, the above example is only a feasible embodiment and is not intended to limit the present invention.

[第二實施例][Second embodiment]

參閱圖9所示,圖9為本發明第二實施例的電容耦合封裝結構的示意圖。第二實施例與第一實施例主要不同之處在於懸浮支架FL的設置方式。另外,須說明的是,第二實施例的電容耦合封裝結構的其他結構與第一實施例相仿,在此不再贅述。Referring to FIG. 9, FIG. 9 is a schematic diagram of a capacitive coupling package structure of the second embodiment of the present invention. The second embodiment differs from the first embodiment mainly in the arrangement of the suspension bracket FL. In addition, it should be noted that the other structures of the capacitive coupling package structure of the second embodiment are similar to those of the first embodiment, and will not be described in detail here.

在本實施例中,如圖9所示,3個傳送器模組3設置於第一引線架1的第一表面11,3個接收器模組4對應設置於第二引線架2的第二表面21,以形成具有3個通道(即第一通道、第二通道及第三通道)的多信號通道電容耦合封裝結構。進行封裝時第一引線架1可以相對軸X進行翻轉以使第一引線架1設置於第二引線架2的正上方,也就是使得第一引線架1的第一表面11與所述第二引線架2的第二表面21相互面對,則設置於第一引線架1的第一通道上的第一信號輸出極板33(即圖9上半部所示之C1+)及第二信號輸出極板34(即圖9上半部所示之C1-)能夠分別與設置於對應第二引線架2的第一通道上的第一信號輸入極板43(即圖9下半部所示之C1+)及第二信號輸入極板44(即圖9下半部所示之C1-)彼此對應,第一引線架1的第二通道上的第一信號輸出極板33(即圖9上半部所示之C2+)及第二信號輸出極板34(即圖9上半部所示之C2-)能夠分別與設置於對應第二引線架2的第二通道上的第一信號輸入極板43(即圖9下半部所示之C2+)及第二信號輸入極板44(即圖9下半部所示之C2-)彼此對應,且第一引線架1的第三通道上的第一信號輸出極板33(即圖9上半部所示之C3+)及第二信號輸出極板34(即圖9上半部所示之C3-)能夠分別與設置於對應第二引線架2的第三通道的第一信號輸入極板43(即圖9下半部所示之C3+)及第二信號輸入極板44(即圖9下半部所示之C3-)彼此對應。In this embodiment, as shown in FIG. 9 , three transmitter modules 3 are disposed on the first surface 11 of the first lead frame 1, and three receiver modules 4 are correspondingly disposed on the second surface 21 of the second lead frame 2 to form a multi-signal channel capacitive coupling package structure having three channels (i.e., a first channel, a second channel, and a third channel). During packaging, the first lead frame 1 can be flipped relative to the axis X so that the first lead frame 1 is arranged directly above the second lead frame 2, that is, the first surface 11 of the first lead frame 1 and the second surface 21 of the second lead frame 2 face each other, and the first signal output plate 33 (i.e., C1+ shown in the upper half of FIG. 9) and the second signal output plate 34 (i.e., C1- shown in the upper half of FIG. 9) arranged on the first channel of the first lead frame 1 can correspond to the first signal input plate 43 (i.e., C1+ shown in the lower half of FIG. 9) and the second signal input plate 44 (i.e., C1- shown in the lower half of FIG. 9) arranged on the first channel of the corresponding second lead frame 2, respectively, and the first signal output plate 33 (i.e., C1+ shown in the lower half of FIG. 9) on the second channel of the first lead frame 1 can correspond to each other. 9) and the second signal output electrode 34 (i.e., C2- shown in the upper half of FIG. 9) can respectively correspond to the first signal input electrode 43 (i.e., C2+ shown in the lower half of FIG. 9) and the second signal input electrode 44 (i.e., C2- shown in the lower half of FIG. 9) arranged on the second channel corresponding to the second lead frame 2, and the first signal output electrode 33 (i.e., C3+ shown in the upper half of FIG. 9) and the second signal output electrode 34 (i.e., C3- shown in the upper half of FIG. 9) on the third channel of the first lead frame 1 can respectively correspond to the first signal input electrode 43 (i.e., C3+ shown in the lower half of FIG. 9) and the second signal input electrode 44 (i.e., C3- shown in the lower half of FIG. 9) arranged on the third channel corresponding to the second lead frame 2.

然而,上述所舉的例子只是其中一可行的實施例而並非用以限定本發明。However, the above example is only a feasible embodiment and is not intended to limit the present invention.

[第三實施例][Third Embodiment]

參閱圖10所示,圖10為本發明第三實施例的電容耦合封裝結構的示意圖。第三實施例與第一實施例主要不同之處在於懸浮支架FL的設置方式。另外,須說明的是,第三實施例的電容耦合封裝結構的其他結構與第一實施例及第二實施例相仿,在此不再贅述。Referring to FIG. 10 , FIG. 10 is a schematic diagram of a capacitive coupling package structure of the third embodiment of the present invention. The third embodiment differs from the first embodiment mainly in the arrangement of the suspension bracket FL. In addition, it should be noted that the other structures of the capacitive coupling package structure of the third embodiment are similar to those of the first and second embodiments, and will not be described in detail here.

在本實施例中,如圖10所示,4個傳送器模組3設置於第一引線架1的第一表面11,4個接收器模組4對應設置於第二引線架2的第二表面21,以形成具有4個通道(即第一通道、第二通道、第三通道及第四通道)的多信號通道電容耦合封裝結構。進行封裝時第一引線架1的第一表面11與所述第二引線架2的第二表面21朝向相同方向,平移第一引線架1或第二引線架2,使得第一信號輸出極板33(即圖10上半部所示之C1+、C2+、C3+及C4+)與第一信號輸入極板43(即圖10下半部所示之C1+、C2+、C3+及C4+)彼此對準,以及第二信號輸出極板34(即圖10上半部所示之C1-、C2-、C3-及C4-)與第二信號輸入極板44(即圖10下半部所示之C1-、C2-、C3-及C4-)彼此對準,且4個通道個別的第一信號輸出極板33、第二信號輸出極板34、第一信號輸入極板43及第二信號輸入極板44係通過多個懸浮支架FL懸浮設置於封裝體5,其中一部分的懸浮支架FL在投影面上的投影可以平行於多個第一引腳12及多個第二引腳22,其餘部分的懸浮支架FL在投影面上的投影可以垂直於多個第一引腳12及多個第二引腳22,也就是說,懸浮支架FL的設置朝向水準方向或垂直方向。此外,第一引線架1可以通過多個彼此分離的第一引腳12設置於封裝體5,第二引線架2可以通過多個彼此分離的第二引腳22設置於封裝體5。In this embodiment, as shown in FIG. 10 , four transmitter modules 3 are disposed on the first surface 11 of the first lead frame 1, and four receiver modules 4 are correspondingly disposed on the second surface 21 of the second lead frame 2 to form a multi-signal channel capacitive coupling package structure having four channels (i.e., a first channel, a second channel, a third channel, and a fourth channel). During packaging, the first surface 11 of the first lead frame 1 and the second surface 21 of the second lead frame 2 face the same direction, and the first lead frame 1 or the second lead frame 2 is translated so that the first signal output pad 33 (i.e., C1+, C2+, C3+, and C4+ shown in the upper half of FIG. 10) and the first signal input pad 43 (i.e., C1+, C2+, C3+, and C4+ shown in the lower half of FIG. 10) are aligned with each other, and the second signal output pad 34 (i.e., C1-, C2-, C3-, and C4- shown in the upper half of FIG. 10) and the second signal input pad 44 (i.e., C1+, C2+, C3+, and C4+ shown in the lower half of FIG. 10) are aligned with each other. -, C2-, C3- and C4-) are aligned with each other, and the first signal output pole plate 33, the second signal output pole plate 34, the first signal input pole plate 43 and the second signal input pole plate 44 of each of the four channels are suspended on the package body 5 through a plurality of suspension brackets FL, wherein the projection of a part of the suspension bracket FL on the projection plane can be parallel to the plurality of first pins 12 and the plurality of second pins 22, and the projection of the remaining part of the suspension bracket FL on the projection plane can be perpendicular to the plurality of first pins 12 and the plurality of second pins 22, that is, the suspension bracket FL is arranged in a horizontal direction or a vertical direction. In addition, the first lead frame 1 can be disposed on the package body 5 via a plurality of first leads 12 separated from each other, and the second lead frame 2 can be disposed on the package body 5 via a plurality of second leads 22 separated from each other.

對於在投影面上的投影垂直於多個第一引腳12及多個第二引腳22的懸浮支架FL(垂直懸浮支架),為了滿足隔離要求,第一引線架1的垂直懸浮支架與第二引線架2的垂直懸浮支架的爬行間距(creepage distance)必須大於隔離和安全要求的距離。但通常對於小型封裝,垂直懸浮支架的爬行間距不容易滿足隔離和安全要求的距離。為了克服這一問題,可以採用兩次封裝成型(double molding)的技術將懸浮支架密封在第二層封裝膠體內。這樣第一引線架1的垂直懸浮支架與第二引線架2的垂直懸浮支架的間距只需要大於400um,便可以滿足隔離和安全要求了。For the suspended bracket FL (vertical suspended bracket) whose projection on the projection plane is perpendicular to the first plurality of pins 12 and the second plurality of pins 22, in order to meet the isolation requirements, the creepage distance between the vertical suspended bracket of the first lead frame 1 and the vertical suspended bracket of the second lead frame 2 must be greater than the distance required for isolation and safety. However, for small packages, the creepage distance of the vertical suspended bracket is usually not easy to meet the distance required for isolation and safety. In order to overcome this problem, the double molding technology can be used to seal the suspended bracket in the second layer of packaging gel. In this way, the distance between the vertical suspended bracket of the first lead frame 1 and the vertical suspended bracket of the second lead frame 2 only needs to be greater than 400um to meet the isolation and safety requirements.

然而,上述所舉的例子只是其中一可行的實施例而並非用以限定本發明。However, the above example is only a feasible embodiment and is not intended to limit the present invention.

[第四實施例][Fourth embodiment]

參閱圖11所示,圖11為本發明第四實施例的電容耦合封裝結構的示意圖。第四實施例與第三實施例主要不同之處在於傳送器模組3於第一引線架1的第一表面11及接收器模組4於第二引線架2的第二表面21的設置方式。另外,須說明的是,第四實施例的電容耦合封裝結構的其他結構與第一實施例、第二實施例及第三實施例相仿,在此不再贅述。Referring to FIG. 11 , FIG. 11 is a schematic diagram of a capacitive coupling package structure of a fourth embodiment of the present invention. The fourth embodiment differs from the third embodiment mainly in the arrangement of the transmitter module 3 on the first surface 11 of the first lead frame 1 and the receiver module 4 on the second surface 21 of the second lead frame 2. In addition, it should be noted that the other structures of the capacitive coupling package structure of the fourth embodiment are similar to those of the first embodiment, the second embodiment and the third embodiment, and will not be described in detail here.

在本實施例中,如圖11所示,4個傳送器模組3設置於第一引線架1的第一表面11,4個接收器模組4對應設置於第二引線架2的第二表面21,以形成具有4個通道(即第一通道、第二通道、第三通道及第四通道)的多信號通道電容耦合封裝結構。進行封裝時第一引線架1可以相對軸X進行翻轉以使第一引線架1設置於第二引線架2的正上方,也就是使得第一引線架1的第一表面11與所述第二引線架2的第二表面21相互面對,則設置於第一引線架1的第一通道的第一信號輸出極板33(即圖11上半部所示之C1+)及第二信號輸出極板34(即圖11上半部所示之C1-)能夠分別與設置於對應第二引線架2的第一通道的第一信號輸入極板43(即圖11下半部所示之C1+)及第二信號輸入極板44(即圖11下半部所示之C1-)彼此對應,第一引線架1的第二通道的第一信號輸出極板33(即圖11上半部所示之C2+)及第二信號輸出極板34(即圖11上半部所示之C2-)能夠分別與設置於對應第二引線架2的第二通道的第一信號輸入極板43(即圖11下半部所示之C2+)及第二信號輸入極板44(即圖11下半部所示之C2-)彼此對應,第一引線架1的第三通道的第一信號輸出極板33(即圖11上半部所示之C3+)及第二信號輸出極板34(即圖11上半部所示之C3-)能夠分別與設置於對應第二引線架2的第三通道的第一信號輸入極板43(即圖11下半部所示之C3+)及第二信號輸入極板44(即圖11下半部所示之C3-)彼此對應,且第一引線架1的第四通道的第一信號輸出極板33(即圖11上半部所示之C4+)及第二信號輸出極板34(即圖11上半部所示之C4-)能夠分別與設置於對應第二引線架2的第四通道的第一信號輸入極板43(即圖11下半部所示之C4+)及第二信號輸入極板44(即圖11下半部所示之C4-)彼此對應。In this embodiment, as shown in FIG. 11 , four transmitter modules 3 are disposed on the first surface 11 of the first lead frame 1, and four receiver modules 4 are correspondingly disposed on the second surface 21 of the second lead frame 2, so as to form a multi-signal channel capacitive coupling package structure having four channels (i.e., the first channel, the second channel, the third channel, and the fourth channel). During packaging, the first lead frame 1 can be flipped relative to the axis X so that the first lead frame 1 is disposed directly above the second lead frame 2, that is, the first surface 11 of the first lead frame 1 and the second surface 21 of the second lead frame 2 face each other, then the first signal output plate 33 (i.e., C1+ shown in the upper half of FIG. 11 ) and the second signal output plate 34 (i.e., C1- shown in the upper half of FIG. 11 ) disposed on the first channel of the first lead frame 1 can be respectively disposed on the corresponding second lead frame 21. The first signal input plate 43 (i.e., C1+ shown in the lower half of FIG. 11) and the second signal input plate 44 (i.e., C1- shown in the lower half of FIG. 11) of the first channel of the lead frame 2 correspond to each other, and the first signal output plate 33 (i.e., C2+ shown in the upper half of FIG. 11) and the second signal output plate 34 (i.e., C2- shown in the upper half of FIG. 11) of the second channel of the first lead frame 1 can respectively communicate with the first signal input plate 43 (i.e., C2+ shown in the upper half of FIG. 11) of the second channel of the corresponding second lead frame 2. 11) and the second signal input plate 44 (i.e., C2- shown in the lower half of FIG. 11) correspond to each other, and the first signal output plate 33 (i.e., C3+ shown in the upper half of FIG. 11) and the second signal output plate 34 (i.e., C3- shown in the upper half of FIG. 11) of the third channel of the first lead frame 1 can respectively communicate with the first signal input plate 43 (i.e., C3+ shown in the lower half of FIG. 11) and the second signal input plate 44 (i.e., C2- shown in the lower half of FIG. 11) arranged in the third channel corresponding to the second lead frame 2. 11) correspond to each other, and the first signal output pad 33 (i.e., C4+ shown in the upper half of FIG. 11) and the second signal output pad 34 (i.e., C4- shown in the upper half of FIG. 11) of the fourth channel of the first lead frame 1 can respectively correspond to the first signal input pad 43 (i.e., C4+ shown in the lower half of FIG. 11) and the second signal input pad 44 (i.e., C4- shown in the lower half of FIG. 11) arranged at the fourth channel of the corresponding second lead frame 2.

此外,在本實施例中,如圖11所示,當第一信號輸出極板33(即圖11上半部所示之C1+、C2+、C3+及C4+)、第二信號輸出極板34(即圖11上半部所示之C1-、C2-、C3-及C4-)、第一信號輸入極板43(即圖11下半部所示之C1+、C2+、C3+及C4+)及第二信號輸入極板44(即圖11下半部所示之C1-、C2-、C3-及C4-)分別通過懸浮支架FL懸浮設置於封裝體5時,一部分的懸浮支架FL在投影面上的投影可以平行於多個第一引腳12及多個第二引腳22,其餘部分的懸浮支架FL在投影面上的投影可以垂直於多個第一引腳12及多個第二引腳22,也就是說,懸浮支架FL的設置朝向水準方向或垂直方向。In addition, in this embodiment, as shown in FIG. 11, when the first signal output plate 33 (i.e., C1+, C2+, C3+, and C4+ shown in the upper half of FIG. 11), the second signal output plate 34 (i.e., C1-, C2-, C3-, and C4- shown in the upper half of FIG. 11), the first signal input plate 43 (i.e., C1+, C2+, C3+, and C4+ shown in the lower half of FIG. 11) and the second signal input plate 44 (i.e., C1-, C2-, C3-, and C4- shown in the lower half of FIG. 11) are connected to each other, the first signal output plate 33 is connected to the second signal output plate 34 (i.e., C1-, C2-, C3-, and C4- shown in the upper half of FIG. 11), the first signal input plate 43 (i.e., C1+, C2+, C3+, and C4+ shown in the lower half of FIG. 11) and the second signal input plate 44 (i.e., C1-, C2-, C3-, and C4- shown in the lower half of FIG. 11) are connected to each other. When the C1-, C2-, C3- and C4-) shown in the figure are suspended on the package body 5 through the suspension bracket FL respectively, the projection of a part of the suspension bracket FL on the projection plane can be parallel to the multiple first pins 12 and the multiple second pins 22, and the projection of the remaining part of the suspension bracket FL on the projection plane can be perpendicular to the multiple first pins 12 and the multiple second pins 22, that is, the suspension bracket FL is set in the horizontal direction or the vertical direction.

然而,上述所舉的例子只是其中一可行的實施例而並非用以限定本發明。However, the above example is only a feasible embodiment and is not intended to limit the present invention.

[第五實施例][Fifth Embodiment]

參閱圖12所示,圖12為本發明第五實施例的電容耦合封裝結構的示意圖。第五實施例與第一實施例主要不同之處在於懸浮支架FL的設置方式的設置方式。另外,須說明的是,第五實施例的電容耦合封裝結構的其他結構與第一實施例、第二實施例、第三實施例及第四實施例相仿,在此不再贅述。Referring to FIG. 12, FIG. 12 is a schematic diagram of a capacitive coupling package structure of the fifth embodiment of the present invention. The fifth embodiment differs from the first embodiment mainly in the arrangement of the suspension bracket FL. In addition, it should be noted that the other structures of the capacitive coupling package structure of the fifth embodiment are similar to those of the first embodiment, the second embodiment, the third embodiment and the fourth embodiment, and will not be described in detail here.

在本實施例中,如圖12所示,4個傳送器模組3設置於第一引線架1的第一表面11,4個接收器模組4對應設置於第二引線架2的第二表面21,以形成具有4個通道(即第一通道、第二通道、第三通道及第四通道)的多信號通道電容耦合封裝結構。如圖12所示,進行封裝時第一引線架1的第一表面11與所述第二引線架2的第二表面21朝向相同方向,平移第一引線架1或第二引線架2,當第一信號輸出極板33(即圖12上半部所示之C1+、C2+、C3+及C4+)、第二信號輸出極板34(即圖12上半部所示之C1-、C2-、C3-及C4-)、第一信號輸入極板43(即圖12下半部所示之C1+、C2+、C3+及C4+)及第二信號輸入極板44(即圖12下半部所示之C1-、C2-、C3-及C4-)分別通過懸浮支架FL懸浮設置於封裝體5時,懸浮支架FL在投影面上的投影可以垂直於多個第一引腳12及多個第二引腳22。也就是說,如圖12所示,第一信號輸出極板33(即圖12上半部所示之C1+、C2+、C3+及C4+)及第二信號輸出極板34(即圖12上半部所示之C1-、C2-、C3-及C4-)沿第一引線架1的一寬度方向排列,第一信號輸入極板43(即圖12下半部所示之C1+、C2+、C3+及C4+)及第二信號輸入極板44(即圖12下半部所示之C1-、C2-、C3-及C4-)沿第二引線架2的一寬度方向排列。In this embodiment, as shown in FIG12, four transmitter modules 3 are disposed on the first surface 11 of the first lead frame 1, and four receiver modules 4 are correspondingly disposed on the second surface 21 of the second lead frame 2, so as to form a multi-signal channel capacitive coupling package structure having four channels (i.e., the first channel, the second channel, the third channel, and the fourth channel). As shown in FIG12, during packaging, the first surface 11 of the first lead frame 1 and the second surface 21 of the second lead frame 2 face the same direction, and the first lead frame 1 or the second lead frame 2 is translated. When the first signal output plate 33 (i.e., C1+, C2+, C3+, and C4+ shown in the upper half of FIG12) and the second signal output plate 34 (i.e., C1-, C2-, C3-, and C4+ shown in the upper half of FIG12) are connected to the first signal output plate 33, the second signal output plate 34 (i.e., C1-, C2-, C3-, and C4+ shown in the upper half of FIG12) are connected to the second ... 4-), the first signal input plate 43 (i.e., C1+, C2+, C3+, and C4+ as shown in the lower half of FIG. 12) and the second signal input plate 44 (i.e., C1-, C2-, C3-, and C4- as shown in the lower half of FIG. 12) are suspended on the package body 5 through the suspension bracket FL respectively, and the projection of the suspension bracket FL on the projection plane can be perpendicular to the plurality of first pins 12 and the plurality of second pins 22. That is, as shown in Figure 12, the first signal output pole plate 33 (i.e., C1+, C2+, C3+ and C4+ shown in the upper half of Figure 12) and the second signal output pole plate 34 (i.e., C1-, C2-, C3- and C4- shown in the upper half of Figure 12) are arranged along a width direction of the first lead frame 1, and the first signal input pole plate 43 (i.e., C1+, C2+, C3+ and C4+ shown in the lower half of Figure 12) and the second signal input pole plate 44 (i.e., C1-, C2-, C3- and C4- shown in the lower half of Figure 12) are arranged along a width direction of the second lead frame 2.

綜上所述,N個通道的多信號通道電容耦合封裝結構需對應設置2*M*N個懸浮支架FL(floating lead),N,M≥2。In summary, a multi-signal channel capacitive coupling package structure with N channels needs to be equipped with 2*M*N floating leads FL (floating leads), where N, M≥2.

舉例來說,當通道為三個(N=3)且信號輸出/輸入極板的數量M為2,則信號輸出側的懸浮支架與對應信號輸入側的懸浮支架皆為6個(即圖8-9上下半部所示之C1+、C1-、C2+、C2-、C3+及C3-各自對應且獨立的懸浮支架FL),上下加總為12個。當通道為四個(N=4)且信號輸出/輸入極板的數量M為2,則信號輸出側的懸浮支架與對應信號輸入側的懸浮支架皆為8個(即圖10-12上下半部所示之C1+、C1-、C2+、C2-、C3+、C3-、C4+及C4-各自對應且獨立的懸浮支架FL),上下加總為16個。For example, when there are three channels (N=3) and the number of signal output/input poles M is 2, the number of suspension brackets on the signal output side and the corresponding signal input side are both 6 (i.e., the independent suspension brackets FL corresponding to C1+, C1-, C2+, C2-, C3+ and C3- shown in the upper and lower halves of Figure 8-9), totaling 12. When there are four channels (N=4) and the number of signal output/input poles M is 2, the number of suspension brackets on the signal output side and the corresponding signal input side are both 8 (i.e., the independent suspension brackets FL corresponding to C1+, C1-, C2+, C2-, C3+, C3-, C4+ and C4- shown in the upper and lower halves of Figure 10-12), totaling 16.

然而,上述所舉的例子只是其中一可行的實施例而並非用以限定本發明。However, the above example is only a feasible embodiment and is not intended to limit the present invention.

[第六實施例][Sixth Embodiment]

本發明的電容耦合封裝結構可以根據實際應用而使用不同的製程製得。舉例來說,本發明的電容耦合封裝結構可以先形成電路基板,之後進行電路集成,最後再進行封裝製程而完成電容耦合封裝結構。The capacitive coupling package structure of the present invention can be manufactured using different processes according to actual applications. For example, the capacitive coupling package structure of the present invention can first form a circuit substrate, then perform circuit integration, and finally perform a packaging process to complete the capacitive coupling package structure.

在一實施例中,傳送器模組3與接收器模組4設置可設置於同一基板的相對表面上,基板為介電質材料,每個第一引腳12的一部分及每個第二引腳22的一部分被介電質材料所包圍或設置於介電質材料表面,且介電質材料的上表面及下表面可形成圖案化導電材料層,亦即傳送器模組3與接收器模組4分別設置於圖案化導電材料層,之後再進行封裝製程而完成電容耦合封裝結構。In one embodiment, the transmitter module 3 and the receiver module 4 can be arranged on opposite surfaces of the same substrate, the substrate is a dielectric material, a portion of each first pin 12 and a portion of each second pin 22 are surrounded by the dielectric material or arranged on the surface of the dielectric material, and the upper surface and the lower surface of the dielectric material can form a patterned conductive material layer, that is, the transmitter module 3 and the receiver module 4 are respectively arranged on the patterned conductive material layer, and then the packaging process is performed to complete the capacitive coupling packaging structure.

或者,傳送器模組3與接收器模組4設置可設置於不同基板的任一表面,每個第一引腳12的一部分及每個第二引腳22的一部分可分別設置不同的基板上,每個第一引腳12的一部分設置於第一基板上、每個第二引腳22的一部分設置於第二基板上,第一基板和第二基板為介電質材料,每個第一引腳12的另一部分及每個第二引腳22的另一部分分別被介電質材料所包圍或設置於介電質材料表面(亦即可將介電質材料層視為本發明前述實施例的第一引線架1與第二引線架2),且介電質材料的上表面及下表面可形成圖案化導電材料,亦即傳送器模組3與接收器模組4分別設置於圖案化導電材料,進一步而言,如圖4或圖5所示,傳送器模組3與接收器模組4設置在朝向相同或不同方向的兩個不同基板表面上,以第一基板或第二基板或二者的組合作為間隔物,亦即介電質材料設置於傳送器模組3與接收器模組4之間,而提供間隙d後,之後再進行封裝製程而完成電容耦合封裝結構。Alternatively, the transmitter module 3 and the receiver module 4 may be disposed on any surface of different substrates, a portion of each first pin 12 and a portion of each second pin 22 may be disposed on different substrates, a portion of each first pin 12 is disposed on the first substrate, a portion of each second pin 22 is disposed on the second substrate, the first substrate and the second substrate are dielectric materials, another portion of each first pin 12 and another portion of each second pin 22 are respectively surrounded by the dielectric material or disposed on the surface of the dielectric material (that is, the dielectric material layer can be regarded as the aforementioned embodiment of the present invention). The first lead frame 1 and the second lead frame 2 are provided, and the upper surface and the lower surface of the dielectric material can form a patterned conductive material, that is, the transmitter module 3 and the receiver module 4 are respectively arranged on the patterned conductive material. Further, as shown in FIG. 4 or FIG. 5, the transmitter module 3 and the receiver module 4 are arranged on two different substrate surfaces facing the same or different directions, with the first substrate or the second substrate or a combination of the two as a spacer, that is, the dielectric material is arranged between the transmitter module 3 and the receiver module 4, and after providing a gap d, a packaging process is then performed to complete the capacitive coupling packaging structure.

在一實施例中,介電質材料可以為陶瓷材料所製成,較佳地,陶瓷材料可以為氮化鋁、氧化鋁或其任意組合,但本發明不限於此。在一實施例中,導電材料層可以為銅所製成,但本發明不限於此。In one embodiment, the dielectric material can be made of a ceramic material, preferably, the ceramic material can be aluminum nitride, aluminum oxide or any combination thereof, but the present invention is not limited thereto. In one embodiment, the conductive material layer can be made of copper, but the present invention is not limited thereto.

然而,上述所舉的例子只是其中一可行的實施例而並非用以限定本發明。However, the above example is only a feasible embodiment and is not intended to limit the present invention.

[實施例的有益效果][Beneficial Effects of Embodiments]

本發明的其中一有益效果在於,本發明所提供的電容耦合封裝結構,其能通過“第一引線架與所述第二引線架之間具有一間隙”、“第一信號輸入極板、第二信號輸入極板、第一信號輸出極板及第二信號輸出極板分別通過懸浮支架設置於間隔物”、“當任一傳送器模組設置於第一引線架的第一表面上或第二引線架的第二表面上時,任一傳送器模組的對應接收器模組設置於第二引線架的第二表面上或第一引線架的第一表面上” 以及“多個傳送器模組可以不全部設置於第一引線架的第一表面上或第二引線架的第二表面上”的技術方案,不僅提供多信號通道電容耦合還可提升電容耦合封裝結構製備靈活性及有效減小體積,並可通過調整間隙的距離使整體電容值得以調整。One of the beneficial effects of the present invention is that the capacitive coupling package structure provided by the present invention can be realized by "a gap between the first lead frame and the second lead frame", "the first signal input plate, the second signal input plate, the first signal output plate and the second signal output plate are respectively arranged on the spacer through the suspension bracket", "when any transmitter module is arranged on the first surface of the first lead frame or the second surface of the second lead frame, the corresponding receiver module of any transmitter module is arranged on the second surface of the second lead frame or the first surface of the first lead frame" As well as the technical solution of "multiple transmitter modules may not all be arranged on the first surface of the first lead frame or the second surface of the second lead frame", it not only provides multi-signal channel capacitive coupling but also enhances the flexibility of capacitive coupling packaging structure preparation and effectively reduces the volume, and the overall capacitance value can be adjusted by adjusting the distance of the gap.

更進一步來說,本發明所提供的電容耦合封裝結構,傳送器模組還包括至少一功能性半導體元件,至少一功能性半導體元件電性連接於信號輸入引腳與傳送器的輸入端之間,及/或接收器模組還包括至少一功能性半導體元件,至少一功能性半導體元件電性連接於接收器的輸出端與信號輸出引腳之間,可以在有限的結構空間中達到輸出信號的控制。Furthermore, in the capacitive coupling package structure provided by the present invention, the transmitter module further includes at least one functional semiconductor element, at least one functional semiconductor element is electrically connected between the signal input pin and the input end of the transmitter, and/or the receiver module further includes at least one functional semiconductor element, at least one functional semiconductor element is electrically connected between the output end of the receiver and the signal output pin, so that the control of the output signal can be achieved in a limited structural space.

以上所公開的內容僅為本發明的優選可行實施例,並非因此侷限本發明的申請專利範圍,所以凡是運用本發明說明書及圖式內容所做的等效技術變化,均包含於本發明的申請專利範圍內。The contents disclosed above are only preferred feasible embodiments of the present invention and are not intended to limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made using the contents of the specification and drawings of the present invention are included in the scope of the patent application of the present invention.

1:第一引線架 11:第一表面 12:第一引腳 2:第二引線架 21:第二表面 22:第二引腳 3:傳送器模組 31:傳送器 32:信號輸入引腳 33:第一信號輸入極板 34:第二信號輸入極板 4:接收器模組 41:接收器 42:信號輸出引腳 43:第一信號輸出極板 44:第二信號輸出極板 5:封裝體 C1+、C2+、C3+、C4+:第一信號輸入極板/第一信號輸出極板 C1-、C2-、C3-、C4-:第二信號輸入極板/第二信號輸出極板 d:間隙 E:功能性半導體元件 FL:懸浮支架 X:軸 1: First lead frame 11: First surface 12: First lead 2: Second lead frame 21: Second surface 22: Second lead 3: Transmitter module 31: Transmitter 32: Signal input pin 33: First signal input plate 34: Second signal input plate 4: Receiver module 41: Receiver 42: Signal output pin 43: First signal output plate 44: Second signal output plate 5: Package C1+, C2+, C3+, C4+: First signal input plate/First signal output plate C1-, C2-, C3-, C4-: Second signal input plate/Second signal output plate d: gap E: functional semiconductor element FL: suspension bracket X: axis

圖1至圖3為本發明第一實施例的電容耦合封裝結構的傳送器模組及接收器模組的設置示意圖。1 to 3 are schematic diagrams of the configuration of a transmitter module and a receiver module of a capacitive coupling package structure according to a first embodiment of the present invention.

圖4為本發明一實施例的電容耦合封裝結構的示意圖。FIG. 4 is a schematic diagram of a capacitive coupling packaging structure according to an embodiment of the present invention.

圖5為本發明另一實施例的電容耦合封裝結構的示意圖。FIG. 5 is a schematic diagram of a capacitive coupling packaging structure according to another embodiment of the present invention.

圖6為本發明第一實施例的電容耦合封裝結構設置有的功能性半導體元件的示意圖。FIG6 is a schematic diagram of a functional semiconductor element provided in the capacitive coupling package structure of the first embodiment of the present invention.

圖7為本發明第一實施例的電容耦合封裝結構設置有的功能性半導體元件的另一示意圖。FIG. 7 is another schematic diagram of a functional semiconductor element provided in the capacitive coupling package structure of the first embodiment of the present invention.

圖8為本發明第一實施例的電容耦合封裝結構的示意圖。FIG8 is a schematic diagram of a capacitive coupling packaging structure according to the first embodiment of the present invention.

圖9為本發明第二實施例的電容耦合封裝結構的示意圖。FIG9 is a schematic diagram of a capacitive coupling packaging structure according to a second embodiment of the present invention.

圖10為本發明第三實施例的電容耦合封裝結構的示意圖。FIG. 10 is a schematic diagram of a capacitive coupling packaging structure according to a third embodiment of the present invention.

圖11為本發明第四實施例的電容耦合封裝結構的示意圖。FIG. 11 is a schematic diagram of a capacitive coupling packaging structure according to a fourth embodiment of the present invention.

圖12為本發明第五實施例的電容耦合封裝結構的示意圖。FIG. 12 is a schematic diagram of a capacitive coupling packaging structure according to a fifth embodiment of the present invention.

1:第一引線架 1: First lead frame

11:第一表面 11: First surface

12:第一引腳 12: First pin

2:第二引線架 2: Second lead frame

21:第二表面 21: Second surface

22:第二引腳 22: Second pin

5:封裝體 5: Package body

C1+、C2+、C3+:第一信號輸入極板/第一信號輸出極板 C1+, C2+, C3+: First signal input plate/first signal output plate

C1-、C2-、C3-:第二信號輸入極板/第二信號輸出極板 C1-, C2-, C3-: Second signal input plate/second signal output plate

FL:懸浮支架 FL: Floating bracket

Claims (16)

一種電容耦合封裝結構,其包括: 一第一引線架; 一第二引線架,所述第二引線架對應並對準所述第一引線架,且所述第一引線架與所述第二引線架之間具有一間隙; 多個傳送器模組,多個所述傳送器模組分別設置於所述第一引線架的一第一表面上或所述第二引線架的一第二表面上,每一所述傳送器模組包括一傳送器、一信號輸入引腳、一第一信號輸出極板及一第二信號輸出極板,所述傳送器的一輸入端電性連接所述信號輸入引腳,所述傳送器的一輸出端分別電性連接所述第一信號輸出極板及所述第二信號輸出極板; 多個接收器模組,多個所述接收器模組分別設置於所述第一引線架的所述第一表面上或所述第二引線架的所述第二表面上,每一所述接收器模組包括一接收器、一信號輸出引腳、一第一信號輸入極板及一第二信號輸入極板,所述接收器的一輸入端分別電性連接所述第一信號輸入極板及所述第二信號輸入極板,所述接收器的一輸出端電性連接所述信號輸出引腳;以及 一間隔物,所述間隔物設置於所述間隙中; 其中,多個所述接收器模組分別對應多個所述傳送器模組; 其中,所述第一信號輸入極板、所述第二信號輸入極板、所述第一信號輸出極板及所述第二信號輸出極板分別通過多個懸浮支架設置於所述間隔物; 其中,當任一所述傳送器模組設置於所述第一引線架的所述第一表面上或所述第二引線架的所述第二表面上時,任一所述傳送器模組的對應所述接收器模組設置於所述第二引線架的所述第二表面上或所述第一引線架的所述第一表面上。 A capacitive coupling package structure, comprising: a first lead frame; a second lead frame, the second lead frame corresponds to and aligns with the first lead frame, and there is a gap between the first lead frame and the second lead frame; a plurality of transmitter modules, the plurality of transmitter modules are respectively arranged on a first surface of the first lead frame or a second surface of the second lead frame, each of the transmitter modules comprises a transmitter, a signal input pin, a first signal output plate and a second signal output plate, an input end of the transmitter is electrically connected to the signal input pin, and an output end of the transmitter is respectively electrically connected to the first signal output plate and the second signal output plate; A plurality of receiver modules, wherein the plurality of receiver modules are respectively arranged on the first surface of the first lead frame or the second surface of the second lead frame, each of the receiver modules comprises a receiver, a signal output pin, a first signal input plate and a second signal input plate, an input end of the receiver is respectively electrically connected to the first signal input plate and the second signal input plate, and an output end of the receiver is electrically connected to the signal output pin; and a spacer, wherein the spacer is arranged in the gap; wherein the plurality of receiver modules respectively correspond to the plurality of transmitter modules; wherein the first signal input plate, the second signal input plate, the first signal output plate and the second signal output plate are respectively arranged on the spacer through a plurality of suspension brackets; Wherein, when any of the transmitter modules is disposed on the first surface of the first lead frame or the second surface of the second lead frame, the corresponding receiver module of any of the transmitter modules is disposed on the second surface of the second lead frame or the first surface of the first lead frame. 如請求項1所述的電容耦合封裝結構,其中,所述間隙的一距離為50 μm至600 μm。A capacitive coupling package structure as described in claim 1, wherein a distance of the gap is 50 μm to 600 μm. 如請求項1所述的電容耦合封裝結構,其中,至少一個所述傳送器模組設置於所述第一引線架的所述第一表面及所述第二引線架的所述第二表面中的其中之一。The capacitive coupling package structure as described in claim 1, wherein at least one of the transmitter modules is disposed on one of the first surface of the first lead frame and the second surface of the second lead frame. 如請求項1所述的電容耦合封裝結構,其中,所述第一引線架的所述第一表面與所述第二引線架的所述第二表面朝向相同方向。The capacitive coupling package structure as described in claim 1, wherein the first surface of the first lead frame and the second surface of the second lead frame face the same direction. 如請求項1所述的電容耦合封裝結構,其中,所述第一引線架的所述第一表面與所述第二引線架的所述第二表面朝向不同方向。The capacitive coupling package structure as described in claim 1, wherein the first surface of the first lead frame and the second surface of the second lead frame face different directions. 如請求項1所述的電容耦合封裝結構,其中,所述第一引線架包括多個彼此分離的第一引腳,所述第二引線架包括多個彼此分離的第二引腳,且多個所述懸浮支架在投影面上的投影平行或垂直於多個所述第一引腳及多個所述第二引腳。A capacitive coupling package structure as described in claim 1, wherein the first lead frame includes a plurality of first leads separated from each other, the second lead frame includes a plurality of second leads separated from each other, and the projections of the plurality of suspended supports on the projection plane are parallel or perpendicular to the plurality of first leads and the plurality of second leads. 如請求項6所述的電容耦合封裝結構,其中,所述多個平行於所述第一引腳及多個所述第二引腳的懸浮支架在投影面上的投影對應於其所對應的相鄰的兩個所述第一引腳之間的一中心線或其所對應的相鄰的兩個所述第二引腳之間的一中心線。A capacitive coupling package structure as described in claim 6, wherein the projections of the multiple suspended supports parallel to the first pins and the multiple second pins on the projection plane correspond to a center line between two adjacent first pins corresponding thereto or a center line between two adjacent second pins corresponding thereto. 如請求項6所述的電容耦合封裝結構,其中,所述第一引線架包括多個彼此分離的第一引腳,所述第二引線架包括多個彼此分離的第二引腳,且多個所述懸浮支架的一部份在投影面上的投影平行於多個所述第一引腳及多個所述第二引腳,多個所述懸浮支架的其餘部份在投影面上的投影垂直於多個所述第一引腳及多個所述第二引腳。A capacitive coupling package structure as described in claim 6, wherein the first lead frame includes a plurality of first pins separated from each other, the second lead frame includes a plurality of second pins separated from each other, and a portion of the plurality of suspended supports has a projection on a projection plane parallel to the plurality of first pins and the plurality of second pins, and a remaining portion of the plurality of suspended supports has a projection on a projection plane perpendicular to the plurality of first pins and the plurality of second pins. 如請求項8所述的電容耦合封裝結構,其中,在投影面上的投影垂直於所述第一引腳的多個所述懸浮支架的所述其餘部份中的每一所述懸浮支架及在投影面上的投影垂直於所述第二引腳的多個所述懸浮支架的所述其餘部份中的對應懸浮支架之間的距離至少為400μm。A capacitive coupling package structure as described in claim 8, wherein the distance between each of the suspended supports in the remaining portions of the plurality of suspended supports whose projections on the projection plane are perpendicular to the first pin and the distance between the corresponding suspended supports in the remaining portions of the plurality of suspended supports whose projections on the projection plane are perpendicular to the second pin is at least 400 μm. 如請求項1所述的電容耦合封裝結構,其中,多個所述第一信號輸入極板及多個所述第二信號輸入極板沿所述第一引線架的一長度方向排列,多個所述第一信號輸出極板及多個所述第二信號輸出極板沿所述第二引線架的一長度方向排列,且多個所述第一信號輸入極板分別對應多個所述第一信號輸出極板,多個所述第二信號輸入極板分別對應多個所述第二信號輸出極板。A capacitive coupling packaging structure as described in claim 1, wherein a plurality of the first signal input poles and a plurality of the second signal input poles are arranged along a length direction of the first lead frame, a plurality of the first signal output poles and a plurality of the second signal output poles are arranged along a length direction of the second lead frame, and a plurality of the first signal input poles respectively correspond to a plurality of the first signal output poles, and a plurality of the second signal input poles respectively correspond to a plurality of the second signal output poles. 如請求項1所述的電容耦合封裝結構,其中,多個所述第一信號輸入極板及多個所述第二信號輸入極板沿所述第一引線架的一寬度方向排列,多個所述第一信號輸出極板及多個所述第二信號輸出極板沿所述第二引線架的一寬度方向排列,且多個所述第一信號輸入極板分別對應多個所述第一信號輸出極板,多個所述第二信號輸入極板分別對應多個所述第二信號輸出極板。A capacitive coupling packaging structure as described in claim 1, wherein a plurality of the first signal input poles and a plurality of the second signal input poles are arranged along a width direction of the first lead frame, a plurality of the first signal output poles and a plurality of the second signal output poles are arranged along a width direction of the second lead frame, and a plurality of the first signal input poles respectively correspond to a plurality of the first signal output poles, and a plurality of the second signal input poles respectively correspond to a plurality of the second signal output poles. 如請求項1至11所述的電容耦合封裝結構,更包含至少一功能性半導體元件,設置於所述接收器模組或所述傳送器模組中,所述至少一功能性半導體元件電性連接於所述接收器的所述輸出端與所述信號輸出引腳之間或電性連接於所述信號輸入引腳與所述傳送器的所述輸入端之間。The capacitive coupling package structure as described in claims 1 to 11 further includes at least one functional semiconductor element, which is arranged in the receiver module or the transmitter module, and the at least one functional semiconductor element is electrically connected between the output end of the receiver and the signal output pin or electrically connected between the signal input pin and the input end of the transmitter. 如請求項12中所述的電容耦合封裝結構,其中,所述至少一功能性半導體元件為絕緣柵雙極電晶體(Insulated Gate Bipolar Transistor,IGBT)、數位類比轉換器電路(Digital to analog converter,DAC)或類比數位轉換器電路(Analog to Digital converter,ADC)。A capacitively coupled package structure as described in claim 12, wherein the at least one functional semiconductor element is an insulated gate bipolar transistor (IGBT), a digital to analog converter circuit (DAC) or an analog to digital converter circuit (ADC). 如請求項1至11所述的電容耦合封裝結構,其中,所述間隔物可以為一封裝體,所述封裝體包覆所述第一引線架及所述第二引線架且填充於所述第一引線架及所述第二引線架之間。In the capacitive coupling package structure as described in claims 1 to 11, the spacer may be a package body, which covers the first lead frame and the second lead frame and fills the space between the first lead frame and the second lead frame. 如請求項1至11所述的電容耦合封裝結構,其中,所述間隔物可以為一介電材板或多層陶瓷板, 所述第一信號輸入極板及所述第一信號輸出極板形成於所述間隔物的一表面,所述第二信號輸入極板及所述第二信號輸出極板形成於所述間隔物的另一表面。A capacitive coupling package structure as described in claims 1 to 11, wherein the spacer can be a dielectric material plate or a multi-layer ceramic plate, the first signal input pole plate and the first signal output pole plate are formed on one surface of the spacer, and the second signal input pole plate and the second signal output pole plate are formed on another surface of the spacer. 如請求項1至11所述的電容耦合封裝結構,其中,所述多信號通道定義為N個通道時,則多個所述懸浮支架為2*M*N個懸浮支架,N,M≥2。A capacitive coupling package structure as described in claim items 1 to 11, wherein when the multi-signal channel is defined as N channels, the plurality of the suspension brackets are 2*M*N suspension brackets, N, M≥2.
TW111147287A 2022-12-09 2022-12-09 Capacitor coupling package structure TWI843323B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW111147287A TWI843323B (en) 2022-12-09 2022-12-09 Capacitor coupling package structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW111147287A TWI843323B (en) 2022-12-09 2022-12-09 Capacitor coupling package structure

Publications (2)

Publication Number Publication Date
TWI843323B TWI843323B (en) 2024-05-21
TW202425267A true TW202425267A (en) 2024-06-16

Family

ID=92077115

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111147287A TWI843323B (en) 2022-12-09 2022-12-09 Capacitor coupling package structure

Country Status (1)

Country Link
TW (1) TWI843323B (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI463639B (en) * 2011-01-28 2014-12-01 Xintec Inc Capacitive coupler package structure
US8680690B1 (en) * 2012-12-07 2014-03-25 Nxp B.V. Bond wire arrangement for efficient signal transmission
WO2018009167A1 (en) * 2016-07-02 2018-01-11 Intel Corporation Rlink-on-die interconnect features to enable signaling
TWI642147B (en) * 2018-01-29 2018-11-21 新加坡商光寶新加坡有限公司 Capacitor coupling package structure for capacitive coupling isolator

Also Published As

Publication number Publication date
TWI843323B (en) 2024-05-21

Similar Documents

Publication Publication Date Title
TW419810B (en) Semiconductor device
JP5366932B2 (en) Ultra high-speed signal transmission / reception
US9960671B2 (en) Isolator with reduced susceptibility to parasitic coupling
US9337253B2 (en) Method and apparatus for constructing an isolation capacitor in an integrated circuit
CN105047634A (en) Isolation between semiconductor components
US20100188182A1 (en) Narrowbody Coil Isolator
US20140055217A1 (en) Die-to-die electrical isolation in a semiconductor package
JP2010206798A (en) High voltage isolation dual capacitor communication system
GB2461156A (en) High voltage drive circuit having capacitive isolation
TW201419649A (en) Digital isolator with improved CMTI
JP2004281625A (en) Semiconductor device
JP2005203775A (en) Multichip package
US11387169B2 (en) Transistor with I/O ports in an active area of the transistor
TWI843323B (en) Capacitor coupling package structure
US9742391B2 (en) Single-chip multi-domain galvanic isolation device and method
TWI787679B (en) Monolithic integrated isolator device and system having monolithic isolator
WO2024138964A1 (en) High-voltage capacitive isolator
US20230344467A1 (en) Circuit support structure with integrated isolation circuitry
TW201511215A (en) Stacked package of voltage regulator and method for fabricating the same
CN215600357U (en) SOP8L packaging lead frame with high power density
CN118173509A (en) Capacitive coupling packaging structure
TWI222187B (en) Semiconductor device
TWI642147B (en) Capacitor coupling package structure for capacitive coupling isolator
JPH0499056A (en) Composite integrated circuit chip
US11942402B2 (en) Laminate stacked on die for high voltage isolation capacitor