TW202422840A - Semiconductor device - Google Patents

Abstract

A semiconductor device includes a plurality of active area structures, one or more active devices, and a metal layer. One or more active devices include portions of the plurality of active area structures. A metal layer is formed on the plurality of active area structures and separated from the one or more active devices by one or more dummy gate layers. The metal layer is configured to measure, due to a change of resistance in the metal layer, a temperature of the plurality of active area structures.

Description

Semiconductor components

The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device having a metal layer covering an active area structure.

One method of monitoring the temperature of a semiconductor device includes using a diode or a junction of a bipolar junction transistor (BJT) in an area of the substrate near the transistor structure being measured. Another method of monitoring the temperature of a semiconductor device includes using the gate of the transistor structure to sense the temperature.

One embodiment of the present disclosure is directed to a semiconductor device including a plurality of active area structures, one or more active components, and a metal layer. The one or more active components include portions of the active area structures. The metal layer covers the active area structures and is separated from the one or more active components by one or more virtual gate layers, wherein the metal layer is used to measure the temperature of the active area structures caused by a resistance change in the metal layer.

According to an embodiment of the present disclosure, a semiconductor device is provided, comprising a plurality of active region structures, one or more active components, a first virtual gate layer, a second virtual gate layer, and a metal layer. The one or more active components include multiple portions of the active region structure. The metal layer covers the active region structure and is disposed between the first virtual gate layer and the second virtual gate layer; and is electrically isolated from the active region, wherein the metal layer is used to measure a temperature of the active region structure caused by a resistance change in the metal layer.

According to an embodiment of the present disclosure, a semiconductor device is provided, comprising an active region structure and a first active device and a second active device. The first active device and the second active device include multiple portions of the active region structure, wherein the first active device and the second active device are configured in series. The semiconductor device further comprises a first virtual gate layer, a second virtual gate layer and a metal layer. The first virtual gate layer and the second virtual gate layer are configured between the first active device and the second active device. The metal layer covers the active region structure and is configured between the first virtual gate layer and the second virtual gate layer. The metal layer is used to measure a temperature of the active area structure due to a resistance change in the metal layer.

The following disclosure provides many different embodiments or examples for implementing the different features of the provided targets. Specific examples of components, values, steps, materials, arrangements, etc. are described below to simplify the content of an embodiment of the present disclosure. Of course, these are only examples and are intended to be restrictive. Other components, values, operations, materials, arrangements, etc. can be imagined. For example, forming a first feature above or on a second feature in the following description can include an embodiment in which the first feature and the second feature are formed to be in direct contact, and can also include an embodiment in which additional features can be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, an embodiment of the present disclosure can repeatedly refer to numbers and/or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the various embodiments and/or configurations discussed.

Additionally, spatially relative terms such as "below," "below," "lower," "above," "upper," etc. may be used herein to simplify the description to describe the relationship of one element or feature to another element or feature as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device/element in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

One or more embodiments of the present disclosure include methods for on-chip temperature measurement/monitoring of three-dimensional (3D) active devices, such as 3D metal oxide semiconductor field effect transistors (MOSFET), fin field-effect transistors (FinFET), gate-all-around (GAA) FET, etc. One method for on-chip temperature measurement/monitoring includes a source metal resistor for detecting the temperature of the 3D active device. Another method uses a dual polysilicon gate arrangement or a common source and common gate configuration to detect the temperature of the 3D active device.

FIG. 1A is a schematic diagram of a semiconductor device 100 that can be used to measure the temperature of an active device according to one embodiment. In at least some embodiments, the semiconductor device 100 is used to measure the temperature of a 3D active device. According to various embodiments, FIG. 1B is a schematic diagram of an equivalent circuit of the semiconductor device 100, FIG. 1C is a graph of the relationship between the temperature and the resistance of the sensing metal resistor 120 of the semiconductor device 100, and FIG. 1D and FIG. 1E are schematic diagrams of a cross-section of the semiconductor device 100 along the section line A-A' of FIG. 1A.

The semiconductor device 100 includes active area structures 102, 103, 104, 105 and 106 arranged in substantially parallel rows extending in a first direction (Y axis), and a plurality of gate layers 108, 110, 114, 118, 122 and 126 arranged in substantially parallel columns and extending in a second direction (X axis) substantially perpendicular to the first direction.

The active region structures 102-106 are continuous sections in or on a substrate (e.g., substrate 170) such as depicted in FIG. 1D and FIG. 1E, have n-type or p-type doping and include various semiconductor structures, including source-drain (S/D) structures, such as S/D structures 102SD-106SD shown in FIG. 1D and FIG. 1E. In some embodiments, the active region structures 102-106 are located in a well (not shown) (i.e., an n-well or a p-well) in the substrate.

In some embodiments, the active area structures 102 - 106 are electrically isolated from other devices in the substrate by one or more isolation structures (not shown), such as one or more shallow trench isolation (STI) structures.

The S/D structure is a semiconductor structure configured to have a doping type opposite to the doping type of other portions of the active area structures 102-106. In some embodiments, the S/D structure is configured to have a lower resistivity than other portions of the active area structures 102-106. In some embodiments, the S/D structure includes one or more portions having a doping concentration greater than one or more doping concentrations that would otherwise exist throughout the active area structures 102-106. In various embodiments, the S/D structure includes an epitaxial region of a semiconductor material such as silicon, silicon germanium (SiGe), and/or silicon carbide (SiC).

Each gate layer includes a conductive material (e.g., metal or polysilicon), covers each active area structure 102-106, at least partially surrounds each active area structure 102-106 in some embodiments, and is electrically isolated from each active area structure 102-106 by one or more dielectric layers. Thus, the plurality of gate layers are used to control the gate structure components of the conductive channel in the underlying active area structure 102-106 based on the applied voltage. The plurality of gate layers include virtual gate layers 108, 110, 118 and 122, and active gate layers 114 and 126.

The active region structures 102-106 extend at least between the first dummy gate layer 108 and the second dummy gate layer 110 and include source/drain (S/D) structures (not shown in FIG. 1A ) adjacent to some or all of the plurality of gate layers, which will be further discussed below with respect to FIG. 1D and FIG. 1E . The first source metal layer 112 covers and contacts the S/D structures of the active region structures 102-106 and extends in the second direction. The first source metal layer 112 is between the first dummy gate layer 108 and the first active gate layer 114 . The first drain metal layer 116 covers and contacts the S/D structures of the active area structures 102-106 and extends in a second direction substantially parallel to the first dummy gate layer 108. The first drain metal layer 116 is between the first active gate layer 114 and the third dummy gate layer 118. Therefore, the first source metal layer 112, the first active gate layer 114, the first drain metal layer 116, the channel portion of each of the active area structures 102-106 located below the first active gate layer 114, and the adjacent S/D structures are used to form a first active device MA1.

The sensing metal resistor 120 covers and contacts the S/D structures of the active region structures 102-106 between the third dummy gate layer 118 and the fourth dummy gate layer 122. The sensing metal resistor 120 extends in a second direction (X) that is substantially parallel to the first dummy gate layer 108.

The second source metal layer 124 covers and contacts the S/D structures of the active region structures 102 to 106 between the fourth dummy gate layer 122 and the second active gate layer 126. The second source metal layer 124 extends in the second direction (X) and is substantially parallel to the first dummy gate layer 108. The second drain metal layer 128 covers and contacts the S/D structures of the active region structures 102 to 106 between the second active gate layer 126 and the second dummy gate layer 110. The second drain metal layer 128 extends in the second direction (X) and is substantially parallel to the first dummy gate layer 108. Thus, the second source metal layer 124, the second active gate layer 126, the second drain metal layer 128, the channel portion of each of the active region structures 102-106 located below the second active gate layer 126, and the adjacent S/D structure are used to form the second active device MA2.

Thus, the active area structures 102-106 are arranged as an active area structure channel 130 including the first active element MA1 and the second active element MA2. Since the active area structures 102-106 have a higher thermal conductivity than the surrounding dielectric layer (not shown), the temperature of the active gate layers 114 and 126, the drain metal layers 116 and 128, the source metal layers 112 and 124, the active area structures 102-106 under the sensing metal resistor 120, and the sensing metal resistor itself are substantially the same.

Vias 132, 134, and 136 electrically connect first source metal layer 112, first active gate layer 114, and first drain metal layer 116 to respective overlying metal sections (not shown), for example, the first metal layer section, so that an active device MA1 is included in an integrated circuit (IC). Vias 138, 140, and 142 electrically connect second source metal layer 124, second active gate layer 126, and second drain metal layer 128 to respective overlying metal sections (not shown), for example, the first metal layer section, so that an active device MA2 is included in an IC.

Vias 144 and 146 electrically connect opposite ends of the sensing metal resistor 120 to an overlying metal section (not shown), such as a first metal layer section, so that the sensing metal resistor 120 is included in a test circuit layout so that the resistance value of the sensing metal resistor 120 can be measured as described below.

In operation, the third dummy gate layer 118 and the fourth dummy gate layer 122 electrically isolate the sensing metal resistor 120 from the first active device MA1 and the second active device MA2 during resistance measurement. The electrical isolation between the sensing metal resistor 120, the first active device MA1 and the second active device MA2 enables accurate resistance measurement by substantially preventing current from the first active device MA1 and the second active device MA2 from affecting the result measured at the sensing metal resistor 120 through the vias 144 and 146.

In a measurement operation, the vias 144 and 146 are electrically coupled to one or more measuring instruments (not shown), a voltage drop is generated across the sensing metal resistor 120 based on a current applied through the sensing metal resistor 120, and the resistance value of the sensing metal resistor 120 is calculated. In some embodiments, the resistance of the sensing metal resistor 120 has a linear relationship with temperature, and the temperature of the active area structures 102-106 distributed on the active area structure channel 130 is determined by finding the resistance of the sensing metal resistor 120.

In some embodiments, the active region structures 102-106 are configured for PMOS technology, NMOS technology, CMOS technology, FinFET technology, etc.

In some embodiments, the sensing metal resistor 120 includes a resistive metal material such as nickel-chromium alloy or carbon. In some embodiments, the sensing metal resistor 120 is a metal oxide film. In some embodiments, the sensing metal resistor 120 includes copper (Cu).

In some embodiments, vias 132, 134, 136, 138, 140, 142, 144, and 146 correspond to holes etched in an interlayer dielectric that are filled with one or more metals. In various embodiments, vias 132, 134, 136, 138, 140, 142, 144, and 146 are via structures that are similar or different in form relative to each other.

FIG. 1B is a schematic diagram of a circuit model 150 of a semiconductor device 100 according to an embodiment. The circuit model 150 includes a current source Iref connected in series with a resistor R. The current source Iref is connected between a power voltage source Vc and a node 152. The resistor R is connected between the node 152 and ground. The voltage Vr is the voltage drop across the resistor R. The current source Iref corresponds to the current applied to the sensing metal resistor 120. The voltage Vr corresponds to the voltage across the sensing metal resistor 120. The resistor R is the measured resistance of the sensing metal resistor 120. The readout circuit 156 is connected to the node 152 and measures the voltage Vr at the node 152. Equation (1):

R = Vr/Iref   Equation (1)

Used to calculate the resistance value of the sensing metal resistor 120.

FIG. 1C includes a graph 158 of the linear relationship between the resistance R of the sensing metal resistor 120 and the temperature. The graph 158 includes a temperature axis (X axis) and a resistance axis (Y axis). After calculating the resistance R using the above equation (1), the temperature of the sensing metal resistor 120 is determined based on the relationship between the resistance R of the sensing metal resistor and the temperature (e.g., the linear relationship shown in the graph 158). Different materials have different temperatures corresponding to specific resistance values. The temperature at different resistances can be calculated using standard tools (such as MATLAB, etc.).

The readout circuit 156 measures the voltage Vr at the node 152. In some embodiments, the readout circuit 156 displays the measured voltage. In some embodiments, the readout circuit 156 displays only the resistance value R. In some embodiments, the readout circuit 156 displays only the value of the temperature based on the calculated resistance value. In some embodiments, the readout circuit 156 includes an analog to digital converter (ADC) that allows the readout circuit 156 to convert the analog reading of the voltage Vr into digital for operation with other digital systems. In some embodiments, the readout circuit 156 includes an amplifier arrangement, such as an operational amplifier, to amplify the voltage Vr for detection and measurement.

In the non-limiting example depicted in the cross-section of FIG. 1D , the semiconductor device 100 corresponds to FinFET technology in which active area structures 102-106 are used as fin structures separated from each other by a dielectric layer 160 and extending upward from an underlying substrate 170. The active area structures 102-106 include corresponding S/D structures 102SD-106SD that contact and are electrically connected to a sense metal resistor 120.

In the non-limiting example depicted in the cross-section of FIG. 1E , the semiconductor device 100 corresponds to GAA technology in which the S/D structures 102SD-106SD are the only portions of the active area structures 102-106 in the cross-sectional plane. The S/D structures 102SD-106SD are in contact with and electrically connected to the sense metal resistor 120 and are separated from the extension portions 102E-106E of the substrate 170 by the dielectric layer 160. The extension portions 102E-106E correspond to the manufacturing method of forming the active area structures 102-106 and are not active components of the semiconductor device 100.

In each of the non-limiting examples of FIG. 1D and FIG. 1E , the channel regions (not shown) of the active area structures 102 to 106 are adjacent to the S/D structures 102SD to 106SD that are in contact with the sense metal resistor 120. In various embodiments, the semiconductor device 100 includes configurations other than those depicted in FIG. 1D and FIG. 1E , whereby the sense metal resistor 120 is in contact with the S/D structures adjacent to the channel regions of the active area structures 102 to 106.

Because the sensing metal resistor 120 contacts the S/D structures 102SD-106SD of the channel region adjacent to the active region structures 102-106, the temperature of the sensing metal resistor 120 is substantially the same as the temperature of the channel region. Therefore, the temperature value calculated based on the resistance measurement of the sensing metal resistor 120 is more accurate than the temperature value obtained by a method not based on the resistance measurement of the sensing metal resistor (e.g., a method based on substrate diode characteristics).

FIG. 2A is a schematic diagram of a semiconductor device 200 having a dual gate layer arrangement as part of a common source common gate transistor configuration according to an embodiment, which can be used to measure the temperature of a 3D active device. The semiconductor device 200 includes active area structures 202, 203, 204, 205, and 206, which are arranged in a row substantially in parallel and extend along a first direction (Y). The active area structures 202, 203, 204, 205, and 206 extend between a first gate layer 208 and a second dummy gate layer 210. The first dummy gate layer 208 and the second dummy gate layer 210 are arranged in a row substantially in parallel and extend in a second direction (X) substantially perpendicular to the first direction (Y). The drain metal layer 212 is formed on the active region structures 202, 203, 204, 205 and 206 and extends in the second direction (X). The drain metal layer 212 is located between the first dummy gate layer 208 and the sense gate layer 214. The sense gate layer 214 extends in the second direction and is substantially parallel to the first dummy gate layer 208. The first metal layer 216 is formed on the active region structures 202, 203, 204, 205 and 206 and extends in the second direction and is substantially parallel to the first dummy gate layer 208. The first metal layer 216 is located between the sense gate layer 214 and the switch gate layer 218. The switch gate layer 218 extends in the second direction and is substantially parallel to the first dummy gate layer 208. Therefore, the first metal layer 216, the sense gate layer 214, the drain metal layer 212, the channel portion of each active area structure 202-206 under the sense gate layer 214, and the adjacent S/D structures (not shown) in the active area structures 202-206 are used to form the first active device M1.

The source metal layer 220 is formed on the active area structures 202, 203, 204, 205 and 206, and extends in the second direction and is substantially parallel to the first dummy gate layer 208. The source metal layer 220 is located between the switch gate layer 218 and the second dummy gate layer 210. Therefore, the source metal layer 220, the switch gate layer 218, the first metal layer 216, the channel portion of each active area structure 202-206 located under the switch gate layer 218, and the adjacent S/D structure (not shown) in the active area structures 202-206 are used to form the second active element M2. The first metal layer 216 is used as the source of the first active element M1 and the drain of the second active element M2, so that the active elements M1 and M2 are arranged in a common source and common gate configuration. The first metal layer 216 couples the source of the first active element M1 to the drain of the second active element M2. Moreover, the first metal layer 216 allows current to flow between the source of the first active element M1 and the drain of the second active element M2.

The vias 226, 228, 230, 232, and 234 electrically connect the first active device M1 and the second active device M2 to an overlying metal section (not shown), such as a first metal layer section, so that the active devices M1 and M2 are included in a test circuit layout.

Vias 228 and 230 located at opposite ends of the sense gate layer 214 of the first active device M1 enable measurement of the resistance of the switching gate layer 218 during a measurement operation. Since the sense gate layer 214 is close to the channel region of the active area structures 202, 203, 204, 205, and 206, the temperature measurement of the sense gate layer 214 indicates the channel region temperature.

In the measurement operation, the second active element M2 is used to receive an AC signal, thereby operating as a switch under AC operation. The second active element M2 is coupled to an AC signal source, which is used to make the AC operation simulate the operation of one or more active elements of the IC circuit. In some embodiments, the second active element M2 is turned on when the AC signal of the AC signal source is positive, and is turned off when the AC signal is negative. In the above-mentioned common source and common gate configuration, the first active element M1 operates in a saturation region with high output resistance. The second active element M2 operates in a linear region with low output resistance. As shown in Figure 2A, the first active element M1 and the second active element M2 are connected in series via the first metal layer 216, wherein when the second active element is turned on, the AC current I_ac flows through the source of the first active element M1 and the drain of the second active element M2. Since the channel resistance of the first active device M1 is substantially greater than the channel resistance of the second active device M2 based on the common source and common gate configuration, most of the power is consumed in the first active device M1.

The channel resistance of the sense gate layer 214 is linearly proportional to the temperature of the channel regions of the active area structures 202, 203, 204, 205, and 206 beneath the sense gate layer 214. Once the resistance of the sense gate layer 214 is calculated, the linear relationship is used to determine the temperature of the channel regions of the active area structures 202, 203, 204, 205, and 206.

In operation, in some embodiments, the resistance of the sense gate layer 214 of the first active device M1 is measured by applying an AC signal to the switching gate layer 218 while biasing the sense gate layer 214 with a DC voltage higher than the threshold voltage of the first active device M1, thereby switching the first active device M1 on. When the current I_ac is thereby induced via the common source and common gate configuration, a test current is applied and the voltage drop across the sense gate layer 214 is measured via the vias 228 and 230. The resistance value of the sense gate layer 214 is calculated using the voltage drop measured across the sense gate layer 214 and the test current. The temperature of the channel regions of the active region structures 202, 203, 204, 205, and 206 is determined using the resistance value of the sensing gate layer 214 using the linear relationship between the resistance of the gate layer and the temperature discussed herein. Because the first active element M1 thus operates in the saturation region in response to the AC signal, the determined temperature corresponds to the temperature of one or more active elements of the IC circuit simulated by the AC signal.

The through hole 232 of the switching gate layer 218 is used to allow the second active element M2 to be triggered under AC operation or in response to a step function. In operation, in some embodiments, an AC or step signal is applied to the gate of the second active element M2 for triggering, so that the second active element M2 is turned on or off for testing depending on the value of the AC or step signal. Using this method, transient temperature values can be measured under AC operation or in response to a step signal. In some embodiments, the gate of the second active element M2 is always turned on for testing under DC operating conditions.

In some embodiments, the semiconductor device 200 allows other active devices or repeated structures to be formed on the active region structures 202-206 based on the first dummy gate layer 208 and the second dummy gate layer 210. If new active devices are formed on the active region structures 202-206, the first dummy gate layer 208 and the second dummy gate layer 210 provide sufficient electrical isolation.

In various embodiments, the first active device M1 and the second active device M2 are configured for PMOS technology, NMOS technology, CMOS technology, FinFET technology, etc.

In some embodiments, vias 226, 228, 230, 232, 234, and 236 correspond to holes etched in an interlayer dielectric that are filled with one or more metals. In various embodiments, vias 226, 228, 230, 232, 234, and 236 are via structures that are similar or different in form from one another.

FIG. 2B is a schematic diagram of equivalent circuits 242, 244, and 246 of a semiconductor device 200 according to an embodiment. FIG. 2B includes a first equivalent circuit 242 of the semiconductor device 200. The equivalent circuit 242 includes a first active element M1 coupled to an AC switch 248, which indicates a second active element M2 under AC operation. As discussed herein, the switching gate layer 218 of the second active element M2 is switched on and off using an AC signal 249 under AC operation to indicate the switch 248.

When the AC switch 248 is turned on, the second equivalent circuit 244 models when the first active element M1 operates in the saturation region and the second active element M2 operates in the linear region. The second equivalent circuit 244 includes a resistor Ron M1, which corresponds to the output channel resistance of the first active element M1 in the saturation region. The resistor Ron M1 is coupled between the drain of the first active element M1 and the second resistor Ron M2, which corresponds to the output channel resistance of the second active element M2 in the linear region. Based on the common source and common gate arrangement, the resistor Ron M1 is larger than the resistor Ron M2. In some embodiments, the size of the first active device M1 matches the size of one or more active devices emulated by the semiconductor device 200, so that the resistor Ron M1 matches the output channel resistance of the one or more active devices.

The third equivalent circuit 246 models the semiconductor device 200 as a resistor Ron M1 based on the common source and common gate arrangement of the semiconductor device 200 because Ron M1 >> Ron M2.

In some embodiments, the readout circuit measures the voltage across the sense gate layer 214 and displays the result. In some embodiments, the readout circuit is a readout circuit as described in conjunction with FIG. 1B . In some embodiments, the readout circuit is programmed to display only the value of the temperature based on the calculated value of the resistance of the sense gate layer 214 . In some embodiments, the readout circuit includes an analog-to-digital converter (ADC) to measure the voltage across the sense gate layer 214 . In some embodiments, the readout circuit includes an opAmp arrangement to measure the voltage across the sense gate layer 214 .

FIG. 3 is a schematic diagram of a semiconductor device 300 that can be used to measure temperature under AC or transient operation according to one embodiment. The semiconductor device 300 includes active area structures 302, 304, 306, 308, and 310, which are arranged in a row substantially in parallel and extend along a first direction (Y). The semiconductor device 300 includes a temperature monitor element 314 and an active element M0, each disposed on the active area structures 302, 304, 306, 308, and 310. The temperature monitor element 314 is equivalent to the semiconductor device 200 discussed above with respect to FIG. 2A, which is inverted relative to the first direction (Y). The active device M0 includes a source metal layer 318 between the second dummy gate layer 210 and the active gate layer 320 of the temperature monitoring device 314. The drain metal layer 322 is located between the active gate layer 320 and the third dummy gate layer 324.

As discussed above with respect to the semiconductor device 200, the temperature monitor element 314 can be used to measure the temperature of the channel region of the active region structures 302, 304, 306, 308, and 310 located below the sense gate layer 214 under transient and/or AC operating conditions. In operation, based on the temperature monitor element 314 and the common source and common gate arrangement of the active devices M0 and M1 having a matching configuration, by switching the active device M2 to turn on and applying the same AC and/or transient signal to the active gate layer 320 of the active device M0 and the switching gate layer 218 of the second active device M1, the same current I_ac is induced in each of the active devices M0 and M2. Therefore, the same temperature is generated in each channel region of the active region structures 302, 304, 306, 308 and 310 corresponding to the active devices M0 and M2, and the temperature determined by measuring the sensing gate layer 214 corresponds to the temperature of the active device M0.

In some embodiments, in operation, all active components in semiconductor device 300 are not in operation, and temperature monitor component 314 is used to measure the temperature of the substrate.

Virtual gate layers 208, 210, and 324 provide electrical isolation between the temperature monitor element 314 and other active elements including the active element M0. In some embodiments, in addition to the active element M0, there are many active elements (not shown) that share the active area structures 302-310 with the temperature monitor element 314, and in addition to the virtual gate layers 208, 210, and 324, there are one or more virtual gate layers (not shown) that electrically isolate the additional active elements from the temperature monitor element 314.

In different embodiments, the active device M0 is configured for PMOS technology, NMOS technology, CMOS technology, GAA FET technology, FinFET technology, etc.

4 is a flow chart of a method 400 for measuring the temperature of a channel region according to one or more embodiments. In various embodiments, the method 400 can be used to measure the temperature of a channel region of an active region structure shared by one or more active devices or to simulate the operation of one or more active devices.

In step 402, in some embodiments, a metal layer, such as a sense metal resistor 120 (FIG. 1A) or a sense gate layer 214 (FIG. 2A), is formed on an active area structure, such as active area structures 102, 103, 104, 105, and 106 (FIG. 1A), active area structures 202, 203, 204, 205, and 206 (FIG. 2A), or active area structures 302, 304, 306, 308, and 310. In some embodiments, the metal layer is a cap metal layer. In some embodiments, the metal layer is polysilicon or a metal gate layer. In some embodiments, the metal layer is a drain metal layer. In some embodiments, the metal layer is a source metal layer.

In step 404, a current is applied to a metal layer, such as the sensing metal resistor 120 (FIG. 1A) or the sensing gate layer 214 (FIG. 2A). In some embodiments, applying the current to the metal layer includes providing the current to the metal layer through a pair of vias, such as vias 144 and 146 (FIG. 1A) or vias 228 and 230 (FIG. 2A).

Applying the current includes applying a DC current, as discussed above with respect to FIGS. 1A to 3. In some embodiments, applying the current includes applying a DC current to a first gate layer of a first active element in a common source and common gate arrangement, and applying an AC and/or transient signal to a second gate layer of a second active element in the common source and common gate arrangement, as discussed above with respect to FIGS. 2A to 3.

In step 406, a voltage on a metal layer (such as sensing metal resistor 120 (FIG. 1A) or sensing gate layer 214 (FIG. 2A)) is measured, such as by a readout circuit (FIG. 1A). In some embodiments, the readout circuit is used to measure the voltage on the above-mentioned metal layer. In some embodiments, the readout circuit is a resistive readout circuit. In some embodiments, the readout circuit is a 4-point Kelvin structure with a dual bridge configuration to measure resistance levels below 1 ohm. In some embodiments, the readout circuit includes an analog-to-digital converter. In some embodiments, the readout circuit includes an operational amplifier.

In some embodiments, measuring the voltage on the metal layer includes measuring the voltage through a pair of vias, such as vias 144 and 146 (FIG. 1A) or vias 228 and 230 (FIG. 2A).

In step 408, the resistance of the metal layer (such as the sense metal resistor 120 (FIG. 1A) or the sense gate layer 214 (FIG. 2A)) is determined using the measured voltage on the metal layer and the current applied to the metal layer, as discussed above with respect to FIGS. 1A-3.

In step 410, the temperature of a channel region of an active area structure located below a metal layer (such as sensing metal resistor 120 (FIG. 1A) or sensing polysilicon gate layer 214 (FIG. 2A)) is calculated using the linear relationship between the temperature and resistance of the metal layer, as discussed above with respect to FIGS. 1A to 3. In some embodiments, calculating the temperature of the channel region includes calculating the channel region of an active area structure shared by multiple active elements. In some embodiments, calculating the temperature includes calculating a transient temperature change of the active element under AC or DC operation. In some embodiments, calculating the temperature includes calculating the temperature of the substrate when all active elements disposed on the active area structure are turned off.

One aspect of the present specification relates to an apparatus for monitoring the temperature of a semiconductor device including a plurality of active area structures. One or more active devices include portions of the plurality of active area structures. A metal layer covers the plurality of active area structures and is separated from the one or more active devices by one or more virtual gate layers, wherein the metal layer is used to measure the temperature of the plurality of active area structures caused by a change in resistance in the metal layer.

In some embodiments, an apparatus for monitoring temperature of a semiconductor device is provided wherein the active area structures include fins of a fin field effect transistor (FinFET).

In some embodiments, an apparatus for monitoring temperature of a semiconductor device is provided wherein the active area structures include a channel of a gate-all-around (GAA) field effect transistor (FET).

In some embodiments, the device for monitoring the temperature of a semiconductor device includes a nickel-chromium alloy, carbon, a metal oxide, or copper (Cu).

In some embodiments, the device for monitoring the temperature of a semiconductor device also includes a pair of through holes at opposite ends of the metal layer, whereby the metal layer is configured to receive a current.

In some embodiments, the apparatus for monitoring temperature of a semiconductor device wherein the metal layer is configured to have a voltage drop between the pair of vias in response to the current.

In some embodiments, the apparatus for monitoring temperature of a semiconductor device includes a resistance of the metal layer that is linearly proportional to the temperature of the active area structures.

In some embodiments, the apparatus for monitoring temperature of a semiconductor device includes at least one of the one or more active devices being a three-dimensional (3D) active device.

In some embodiments, the apparatus for monitoring temperature of a semiconductor device includes a drain metal layer formed on the active area structures.

In some embodiments, the apparatus for monitoring the temperature of a semiconductor device wherein the one or more active devices are configured to be turned off when measuring a temperature of a substrate including the active area structures.

Another aspect of the specification relates to a semiconductor device including a first virtual gate layer and a second virtual gate layer. A plurality of active area structures extend between the first virtual gate layer and the second virtual gate layer. A first metal layer covers the plurality of active area structures. The first active device includes portions of the plurality of active area structures between the first virtual gate layer and the first metal layer. The first active element includes a drain metal layer on the plurality of active area structures and between the first dummy gate layer and the first metal layer, and a first active gate layer covering the plurality of active area structures between the drain metal layer and the first metal layer. The second active element includes portions of the plurality of active area structures between the first metal layer and the second dummy gate layer. The second active element includes a source metal layer on the plurality of active area structures between the first metal layer and the second dummy gate layer; and a second active gate layer covering the plurality of active area structures between the first metal layer and the source metal layer. The first active element and the second active element are coupled in series. The first active gate layer of the first active element is used to sense the temperature of the plurality of active region structures.

In some embodiments, the semiconductor device wherein the first active device comprises a fin field effect transistor (FinFET).

In some embodiments, the semiconductor device wherein the first active device comprises a gate-all-around (GAA) field effect transistor (FET).

In some embodiments, the semiconductor device wherein based on the series coupling arrangement, the operating channel resistance of the first active device is greater than the operating channel resistance of the second active device.

In some embodiments, the semiconductor device wherein the first active device is thereby configured to operate in a saturation region.

In some embodiments, the semiconductor device wherein the second active device is thereby configured to operate in a linear region.

In some embodiments, a semiconductor device wherein a resistance of the first active gate layer is linearly proportional to the temperature of the active region structures.

Another aspect of the specification includes a method for measuring the temperature of a semiconductor device. The method includes: applying a current to a gate layer of a first device connected in series with a second device; switching a gate structure of the second device to control the flow of current between the second device and the first device; and measuring a voltage drop across the gate structure of the first device.

In some embodiments, wherein the switching the gate structure of the second component includes applying an AC signal to the gate structure of the second component.

In some embodiments, switching the gate structure of the second device includes applying a step function signal to the gate structure of the second device.

The features of several embodiments have been previously summarized so that those skilled in the art can better understand the various aspects of an embodiment of the present disclosure. Those skilled in the art should understand that they can easily use an embodiment of the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and/or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of an embodiment of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of an embodiment of the present disclosure.

100, 200, 300: semiconductor element 102, 103, 104, 105, 106, 202, 203, 204, 205, 206, 302, 304, 306, 308, 310: active region structure 102SD~106SD: S/D pole structure 108, 110, 126: gate layer 112: first source metal layer 114: first active gate layer 116: first drain metal layer 118: third virtual gate layer 120: sensing metal resistor 122: fourth virtual gate layer 124: Second source metal layer 128: Second drain metal layer 130: Active area structure channel 132,134,136,138,140,142,144,146,226,228,230,232,234: Through hole 102E～106E: Extension part MA1,M1: First active element MA2,M2: Second active element 150: Circuit model 152: Node 156: Read circuit 158: Curve graph Vc: Power voltage source Vr: Voltage Iref: Current source I_ac: AC current X,Y: Direction A-A’: Section line R: Resistor 160: Dielectric layer 170: substrate 208: first virtual gate layer 210: second virtual gate layer 212,322: drain metal layer 214: sense gate layer 216: first metal layer 218: switch gate layer 220,318: source metal layer 242,244,246: equivalent circuit 248: AC switch 249: AC signal 314: temperature monitoring element 320: active gate layer 324: virtual gate layer 400: method 402,404,406,408,410: Steps

Various aspects of an embodiment of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the sizes of the various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1A is a schematic diagram of a semiconductor element for measuring temperature using a sensing metal resistor according to an embodiment; FIG. 1B is a schematic diagram of an equivalent circuit of the semiconductor element of FIG. 1A according to an embodiment; FIG. 1C is a curve diagram of the relationship between temperature and resistance of a sensing metal resistor according to an embodiment; FIG. 1D and FIG. 1E are cross-sectional schematic diagrams of the semiconductor element of FIG. 1A according to an embodiment; FIG. 2A to FIG. 2B are schematic diagrams of a semiconductor element for measuring temperature using a sensing gate according to an embodiment; FIG. 3 is a schematic diagram of a semiconductor element for measuring transient temperature changes according to an embodiment; FIG. 4 is a flow chart of a method for measuring temperature according to one or more embodiments.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

100:Semiconductor components

102~106: Active region structure

108,110,126: Gate layer

112: First source metal layer

114: First active gate layer

116: First drain metal layer

118: The third virtual gate layer

120: Sensing metal resistor

122: Fourth virtual gate layer

124: Second source metal layer

128: Second drain metal layer

130: Active area structure channel

132,134,136,138,140,142,144,146:Through hole

MA1: first active component

MA2: Second active element

X,Y: direction

A-A’: section line

Claims (10)

A semiconductor device comprises: a plurality of active area structures; one or more active elements, including multiple parts of the active area structures; and a metal layer, the metal layer covering the active area structures and separated from the one or more active elements by one or more virtual gate layers, wherein the metal layer is used to measure a temperature of the active area structures caused by a resistance change in the metal layer. A semiconductor device as described in claim 1, wherein the active region structures include fins of a fin field effect transistor. A semiconductor device as described in claim 1, wherein the active region structures include a trench of a wrap-around gate field effect transistor. A semiconductor device as described in claim 1, wherein the metal layer includes nickel-chromium alloy, carbon, metal oxide, or copper. The semiconductor element as described in claim 1 further includes a pair of through holes at opposite ends of the metal layer, whereby the metal layer is used to receive a current. A semiconductor device as described in claim 5, wherein the metal layer is configured to have a voltage drop between the pair of through holes in response to the current. A semiconductor device as described in claim 1, wherein a resistance of the metal layer is linearly proportional to the temperature of the active region structures. A semiconductor device as described in claim 1, wherein the metal layer includes a drain metal layer formed on the active area structures. A semiconductor device comprises: a plurality of active region structures; one or more active devices, including multiple parts of the active region structures; a first virtual gate layer; a second virtual gate layer; and a metal layer, the metal layer covers the active region structures, is arranged between the first virtual gate layer and the second virtual gate layer; and is electrically isolated from the active regions, wherein the metal layer is used to measure a temperature of the active region structures caused by a resistance change in the metal layer. A semiconductor device comprises: a plurality of active region structures; a first active device and a second active device, comprising a plurality of portions of the active region structures, wherein the first active device and the second active device are arranged in series; a first virtual gate layer; a second virtual gate layer, wherein the first virtual gate layer and the second virtual gate layer are arranged between the first active device and the second active device; and a metal layer, the metal layer covers the active region structures and is arranged between the first virtual gate layer and the second virtual gate layer; The metal layer is used to measure a temperature of the active region structures caused by a resistance change in the metal layer.