TW202422628A - Precise feedback control of bias voltage tailored waveform for plasma etch processes - Google Patents

Precise feedback control of bias voltage tailored waveform for plasma etch processes Download PDF

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TW202422628A
TW202422628A TW112126858A TW112126858A TW202422628A TW 202422628 A TW202422628 A TW 202422628A TW 112126858 A TW112126858 A TW 112126858A TW 112126858 A TW112126858 A TW 112126858A TW 202422628 A TW202422628 A TW 202422628A
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voltage
edge ring
waveform
electrode
bias
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TW112126858A
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明烈 崔
垠 吳
亞歷山大 米勒 派特森
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美商蘭姆研究公司
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Abstract

A bias electrode and a mid-level electrode are disposed within a substrate support. A lower portion of the substrate support exists between the bias electrode and the mid-level electrode. An upper portion of the substrate support exists between the mid-level electrode and a top surface of the substrate support. A voltage supply system supplies a bias voltage tailored radiofrequency waveform to the bias electrode. A voltage measurement system measures a first voltage on the bias electrode and a second voltage on the mid-level electrode. A controller uses the first voltage, the second voltage, a capacitance of the substrate support lower portion, and a capacitance of the substrate support upper portion to determine a voltage on a top surface of a substrate present on the top surface of the substrate support. The controller conveys the voltage on the top surface of the substrate to the voltage supply system.

Description

電漿蝕刻製程用的偏壓電壓定制波形之精準回饋控制Precise feedback control of bias voltage customized waveform for plasma etching process

本揭示內容係關於電漿處理系統用的基板支撐系統及邊緣環系統、以及控制基板上電壓的方法,特別係關於電漿處理製程用的偏壓電壓定制波形之回饋控制。The present disclosure relates to a substrate support system and an edge ring system for a plasma processing system, and a method of controlling voltage on a substrate, and more particularly to feedback control of a customized waveform of a bias voltage for a plasma processing process.

電漿處理系統係用於在半導體晶圓上製造例如晶片/晶粒的半導體裝置。在電漿處理系統中,半導體晶圓係曝露至諸多型式的電漿以例如經由材料沉積及/或材料移除及/或材料植入及/或材料修改等等造成半導體晶圓之條件的指定變更。於半導體晶圓的電漿處理期間,射頻(RF)功率係經由腔室內的製程氣體傳輸以在對半導體晶圓曝露時將製程氣體變換為電漿。例如自由基和離子的電漿之反應成分與半導體晶圓上的材料相互作用以在半導體晶圓上達到指定效果。在某些電漿處理系統中,於半導體晶圓之位準施加偏壓電壓以將電漿內的帶電成分引向半導體晶圓。Plasma processing systems are used to manufacture semiconductor devices such as chips/dies on semiconductor wafers. In a plasma processing system, a semiconductor wafer is exposed to various types of plasma to cause a specified change in the condition of the semiconductor wafer, such as through material deposition and/or material removal and/or material implantation and/or material modification, etc. During plasma processing of a semiconductor wafer, radio frequency (RF) power is delivered through a process gas in a chamber to convert the process gas into plasma when exposed to the semiconductor wafer. Reactive components of the plasma, such as free radicals and ions, interact with materials on the semiconductor wafer to achieve a specified effect on the semiconductor wafer. In some plasma processing systems, a bias voltage is applied at the level of the semiconductor wafer to direct the charged components within the plasma toward the semiconductor wafer.

隨著半導體產業不斷朝著縮小晶片尺寸及改良晶片效能前進,有必要使用更高密度及高縱橫比特徵部以於晶片上定義電晶體,而導致電晶體對於製造製程變異更為敏感。隨著晶片上特徵部尺寸的縮減,僅僅些許原子的某些製造製程變異便可能需要蝕刻均勻性控制的改良。跨半導體晶圓的離子通量、離子能量、及離子角分布的均勻性係對於微電子製造之電漿蝕刻與沈積的嚴苛要求。並且,半導體晶圓之邊緣處的實質上均勻離子通量、離子能量、及離子角分布的達成係有意義的挑戰,因為基板上接近10%的晶粒會受到發生在距半導體晶圓之外周緣約5 mm之徑向距離內的製造製程結果影響。便是在此脈絡中產生本文所述的諸多實施例。As the semiconductor industry continues to move toward smaller chip sizes and improved chip performance, it is necessary to use higher density and high aspect ratio features to define transistors on the chip, resulting in transistors that are more sensitive to manufacturing process variations. As the size of features on the chip decreases, certain manufacturing process variations of just a few atoms may require improvements in etch uniformity control. Uniformity of ion flux, ion energy, and ion angular distribution across a semiconductor wafer are stringent requirements for plasma etching and deposition for microelectronics manufacturing. Furthermore, achieving substantially uniform ion flux, ion energy, and ion angular distribution at the edge of a semiconductor wafer is a significant challenge because approximately 10% of the die on a substrate are affected by the results of the manufacturing process occurring within a radial distance of approximately 5 mm from the outer periphery of the semiconductor wafer. It is in this context that many of the embodiments described herein arise.

在示例性的實施例中,系統包括配置在基板支撐件內的偏壓電極。基板支撐件具有配置以支撐基板的頂面。系統亦包括配置在基板支撐件內的中階電極,使得基板支撐件的下部存在於偏壓電極與中階電極之間,並且使得基板支撐件的上部存在於中階電極與基板支撐件的頂面之間。系統亦包括連接以供應偏壓電壓定制射頻波形至偏壓電極的電壓供應系統。系統亦包括連接以量測偏壓電極上之第一電壓與中階電極上之第二電壓的電壓量測系統。系統亦包括控制器,控制器係配置以使用所量測第一電壓、所量測第二電壓、基板支撐件之下部之電容、及基板支撐件之上部之電容以判定當基板存在於基板支撐件之頂面上時基板之頂面上的電壓。控制器係配置以將關於基板之頂面上電壓的資訊傳遞至電壓供應系統。In an exemplary embodiment, the system includes a bias electrode configured in a substrate support. The substrate support has a top surface configured to support a substrate. The system also includes an intermediate electrode configured in the substrate support such that a lower portion of the substrate support is located between the bias electrode and the intermediate electrode, and such that an upper portion of the substrate support is located between the intermediate electrode and the top surface of the substrate support. The system also includes a voltage supply system connected to supply a bias voltage customized RF waveform to the bias electrode. The system also includes a voltage measurement system connected to measure a first voltage on the bias electrode and a second voltage on the intermediate electrode. The system also includes a controller configured to use the measured first voltage, the measured second voltage, the capacitance of the lower portion of the substrate support, and the capacitance of the upper portion of the substrate support to determine a voltage on the top surface of the substrate when the substrate is present on the top surface of the substrate support. The controller is configured to transmit information about the voltage on the top surface of the substrate to the voltage supply system.

在示例性的實施例中,揭示用於電漿處理系統的基板支撐系統。基板支撐系統包括基板支撐件,基板支撐件具有配置以支撐基板的頂面。基板支撐系統亦包括配置在基板支撐件內的偏壓電極。偏壓電極係配置以控制基板之頂面上的電壓。偏壓電極係連接以接收來自電壓供應系統的偏壓電壓定制射頻波形。偏壓電極係配置以電性接收第一連接器以用於量測偏壓電極上的第一電壓。基板支撐系統亦包括配置在基板支撐件內的中階電極,使得基板支撐件的下部存在於偏壓電極與中階電極之間,並且使得基板支撐件的上部存在於中階電極與基板支撐件的頂面之間。中階電極係配置以電性接收第二連接器以用於量測中階電極上的第二電壓。In an exemplary embodiment, a substrate support system for a plasma processing system is disclosed. The substrate support system includes a substrate support having a top surface configured to support a substrate. The substrate support system also includes a bias electrode configured in the substrate support. The bias electrode is configured to control a voltage on the top surface of the substrate. The bias electrode is connected to receive a bias voltage customized RF waveform from a voltage supply system. The bias electrode is configured to electrically receive a first connector for measuring a first voltage on the bias electrode. The substrate support system also includes an intermediate electrode disposed within the substrate support such that a lower portion of the substrate support resides between the bias electrode and the intermediate electrode and an upper portion of the substrate support resides between the intermediate electrode and a top surface of the substrate support. The intermediate electrode is configured to electrically receive a second connector for measuring a second voltage on the intermediate electrode.

在示例性的實施例中,揭示用於電漿處理系統的邊緣環系統。邊緣環系統包括配置以侷限基板支撐件的邊緣環。邊緣環系統亦包括配置在邊緣環內的邊緣環電極。邊緣環電極係配置以控制邊緣環之頂面上的電壓。邊緣環電極係連接以接收來自電壓供應系統的偏壓電壓定制射頻波形。邊緣環電極係配置以電性接收第一連接器以用於量測邊緣環電極上的第一電壓。邊緣環系統亦包括配置在邊緣環內的邊緣環中階電極,使得邊緣環的下部存在於邊緣環電極與邊緣環中階電極之間,並且使得邊緣環的上部存在於邊緣環中階電極與邊緣環的頂面之間。邊緣環中階電極係配置以電性接收第二連接器以用於量測邊緣環中階電極上的第二電壓。In an exemplary embodiment, an edge ring system for a plasma processing system is disclosed. The edge ring system includes an edge ring configured to confine a substrate support. The edge ring system also includes an edge ring electrode configured within the edge ring. The edge ring electrode is configured to control the voltage on the top surface of the edge ring. The edge ring electrode is connected to receive a bias voltage customized RF waveform from a voltage supply system. The edge ring electrode is configured to electrically receive a first connector for measuring a first voltage on the edge ring electrode. The edge ring system also includes an edge ring intermediate electrode disposed in the edge ring so that a lower portion of the edge ring exists between the edge ring electrode and the edge ring intermediate electrode, and an upper portion of the edge ring exists between the edge ring intermediate electrode and a top surface of the edge ring. The edge ring intermediate electrode is configured to electrically receive a second connector for measuring a second voltage on the edge ring intermediate electrode.

在示例性的實施例中,揭示用於控制基板上電壓的方法。方法包括操作電壓供應系統以供應偏壓電壓定制射頻波形至基板支撐件內的偏壓電極。方法亦包括於給定時間量測偏壓電極上的第一電壓。方法亦包括於給定時間量測中階電極上的第二電壓。中階電極係配置在基板支撐件內,使得基板支撐件的下部存在於偏壓電極與中階電極之間,並且使得基板支撐件的上部存在於中階電極與基板支撐件的頂面之間。方法亦包括使用所量測第一電壓、所量測第二電壓、基板支撐件之下部之電容、及基板支撐件之上部之電容以於給定時間判定當基板存在於基板支撐件之頂面上時基板之頂面上的電壓。In an exemplary embodiment, a method for controlling a voltage on a substrate is disclosed. The method includes operating a voltage supply system to supply a bias voltage custom RF waveform to a bias electrode within a substrate support. The method also includes measuring a first voltage on the bias electrode at a given time. The method also includes measuring a second voltage on an intermediate electrode at a given time. The intermediate electrode is configured within the substrate support so that a lower portion of the substrate support is between the bias electrode and the intermediate electrode, and so that an upper portion of the substrate support is between the intermediate electrode and a top surface of the substrate support. The method also includes using the measured first voltage, the measured second voltage, the capacitance of a lower portion of the substrate support, and the capacitance of an upper portion of the substrate support to determine a voltage on a top surface of the substrate when the substrate is present on the top surface of the substrate support at a given time.

從以下詳細說明內容及隨附圖式中將更顯見本文所揭示之實施例的其他實施態樣與優點。Other embodiments and advantages of the embodiments disclosed herein will become more apparent from the following detailed description and the accompanying drawings.

在以下說明內容中,提出眾多具體細節以便提供對於本揭示內容的透徹理解。然而,熟習本技術領域人士將顯見可在不具有某些或全部的此些具體細節的情況下實現本揭示內容的實施例。在其他方面,為了不對本揭示內容造成不必要地混淆而沒有詳細描述眾所周知的製程操作。In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that embodiments of the present disclosure may be implemented without some or all of these specific details. In other respects, well-known process operations are not described in detail in order not to unnecessarily obscure the present disclosure.

依據某些實施例,圖1A顯示穿越電漿處理系統100的垂直剖面圖。電漿處理系統100包括腔室101。線圈109係配置在腔室101的窗口107上方。在諸多實施例中,窗口107係由例如石英或其他相似材料的介電材料形成而允許RF功率從線圈109經由窗口107傳輸並進入腔室101內的電漿處理區102。腔室101係電性連接至參考接地電位104。電漿處理系統100包括連接以經由阻抗匹配網路111輸送RF功率至線圈109的TCP(變壓器耦合電漿)RF產生器113,如連接115所示。1A shows a vertical cross-section through a plasma processing system 100, according to some embodiments. The plasma processing system 100 includes a chamber 101. A coil 109 is disposed above a window 107 of the chamber 101. In many embodiments, the window 107 is formed of a dielectric material such as quartz or other similar material to allow RF power to be transmitted from the coil 109 through the window 107 and into the plasma processing region 102 within the chamber 101. The chamber 101 is electrically connected to a reference ground potential 104. The plasma processing system 100 includes a TCP (transformer coupled plasma) RF generator 113 connected to deliver RF power to the coil 109 via an impedance matching network 111, as shown by connection 115.

電漿處理系統100亦配備以提供製程氣體或製程氣體混合物進入電漿處理區102的受控流動,如箭號117所示。隨著RF功率傳輸進入並通過電漿處理區102,RF功率將曝露至腔室101內於基板支撐件103上支撐之基板105的製程氣體/混合物變換為電漿處理區102內的電漿119。基板支撐件103具有配置以於藉由在基板支撐件103上方產生之電漿119處理基板105之頂面105T的期間支撐基板105的頂面103T。在某些實施例中,基板支撐件103係配置以產生將基板105夾持至基板支撐件103之頂面103T之靜電力的靜電卡盤。The plasma processing system 100 is also configured to provide a controlled flow of a process gas or process gas mixture into the plasma processing region 102, as indicated by arrow 117. As RF power is delivered into and through the plasma processing region 102, the RF power transforms the process gas/mixture exposed to the substrate 105 supported on the substrate support 103 within the chamber 101 into a plasma 119 within the plasma processing region 102. The substrate support 103 has a top surface 103T configured to support the substrate 105 during processing of the top surface 105T of the substrate 105 by the plasma 119 generated above the substrate support 103. In some embodiments, the substrate support 103 is an electrostatic chuck configured to generate an electrostatic force to clamp the substrate 105 to the top surface 103T of the substrate support 103.

在諸多實施例中,產生電漿119以致使對於基板105之受控方式的改變。在諸多製造製程中,對基板105的改變可為基板105上材料或表面條件的改變。例如,在諸多製造製程中,對基板105的改變可包括一或更多的基板105中材料的蝕刻、基板105上材料的沉積、材料進入基板105的植入、及/或存在於基板105上之材料的修改。並且,在某些實施例中,電漿119係在沒有基板105存在的情況下產生於電漿處理區102中以提供腔室101之清潔。應理解的是,電漿處理系統100可為其中傳輸RF功率至電漿處理區102內之製程氣體/混合物的任意型式之電漿處理系統,以於被支撐在基板支撐件103之頂面103T上的基板105上方產生電漿119。電漿處理系統100亦配備以提供用於電漿處理區102中氣體及處理副產物材料經由排氣系統的移除,如箭號121所示。In many embodiments, the plasma 119 is generated to cause a controlled change to the substrate 105. In many manufacturing processes, the change to the substrate 105 can be a change in a material or surface condition on the substrate 105. For example, in many manufacturing processes, the change to the substrate 105 can include one or more of etching of a material in the substrate 105, deposition of a material on the substrate 105, implantation of a material into the substrate 105, and/or modification of a material present on the substrate 105. Also, in some embodiments, the plasma 119 is generated in the plasma processing region 102 in the absence of the substrate 105 to provide cleaning of the chamber 101. It should be understood that the plasma processing system 100 may be any type of plasma processing system in which RF power is delivered to the process gas/mixture within the plasma processing region 102 to generate the plasma 119 above the substrate 105 supported on the top surface 103T of the substrate support 103. The plasma processing system 100 is also configured to provide for the removal of gases and process byproduct materials in the plasma processing region 102 via an exhaust system, as indicated by arrow 121.

依據某些實施例,參考圖1A中視面A-A,圖1B顯示配置在基板支撐件103上之基板105的俯視圖。在某些實施例中,基板105係正在進行製造程序的半導體晶圓。然而,應理解在諸多實施例中,基板105基本上可為接受電漿為基製造製程的任何型式之基板。例如,在某些實施例中,基板105係由矽、藍寶石、GaN、GaAs或SiC、及/或其他基板材料形成,並且可包括玻璃面板/基板、金屬箔、金屬片、聚合物材料、或其他相似者。並且,在諸多實施例中,基板105可在形態、形狀、及/或尺寸上變化。例如,在某些實施例中,基板105係具有200 mm、300 mm、450 mm、或其他尺寸之外徑的半導體晶圓。並且,在某些實施例中,基板105係非圓形的基板,例如用於平面顯示器或與其相似者之除了其他形狀以外的矩形基板。According to some embodiments, with reference to view A-A in FIG. 1A , FIG. 1B shows a top view of a substrate 105 disposed on a substrate support 103. In some embodiments, the substrate 105 is a semiconductor wafer undergoing a manufacturing process. However, it should be understood that in many embodiments, the substrate 105 can be substantially any type of substrate that is amenable to plasma-based manufacturing processes. For example, in some embodiments, the substrate 105 is formed of silicon, sapphire, GaN, GaAs, or SiC, and/or other substrate materials, and can include a glass panel/substrate, metal foil, metal sheet, polymer material, or the like. Also, in many embodiments, the substrate 105 can vary in form, shape, and/or size. For example, in some embodiments, the substrate 105 is a semiconductor wafer having an outer diameter of 200 mm, 300 mm, 450 mm, or other sizes. Furthermore, in some embodiments, the substrate 105 is a non-circular substrate, such as a rectangular substrate among other shapes used in flat panel displays or the like.

如圖1A中所示,在某些實施例中,偏壓電極123係配置在基板支撐件103內的基板支撐件103之頂面103T下方。在某些實施例中,基板支撐件103係由例如陶瓷材料或其他型式之介電材料的介電材料形成,而具有由導電材料形成的偏壓電極123。在某些實施例中,電漿處理系統100包括連接以經由阻抗匹配網路127輸送偏壓RF功率至偏壓電極123的偏壓RF產生器125,如連接129所示。偏壓電極123係配置以施加偏壓電壓至基板105的頂面105T以吸引或排斥電漿119的帶電成分朝向或遠離基板105。As shown in FIG. 1A , in some embodiments, the bias electrode 123 is disposed within the substrate support 103 below the top surface 103T of the substrate support 103. In some embodiments, the substrate support 103 is formed of a dielectric material, such as a ceramic material or other type of dielectric material, with the bias electrode 123 formed of a conductive material. In some embodiments, the plasma processing system 100 includes a bias RF generator 125 connected to deliver bias RF power to the bias electrode 123 via an impedance matching network 127, as shown by connection 129. The bias electrode 123 is configured to apply a bias voltage to the top surface 105T of the substrate 105 to attract or repel charged components of the plasma 119 toward or away from the substrate 105 .

應理解的是,在諸多實施例中,電漿處理系統100的操作可包括許多其他額外的操作,例如控制基板105的溫度,及/或除了其他額外操作以外,施加額外RF功率至配置在基板支撐件103內的一或更多電極以產生額外電漿。並且,在諸多實施例中,依據指定時程的指定配方操作電漿處理系統100以控制下列一或更多者:製程氣體(一或多)至電漿處理區102的供應、電漿處理區102內的壓力及溫度、RF功率至線圈109的供應、偏壓RF功率至偏壓電極123的供應、基本上關聯於電漿處理系統100之操作的任何其他製程參數。It should be understood that in various embodiments, the operation of the plasma processing system 100 may include a number of other additional operations, such as controlling the temperature of the substrate 105, and/or applying additional RF power to one or more electrodes disposed within the substrate support 103 to generate additional plasma, among other additional operations. Also, in various embodiments, the plasma processing system 100 is operated according to a specified recipe for a specified schedule to control one or more of the following: the supply of process gas(es) to the plasma processing region 102, the pressure and temperature within the plasma processing region 102, the supply of RF power to the coil 109, the supply of bias RF power to the bias electrode 123, and substantially any other process parameter associated with the operation of the plasma processing system 100.

偏壓RF產生器125係用於基板105之使用正弦波形電壓的偏壓處理。當供應RF信號至偏壓電極123時,基板105之頂面105T上的電壓於RF信號的頻率下週期性振盪。此用於供應RF偏壓電壓至基板105的技術導致用於基板105之頂面105T上特徵部之蝕刻的轟擊離子能量的不受控分佈。在某些實施例中,因為偏壓RF產生器125具有RF電壓振幅的一維控制鈕,故偏壓RF產生器125無法獨立地控制入射至基板105上的離子通量。在此些實施例中,藉由使用TCP RF產生器113供應至線圈109的RF功率以及藉由基板105之頂面105T上RF偏壓電壓的振幅來判定入射至基板105上的離子通量,RF偏壓電壓的振幅直接影響入射至基板105之頂面105T上之離子的能量。在某些實施例中,偏壓RF產生器125能夠以功率調節模式抑或電壓調節模式來調節輸出RF功率。The bias RF generator 125 is used for biasing the substrate 105 using a sinusoidal waveform voltage. When an RF signal is supplied to the bias electrode 123, the voltage on the top surface 105T of the substrate 105 oscillates periodically at the frequency of the RF signal. This technique for supplying the RF bias voltage to the substrate 105 results in an uncontrolled distribution of the impact ion energy used for etching features on the top surface 105T of the substrate 105. In some embodiments, because the bias RF generator 125 has a one-dimensional control knob for the RF voltage amplitude, the bias RF generator 125 cannot independently control the ion flux incident on the substrate 105. In these embodiments, the ion flux incident on the substrate 105 is determined by the RF power supplied to the coil 109 using the TCP RF generator 113 and by the amplitude of the RF bias voltage on the top surface 105T of the substrate 105, and the amplitude of the RF bias voltage directly affects the energy of the ions incident on the top surface 105T of the substrate 105. In some embodiments, the bias RF generator 125 can adjust the output RF power in either a power adjustment mode or a voltage adjustment mode.

依據某些實施例,圖2顯示基板105之頂面105T上電壓,基板105之頂面105T上電壓響應藉由偏壓RF產生器125之固定振幅RF電壓至偏壓電極123的供應,而具有出現於基板105之頂面105T處的兩不同離子通量條件。曲線V(輸出)201表示藉由偏壓RF產生器125供應至偏壓電極123的固定振幅RF電壓。曲線V(基板頂部 1 Amp)203表示響應所供應RF偏壓電壓V(輸出)201的基板105之頂面105T上電壓,而具有出現在基板105之頂面105T上的1 Amp離子電流。曲線V(基板頂部 0.5 Amp)205表示響應所供應RF偏壓電壓V(輸出)201的基板105之頂面105T上電壓,而具有出現在基板105之頂面105T上的0.5 Amp離子電流。圖2顯現出即使具有藉由偏壓RF產生器125供應至偏壓電極123的固定振幅RF偏壓電壓,基板105之頂面105T上電壓仍可隨著電漿119的密度以及隨著入射至基板105上的離子通量變化。此外,基板105之頂面105T上電漿引起的電壓行為變化乃產生關於基板105製造配方從一處理腔室至另一處理腔室之移送、以及關於基板105製造配方之修改的挑戰。2 shows the voltage on the top surface 105T of the substrate 105 in response to the supply of a fixed amplitude RF voltage to the bias electrode 123 by the bias RF generator 125, with two different ion flux conditions appearing at the top surface 105T of the substrate 105. Curve V(output) 201 represents the fixed amplitude RF voltage supplied to the bias electrode 123 by the bias RF generator 125. Curve V(substrate top 1 Amp) 203 represents the voltage on the top surface 105T of the substrate 105 in response to the supplied RF bias voltage V(output) 201, and has a 1 Amp ion current appearing on the top surface 105T of the substrate 105. Curve V(substrate top 0.5 Amp) 205 represents the voltage on the top surface 105T of the substrate 105 in response to the supplied RF bias voltage V(output) 201, and has a 0.5 Amp ion current appearing on the top surface 105T of the substrate 105. 2 shows that even with a fixed amplitude RF bias voltage supplied to the bias electrode 123 by the bias RF generator 125, the voltage on the top surface 105T of the substrate 105 can vary with the density of the plasma 119 and with the ion flux incident on the substrate 105. Furthermore, the variation in the plasma-induced voltage behavior on the top surface 105T of the substrate 105 creates challenges with respect to the transfer of substrate 105 manufacturing recipes from one processing chamber to another, and with respect to the modification of substrate 105 manufacturing recipes.

依據某些實施例,圖3A顯示穿越電漿處理系統300的垂直剖面圖。電漿處理系統300係圖1A之電漿處理系統100的變形。電漿處理系統300包括腔室101、窗口107、及腔室101內的電漿處理區102。電漿處理系統300亦包括TCP RF產生器113、阻抗匹配網路111、連接115、及配置於窗口107上方的線圈109。電漿處理系統300亦提供如箭號117所示之製程氣體進入電漿處理區102的供應,以及如箭號121所示之製程氣體及副產物材料從電漿處理區102的移除。從TCP RF產生器113途經線圈109及RF透明窗口107供應至電漿處理區102的RF功率將曝露至基板105的製程氣體變換為電漿處理區102內的電漿119。According to some embodiments, FIG. 3A shows a vertical cross-sectional view through a plasma processing system 300. The plasma processing system 300 is a variation of the plasma processing system 100 of FIG. 1A. The plasma processing system 300 includes a chamber 101, a window 107, and a plasma processing region 102 within the chamber 101. The plasma processing system 300 also includes a TCP RF generator 113, an impedance matching network 111, a connection 115, and a coil 109 disposed above the window 107. The plasma processing system 300 also provides for the supply of process gases into the plasma processing region 102 as indicated by arrows 117, and the removal of process gases and byproduct materials from the plasma processing region 102 as indicated by arrows 121. RF power supplied from the TCP RF generator 113 through the coil 109 and the RF transparent window 107 to the plasma processing zone 102 transforms the process gas exposed to the substrate 105 into a plasma 119 within the plasma processing zone 102 .

電漿處理系統300包括基板支撐件301,基板支撐件301係關於圖1A所述之基板支撐件103的變形。基板支撐件301具有配置以於處理期間支撐基板105的頂面301T。在某些實施例中,基板支撐件301係配置以產生將基板105夾持至基板支撐件301之頂面301T之靜電力的靜電卡盤。基板支撐件301亦包括配置在基板支撐件301內於基板支撐件301之頂面301T下方的偏壓電極123。在某些實施例中,基板支撐件301係由例如陶瓷材料或其他型式之介電材料的介電材料形成,而具有由導電材料形成的偏壓電極123。在基板支撐件301中,偏壓電極123係配置以施加偏壓電壓至基板105的頂面105T以吸引或排斥電漿119的帶電成分朝向或遠離基板105。The plasma processing system 300 includes a substrate support 301 that is a variation of the substrate support 103 described with respect to FIG. 1A . The substrate support 301 has a top surface 301T configured to support a substrate 105 during processing. In certain embodiments, the substrate support 301 is an electrostatic chuck configured to generate an electrostatic force to clamp the substrate 105 to the top surface 301T of the substrate support 301. The substrate support 301 also includes a bias electrode 123 disposed within the substrate support 301 below the top surface 301T of the substrate support 301. In some embodiments, the substrate support 301 is formed of a dielectric material such as a ceramic material or other types of dielectric materials, and has a bias electrode 123 formed of a conductive material. In the substrate support 301, the bias electrode 123 is configured to apply a bias voltage to the top surface 105T of the substrate 105 to attract or repel the charged components of the plasma 119 toward or away from the substrate 105.

在電漿處理系統300中,邊緣環315圍繞基板支撐件301,使得基板支撐件301的頂面301T受邊緣環315侷限。依據某些實施例,參考圖3A中視面A-A,圖3B顯示具有圍繞基板支撐件301之邊緣環315的配置在基板支撐件301上之基板105的俯視圖。邊緣環電極323係配置在邊緣環315內。在某些實施例中,邊緣環315係由介電材料形成,而具有由導電材料形成的邊緣環電極323。在某些實施例中,基板支撐件301於邊緣環315下方徑向地向外延伸,使得基板支撐件301的外徑部分提供於其上配置邊緣環315的支撐結構。然而,無論如何垂直地支撐邊緣環315,皆應理解邊緣環315乃侷限基板支撐件301的頂面301T。In the plasma processing system 300, the edge ring 315 surrounds the substrate support 301 such that the top surface 301T of the substrate support 301 is bounded by the edge ring 315. According to some embodiments, referring to the view A-A in FIG. 3A, FIG. 3B shows a top view of the substrate 105 disposed on the substrate support 301 with the edge ring 315 surrounding the substrate support 301. The edge ring electrode 323 is disposed within the edge ring 315. In some embodiments, the edge ring 315 is formed of a dielectric material and has the edge ring electrode 323 formed of a conductive material. In some embodiments, the substrate support 301 extends radially outward below the edge ring 315, such that an outer diameter portion of the substrate support 301 provides a support structure on which the edge ring 315 is disposed. However, regardless of how the edge ring 315 is vertically supported, it should be understood that the edge ring 315 circumscribes the top surface 301T of the substrate support 301.

偏壓電極123係電性連接至偏壓電壓供應系統333,如連接335所示。邊緣環電極323亦電性連接至偏壓電壓供應系統333,如連接337所示。偏壓電壓供應系統333係配置以控制偏壓電極123上的電壓以及邊緣環電極323上的電壓。偏壓電極123係配置以控制當基板105存在於基板支撐件301之頂面301T上時基板105之頂面105T上的電壓。由於存在於偏壓電極123與基板105之頂面105T之間的諸多材料,例如介電材料與存在於基板支撐件301內偏壓電極123上方的其他材料之組合以及基板105本身的材料,施加至偏壓電極123的電壓可與基板105之頂面105T上的相應電壓不同。在某些實施例中,可將存在於偏壓電極123與基板105之頂面105T之間的材料電性地表示為實質上固定電容。電壓量測裝置311係連接以量測偏壓電極123上的電壓,如連接313所示。The bias electrode 123 is electrically connected to the bias voltage supply system 333, as shown by connection 335. The edge ring electrode 323 is also electrically connected to the bias voltage supply system 333, as shown by connection 337. The bias voltage supply system 333 is configured to control the voltage on the bias electrode 123 and the voltage on the edge ring electrode 323. The bias electrode 123 is configured to control the voltage on the top surface 105T of the substrate 105 when the substrate 105 is present on the top surface 301T of the substrate support 301. Due to the presence of a number of materials between the bias electrode 123 and the top surface 105T of the substrate 105, such as a combination of dielectric materials and other materials present above the bias electrode 123 within the substrate support 301, as well as the material of the substrate 105 itself, the voltage applied to the bias electrode 123 may be different from the corresponding voltage on the top surface 105T of the substrate 105. In some embodiments, the material present between the bias electrode 123 and the top surface 105T of the substrate 105 may be electrically represented as a substantially fixed capacitance. The voltage measurement device 311 is connected to measure the voltage on the bias electrode 123, as shown by the connection 313.

除了偏壓電極123以外,基板支撐件301亦包括中階電極302。中階電極302係配置在基板支撐件301內,使得基板支撐件301的下部303存在於偏壓電極123與中階電極302之間,並且使得基板支撐件301的上部305存在於中階電極302與基板支撐件301的頂面301T之間。在某些實施例中,中階電極302係靠近施加嵌位電壓處配置以將基板105夾持至基板支撐件301上。在諸多實施例中,可以不同方式配置中階電極302。例如,在某些實施例中,中階電極302實質上係圓盤狀。在某些實施例中,中階電極302具有光柵形狀。在某些實施例中,中階電極302具有幅條形狀。在某些實施例中,中階電極302係配置為同心間隔開之環形圈的組合。應理解的是,基本上可以任何方式配置中階電極302,只要在中階電極302上量測的電壓代表於基板支撐件301內中階電極302之垂直位置處跨/穿越基板支撐件301存在的電壓。在某些實施例中,使用配置在基板支撐件301內的一或更多嵌位電極作為中階電極302,其中施加已知嵌位電壓至一或更多嵌位電極以產生將基板105夾持至基板支撐件301上的靜電吸引力。電壓量測裝置307係連接以量測中階電極302上的電壓,如連接309所示。In addition to the bias electrode 123, the substrate support 301 also includes an intermediate electrode 302. The intermediate electrode 302 is disposed in the substrate support 301 such that a lower portion 303 of the substrate support 301 is located between the bias electrode 123 and the intermediate electrode 302, and an upper portion 305 of the substrate support 301 is located between the intermediate electrode 302 and a top surface 301T of the substrate support 301. In some embodiments, the intermediate electrode 302 is disposed near where the clamping voltage is applied to clamp the substrate 105 to the substrate support 301. In various embodiments, the intermediate electrode 302 may be configured in different ways. For example, in some embodiments, the intermediate electrode 302 is substantially disk-shaped. In some embodiments, the intermediate electrode 302 has a grating shape. In some embodiments, the intermediate electrode 302 has a spoke shape. In some embodiments, the intermediate electrode 302 is configured as a combination of concentrically spaced annular rings. It should be understood that the intermediate electrode 302 can be configured in substantially any manner as long as the voltage measured on the intermediate electrode 302 represents the voltage that exists across/through the substrate support 301 at the vertical position of the intermediate electrode 302 within the substrate support 301. In some embodiments, one or more clamping electrodes disposed within the substrate support 301 are used as the intermediate electrode 302, wherein a known clamping voltage is applied to the one or more clamping electrodes to generate an electrostatic attraction force to clamp the substrate 105 to the substrate support 301. A voltage measurement device 307 is connected to measure the voltage on the intermediate electrode 302, as shown by connection 309.

邊緣環電極323係配置以控制邊緣環315之頂面315T上的電壓。由於介電材料及存在於邊緣環315內邊緣環電極323上方的其他材料,施加至邊緣環電極323的電壓可與邊緣環315之頂面315T上的相應電壓不同。在某些實施例中,可將存在於邊緣環電極323與邊緣環315之頂面315T之間的材料電性地表示為實質上固定電容。電壓量測裝置325係連接以量測邊緣環電極323上的電壓,如連接327所示。The edge ring electrode 323 is configured to control the voltage on the top surface 315T of the edge ring 315. Due to the dielectric material and other materials present in the edge ring 315 above the edge ring electrode 323, the voltage applied to the edge ring electrode 323 can be different from the corresponding voltage on the top surface 315T of the edge ring 315. In some embodiments, the material present between the edge ring electrode 323 and the top surface 315T of the edge ring 315 can be electrically represented as a substantially fixed capacitance. The voltage measurement device 325 is connected to measure the voltage on the edge ring electrode 323, as shown by the connection 327.

除了邊緣環電極323以外,邊緣環315亦包括邊緣環中階電極317。邊緣環中階電極317係配置在邊緣環315內,使得邊緣環315的下部319存在於邊緣環電極323與邊緣環中階電極317之間,並且使得邊緣環315的上部321存在於邊緣環中階電極317與邊緣環315的頂面315T之間。電壓量測裝置329係連接以量測邊緣環中階電極317上的電壓,如連接331所示。在諸多實施例中,可以不同方式配置邊緣環中階電極317。例如,在某些實施例中,邊緣環中階電極317形狀為環形圈。在某些實施例中,邊緣環中階電極317具有光柵/幅條形狀而具有電性連接至間隔開的徑向定向光柵/輻條結構之組合的一或更多環形圈。在某些實施例中,邊緣環中階電極317係配置為同心間隔開之環形圈的組合。應理解的是,基本上可以任何方式配置邊緣環中階電極317,只要在邊緣環中階電極317上量測的電壓代表於邊緣環315內邊緣環中階電極317之垂直位置處跨/穿越邊緣環315存在的電壓。In addition to the edge ring electrode 323, the edge ring 315 also includes an edge ring intermediate electrode 317. The edge ring intermediate electrode 317 is disposed within the edge ring 315 such that a lower portion 319 of the edge ring 315 exists between the edge ring electrode 323 and the edge ring intermediate electrode 317, and an upper portion 321 of the edge ring 315 exists between the edge ring intermediate electrode 317 and a top surface 315T of the edge ring 315. The voltage measuring device 329 is connected to measure the voltage on the edge ring intermediate electrode 317, as shown by connection 331. In many embodiments, the edge ring intermediate electrode 317 can be configured in different ways. For example, in some embodiments, the edge ring intermediate electrode 317 is in the shape of an annular ring. In some embodiments, the edge ring intermediate electrode 317 has a grating/strip shape and has one or more annular rings electrically connected to a combination of spaced radially oriented grating/strip structures. In some embodiments, the edge ring intermediate electrode 317 is configured as a combination of concentrically spaced annular rings. It should be understood that the edge ring mid-electrode 317 can be configured in essentially any manner as long as the voltage measured on the edge ring mid-electrode 317 is representative of the voltage that exists across/through the edge ring 315 at the vertical position of the edge ring mid-electrode 317 within the edge ring 315.

依據某些實施例,參考圖3A中視面B-B,圖3C顯示基板支撐件301內中階電極302以及邊緣環315內邊緣環中階電極317的俯視圖。在某些實施例中,電壓量測裝置311、325、307、及329以及分別相關聯的連接313、327、309、及331係偏壓電壓供應系統333之電壓量測系統的一部分。在某些實施例中,基板支撐件301內中階電極302以及邊緣環315內邊緣環中階電極317係位於電漿處理系統300內的實質上相同垂直高度處,例如圖3A中所描繪的。然而,在某些實施例中,基板支撐件301內中階電極302以及邊緣環315內邊緣環中階電極317係位於電漿處理系統300內的不同垂直高度處。According to some embodiments, referring to view B-B in FIG3A , FIG3C shows a top view of the mid-stage electrode 302 in the substrate support 301 and the edge ring mid-stage electrode 317 in the edge ring 315. In some embodiments, the voltage measurement devices 311, 325, 307, and 329 and the associated connections 313, 327, 309, and 331, respectively, are part of a voltage measurement system of a bias voltage supply system 333. In some embodiments, the mid-step electrode 302 in the substrate support 301 and the edge ring mid-step electrode 317 in the edge ring 315 are located at substantially the same vertical height in the plasma processing system 300, such as depicted in FIG3A. However, in some embodiments, the mid-step electrode 302 in the substrate support 301 and the edge ring mid-step electrode 317 in the edge ring 315 are located at different vertical heights in the plasma processing system 300.

依據某些實施例,圖3D顯示為圖3A之偏壓電壓供應系統333之示例性實施方式的偏壓電壓供應系統333A。可將偏壓電極123與邊緣環電極323、連同分別與它們相關聯的電連接335與337視為偏壓電壓供應系統333A的組件。偏壓電壓供應系統333A包括電壓供應系統341,電壓供應系統341具有經由濾波器343電性連接至偏壓電壓供應節點345的輸出,如連接347及349所示。電壓供應系統341係配置以產生指定偏壓電壓定制波形342作為偏壓電壓供應節點345上時間的函數。在某些實施例中,指定偏壓電壓定制波形342包括偏壓電壓階躍部分(Vstep)342A以及依時變化偏壓電壓部分(dV/dT)342B。在某些實施例中,指定偏壓電壓定制波形342係定義為持續的脈衝循環系列,其中每一脈衝循環包括開(on)期間與關(off)期間。電壓供應系統341係以雙向資料/信號通訊方式與控制器351連接,控制器351係可程式化以指導電壓供應系統341的操作以針對基板105上特定電漿處理操作所需而產生基本上任何形式的指定偏壓電壓定制波形342。According to some embodiments, FIG3D shows a bias voltage supply system 333A that is an exemplary implementation of the bias voltage supply system 333 of FIG3A. The bias electrode 123 and the edge ring electrode 323, together with the electrical connections 335 and 337 associated therewith, respectively, can be considered as components of the bias voltage supply system 333A. The bias voltage supply system 333A includes a voltage supply system 341 having an output electrically connected to a bias voltage supply node 345 via a filter 343, as shown by connections 347 and 349. The voltage supply system 341 is configured to generate a specified bias voltage customized waveform 342 as a function of time at a bias voltage supply node 345. In some embodiments, the specified bias voltage customized waveform 342 includes a bias voltage step portion (Vstep) 342A and a time-varying bias voltage portion (dV/dT) 342B. In some embodiments, the specified bias voltage customized waveform 342 is defined as a continuous series of pulse cycles, where each pulse cycle includes an on period and an off period. The voltage supply system 341 is connected to the controller 351 in a bidirectional data/signal communication manner, and the controller 351 is programmable to direct the operation of the voltage supply system 341 to generate essentially any form of a specified bias voltage customized waveform 342 required for a specific plasma processing operation on the substrate 105.

依據某些實施例,圖3E顯示電壓供應系統341的示例性實施方式。電壓供應系統341包括彼此以串聯方式電性連接的第一電壓供應器344A及第二電壓供應器344B,使得兩供應器的輸出電壓相加總。在某些實施例中,第一電壓供應器344A及第二電壓供應器344B的每一者係直流電壓供應器。第一電壓供應器344A係配置以依據對應指定偏壓電壓定制波形342的指定脈衝排程產生依時定電壓幅值。例如,圖3E顯示由第一電壓供應器344A產生及輸出的示例性脈衝電壓波形385而最終將變成指定偏壓電壓定制波形342的偏壓電壓階躍部分(Vstep)342A。第一電壓供應器344A的輸出係電性連接至第二電壓供應器344B的輸入,如電連接383所示。第二電壓供應器344B的輸出係電性連接至電壓供應系統341的輸出,如電連接347所示。第二電壓供應器344B係配置以產生依時變化脈衝電壓波形387而最終將變成指定偏壓電壓定制波形342的依時變化偏壓電壓部分(dV/dT)342B。在某些實施例中,依時變化脈衝電壓波形387實質上線性地變化作為在每一脈衝循環之on期間中的時間之函數。並且,在某些實施例中,依時變化脈衝電壓波形387以實質上線性的方式在幅值上增加而作為在每一脈衝循環之on期間中的時間之函數。於第二電壓供應器344B的輸出處,脈衝電壓波形385與依時變化脈衝電壓波形387相結合以產生指定偏壓電壓定制波形342。以此方式,由電壓供應系統341提供至偏壓電壓供應節點345的輸出電壓係藉由第一電壓供應器344A所產生之脈衝電壓波形385與藉由第二電壓供應器344B所產生之脈衝電壓波形387的結合。第一電壓供應器344A及第二電壓供應器344B的每一者係以雙向資料/信號通訊方式與控制器351連接,而控制器351指導第一電壓供應器344A與第二電壓供應器344B的操作以同步脈衝電壓波形385與387的相位和工作週期,以便產生指定偏壓電壓定制波形342。According to some embodiments, FIG. 3E shows an exemplary implementation of a voltage supply system 341. The voltage supply system 341 includes a first voltage supply 344A and a second voltage supply 344B electrically connected to each other in series so that the output voltages of the two supplies are summed. In some embodiments, each of the first voltage supply 344A and the second voltage supply 344B is a DC voltage supply. The first voltage supply 344A is configured to generate a time-dependent voltage amplitude according to a specified pulse schedule corresponding to the specified bias voltage customized waveform 342. For example, FIG3E shows an exemplary pulse voltage waveform 385 generated and output by the first voltage supply 344A, which will eventually become the bias voltage step portion (Vstep) 342A of the specified bias voltage custom waveform 342. The output of the first voltage supply 344A is electrically connected to the input of the second voltage supply 344B, as shown by electrical connection 383. The output of the second voltage supply 344B is electrically connected to the output of the voltage supply system 341, as shown by electrical connection 347. The second voltage supply 344B is configured to generate a time-varying pulse voltage waveform 387 that will ultimately become a time-varying bias voltage portion (dV/dT) 342B of the specified bias voltage custom waveform 342. In some embodiments, the time-varying pulse voltage waveform 387 varies substantially linearly as a function of the time during the on period of each pulse cycle. Also, in some embodiments, the time-varying pulse voltage waveform 387 increases in amplitude in a substantially linear manner as a function of the time during the on period of each pulse cycle. At the output of the second voltage supply 344B, the pulse voltage waveform 385 is combined with the time-varying pulse voltage waveform 387 to produce the specified bias voltage customized waveform 342. In this way, the output voltage provided by the voltage supply system 341 to the bias voltage supply node 345 is a combination of the pulse voltage waveform 385 generated by the first voltage supply 344A and the pulse voltage waveform 387 generated by the second voltage supply 344B. Each of the first voltage supply 344A and the second voltage supply 344B is connected to the controller 351 in a bidirectional data/signal communication manner, and the controller 351 directs the operation of the first voltage supply 344A and the second voltage supply 344B to synchronize the phase and duty cycle of the pulse voltage waveforms 385 and 387 to generate a specified bias voltage customized waveform 342.

返回參考圖3D,偏壓電壓供應系統333A包括配置以用受控方式將存在於偏壓電壓供應節點345上的電壓施加至偏壓電極123與邊緣環電極323之每一者的分路電路353。分路電路353包括第一支路355及第二支路357。第一支路355係在偏壓電壓供應節點345與偏壓電極123之間電性連接。第一支路355包括串聯電容器359及並聯電容器361。在某些實施例中,串聯電容器359及並聯電容器361的每一者係各別的可變電容器而可各自具有藉由控制器351的方式遠端控制的電容設定,控制器351係與分路電路353雙向資料/信號通訊。在某些實施例中,第一支路355包括實施以實行串聯電容器359之旁路的切換裝置360,使得偏壓電壓供應節點345能夠可切換地電性連接至串聯電容器359的輸入端抑或藉由電連接335的方式直接連接至偏壓電極123。以此方式,切換裝置360係受控以使串聯電容器359在偏壓電壓供應節點345與偏壓電極123之間串聯地電性連接,抑或將串聯電容器359從配置在偏壓電壓供應節點345與偏壓電極123之間有效地電性移除。並且,在某些實施例中,第一支路355包括實施使得並聯電容器361可電性連接至電連接335或從電連接335斷開的切換裝置362,電連接335從第一支路355的輸出延伸至偏壓電極123。以此方式,切換裝置362係受控以在偏壓電極123與參考接地電位367之間電性連接並聯電容器361,抑或將並聯電容器361從第一支路355中有效地電性移除。Referring back to FIG. 3D , the bias voltage supply system 333A includes a shunt circuit 353 configured to apply the voltage present on the bias voltage supply node 345 to each of the bias electrode 123 and the edge ring electrode 323 in a controlled manner. The shunt circuit 353 includes a first branch 355 and a second branch 357. The first branch 355 is electrically connected between the bias voltage supply node 345 and the bias electrode 123. The first branch 355 includes a series capacitor 359 and a parallel capacitor 361. In some embodiments, each of the series capacitor 359 and the shunt capacitor 361 is a respective variable capacitor and can each have a capacitance setting that is remotely controlled by means of a controller 351 that is in bidirectional data/signal communication with the shunt circuit 353. In some embodiments, the first branch 355 includes a switching device 360 that is implemented to bypass the series capacitor 359 so that the bias voltage supply node 345 can be switchably electrically connected to the input of the series capacitor 359 or directly connected to the bias electrode 123 by means of the electrical connection 335. In this manner, the switching device 360 is controlled to electrically connect the series capacitor 359 in series between the bias voltage supply node 345 and the bias electrode 123, or to effectively electrically remove the series capacitor 359 from being configured between the bias voltage supply node 345 and the bias electrode 123. Also, in some embodiments, the first branch 355 includes a switching device 362 that implements a parallel capacitor 361 that can be electrically connected to or disconnected from the electrical connection 335, which extends from the output of the first branch 355 to the bias electrode 123. In this way, the switching device 362 is controlled to electrically connect the shunt capacitor 361 between the bias electrode 123 and the reference ground potential 367, or to effectively electrically remove the shunt capacitor 361 from the first branch 355.

第二支路357係在偏壓電壓供應節點345與邊緣環電極323之間電性連接。第二支路357包括串聯電容器363及並聯電容器365。在某些實施例中,串聯電容器363及並聯電容器365的每一者係各別的可變電容器而可各自具有藉由控制器351的方式遠端控制的電容設定,控制器351係與分路電路353雙向資料/信號通訊。在某些實施例中,第二支路357包括實施以實行串聯電容器363之旁路的切換裝置369,使得偏壓電壓供應節點345能夠可切換地電性連接至串聯電容器363的輸入端抑或藉由電連接337的方式直接連接至邊緣環電極323。以此方式,切換裝置369係受控以使串聯電容器363在偏壓電壓供應節點345與邊緣環電極323之間串聯地電性連接,抑或將串聯電容器363從配置在偏壓電壓供應節點345與邊緣環電極323之間有效地電性移除。並且,在某些實施例中,第二支路357包括實施使得並聯電容器365可電性連接至電連接337或從電連接337斷開的切換裝置371,電連接337從第二支路357的輸出延伸至邊緣環電極323。以此方式,切換裝置371係受控以在邊緣環電極323與參考接地電位367之間電性連接並聯電容器365,抑或將並聯電容器365從第二支路357中有效地電性移除。The second branch 357 is electrically connected between the bias voltage supply node 345 and the edge ring electrode 323. The second branch 357 includes a series capacitor 363 and a shunt capacitor 365. In some embodiments, each of the series capacitor 363 and the shunt capacitor 365 is a respective variable capacitor and can each have a capacitance setting that is remotely controlled by means of a controller 351 that is in bidirectional data/signal communication with the shunt circuit 353. In some embodiments, the second branch 357 includes a switching device 369 implemented to bypass the series capacitor 363, so that the bias voltage supply node 345 can be switchably electrically connected to the input terminal of the series capacitor 363 or directly connected to the edge ring electrode 323 by way of the electrical connection 337. In this way, the switching device 369 is controlled to electrically connect the series capacitor 363 in series between the bias voltage supply node 345 and the edge ring electrode 323, or to effectively electrically remove the series capacitor 363 from being configured between the bias voltage supply node 345 and the edge ring electrode 323. Also, in some embodiments, the second branch 357 includes a switching device 371 that implements a shunt capacitor 365 that can be electrically connected to or disconnected from an electrical connection 337 that extends from the output of the second branch 357 to the edge ring electrode 323. In this way, the switching device 371 is controlled to electrically connect the shunt capacitor 365 between the edge ring electrode 323 and the reference ground potential 367, or to effectively electrically remove the shunt capacitor 365 from the second branch 357.

在某些實施例中,第一支路355係配置使得串聯電容器359及並聯電容器361斷離,且第二支路357係配置使得串聯電容器363及並聯電容器365接合。更具體而言,在此些實施例中,切換裝置360及362係設定使得偏壓電壓供應節點345直接電性連接至偏壓電極123,且切換裝置369及371係設定使得從偏壓電壓供應節點345傳遞至邊緣環電極323的偏壓電壓受串聯電容器363及並聯電容器365控制。從而,在此些實施例中,由電壓供應系統341輸出的偏壓電壓定制波形342係供應至偏壓電極123,並且由電壓供應系統341輸出之偏壓電壓定制波形342的修改版本係供應至邊緣環電極323。In some embodiments, the first branch 355 is configured to disconnect the series capacitor 359 and the parallel capacitor 361, and the second branch 357 is configured to connect the series capacitor 363 and the parallel capacitor 365. More specifically, in these embodiments, the switching devices 360 and 362 are configured to connect the bias voltage supply node 345 directly to the bias electrode 123, and the switching devices 369 and 371 are configured to control the bias voltage transmitted from the bias voltage supply node 345 to the edge ring electrode 323 by the series capacitor 363 and the parallel capacitor 365. Thus, in these embodiments, the bias voltage customized waveform 342 output by the voltage supply system 341 is supplied to the bias electrode 123, and a modified version of the bias voltage customized waveform 342 output by the voltage supply system 341 is supplied to the edge ring electrode 323.

在某些實施例中,第一支路355係配置使得串聯電容器359及並聯電容器361接合,且第二支路357係配置使得串聯電容器363及並聯電容器365接合。更具體而言,在此些實施例中,切換裝置360及362係設定使得從偏壓電壓供應節點345傳遞至偏壓電極123的偏壓電壓受串聯電容器359及並聯電容器361控制,且切換裝置369及371係設定使得從偏壓電壓供應節點345傳遞至邊緣環電極323的偏壓電壓受串聯電容器363及並聯電容器365控制。從而,在此些實施例中,由電壓供應系統341輸出之偏壓電壓定制波形342的第一修改版本係供應至偏壓電極123,並且由電壓供應系統341輸出之偏壓電壓定制波形342的第二修改版本係供應至邊緣環電極323。In some embodiments, the first branch 355 is configured so that the series capacitor 359 and the parallel capacitor 361 are connected, and the second branch 357 is configured so that the series capacitor 363 and the parallel capacitor 365 are connected. More specifically, in these embodiments, the switching devices 360 and 362 are configured so that the bias voltage transmitted from the bias voltage supply node 345 to the bias electrode 123 is controlled by the series capacitor 359 and the parallel capacitor 361, and the switching devices 369 and 371 are configured so that the bias voltage transmitted from the bias voltage supply node 345 to the edge ring electrode 323 is controlled by the series capacitor 363 and the parallel capacitor 365. Thus, in these embodiments, a first modified version of the bias voltage customized waveform 342 output by the voltage supply system 341 is supplied to the bias electrode 123, and a second modified version of the bias voltage customized waveform 342 output by the voltage supply system 341 is supplied to the edge ring electrode 323.

此外,在某些實施例中,可在第一支路355中接合串聯電容器359,而斷離並聯電容器361。在某些實施例中,可在第一支路355中接合並聯電容器361,而斷離串聯電容器359。並且,在某些實施例中,可在第二支路357中接合串聯電容器363,而斷離並聯電容器365。在某些實施例中,可在第二支路357中接合並聯電容器365,而斷離串聯電容器363。Additionally, in some embodiments, series capacitor 359 may be engaged in first branch 355 and shunt capacitor 361 may be disconnected. In some embodiments, shunt capacitor 361 may be engaged in first branch 355 and series capacitor 359 may be disconnected. And, in some embodiments, series capacitor 363 may be engaged in second branch 357 and shunt capacitor 365 may be disconnected. In some embodiments, shunt capacitor 365 may be engaged in second branch 357 and series capacitor 363 may be disconnected.

在某些實施例中,例如電壓/電流感測器(VI感測器)的電壓感測器373係連接以量測偏壓電壓供應節點345上的即時電壓,並將關於此量測電壓的資訊傳遞至控制器351。在某些實施例中,例如電壓/電流感測器(VI感測器)的電壓感測器375係連接以量測於第一支路355之輸出處的即時電壓,並將關於此量測電壓的資訊傳遞至控制器351。在某些實施例中,例如電壓/電流感測器(VI感測器)的電壓感測器377係連接以量測於第二支路357之輸出處的即時電壓,並將關於此量測電壓的資訊傳遞至控制器351。在諸多實施例中,控制器351係配置以使用藉由電壓感測器373、375、及377中的一或更多者所量測的電壓作為回饋信號(一或多)以用於控制電壓供應系統341以及串聯電容器359、並聯電容器361、串聯電容器363、及並聯電容器365中之一或更多者的操作。In some embodiments, a voltage sensor 373, such as a voltage/current flow sensor (VI sensor), is connected to measure the instantaneous voltage on the bias voltage supply node 345 and transmits information about the measured voltage to the controller 351. In some embodiments, a voltage sensor 375, such as a voltage/current flow sensor (VI sensor), is connected to measure the instantaneous voltage at the output of the first branch 355 and transmits information about the measured voltage to the controller 351. In some embodiments, a voltage sensor 377, such as a voltage/current sensor (VI sensor), is connected to measure the instantaneous voltage at the output of the second branch 357 and transmit information about the measured voltage to the controller 351. In many embodiments, the controller 351 is configured to use the voltage measured by one or more of the voltage sensors 373, 375, and 377 as feedback signals (one or more) for controlling the operation of the voltage supply system 341 and one or more of the series capacitor 359, the shunt capacitor 361, the series capacitor 363, and the shunt capacitor 365.

並且,在某些實施例中,偏壓電壓供應系統333A包括連接以經由各別的阻抗匹配網路381-1至381-N供應RF偏壓電壓至偏壓電壓供應節點345的若干(N)RF產生器379-1至379-N,其中N大於或等於1。RF產生器379-1至379-N中的每一者係以雙向資料/信號通訊方式與控制器351連接。於偏壓電壓供應節點345處,藉由RF產生器379-1至379-N輸出的RF電壓信號(一或多)與藉由電壓供應系統341輸出的偏壓電壓定制波形342相結合。在偏壓電壓供應系統333A的某些實施例中實施RF產生器379-1至379-N以及相應的阻抗匹配網路381-1至381-N。然而,在偏壓電壓供應系統333A的其他實施例中,不實施RF產生器379-1至379-N以及相應的阻抗匹配網路381-1至381-N。Also, in some embodiments, the bias voltage supply system 333A includes a plurality (N) of RF generators 379-1 to 379-N connected to supply RF bias voltage to the bias voltage supply node 345 via respective impedance matching networks 381-1 to 381-N, where N is greater than or equal to 1. Each of the RF generators 379-1 to 379-N is connected to the controller 351 in bidirectional data/signal communication. At the bias voltage supply node 345, the RF voltage signal (one or more) output by the RF generators 379-1 to 379-N is combined with the bias voltage customized waveform 342 output by the voltage supply system 341. In some embodiments of the bias voltage supply system 333A, RF generators 379-1 to 379-N and corresponding impedance matching networks 381-1 to 381-N are implemented. However, in other embodiments of the bias voltage supply system 333A, RF generators 379-1 to 379-N and corresponding impedance matching networks 381-1 to 381-N are not implemented.

依據某些實施例,圖3F顯示藉由電壓供應系統341產生的示例性偏壓電壓定制波形342、以及在基板105之頂面105T上的相應偏壓電壓波形372、以及在邊緣環315之頂面315T上的相應偏壓電壓波形374。偏壓電壓定制波形342包括偏壓電壓階躍部分(Vstep)342A以及依時變化偏壓電壓部分(dV/dT)342B。偏壓電壓定制波形342係在偏壓電壓供應節點345上產生。因而,在基板105之頂面105T上的偏壓電壓波形372係基於藉由第一支路355修改的偏壓電壓定制波形342。相似地,在邊緣環315之頂面315T上的偏壓電壓波形374係基於藉由第二支路357修改的偏壓電壓定制波形342。偏壓電壓波形372包括階躍部分372A以及斜坡部分372B。偏壓電壓波形374包括階躍部分374A以及斜坡部分374B。According to some embodiments, FIG. 3F shows an exemplary bias voltage customized waveform 342 generated by a voltage supply system 341, and a corresponding bias voltage waveform 372 on the top surface 105T of the substrate 105, and a corresponding bias voltage waveform 374 on the top surface 315T of the edge ring 315. The bias voltage customized waveform 342 includes a bias voltage step portion (Vstep) 342A and a time-varying bias voltage portion (dV/dT) 342B. The bias voltage customized waveform 342 is generated on a bias voltage supply node 345. Thus, the bias voltage waveform 372 on the top surface 105T of the substrate 105 is based on the bias voltage customized waveform 342 modified by the first branch 355. Similarly, the bias voltage waveform 374 on the top surface 315T of the edge ring 315 is based on the bias voltage customized waveform 342 modified by the second branch 357. The bias voltage waveform 372 includes a step portion 372A and a ramp portion 372B. The bias voltage waveform 374 includes a step portion 374A and a ramp portion 374B.

在第一支路355中的並聯電容器361控制基板105之頂面105T上的偏壓電壓波形372之階躍部分372A的幅值。具體而言,並聯電容器361的電容設定可受控以將階躍部分372A的幅值設定為偏壓電壓階躍部分(Vstep)342A之幅值的百分比(0至100%)。若在第一支路355中斷離(或不存在)並聯電容器361,則階躍部分372A的幅值係偏壓電壓階躍部分(Vstep)342A之幅值的固定百分比,並取決於存在於偏壓電極123與基板105的頂面105T之間的基板支撐件301與基板105之材料的本質電容效應。上述偏壓電壓階躍部分(Vstep)342A之幅值的固定百分比係取決於電壓供應系統341之輸出與基板105的頂面105T之間的結構。例如,在結構中可能存在雜散並聯電容,例如濾波器343、阻抗匹配網路381-1至381-N、以及電連接347、349、345、及335。並且,當偏壓電壓階躍部分(Vstep)342A的上升時間相較於穿越電漿鞘之離子旅行時間相對較長時,由於在Vstep 342A之上升時間期間的離子通量,在電壓供應系統341之輸出與基板105的頂面105T之間的串聯電容可降低上述Vstep 342A之幅值的固定百分比。例如,在某些實施例中,可針對某些目的在濾波器343、基板支撐件301、基板105、及/或電連接347、349、345、及335中插入諸多串聯電容。可藉由具有相對較短的Vstep 342A之上升時間而大部分地消除起因於串聯電容之上述Vstep 342A之幅值的固定百分比下降,例如,Vstep << 1微秒。The shunt capacitor 361 in the first branch 355 controls the amplitude of the step portion 372A of the bias voltage waveform 372 on the top surface 105T of the substrate 105. Specifically, the capacitance setting of the shunt capacitor 361 can be controlled to set the amplitude of the step portion 372A as a percentage (0 to 100%) of the amplitude of the bias voltage step portion (Vstep) 342A. If the parallel capacitor 361 is disconnected (or does not exist) in the first branch 355, the amplitude of the step portion 372A is a fixed percentage of the amplitude of the bias voltage step portion (Vstep) 342A, and depends on the intrinsic capacitance effect of the substrate support 301 and the material of the substrate 105 between the bias electrode 123 and the top surface 105T of the substrate 105. The fixed percentage of the amplitude of the bias voltage step portion (Vstep) 342A is determined by the structure between the output of the voltage supply system 341 and the top surface 105T of the substrate 105. For example, stray shunt capacitance may exist in structures such as filter 343, impedance matching networks 381-1 to 381-N, and electrical connections 347, 349, 345, and 335. Also, when the rise time of the bias voltage step portion (Vstep) 342A is relatively long compared to the ion travel time through the plasma sheath, the series capacitance between the output of the voltage supply system 341 and the top surface 105T of the substrate 105 may reduce the magnitude of the above Vstep 342A by a fixed percentage due to the ion flux during the rise time of Vstep 342A. For example, in some embodiments, multiple series capacitors may be inserted for certain purposes in the filter 343, substrate support 301, substrate 105, and/or electrical connections 347, 349, 345, and 335. The fixed percentage drop in the magnitude of Vstep 342A due to the series capacitors may be largely eliminated by having a relatively short rise time of Vstep 342A, e.g., Vstep << 1 microsecond.

在第一支路355中的串聯電容器359控制基板105之頂面105T上的偏壓電壓波形372之斜坡部分372B的斜率(相對於時間的電壓變動)。當施加電壓至偏壓電極123時,存在從電漿119朝向基板105之頂面105T的離子電流,而將基板105之頂面105T上的負電荷放電並且相應地造成基板105之頂面105T上負電壓之幅值隨著時間的減少。為了補償此離子引起的基板105之頂面105T上負電壓之幅值的減少,偏壓電壓定制波形342的依時變化偏壓電壓部分(dV/dT)342B提供隨著時間的偏壓電壓增加。串聯電容器359的電容設定係受控以將偏壓電壓的變動調諧作為基板105之頂面105T上時間的函數以補償離子引起的基板105之頂面105T上負電荷的放電。在某些實施例中,串聯電容器359的電容設定係受控以於偏壓電壓定制波形342的on期間中維持基板105之頂面105T上的實質上恆定電壓。然而,在其他實施例中,串聯電容器359的電容設定係受控以達成所期望的電壓變動而作為於偏壓電壓定制波形342的on期間中基板105之頂面105T上時間的函數(正dV/dT及/或負dV/dT)。若在第一支路355中斷離/旁路(或不存在)串聯電容器359,則作為於偏壓電壓定制波形342的on期間中基板105之頂面105T上時間之函數(dV/dT)的電壓變動將追隨偏壓電壓定制波形342的依時變化偏壓電壓部分(dV/dT)342B,而具有基於存在於偏壓電極123與基板105的頂面105T之間的基板支撐件301與基板105之材料之本質電容效應的固定電壓幅值偏移。在某些實施例中,上述固定電壓幅值偏移亦可基於在電壓供應系統341之輸出與基板105的頂面105T之間的本質串聯電容。在某些實施例中,上述本質串聯電容相應於針對某些目的在濾波器343、基板支撐件301、基板105、及/或電連接347、349、345、及335中插入的諸多串聯電容。The series capacitor 359 in the first branch 355 controls the slope (voltage variation with respect to time) of the ramp portion 372B of the bias voltage waveform 372 on the top surface 105T of the substrate 105. When voltage is applied to the bias electrode 123, there is an ion current from the plasma 119 toward the top surface 105T of the substrate 105, which discharges the negative charge on the top surface 105T of the substrate 105 and correspondingly causes the magnitude of the negative voltage on the top surface 105T of the substrate 105 to decrease with time. To compensate for the ion-induced decrease in the magnitude of the negative voltage on the top surface 105T of the substrate 105, the time-dependent bias voltage portion (dV/dT) 342B of the bias voltage customized waveform 342 provides a bias voltage increase over time. The capacitance setting of the series capacitor 359 is controlled to tune the variation of the bias voltage as a function of time on the top surface 105T of the substrate 105 to compensate for the ion-induced discharge of the negative charge on the top surface 105T of the substrate 105. In some embodiments, the capacitance setting of the series capacitor 359 is controlled to maintain a substantially constant voltage on the top surface 105T of the substrate 105 during the on period of the bias voltage customized waveform 342. However, in other embodiments, the capacitance setting of the series capacitor 359 is controlled to achieve a desired voltage variation as a function of time (positive dV/dT and/or negative dV/dT) on the top surface 105T of the substrate 105 during the on period of the bias voltage customized waveform 342. If the series capacitor 359 is disconnected/bypassed (or does not exist) in the first branch 355, then the voltage variation as a function of time (dV/dT) on the top surface 105T of the substrate 105 during the on period of the bias voltage customized waveform 342 will track the time-dependent bias voltage portion (dV/dT) 342B of the bias voltage customized waveform 342, and have a fixed voltage amplitude offset based on the intrinsic capacitive effect of the substrate support 301 and the material of the substrate 105 between the bias electrode 123 and the top surface 105T of the substrate 105. In some embodiments, the fixed voltage amplitude offset may also be based on an intrinsic series capacitance between the output of the voltage supply system 341 and the top surface 105T of the substrate 105. In some embodiments, the intrinsic series capacitance corresponds to a plurality of series capacitors inserted in the filter 343, the substrate support 301, the substrate 105, and/or the electrical connections 347, 349, 345, and 335 for some purpose.

在第二支路357中的並聯電容器365控制邊緣環315之頂面315T上的偏壓電壓波形374之階躍部分374A的幅值。具體而言,並聯電容器365的電容設定可受控以將階躍部分374A的幅值設定為偏壓電壓階躍部分(Vstep)342A之幅值的百分比(0至100%)。若在第二支路357中斷離(或不存在)並聯電容器365,則階躍部分374A的幅值係偏壓電壓階躍部分(Vstep)342A之幅值的固定百分比,並取決於存在於邊緣環電極323與邊緣環315的頂面315T之間的邊緣環315材料的本質電容效應。在某些實施例中,階躍部分374A的幅值亦可基於在電壓供應系統341之輸出與邊緣環315的頂面315T之間的本質串聯電容。在某些實施例中,上述本質串聯電容相應於針對某些目的在濾波器343、邊緣環315、及/或電連接347、349、345、及337中插入的諸多串聯電容。The parallel capacitor 365 in the second branch 357 controls the amplitude of the step portion 374A of the bias voltage waveform 374 on the top surface 315T of the edge ring 315. Specifically, the capacitance setting of the parallel capacitor 365 can be controlled to set the amplitude of the step portion 374A as a percentage (0 to 100%) of the amplitude of the bias voltage step portion (Vstep) 342A. If the shunt capacitor 365 is disconnected (or not present) in the second branch 357, the magnitude of the step portion 374A is a fixed percentage of the magnitude of the bias voltage step portion (Vstep) 342A and depends on the intrinsic capacitance effect of the edge ring 315 material between the edge ring electrode 323 and the top surface 315T of the edge ring 315. In some embodiments, the magnitude of the step portion 374A can also be based on the intrinsic series capacitance between the output of the voltage supply system 341 and the top surface 315T of the edge ring 315. In some embodiments, the intrinsic series capacitance described above corresponds to a plurality of series capacitors inserted in the filter 343, the edge ring 315, and/or the electrical connections 347, 349, 345, and 337 for certain purposes.

在第二支路357中的串聯電容器363控制邊緣環315之頂面315T上的偏壓電壓波形374之斜坡部分374B的斜率(相對於時間的電壓變動)。當施加電壓至邊緣環電極323時,存在從電漿119朝向邊緣環315之頂面315T的離子電流,而將邊緣環315之頂面315T上的負電荷放電並且相應地造成邊緣環315之頂面315T上負電壓之幅值隨著時間的減少。為了補償此離子引起的邊緣環315之頂面315T上負電壓之幅值的減少,偏壓電壓定制波形342的依時變化偏壓電壓部分(dV/dT)342B提供隨著時間的偏壓電壓增加。串聯電容器363的電容設定係受控以將偏壓電壓的變動調諧作為邊緣環315之頂面315T上時間的函數以補償離子引起的邊緣環315之頂面315T上負電荷的放電。在某些實施例中,串聯電容器363的電容設定係受控以於偏壓電壓定制波形342的on期間中維持邊緣環315之頂面315T上的實質上恆定電壓。然而,在其他實施例中,串聯電容器363的電容設定係受控以達成所期望的電壓變動而作為於偏壓電壓定制波形342的on期間中邊緣環315之頂面315T上時間的函數(正dV/dT及/或負dV/dT)。若在第二支路357中斷離/旁路(或不存在)串聯電容器363,則作為於偏壓電壓定制波形342的on期間中邊緣環315之頂面315T上時間之函數(dV/dT)的電壓變動將追隨偏壓電壓定制波形342的依時變化偏壓電壓部分(dV/dT)342B,而具有基於存在於邊緣環電極323與邊緣環315的頂面315T之間的邊緣環315材料之本質電容效應的固定電壓幅值偏移。在某些實施例中,上述固定電壓幅值偏移亦可基於在電壓供應系統341之輸出與邊緣環315的頂面315T之間的本質串聯電容。在某些實施例中,上述本質串聯電容相應於針對某些目的在濾波器343、邊緣環315、及/或電連接347、349、345、及337中插入的諸多串聯電容。The series capacitor 363 in the second branch 357 controls the slope (voltage variation with respect to time) of the ramp portion 374B of the bias voltage waveform 374 on the top surface 315T of the edge ring 315. When voltage is applied to the edge ring electrode 323, there is an ion current from the plasma 119 toward the top surface 315T of the edge ring 315, which discharges the negative charge on the top surface 315T of the edge ring 315 and correspondingly causes the magnitude of the negative voltage on the top surface 315T of the edge ring 315 to decrease with time. To compensate for this ion-induced decrease in the magnitude of the negative voltage on the top surface 315T of the edge ring 315, the time-dependent bias voltage portion (dV/dT) 342B of the bias voltage customized waveform 342 provides a bias voltage increase over time. The capacitance setting of the series capacitor 363 is controlled to tune the variation of the bias voltage as a function of time on the top surface 315T of the edge ring 315 to compensate for the ion-induced discharge of the negative charge on the top surface 315T of the edge ring 315. In some embodiments, the capacitance setting of the series capacitor 363 is controlled to maintain a substantially constant voltage on the top surface 315T of the edge ring 315 during the on period of the bias voltage customized waveform 342. However, in other embodiments, the capacitance setting of the series capacitor 363 is controlled to achieve a desired voltage variation as a function of time (positive dV/dT and/or negative dV/dT) on the top surface 315T of the edge ring 315 during the on period of the bias voltage customized waveform 342. If the series capacitor 363 is disconnected/bypassed (or does not exist) in the second branch 357, then the voltage variation as a function of time (dV/dT) on the top surface 315T of the edge ring 315 during the on period of the bias voltage customized waveform 342 will track the time-dependent bias voltage portion (dV/dT) 342B of the bias voltage customized waveform 342, with a fixed voltage amplitude offset based on the intrinsic capacitance effect of the edge ring 315 material between the edge ring electrode 323 and the top surface 315T of the edge ring 315. In some embodiments, the fixed voltage amplitude offset may also be based on an intrinsic series capacitance between the output of the voltage supply system 341 and the top surface 315T of the edge ring 315. In some embodiments, the intrinsic series capacitance corresponds to a plurality of series capacitors inserted in the filter 343, the edge ring 315, and/or the electrical connections 347, 349, 345, and 337 for some purpose.

依據某些實施例,圖3G顯示為圖3A之偏壓電壓供應系統333之示例性實施方式的偏壓電壓供應系統333B。偏壓電壓供應系統333B包括第一電壓供應系統390及第二電壓供應系統395。第一電壓供應系統390包括具有經由濾波器392及電連接335連接至偏壓電極123之輸出的電壓供應系統391。電壓供應系統391係以與電壓供應系統341相同的方式配置。因而,電壓供應系統391產生並供應指定偏壓電壓定制波形342-1至偏壓電極123。指定偏壓電壓定制波形342-1包括階躍部分342A1以及斜坡部分342B1。濾波器392係配置以防止RF信號進入電壓供應系統391。在諸多實施例中,濾波器392係低通濾波器或陷波濾波器。According to some embodiments, FIG3G shows a bias voltage supply system 333B that is an exemplary implementation of the bias voltage supply system 333 of FIG3A. The bias voltage supply system 333B includes a first voltage supply system 390 and a second voltage supply system 395. The first voltage supply system 390 includes a voltage supply system 391 having an output connected to the bias electrode 123 via a filter 392 and an electrical connection 335. The voltage supply system 391 is configured in the same manner as the voltage supply system 341. Thus, the voltage supply system 391 generates and supplies a specified bias voltage customized waveform 342-1 to the bias electrode 123. The specified bias voltage customized waveform 342-1 includes a step portion 342A1 and a ramp portion 342B1. The filter 392 is configured to prevent the RF signal from entering the voltage supply system 391. In many embodiments, the filter 392 is a low pass filter or a notch filter.

第一電壓供應系統390亦可選地包括連接以經由各別的阻抗匹配網路394-1至394-N供應RF偏壓電壓至偏壓電極123的若干(N)RF產生器393-1至393-N,其中N大於或等於1。RF產生器393-1至393-N中的每一者係以雙向資料/信號通訊方式與控制器351連接。控制器351操作以同步藉由電壓供應系統391以及RF產生器393-1至393-N之每一者輸出的偏壓電壓波形。藉由RF產生器393-1至393-N輸出的RF電壓信號(一或多)在電連接335上與藉由電壓供應系統391輸出的偏壓電壓定制波形342-1相結合。在第一電壓供應系統390的某些實施例中實施RF產生器393-1至393-N以及相應的阻抗匹配網路394-1至394-N。然而,在某些實施例中,於第一電壓供應系統390中不實施RF產生器393-1至393-N以及相應的阻抗匹配網路394-1至394-N。The first voltage supply system 390 also optionally includes a plurality (N) of RF generators 393-1 to 393-N connected to supply RF bias voltage to the bias electrode 123 via respective impedance matching networks 394-1 to 394-N, where N is greater than or equal to 1. Each of the RF generators 393-1 to 393-N is connected in bidirectional data/signal communication with the controller 351. The controller 351 operates to synchronize the bias voltage waveform output by the voltage supply system 391 and each of the RF generators 393-1 to 393-N. The RF voltage signal(s) output by the RF generators 393-1 to 393-N are combined on electrical connection 335 with the bias voltage customized waveform 342-1 output by the voltage supply system 391. The RF generators 393-1 to 393-N and corresponding impedance matching networks 394-1 to 394-N are implemented in some embodiments of the first voltage supply system 390. However, in some embodiments, the RF generators 393-1 to 393-N and corresponding impedance matching networks 394-1 to 394-N are not implemented in the first voltage supply system 390.

第二電壓供應系統395包括具有經由濾波器397及電連接337連接至邊緣環電極323之輸出的電壓供應系統396。電壓供應系統396係以與電壓供應系統341相同的方式配置。因而,電壓供應系統396產生並供應指定偏壓電壓定制波形342-2至邊緣環電極323。指定偏壓電壓定制波形342-2包括階躍部分342A2以及斜坡部分342B2。濾波器397係配置以防止RF信號進入電壓供應系統396。在諸多實施例中,濾波器397係低通濾波器或陷波濾波器。The second voltage supply system 395 includes a voltage supply system 396 having an output connected to the edge ring electrode 323 via a filter 397 and an electrical connection 337. The voltage supply system 396 is configured in the same manner as the voltage supply system 341. Thus, the voltage supply system 396 generates and supplies a specified bias voltage customized waveform 342-2 to the edge ring electrode 323. The specified bias voltage customized waveform 342-2 includes a step portion 342A2 and a ramp portion 342B2. The filter 397 is configured to prevent RF signals from entering the voltage supply system 396. In many embodiments, filter 397 is a low pass filter or a notch filter.

第二電壓供應系統395亦可選地包括連接以經由各別的阻抗匹配網路399-1至399-N供應RF偏壓電壓至邊緣環電極323的若干(N)RF產生器398-1至398-N,其中N大於或等於1。RF產生器398-1至398-N中的每一者係以雙向資料/信號通訊方式與控制器351連接。控制器351操作以同步藉由電壓供應系統396以及RF產生器398-1至398-N之每一者輸出的偏壓電壓波形。藉由RF產生器398-1至398-N輸出的RF電壓信號(一或多)在電連接337上與藉由電壓供應系統396輸出的偏壓電壓定制波形342-2相結合。在第二電壓供應系統395的某些實施例中實施RF產生器398-1至398-N以及相應的阻抗匹配網路399-1至399-N。然而,在某些實施例中,於第二電壓供應系統395中不實施RF產生器398-1至398-N以及相應的阻抗匹配網路399-1至399-N。The second voltage supply system 395 also optionally includes a plurality (N) of RF generators 398-1 to 398-N connected to supply RF bias voltage to the edge ring electrode 323 via respective impedance matching networks 399-1 to 399-N, where N is greater than or equal to 1. Each of the RF generators 398-1 to 398-N is connected in bidirectional data/signal communication with the controller 351. The controller 351 operates to synchronize the bias voltage waveform output by the voltage supply system 396 and each of the RF generators 398-1 to 398-N. The RF voltage signal(s) output by the RF generators 398-1 to 398-N are combined on electrical connection 337 with the bias voltage custom waveform 342-2 output by the voltage supply system 396. The RF generators 398-1 to 398-N and corresponding impedance matching networks 399-1 to 399-N are implemented in some embodiments of the second voltage supply system 395. However, in some embodiments, the RF generators 398-1 to 398-N and corresponding impedance matching networks 399-1 to 399-N are not implemented in the second voltage supply system 395.

在某些實施例中,偏壓電壓定制波形342-1係產生以於偏壓電壓定制波形342-1內每一脈衝循環的on期間中維持基板105之頂面105T上的實質上恆定電壓,且偏壓電壓定制波形342-2係產生以於偏壓電壓定制波形342-2內每一脈衝循環的on期間中維持邊緣環315之頂面315T上的實質上恆定電壓,使得於偏壓電壓定制波形342-1及342-2中脈衝循環的並行on期間中維持實質上恆定電壓差,其中實質上恆定電壓差係定義以維持跨基板105與邊緣環315之間過渡的實質上平坦電漿鞘邊界。在某些實施例中,偏壓電壓定制波形342-1的階躍部分342A1以及偏壓電壓定制波形342-2的階躍部分342A2係同步受控以達成在基板105的頂面105T與邊緣環315的頂面315T之間的指定電壓差。並且,在某些實施例中,偏壓電壓定制波形342-1的斜坡部分342B1係受控以補償在偏壓電壓定制波形342-1之每一脈衝循環的on期間由離子引起的基板105之頂面105T上負電荷的放電,使得在偏壓電壓定制波形342-1之每一脈衝循環的on期間於基板105之頂面105T上的電壓保持實質上恆定。並且,在某些實施例中,偏壓電壓定制波形342-2的斜坡部分342B2係受控以補償在偏壓電壓定制波形342-2之每一脈衝循環的on期間由離子引起的邊緣環315之頂面315T上負電荷的放電,使得在偏壓電壓定制波形342-2之每一脈衝循環的on期間於邊緣環315之頂面315T上的電壓保持實質上恆定。In some embodiments, the bias voltage customized waveform 342-1 is generated to maintain a substantially constant voltage on the top surface 105T of the substrate 105 during the on period of each pulse cycle in the bias voltage customized waveform 342-1, and the bias voltage customized waveform 342-2 is generated to maintain a substantially constant voltage on the top surface 105T of the substrate 105 during the on period of each pulse cycle in the bias voltage customized waveform 342-2. A substantially constant voltage is maintained on the top surface 315T of the edge ring 315 during the period, so that a substantially constant voltage difference is maintained during the parallel on period of the pulse cycles in the bias voltage customized waveforms 342-1 and 342-2, wherein the substantially constant voltage difference is defined to maintain a substantially flat plasma sheath boundary transitioning between the substrate 105 and the edge ring 315. In some embodiments, the step portion 342A1 of the bias voltage customized waveform 342-1 and the step portion 342A2 of the bias voltage customized waveform 342-2 are synchronously controlled to achieve a specified voltage difference between the top surface 105T of the substrate 105 and the top surface 315T of the edge ring 315. Furthermore, in some embodiments, the slope portion 342B1 of the bias voltage customized waveform 342-1 is controlled to compensate for the discharge of negative charges on the top surface 105T of the substrate 105 caused by ions during the on period of each pulse cycle of the bias voltage customized waveform 342-1, so that the voltage on the top surface 105T of the substrate 105 during the on period of each pulse cycle of the bias voltage customized waveform 342-1 remains substantially constant. Furthermore, in some embodiments, the slope portion 342B2 of the bias voltage customized waveform 342-2 is controlled to compensate for the discharge of negative charges on the top surface 315T of the edge ring 315 caused by ions during the on period of each pulse cycle of the bias voltage customized waveform 342-2, so that the voltage on the top surface 315T of the edge ring 315 during the on period of each pulse cycle of the bias voltage customized waveform 342-2 remains substantially constant.

在某些實施例中,控制器351操作以同步偏壓電壓定制波形342-1及342-2的相位。在某些實施例中,控制器351操作以同步偏壓電壓定制波形342-1及342-2的相位及工作週期兩者。在某些實施例中,控制器351操作以實施偏壓電壓定制波形342-1與342-2之間的指定相移。在某些實施例中,偏壓電壓定制波形342-1及342-2係定義為具有相對於彼此不同的相位及/或不同的工作週期。並且,在某些實施例中,偏壓電壓定制波形342-1及342-2中的一或二者係定義以實施指定逐級脈衝方案。應理解的是,偏壓電壓定制波形342-1及342-2相對於彼此係可分離且獨立受控的。In some embodiments, the controller 351 operates to synchronize the phases of the bias voltage customized waveforms 342-1 and 342-2. In some embodiments, the controller 351 operates to synchronize both the phases and duty cycles of the bias voltage customized waveforms 342-1 and 342-2. In some embodiments, the controller 351 operates to implement a specified phase shift between the bias voltage customized waveforms 342-1 and 342-2. In some embodiments, the bias voltage customized waveforms 342-1 and 342-2 are defined to have different phases and/or different duty cycles relative to each other. And, in some embodiments, one or both of the bias voltage customized waveforms 342-1 and 342-2 are defined to implement a specified step-by-step pulse scheme. It should be understood that the bias voltage customized waveforms 342-1 and 342-2 are separable and independently controllable relative to each other.

此外,在諸多實施例中,可在偏壓電壓供應系統333B內連接任意數量之例如電壓/電流感測器(VI感測器)的電壓感測器,以於特定位置量測即時電壓,並將關於此所量測即時電壓的資訊傳遞至控制器351。在某些實施例中,控制器351係配置以使用第一電壓供應系統390及/或第二電壓供應系統395內的即時電壓量測以控制電壓供應系統391、RF產生器393-1至393-N、電壓供應系統396、以及RF產生器398-1至398-N中任意一或更多者的操作。Additionally, in many embodiments, any number of voltage sensors, such as voltage/current sensors (VI sensors), may be connected within the bias voltage supply system 333B to measure the real-time voltage at a particular location and transmit information about the measured real-time voltage to the controller 351. In some embodiments, the controller 351 is configured to use the real-time voltage measurements within the first voltage supply system 390 and/or the second voltage supply system 395 to control the operation of any one or more of the voltage supply system 391, the RF generators 393-1 to 393-N, the voltage supply system 396, and the RF generators 398-1 to 398-N.

依據某些實施例,圖4顯示控制器351的示例圖。在某些實施例中,控制器351包括處理器409、儲存硬體單元(HU)411(例如,記憶體)、輸入HU 401、輸出HU 405、輸入/輸出(I/O)介面403、I/O介面407、網路介面控制器(NIC)415、及資料通訊匯流排413。處理器409、儲存HU 411、輸入HU 401、輸出HU 405、I/O介面403、I/O介面407、及NIC 415係經由資料通訊匯流排413與彼此資料通訊。輸入HU 401的範例包括滑鼠、鍵盤、手寫筆、資料獲取系統、資料獲取卡等。輸出HU 405的範例包括顯示器、揚聲器、裝置控制器等。NIC 415的範例包括網路介面卡、網路配接器等。在諸多實施例中,NIC 415係配置以依據一或更多通訊協定及相關聯的實體層操作,例如乙太網路及/或EtherCAT、以及其他等等。I/O介面403及407的每一者係定義以提供耦接至I/O介面之不同硬體單元之間的相容性。例如,可定義I/O介面403以將從輸入HU 401接收的信號變換成與資料通訊匯流排413形式、振幅、及/或速度相容。並且,可定義I/O介面407以將從資料通訊匯流排413接收的信號變換成與輸出HU 405形式、振幅、及/或速度相容。儘管本文所述的諸多操作係藉由控制器351的處理器409執行,但應理解在某些實施例中,可藉由控制器351的多個處理器及/或藉由連接至控制器351之多個計算系統的多個處理器來執行諸多操作。4 shows an example diagram of a controller 351 according to some embodiments. In some embodiments, the controller 351 includes a processor 409, a storage hardware unit (HU) 411 (e.g., memory), an input HU 401, an output HU 405, an input/output (I/O) interface 403, an I/O interface 407, a network interface controller (NIC) 415, and a data communication bus 413. The processor 409, the storage HU 411, the input HU 401, the output HU 405, the I/O interface 403, the I/O interface 407, and the NIC 415 communicate data with each other via the data communication bus 413. Examples of input HU 401 include a mouse, a keyboard, a stylus, a data acquisition system, a data acquisition card, etc. Examples of output HU 405 include a display, a speaker, a device controller, etc. Examples of NIC 415 include a network interface card, a network adapter, etc. In many embodiments, NIC 415 is configured to operate according to one or more communication protocols and associated physical layers, such as Ethernet and/or EtherCAT, among others. Each of I/O interfaces 403 and 407 is defined to provide compatibility between different hardware units coupled to the I/O interface. For example, I/O interface 403 can be defined to convert signals received from input HU 401 into a format, amplitude, and/or speed compatible with data communication bus 413. Also, the I/O interface 407 may be defined to convert signals received from the data communication bus 413 into a format, amplitude, and/or speed compatible with the output HU 405. Although many operations described herein are performed by the processor 409 of the controller 351, it should be understood that in some embodiments, many operations may be performed by multiple processors of the controller 351 and/or by multiple processors of multiple computing systems connected to the controller 351.

在諸多實施例中,電漿處理系統300與電子設備整合以用於在基板105的處理之前、期間、及之後控制電漿處理系統300之操作,其中電子設備係在配置且連接以控制電漿處理系統300之諸多組件及/或子部件的控制器351內實施,控制電漿處理系統300包括偏壓電壓供應系統333。取決於基板105處理需求及/或電漿處理系統300的特定配置,將控制器351程式化以控制本文所揭示的任何製程及/或組件,包括製程氣體(一或多)之輸送、溫度設定(例如,加熱及/或冷卻)、壓力設定、真空設定、功率設定、RF功率供應系統設定、電子信號頻率設定、氣體流速設定、流體輸送設定、位置及操作設定、偏壓電壓供應系統333設定、基板105移送進出電漿處理系統300及/或進出連接至電漿處理系統300或與之介面接合的裝載鎖、以及其他等等。In many embodiments, the plasma processing system 300 is integrated with electronic equipment for controlling the operation of the plasma processing system 300 before, during, and after processing of the substrate 105, wherein the electronic equipment is implemented within a controller 351 configured and connected to control various components and/or sub-components of the plasma processing system 300, including the bias voltage supply system 333. Depending on the substrate 105 processing requirements and/or the specific configuration of the plasma processing system 300, the controller 351 is programmed to control any of the processes and/or components disclosed herein, including the delivery of process gas(es), temperature settings (e.g., heating and/or cooling), pressure settings, vacuum settings, power settings, RF power supply system settings, electronic signal frequency settings, gas flow rate settings, fluid delivery settings, position and operating settings, bias voltage supply system 333 settings, substrate 105 movement into and out of the plasma processing system 300 and/or into and out of a load lock connected to or interfacing with the plasma processing system 300, and the like.

在諸多實施例中,將控制器351定義為具有指導及控制諸多任務/操作之諸多積體電路、邏輯、記憶體、及/或軟體的電子設備,諸多任務/操作例如接收指令、發出指令、控制裝置操作、實行清洗操作、實行端點量測、實行度量衡量測(光學、熱、電等等)、以及其他任務/操作等等。在某些實施例中,控制器351內的積體電路包括一或更多的儲存程式指令之韌體、數位訊號處理器(DSP)、特殊應用積體電路(ASIC)晶片、可程式邏輯裝置(PLD)、一或更多微處理器、及/或執行程式指令(例如軟體)的一或更多微控制器,以及其他計算裝置等等。在某些實施例中,程式指令係以諸多個別設定(或程式檔案)之形式傳送至控制器351,而定義用以在電漿處理系統300內基板105上實現製程的操作性參數。在某些實施例中,操作性參數係包括在由製程工程師定義的配方中,以在一或更多的層、材料、金屬、氧化物、矽、二氧化矽、表面、電路、及/或基板105上之晶粒的製造期間完成一或更多處理步驟。In many embodiments, the controller 351 is defined as an electronic device having integrated circuits, logic, memory, and/or software that directs and controls a variety of tasks/operations, such as receiving instructions, issuing instructions, controlling device operations, performing cleaning operations, performing endpoint measurements, performing metrological measurements (optical, thermal, electrical, etc.), and other tasks/operations, etc. In some embodiments, the integrated circuits within the controller 351 include one or more firmware that stores program instructions, a digital signal processor (DSP), an application specific integrated circuit (ASIC) chip, a programmable logic device (PLD), one or more microprocessors, and/or one or more microcontrollers that execute program instructions (such as software), as well as other computing devices, etc. In some embodiments, program instructions are sent to the controller 351 in the form of a plurality of individual settings (or program files) that define operational parameters for implementing processes on the substrate 105 within the plasma processing system 300. In some embodiments, the operational parameters are included in a recipe defined by a process engineer to perform one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and/or die on the substrate 105.

在某些實施例中,控制器351為電腦的一部分或連接至電腦,電腦係與電漿處理系統300整合、或連接至電漿處理系統300、或以其他方式網路連結至電漿處理系統300、或以上之組合。例如,在某些實施例中,控制器351係在「雲端」中實施或者為晶圓廠主電腦系統的全部或一部分,而允許藉由電漿處理系統300之基板105處理之控制的遠端存取。控制器351實行對電漿處理系統300的遠端存取,以提供製造操作之目前進度的監控、提供先前製造操作之歷史的檢視、提供複數製造操作中趨勢或效能度量指標的檢視,提供處理參數的改變、提供後續處理步驟之設定、提供RF功率供應系統操作參數之規格、提供偏壓電壓供應系統333操作參數之規格、及/或提供新基板製造製程的開啟。In some embodiments, the controller 351 is part of or connected to a computer that is integrated with, connected to, or otherwise networked to the plasma processing system 300, or a combination thereof. For example, in some embodiments, the controller 351 is implemented in the “cloud” or is all or part of a wafer fab host computer system, allowing remote access to control of substrate 105 processing by the plasma processing system 300. The controller 351 implements remote access to the plasma processing system 300 to provide monitoring of the current progress of manufacturing operations, to provide a review of the history of previous manufacturing operations, to provide a review of trends or performance metrics in multiple manufacturing operations, to provide changes in processing parameters, to provide settings for subsequent processing steps, to provide specifications for RF power supply system operating parameters, to provide specifications for bias voltage supply system 333 operating parameters, and/or to provide for the initiation of a new substrate manufacturing process.

在某些實施例中,例如伺服器電腦系統的遠端電腦經由電腦網路將製程配方提供至控制器351,電腦網路包括區域網路及/或網際網路。遠端電腦包括實行參數及/或設定之輸入或程式化的使用者介面,而後所述參數及/或設定從遠端電腦傳送至控制器351。在某些範例中,控制器351接收設定形式之指令以用於處理電漿處理系統300內的基板105。應理解的是,所述設定係特定於待於基板105上執行之製程的型式以及控制器351與之介面接合或進行控制之工具/裝置/組件的型式。在某些實施例中,控制器351係分散式,例如藉由包括以網路連結在一起並針對共通目的而同步化運作的一或更多分散式控制器351,共通目的例如操作處理電漿處理系統300以於基板105上執行指定製程。用於如此目的之控制器351的範例包括與遠端設置(例如在平台層或作為遠端電腦的一部分)之一或更多積體電路通訊的腔室上之一或更多積體電路,其結合以控制腔室中的製程。In some embodiments, a remote computer, such as a server computer system, provides the process recipe to the controller 351 via a computer network, including a local area network and/or the Internet. The remote computer includes a user interface that enables input or programming of parameters and/or settings, which are then transmitted from the remote computer to the controller 351. In some examples, the controller 351 receives instructions in the form of settings for processing the substrate 105 within the plasma processing system 300. It should be understood that the settings are specific to the type of process to be performed on the substrate 105 and the type of tool/device/component that the controller 351 interfaces with or controls. In some embodiments, the controller 351 is distributed, such as by including one or more distributed controllers 351 that are networked together and operate in synchronization for a common purpose, such as operating the plasma processing system 300 to perform a specified process on the substrate 105. Examples of controllers 351 for such purposes include one or more integrated circuits on the chamber that communicate with one or more integrated circuits located remotely (e.g., on a stage level or as part of a remote computer) that combine to control the process in the chamber.

依據某些實施例,圖5顯示藉由例如333A或333B之偏壓電壓供應系統333供應至偏壓電極123之偏壓電壓定制波形501、以及在基板105之頂面105T上產出之相應電壓波形503的範例。偏壓電壓定制波形501相似於關於圖3F所述的指定偏壓電壓定制波形342。並且,於基板105之頂面105T上產出的電壓波形503相似於關於圖3F所述的偏壓電壓波形372。偏壓電壓定制波形501具有在RF區間內具循環頻率的脈衝形狀。應理解的是,偏壓電壓定制波形501係非正弦RF波形。在諸多實施例中,偏壓電壓定制波形501係配置以將電漿119中離子的離子能量分布函數(IEDF)控制在從基板105之頂面105T向上延伸之電性影響的範圍內。例如,在圖5中,偏壓電壓定制波形501係配置以控制電漿119中離子的IEDF以實現於基板105之頂面105T處的實質上單能離子能量分布。偏壓電壓定制波形501於基板105的頂面105T上產生實質上恆定負電壓,如電壓波形503所示,使得當電漿119內的離子被引向基板105之頂面105T時係加速至實質上相同的能階。According to some embodiments, FIG5 shows an example of a bias voltage customized waveform 501 supplied to the bias electrode 123 by a bias voltage supply system 333 such as 333A or 333B, and a corresponding voltage waveform 503 generated on the top surface 105T of the substrate 105. The bias voltage customized waveform 501 is similar to the specified bias voltage customized waveform 342 described with respect to FIG3F. Furthermore, the voltage waveform 503 generated on the top surface 105T of the substrate 105 is similar to the bias voltage waveform 372 described with respect to FIG3F. The bias voltage customized waveform 501 has a pulse shape with a cyclic frequency in the RF region. It should be understood that the bias voltage customized waveform 501 is a non-sinusoidal RF waveform. In many embodiments, the bias voltage customized waveform 501 is configured to control the ion energy distribution function (IEDF) of the ions in the plasma 119 within an electrically affected range extending upward from the top surface 105T of the substrate 105. For example, in FIG. 5 , the bias voltage customized waveform 501 is configured to control the IEDF of the ions in the plasma 119 to achieve a substantially monoenergetic ion energy distribution at the top surface 105T of the substrate 105. The bias voltage customized waveform 501 generates a substantially constant negative voltage on the top surface 105T of the substrate 105, as shown by the voltage waveform 503, so that the ions in the plasma 119 are accelerated to substantially the same energy level when they are introduced to the top surface 105T of the substrate 105.

偏壓電壓供應系統333用以產生偏壓電壓定制波形501並供應偏壓電壓定制波形501至偏壓電極123的操作實現窄IEDF以及於基板105之頂面105T處離子能量及離子通量之獨立控制的成果。然而,在沒有基板105之頂面105T處IEDF及離子通量之即時、原位量測的情況下,基板105之頂面105T處IEDF及離子通量的控制仍係具挑戰性的。實現及維持所需IEDF乃需要基板105之頂面105T處IEDF或電壓的偵測。因為IEDF係取決於基板105之頂面105T處的電壓,故可藉由知悉基板105之頂面105T處的即時電壓而判定基板105之頂面105T處的即時IEDF。然而,基板105之頂面105T處IEDF或電壓的任何直接量測將會需要基板105上實體感測器或探針的部署而會干擾基板105之處理,例如,跨基板105之劣化的電漿119均勻性、及其他問題等等,並且相應地導致下降的半導體晶片製造良率。用於基板105上電壓及電流之控制的非正弦偏壓電壓定制波形501之使用係取決於知悉基板105之頂面105T上的即時電壓。The operation of the bias voltage supply system 333 to generate the bias voltage customized waveform 501 and supply the bias voltage customized waveform 501 to the bias electrode 123 achieves the results of narrow IEDF and independent control of ion energy and ion flux at the top surface 105T of the substrate 105. However, the control of IEDF and ion flux at the top surface 105T of the substrate 105 remains challenging without real-time, in-situ measurement of the IEDF and ion flux at the top surface 105T of the substrate 105. Achieving and maintaining the desired IEDF requires detection of the IEDF or voltage at the top surface 105T of the substrate 105. Because the IEDF depends on the voltage at the top surface 105T of the substrate 105, the real-time IEDF at the top surface 105T of the substrate 105 can be determined by knowing the real-time voltage at the top surface 105T of the substrate 105. However, any direct measurement of the IEDF or voltage at the top surface 105T of the substrate 105 would require the deployment of physical sensors or probes on the substrate 105 which would interfere with the processing of the substrate 105, such as degraded plasma 119 uniformity across the substrate 105, and other issues, and correspondingly lead to reduced semiconductor wafer manufacturing yield. The use of a non-sinusoidal bias voltage custom waveform 501 for control of voltage and current on the substrate 105 depends on knowing the real-time voltage on the top surface 105T of the substrate 105.

本文揭示諸多實施例以用於基板105之頂面105T上電壓的即時間接量測,以實行非正弦偏壓電壓定制波形342、342-1、501的即時閉迴路回饋控制,以便實現並維持基板105之頂面105T上的指定電壓,並且相應地控制基板105之頂面105T處的IEDF。基板105之頂面105T上電壓的有效及準確偵測係重要的,特別係針對包括其中電漿119密度在短時間周期(例如,遠小於1毫秒)內動態改變之脈衝操作的電漿為基基板105製造製程。並且,本文揭示諸多實施例以用於邊緣環315之頂面315T上電壓的即時間接量測,以實行非正弦偏壓電壓定制波形342、342-2的即時閉迴路回饋控制,以便實現並維持邊緣環315之頂面315T上的指定電壓,並且相應地控制邊緣環315之頂面315T處的IEDF。Various embodiments are disclosed herein for real-time indirect measurement of voltage on the top surface 105T of the substrate 105 to implement real-time closed-loop feedback control of the non-sinusoidal bias voltage customized waveform 342, 342-1, 501 to achieve and maintain a specified voltage on the top surface 105T of the substrate 105, and accordingly control the IEDF at the top surface 105T of the substrate 105. Efficient and accurate detection of voltage on the top surface 105T of the substrate 105 is important, particularly for plasma-based substrate 105 manufacturing processes that include pulsed operations in which the plasma 119 density changes dynamically within a short time period (e.g., much less than 1 millisecond). Furthermore, this document discloses a number of embodiments for real-time indirect measurement of the voltage on the top surface 315T of the edge ring 315 to implement real-time closed-loop feedback control of the non-sinusoidal bias voltage customized waveforms 342, 342-2, so as to achieve and maintain a specified voltage on the top surface 315T of the edge ring 315, and correspondingly control the IEDF at the top surface 315T of the edge ring 315.

依據某些實施例,圖6顯示對應於如圖5中顯示之藉由偏壓電壓供應系統333供應至偏壓電極123之偏壓電壓定制波形501的基板支撐件301內中階電極302上的電壓波形601。圖6亦顯示從如圖5中顯示之藉由偏壓電壓供應系統333至偏壓電極123之偏壓電壓定制波形501的供應中在基板105之頂面105T上產生的電壓波形503。藉由由偏壓電壓供應系統333供應至偏壓電極123的偏壓電壓定制波形342、342-1、501控制偏壓電極123電壓。藉由由偏壓電壓供應系統333供應至偏壓電極123的偏壓電壓定制波形342、342-1、501以及入射在基板105之頂面105T上之電漿119中電子與離子兩者來控制基板105之頂面105T上電壓。配置於偏壓電極123與基板支撐件301之頂面301T間基板支撐件301內的電氣隔離中階電極302捕捉電壓波形601,電壓波形601係介於偏壓電壓定制波形342、342-1、501與基板105之頂面105T上電壓波形503之間。According to some embodiments, FIG6 shows a voltage waveform 601 on the intermediate electrode 302 in the substrate support 301 corresponding to the bias voltage customized waveform 501 supplied to the bias electrode 123 by the bias voltage supply system 333 as shown in FIG5 . FIG6 also shows a voltage waveform 503 generated on the top surface 105T of the substrate 105 from the supply of the bias voltage customized waveform 501 to the bias electrode 123 by the bias voltage supply system 333 as shown in FIG5 . The bias electrode 123 voltage is controlled by the bias voltage customized waveform 342, 342-1, 501 supplied to the bias electrode 123 by the bias voltage supply system 333. The voltage on the top surface 105T of the substrate 105 is controlled by both the bias voltage customized waveform 342, 342-1, 501 supplied to the bias electrode 123 by the bias voltage supply system 333 and the electrons and ions in the plasma 119 incident on the top surface 105T of the substrate 105. The electrically isolated intermediate electrode 302 disposed in the substrate support 301 between the bias electrode 123 and the top surface 301T of the substrate support 301 captures the voltage waveform 601, which is between the bias voltage customized waveform 342, 342-1, 501 and the voltage waveform 503 on the top surface 105T of the substrate 105.

偏壓電極123與中階電極302之間的電壓差和偏壓電極123與中階電極302之間的阻抗成正比。相似地,中階電極302與基板105的頂面105T之間的電壓差和中階電極302與基板105的頂面105T之間的阻抗成正比。偏壓電極123與中階電極302之間的阻抗係藉由( 1/j ω C 中階至偏壓電極 )計算之,其中 C 中階至偏壓電極 係介於偏壓電極123與中階電極302之間的基板支撐件301之下部303的電容。中階電極302與基板105的頂面105T之間的阻抗係藉由( 1/j ω C 基板至中階 )計算之,其中 C 基板至中階 係介於中階電極302與基板支撐件301的頂面301T之間的基板支撐件301之上部305的電容。於此假定基板105對於中階電極302與基板105之頂面105T間阻抗的影響係可忽略的。因而,電氣隔離的中階電極302形成拾取如公式1中所示電壓的電容式分壓器,其中 V 中階 係中階電極302上的電壓, V 偏壓電極 係偏壓電極123上的電壓,以及 V 基板 係基板105之頂面105T上的電壓。從公式1中得出,可將中階電極302上的電壓表示為如公式2中所示。並且,從公式1中得出,可將基板105之頂面105T上的電壓表示為如公式3中所示。因而,在具有介於偏壓電極123與中階電極302之間的基板支撐件301之下部303的已知電容( C 中階至偏壓電極 )的情況下,以及具有介於中階電極302與基板支撐件301的頂面301T之間的基板支撐件301之上部305的已知電容( C 基板至中階 )的情況下,以及具有中階電極302上電壓( V 中階 )與偏壓電極123上電壓( V 偏壓電極 )之直接即時量測的情況下,使用公式3間接地判定基板105之頂面105T上的即時電壓( V 基板 )。 The voltage difference between the bias electrode 123 and the intermediate electrode 302 is proportional to the impedance between the bias electrode 123 and the intermediate electrode 302. Similarly, the voltage difference between the intermediate electrode 302 and the top surface 105T of the substrate 105 is proportional to the impedance between the intermediate electrode 302 and the top surface 105T of the substrate 105. The impedance between the bias electrode 123 and the intermediate electrode 302 is calculated by ( 1/j ω Cintermediate to bias electrode ), where Cintermediate to bias electrode is the capacitance of the lower portion 303 of the substrate support 301 between the bias electrode 123 and the intermediate electrode 302. The impedance between the intermediate electrode 302 and the top surface 105T of the substrate 105 is calculated by ( 1/j ω Csubstrate to intermediate ), where Csubstrate to intermediate is the capacitance of the upper portion 305 of the substrate support 301 between the intermediate electrode 302 and the top surface 301T of the substrate support 301. It is assumed here that the substrate 105 has a negligible effect on the impedance between the mid-stage electrode 302 and the top surface 105T of the substrate 105. Therefore, the electrically isolated mid-stage electrode 302 forms a capacitive voltage divider that picks up a voltage as shown in Formula 1, where Vmid is the voltage on the mid-stage electrode 302, Vbias is the voltage on the bias electrode 123, and Vsubstrate is the voltage on the top surface 105T of the substrate 105. From Formula 1, it follows that the voltage on the mid-stage electrode 302 can be expressed as shown in Formula 2. And, from Formula 1, it follows that the voltage on the top surface 105T of the substrate 105 can be expressed as shown in Formula 3. Therefore, in the case of a known capacitance ( Cmidlevel -to-bias-electrode ) of the lower portion 303 of the substrate support 301 between the bias electrode 123 and the mid-level electrode 302, and in the case of a known capacitance ( Csubstrate -to-midlevel ) of the upper portion 305 of the substrate support 301 between the mid-level electrode 302 and the top surface 301T of the substrate support 301, and in the case of direct real-time measurement of the voltage on the mid-level electrode 302 (Vmidlevel ) and the voltage on the bias electrode 123 ( Vbias - electrode ), Formula 3 is used to indirectly determine the real-time voltage ( Vsubstrate ) on the top surface 105T of the substrate 105.

公式1。 = Formula 1. =

公式2。 V 中階 = Formula 2. Vmid =

公式3。 V 基板 = V 中階 + ( V 中階 V 偏壓電極 ) Formula 3. Vsubstrate = Vmidstage + ( Vmid Vbias electrode )

公式1至3中所顯示的相同關係式可應用至邊緣環315以藉由使用邊緣環電極323與邊緣環中階電極317之每一者上的直接即時電壓量測來間接地判定邊緣環315之頂面315T上的電壓。The same relationships shown in Equations 1-3 may be applied to the edge ring 315 to indirectly determine the voltage on the top surface 315T of the edge ring 315 by using direct real-time voltage measurements on each of the edge ring electrode 323 and the edge ring intermediate electrode 317 .

藉由由偏壓電壓供應系統333供應至邊緣環電極323的偏壓電壓定制波形342、342-2控制邊緣環電極323電壓。不僅藉由由偏壓電壓供應系統333供應至邊緣環電極323的偏壓電壓定制波形342、342-2、而且亦藉由入射在邊緣環315之頂面315T上之電漿119中的電子與離子來控制邊緣環315之頂面315T上的電壓。配置於邊緣環電極323與邊緣環315之頂面315T間邊緣環315內的電氣隔離邊緣環中階電極317捕捉介於偏壓電壓定制波形342、342-2與邊緣環315之頂面315T上電壓波形之間的電壓波形。The voltage of the edge ring electrode 323 is controlled by the bias voltage customized waveform 342, 342-2 supplied to the edge ring electrode 323 by the bias voltage supply system 333. The voltage on the top surface 315T of the edge ring 315 is controlled not only by the bias voltage customized waveform 342, 342-2 supplied to the edge ring electrode 323 by the bias voltage supply system 333, but also by the electrons and ions in the plasma 119 incident on the top surface 315T of the edge ring 315. The electrically isolated edge ring intermediate electrode 317 disposed in the edge ring 315 between the edge ring electrode 323 and the top surface 315T of the edge ring 315 captures a voltage waveform between the bias voltage custom waveform 342 , 342 - 2 and the voltage waveform on the top surface 315T of the edge ring 315 .

邊緣環電極323與邊緣環中階電極317之間的電壓差和邊緣環電極323與邊緣環中階電極317之間的阻抗成正比。相似地,邊緣環中階電極317與邊緣環315的頂面315T之間的電壓差和邊緣環中階電極317與邊緣環315的頂面315T之間的阻抗成正比。邊緣環電極323與邊緣環中階電極317之間的阻抗係藉由( 1/j ω C 邊緣環中階至邊緣環電極 )計算之,其中 C 邊緣環中階至邊緣環電極 係介於邊緣環電極323與邊緣環中階電極317之間的邊緣環315之下部319的電容。邊緣環中階電極317與邊緣環315的頂面315T之間的阻抗係藉由( 1/j ω C 邊緣環頂部至邊緣環中階 )計算之,其中 C 邊緣環頂部至邊緣環中階 係介於邊緣環中階電極317與邊緣環315的頂面315T之間的邊緣環315之上部321的電容。因而,電氣隔離的邊緣環中階電極317形成拾取如公式4中所示電壓的電容式分壓器,其中 V 邊緣環中階 係邊緣環中階電極317上的電壓, V 邊緣環電極 係邊緣環電極323上的電壓,以及 V 邊緣環頂部 係邊緣環315之頂面315T上的電壓。從公式4中得出,可將邊緣環中階電極317上的電壓表示為如公式5中所示。並且,從公式4中得出,可將邊緣環315之頂面315T上的電壓表示為如公式6中所示。因而,在具有介於邊緣環電極323與邊緣環中階電極317之間的邊緣環315之下部319的已知電容( C 邊緣環中階至邊緣環電極 )的情況下,以及具有介於邊緣環中階電極317與邊緣環315的頂面315T之間的邊緣環315之上部321的已知電容( C 邊緣環頂部至邊緣環中階 )的情況下,以及具有邊緣環中階電極317上電壓( V 邊緣環中階 )與邊緣環電極323上電壓( V 邊緣環電極 )之直接即時量測的情況下,使用公式6間接地判定邊緣環315之頂面315T上的即時電壓( V 邊緣環頂部 )。 The voltage difference between the edge ring electrode 323 and the edge ring intermediate electrode 317 is proportional to the impedance between the edge ring electrode 323 and the edge ring intermediate electrode 317. Similarly, the voltage difference between the edge ring intermediate electrode 317 and the top surface 315T of the edge ring 315 is proportional to the impedance between the edge ring intermediate electrode 317 and the top surface 315T of the edge ring 315. The impedance between the edge ring electrode 323 and the edge ring middle electrode 317 is calculated by ( 1/jω Cedge ring middle to edge ring electrode ), where Cedge ring middle to edge ring electrode is the capacitance of the lower portion 319 of the edge ring 315 between the edge ring electrode 323 and the edge ring middle electrode 317. The impedance between the edge ring mid-stage electrode 317 and the top surface 315T of the edge ring 315 is calculated by ( 1/j ω C edge ring top to edge ring mid-stage ), where C edge ring top to edge ring mid-stage is the capacitance of the upper portion 321 of the edge ring 315 between the edge ring mid-stage electrode 317 and the top surface 315T of the edge ring 315. Thus, the electrically isolated edge ring mid-stage electrode 317 forms a capacitive voltage divider that picks up a voltage as shown in Equation 4, where Vedge -ring-mid is the voltage on edge ring mid-stage electrode 317, Vedge -ring-electrode is the voltage on edge ring electrode 323, and Vedge- ring-top is the voltage on top surface 315T of edge ring 315. From Equation 4, the voltage on edge ring mid-stage electrode 317 can be expressed as shown in Equation 5. And, from Equation 4, the voltage on top surface 315T of edge ring 315 can be expressed as shown in Equation 6. Thus, with a known capacitance ( Cedge ring middle to edge ring electrode ) of the lower portion 319 of the edge ring 315 between the edge ring electrode 323 and the edge ring middle electrode 317, and with a known capacitance ( Cedge ring top to edge ring middle) of the upper portion 321 of the edge ring 315 between the edge ring middle electrode 317 and the top surface 315T of the edge ring 315, and with a voltage ( Cedge ring top to edge ring middle ) on the edge ring middle electrode 317. In the case of direct real-time measurement of the voltage on the edge ring electrode 323 ( Vedge ring electrode ), the real-time voltage on the top surface 315T of the edge ring 315 ( Vedge ring top ) is indirectly determined using Formula 6.

公式4。 = Formula 4. =

公式5。 V 邊緣環中階 = Formula 5. V edge ring mid-order =

公式6。 V 邊緣環頂部 = V 邊緣環中階 + ( V 邊緣環中階 V 邊緣環電極 ) Formula 6. V edge ring top = V edge ring middle + ( V edge ring middle stage - V edge ring electrode )

依據某些實施例,圖7顯示藉由偏壓電壓供應系統333供應至偏壓電極123之偏壓電壓定制波形701以及在基板105之頂面105T上產生之相應電壓波形703的範例。圖7亦顯示代表產生自藉由TCP RF產生器113至線圈109之TCP RF功率供應的線圈109上電壓的TCP電壓波形705。在圖7的範例中,以脈衝方式供應RF功率至TCP線圈109,使得TCP RF功率的連續ON脈衝被TCP RF功率的OFF脈衝分隔。在電漿處理配方中指定TCP RF功率之ON與OFF脈衝的工作週期,即,相對於OFF之持續時間的ON脈衝之持續時間。偏壓電壓定制波形701至偏壓電極123的供應係同步以與供應至TCP線圈109之TCP RF功率的每一ON脈衝重合。According to some embodiments, FIG7 shows an example of a bias voltage customized waveform 701 supplied to the bias electrode 123 by the bias voltage supply system 333 and a corresponding voltage waveform 703 generated on the top surface 105T of the substrate 105. FIG7 also shows a TCP voltage waveform 705 representing the voltage on the coil 109 resulting from the supply of TCP RF power to the coil 109 by the TCP RF generator 113. In the example of FIG7, RF power is supplied to the TCP coil 109 in a pulsed manner such that consecutive ON pulses of the TCP RF power are separated by OFF pulses of the TCP RF power. The duty cycle of the ON and OFF pulses of the TCP RF power is specified in the plasma processing recipe, i.e., the duration of the ON pulse relative to the duration of the OFF pulse. The supply of the bias voltage customized waveform 701 to the bias electrode 123 is synchronized to coincide with each ON pulse of the TCP RF power supplied to the TCP coil 109.

例如圖7中所示,在具有單階TCP RF功率脈衝的情況下,電漿119歷經在每一脈衝階段中的動態變動,例如密度上的變動。因而,即使供應至偏壓電極123的偏壓電壓定制波形701具有一致脈波圖型而應會在TCP RF功率之ON脈衝的持續時間中產生基板105之頂面105T上電壓波形703中的一致脈波圖型,但電漿119中的動態變動致使基板105之頂面105T上的電壓波形703具有當供應偏壓電壓定制波形701至偏壓電極123時的初始穩定時間,如區域707所示。具體而言,當於TCP RF功率之ON脈衝之起始處首次供應偏壓電壓定制波形701至偏壓電極123以便產生基板105之頂面105T上的電壓波形703時,電漿119密度相對較低而入射在基板105上的離子通量相應地較低。因而,於TCP RF功率之ON脈衝的起始處,基板105上離子的入射通量尚不足以電中和基板105之頂面105T上的負電壓以實現基板105之頂面105T的恆定設定點電壓711。隨著TCP RF功率之ON脈衝續行,電漿119密度增加以達到穩定態而入射在基板105上的離子通量相應地增加以達到穩定態,從而電中和更多的基板105之頂面105T上負電壓,直到於基板105之頂面105T上實現恆定設定點電壓711,如電壓波形703的區域709所示。7 , in the case of a single-step TCP RF power pulse, the plasma 119 undergoes dynamic variations, such as variations in density, in each pulse phase. Thus, even though the bias voltage customized waveform 701 supplied to the bias electrode 123 has a consistent pulse pattern that should produce a consistent pulse pattern in the voltage waveform 703 on the top surface 105T of the substrate 105 during the duration of the ON pulse of the TCP RF power, the dynamic variations in the plasma 119 cause the voltage waveform 703 on the top surface 105T of the substrate 105 to have an initial stabilization time when the bias voltage customized waveform 701 is supplied to the bias electrode 123, as shown in region 707. Specifically, when the bias voltage customized waveform 701 is first supplied to the bias electrode 123 at the beginning of the ON pulse of the TCP RF power to generate the voltage waveform 703 on the top surface 105T of the substrate 105, the density of the plasma 119 is relatively low and the ion flux incident on the substrate 105 is correspondingly low. Therefore, at the beginning of the ON pulse of the TCP RF power, the incident flux of ions on the substrate 105 is not sufficient to electrically neutralize the negative voltage on the top surface 105T of the substrate 105 to achieve the constant set point voltage 711 of the top surface 105T of the substrate 105. As the ON pulse of the TCP RF power continues, the density of the plasma 119 increases to reach a steady state and the ion flux incident on the substrate 105 correspondingly increases to reach a steady state, thereby electrically neutralizing more of the negative voltage on the top surface 105T of the substrate 105 until a constant set point voltage 711 is achieved on the top surface 105T of the substrate 105, as shown in region 709 of the voltage waveform 703.

控制供應至偏壓電極123的偏壓電壓定制波形701係有利的,以便以最小化如區域707所示之電壓波形703之初始穩定時間的方式產生基板105之頂面105T上的電壓波形703。換言之,控制供應至偏壓電極123的偏壓電壓定制波形701係有利的,使得當電漿119密度於TCP RF功率之ON脈衝期間增加至其穩定態狀況時實現並維持基板105之頂面105T上的恆定設定點電壓711。為了以上述方式控制供應至偏壓電極123的偏壓電壓定制波形701,需要具有基板105之頂面105T上電壓的即時判定作為至偏壓電壓供應系統333的回饋控制信號。以上關於公式1至3所述的技術係用以經由即時偏壓電極123電壓( V 偏壓電極 )的直接量測以及即時中階電極302電壓( V 中階 )的直接量測來判定即時基板105頂面105T電壓( V 基板 )。所判定的即時基板105頂面105T電壓( V 基板 )係用以作為閉迴路回饋控制信號以用於控制偏壓電壓定制波形701的產生,以便為了在TCP RF功率之每一ON脈衝的起始之後盡可能快速地實現並維持基板105之頂面105T上的恆定設定點電壓711而以最小化電壓波形703之初始穩定時間的方式產生基板105之頂面105T上的電壓波形703。 It is advantageous to control the bias voltage customized waveform 701 supplied to the bias electrode 123 so as to generate the voltage waveform 703 on the top surface 105T of the substrate 105 in a manner that minimizes the initial settling time of the voltage waveform 703 as shown in the region 707. In other words, it is advantageous to control the bias voltage customized waveform 701 supplied to the bias electrode 123 so as to achieve and maintain a constant set point voltage 711 on the top surface 105T of the substrate 105 as the plasma 119 density increases to its steady state condition during the ON pulse of the TCP RF power. In order to control the bias voltage customized waveform 701 supplied to the bias electrode 123 in the manner described above, it is necessary to have a real-time determination of the voltage on the top surface 105T of the substrate 105 as a feedback control signal to the bias voltage supply system 333. The techniques described above with respect to equations 1 to 3 are used to determine the real-time substrate 105 top surface 105T voltage ( Vsubstrate ) via direct measurement of the real-time bias electrode 123 voltage ( Vbias electrode ) and direct measurement of the real-time mid-level electrode 302 voltage ( Vmid - level ). The determined instantaneous substrate 105 top surface 105T voltage ( Vsubstrate ) is used as a closed-loop feedback control signal for controlling the generation of the bias voltage customized waveform 701 so as to generate the voltage waveform 703 on the top surface 105T of the substrate 105 in a manner that minimizes the initial settling time of the voltage waveform 703 in order to achieve and maintain a constant set point voltage 711 on the top surface 105T of the substrate 105 as quickly as possible after the initiation of each ON pulse of the TCP RF power.

在某些實施例中,即時基板105頂面105T電壓( V 基板 )係經由控制器351提供至偏壓電壓供應系統333,以用於判定待於指定偏壓電壓定制波形342之下一脈衝中實施的指定偏壓電壓定制波形342之調整。應理解的是,基本上可依需求調整指定偏壓電壓定制波形342的任何實施態樣以最小化回饋信號之間的差,即,即時基板105頂面105T電壓( V 基板 )、及恆定設定點電壓711之間。舉例而言,可控制指定偏壓電壓定制波形342的參數,例如初始負電壓(Vstep)、負電壓斜率(dV/dT)、及工作週期(給定脈衝內負電壓的持續時間),以最小化所判定即時基板105頂面105T電壓( V 基板 )與恆定設定點電壓711之間的差。 In certain embodiments, the real-time substrate 105 top surface 105T voltage ( Vsubstrate ) is provided to the bias voltage supply system 333 via the controller 351 for determining the adjustment of the specified bias voltage customized waveform 342 to be implemented in the next pulse of the specified bias voltage customized waveform 342. It should be understood that substantially any implementation of the specified bias voltage customized waveform 342 can be adjusted as needed to minimize the difference between the feedback signal, i.e., the real-time substrate 105 top surface 105T voltage (Vsubstrate ) , and the constant set point voltage 711. For example, parameters of the specified bias voltage custom waveform 342, such as the initial negative voltage (Vstep), the negative voltage slope (dV/dT), and the duty cycle (the duration of the negative voltage within a given pulse), may be controlled to minimize the difference between the determined instantaneous substrate 105 top surface 105T voltage ( Vsubstrate ) and the constant set point voltage 711.

應理解的是,如關於圖7所述的針對基板105之頂面105T上產生之電壓的閉迴路回饋控制方法同樣可應用於控制邊緣環315之頂面315T上產生的電壓。具體而言,以上關於公式4至6所述的技術係用以經由即時邊緣環電極323電壓( V 邊緣環電極 )的直接量測以及即時邊緣環中階電極317電壓( V 邊緣環中階 )的直接量測來判定即時邊緣環315頂面315T電壓( V 邊緣環頂部 )。所判定的即時邊緣環315頂面315T電壓( V 邊緣環頂部 )係用以作為閉迴路回饋控制信號以用於控制施加至邊緣環電極323之偏壓電壓定制波形的產生,以便為了在TCP RF功率之每一ON脈衝的起始之後盡可能快速地實現並維持邊緣環315之頂面315T上的恆定設定點電壓而以最小化電壓波形之初始穩定時間的方式產生邊緣環315之頂面315T上的電壓波形。 It should be understood that the closed loop feedback control method for the voltage generated on the top surface 105T of the substrate 105 as described with respect to Figure 7 can also be applied to control the voltage generated on the top surface 315T of the edge ring 315. Specifically, the techniques described above with respect to equations 4 to 6 are used to determine the voltage ( Vedge ring top) of the top surface 315T of the instant edge ring 315 through direct measurement of the voltage (Vedge ring electrode ) of the instant edge ring electrode 323 and direct measurement of the voltage ( Vedge ring middle ) of the instant edge ring middle electrode 317. The determined instant edge ring 315 top surface 315T voltage ( Vedge ring top ) is used as a closed loop feedback control signal for controlling the generation of a customized waveform of the bias voltage applied to the edge ring electrode 323, so as to generate the voltage waveform on the top surface 315T of the edge ring 315 in a manner that minimizes the initial settling time of the voltage waveform in order to achieve and maintain a constant set point voltage on the top surface 315T of the edge ring 315 as quickly as possible after the initiation of each ON pulse of the TCP RF power.

在某些實施例中,即時邊緣環315頂面315T電壓( V 邊緣環頂部 )係經由控制器351提供至偏壓電壓供應系統333,以用於判定待於指定偏壓電壓定制波形342、342-2之下一脈衝中實施的指定偏壓電壓定制波形342、342-2之調整。應理解的是,基本上可依需求調整指定偏壓電壓定制波形342、342-2的任何實施態樣以最小化回饋信號之間的差,即,即時邊緣環315頂面315T電壓( V 邊緣環頂部 )、以及恆定設定點電壓之間。舉例而言,可控制指定偏壓電壓定制波形342、342-2的參數,例如初始負電壓(Vstep)、負電壓斜率(dV/dT)、及工作週期(給定脈衝內負電壓的持續時間),以最小化所判定即時邊緣環315頂面315T電壓( V 邊緣環頂部 )與恆定設定點電壓之間的差。 In some embodiments, the real-time edge ring 315 top surface 315T voltage ( V edge ring top ) is provided to the bias voltage supply system 333 via the controller 351 for determining the adjustment of the specified bias voltage customized waveform 342, 342-2 to be implemented in the next pulse of the specified bias voltage customized waveform 342, 342-2. It should be understood that basically any implementation of the specified bias voltage customized waveform 342, 342-2 can be adjusted as needed to minimize the difference between the feedback signal, that is, the real-time edge ring 315 top surface 315T voltage ( V edge ring top ), and the constant set point voltage. For example, parameters of the specified bias voltage customized waveform 342, 342-2, such as the initial negative voltage (Vstep), the negative voltage slope (dV/dT), and the duty cycle (the duration of the negative voltage within a given pulse) can be controlled to minimize the difference between the determined instant edge ring 315 top 315T voltage ( Vedge ring top ) and the constant set point voltage.

在某些實施例中,邊緣環315之頂面315T上的電壓( V 邊緣環頂部 )係用以產生在基板105之邊緣附近的均勻電漿119鞘並最小化轟擊離子角分佈函數(IADF)。在某些實施例中,較小的IADF減小對基板105之邊緣附近蝕刻輪廓的傾斜影響,且因而提高製造良率。在某些實施例中,將邊緣環315之頂面315T上的電壓( V 邊緣環頂部 )與基板105之頂面105T上的電壓( V 基板 )進行比較,以產生用於減小基板105之頂面105T與邊緣環315之頂面315T間電壓差的回饋控制信號,其中所述電壓差致使IADF的不利增加。 In some embodiments, the voltage on the top surface 315T of the edge ring 315 ( Vedge ring top ) is used to generate a uniform plasma 119 sheath near the edge of the substrate 105 and minimize the impact ion angular distribution function (IADF). In some embodiments, a smaller IADF reduces the tilt effect on the etch profile near the edge of the substrate 105 and thus improves manufacturing yield. In some embodiments, a voltage on a top surface 315T of the edge ring 315 ( Vedge ring top ) is compared to a voltage on a top surface 105T of the substrate 105 (Vsubstrate ) to generate a feedback control signal for reducing a voltage difference between the top surface 105T of the substrate 105 and the top surface 315T of the edge ring 315, wherein the voltage difference causes an undesirable increase in IADF.

依據某些實施例,圖8顯示藉由偏壓電壓供應系統333供應至偏壓電極123的回饋控制偏壓電壓定制波形801以及在基板105之頂面105T上產生的相應電壓波形803。圖8亦顯示代表產生自藉由TCP RF產生器113至線圈109之TCP RF功率供應的線圈109上電壓的TCP電壓波形805。並且,基於比較目的,圖8顯示圖7中供應至偏壓電極123的無回饋控制偏壓電壓定制波形701以及在基板105之頂面105T上產生的相應電壓波形703。圖8顯示所判定的即時基板105頂面105T電壓( V 基板 )作為回饋信號以實現基板105之頂面105T上恆定設定點電壓811的使用,而致使回饋控制偏壓電壓定制波形801在回饋控制偏壓電壓定制波形801的連續脈衝之間於斜率(dV/dT)上逐步增加,直到電漿119密度於TCP RF功率的ON脈衝期間達到穩定態。 According to some embodiments, FIG8 shows a feedback-controlled bias voltage customized waveform 801 supplied to the bias electrode 123 by the bias voltage supply system 333 and a corresponding voltage waveform 803 generated on the top surface 105T of the substrate 105. FIG8 also shows a TCP voltage waveform 805 representing the voltage on the coil 109 generated from the TCP RF power supply to the coil 109 by the TCP RF generator 113. And, for comparison purposes, FIG8 shows the non-feedback-controlled bias voltage customized waveform 701 supplied to the bias electrode 123 in FIG7 and a corresponding voltage waveform 703 generated on the top surface 105T of the substrate 105. FIG8 shows the determined real-time substrate 105 top surface 105T voltage ( Vsubstrate ) as a feedback signal to implement the use of a constant set point voltage 811 on the top surface 105T of the substrate 105, causing the feedback control bias voltage customized waveform 801 to gradually increase in slope (dV/dT) between consecutive pulses of the feedback control bias voltage customized waveform 801 until the plasma 119 density reaches a steady state during the ON pulse of the TCP RF power.

應理解的是,如關於圖8所述的針對基板105之頂面105T上產生之電壓的閉迴路回饋控制方法同樣可應用於控制邊緣環315之頂面315T上產生的電壓。具體而言,所判定的即時邊緣環315頂面315T電壓( V 邊緣環頂部 )作為回饋信號以實現邊緣環315之頂面315T上恆定設定點電壓的使用乃致使供應至邊緣環電極323的回饋控制偏壓電壓定制波形在供應至邊緣環電極323之回饋控制偏壓電壓定制波形的連續脈衝之間於斜率(dV/dT)上逐步增加,直到電漿119密度於TCP RF功率的ON脈衝期間達到穩定態。 It should be understood that the closed loop feedback control method for the voltage generated on the top surface 105T of the substrate 105 as described with respect to FIG. 8 can also be applied to control the voltage generated on the top surface 315T of the edge ring 315 . Specifically, the determined real-time edge ring 315 top surface 315T voltage ( Vedge ring top ) is used as a feedback signal to achieve a constant set point voltage on the top surface 315T of the edge ring 315, so that the feedback control bias voltage customized waveform supplied to the edge ring electrode 323 gradually increases in slope (dV/dT) between consecutive pulses of the feedback control bias voltage customized waveform supplied to the edge ring electrode 323 until the plasma 119 density reaches a stable state during the ON pulse of the TCP RF power.

依據某些實施例,圖9顯示藉由偏壓電壓供應系統333供應至偏壓電極123的回饋控制偏壓電壓定制波形901以及在基板105之頂面105T上產生的相應電壓波形903。圖9亦顯示代表產生自藉由TCP RF產生器113至線圈109之TCP RF功率供應的線圈109上電壓的TCP電壓波形905。並且,基於比較目的,圖9顯示圖7中供應至偏壓電極123的無回饋控制偏壓電壓定制波形701以及在基板105之頂面105T上產生的相應電壓波形703。圖9顯示所判定的即時基板105頂面105T電壓( V 基板 )作為回饋信號以實現基板105之頂面105T上恆定設定點電壓911的使用,而致使回饋控制偏壓電壓定制波形901在回饋控制偏壓電壓定制波形901的連續脈衝之間於工作週期上逐步增加,直到電漿119密度於TCP RF功率的ON脈衝期間達到穩定態。回饋控制偏壓電壓定制波形901的工作週期係定義為回饋控制偏壓電壓定制波形901於施加負電壓期間之給定脈衝的百分比。回饋控制偏壓電壓定制波形901的工作週期可在回饋控制偏壓電壓定制波形901的脈衝與脈衝之間變化。在某些實施例中,例如於圖9中所示,無論於脈衝期間施加的工作週期為何,回饋控制偏壓電壓定制波形901的斜率(dV/dT)在回饋控制偏壓電壓定制波形901之每一脈衝的負電壓部分期間係實質上恆定的。然而,在某些實施例中,在回饋控制偏壓電壓定制波形901的脈衝與脈衝之間調整回饋控制偏壓電壓定制波形901之每一脈衝之負電壓部分期間的斜率(dV/dT)。 According to some embodiments, FIG9 shows a feedback-controlled bias voltage customized waveform 901 supplied to the bias electrode 123 by the bias voltage supply system 333 and a corresponding voltage waveform 903 generated on the top surface 105T of the substrate 105. FIG9 also shows a TCP voltage waveform 905 representing the voltage on the coil 109 generated from the TCP RF power supply to the coil 109 by the TCP RF generator 113. And, for comparison purposes, FIG9 shows the non-feedback-controlled bias voltage customized waveform 701 supplied to the bias electrode 123 in FIG7 and a corresponding voltage waveform 703 generated on the top surface 105T of the substrate 105. 9 shows the determined real-time substrate 105 top surface 105T voltage ( Vsubstrate ) as a feedback signal to implement the use of a constant set point voltage 911 on the top surface 105T of the substrate 105, causing the feedback control bias voltage customized waveform 901 to be gradually increased in duty cycle between consecutive pulses of the feedback control bias voltage customized waveform 901 until the plasma 119 density reaches a steady state during the ON pulse of the TCP RF power. The duty cycle of the feedback control bias voltage customized waveform 901 is defined as the percentage of a given pulse of the feedback control bias voltage customized waveform 901 during the application of a negative voltage. The duty cycle of the feedback control bias voltage customized waveform 901 may vary from pulse to pulse of the feedback control bias voltage customized waveform 901. In certain embodiments, such as shown in FIG. 9 , the slope (dV/dT) of the feedback control bias voltage customized waveform 901 is substantially constant during the negative voltage portion of each pulse of the feedback control bias voltage customized waveform 901, regardless of the duty cycle applied during the pulse. However, in some embodiments, the slope (dV/dT) during the negative voltage portion of each pulse of the feedback control bias voltage customized waveform 901 is adjusted between pulses of the feedback control bias voltage customized waveform 901.

在某些實施例中,即時基板105頂面105T電壓( V 基板 )係判定為具有夠高的取樣/量測率,使得當即時基板105頂面105T電壓( V 基板 )與設定點電壓911之間的差超過指定閾值時,即時偵測係有可能的。在這些實施例中,每當即時基板105頂面105T電壓( V 基板 )與設定點電壓911之間的差超過指定閾值時,回饋控制偏壓電壓定制波形901之當前脈衝的負電壓部分便自動結束,而相應於偏壓電壓定制波形901之工作週期的自動閉迴路回饋控制。 In some embodiments, the real-time substrate 105 top surface 105T voltage ( Vsubstrate ) is determined to have a sufficiently high sampling/measurement rate so that real-time detection is possible when the difference between the real-time substrate 105 top surface 105T voltage ( Vsubstrate ) and the set point voltage 911 exceeds a specified threshold. In these embodiments, whenever the difference between the real-time substrate 105 top surface 105T voltage ( Vsubstrate ) and the set point voltage 911 exceeds the specified threshold, the negative voltage portion of the current pulse of the feedback control bias voltage customized waveform 901 is automatically terminated, corresponding to automatic closed-loop feedback control of the duty cycle of the bias voltage customized waveform 901.

在某些實施例中,控制偏壓電壓定制波形901的工作週期提供偏壓電壓定制波形901在上電壓邊界與下電壓邊界間延伸之範圍內的限制。並且,在某些實施例中,控制偏壓電壓定制波形901的工作週期依據控制演算法提供電壓突波保護。此外,控制偏壓電壓定制波形901的工作週期提供對原位離子能量的直接影響。在諸多實施例中,可回饋控制偏壓電壓定制波形901的任何一或更多參數以最小化所判定的即時基板105頂面105T電壓( V 基板 )與待於基板105之頂面105T上實現並維持的恆定設定點電壓911之間的差。例如,在某些實施例中,使用所判定的即時基板105頂面105T電壓( V 基板 )作為回饋控制信號而回饋控制偏壓電壓定制波形901之正週期、偏壓電壓定制波形901之負週期、及偏壓電壓定制波形901之頻率中的一或更多者,以便實現並維持基板105之頂面105T上的恆定設定點電壓911。 In some embodiments, controlling the duty cycle of the bias voltage customized waveform 901 provides for limiting the bias voltage customized waveform 901 within a range extending between an upper voltage boundary and a lower voltage boundary. Also, in some embodiments, controlling the duty cycle of the bias voltage customized waveform 901 provides voltage surge protection based on a control algorithm. Furthermore, controlling the duty cycle of the bias voltage customized waveform 901 provides a direct impact on in-situ ion energy. In many embodiments, any one or more parameters of the bias voltage custom waveform 901 may be feedback controlled to minimize the difference between the determined instantaneous substrate 105 top surface 105T voltage ( Vsubstrate ) and a constant set point voltage 911 to be achieved and maintained on the top surface 105T of the substrate 105. For example, in some embodiments, the determined real-time substrate 105 top surface 105T voltage ( Vsubstrate ) is used as a feedback control signal to feedback control one or more of the positive cycle of the bias voltage customized waveform 901, the negative cycle of the bias voltage customized waveform 901, and the frequency of the bias voltage customized waveform 901 so as to achieve and maintain a constant set point voltage 911 on the top surface 105T of the substrate 105.

應理解的是,如關於圖9所述的針對基板105之頂面105T上產生之電壓的閉迴路回饋控制方法同樣可應用於控制邊緣環315之頂面315T上產生的電壓,特別係當實施圖3G的偏壓電壓供應系統333B時。具體而言,所判定的即時邊緣環315頂面315T電壓( V 邊緣環頂部 )作為回饋信號以實現邊緣環315之頂面315T上恆定設定點電壓的使用乃致使供應至邊緣環電極323的回饋控制偏壓電壓定制波形在供應至邊緣環電極323之回饋控制偏壓電壓定制波形的連續脈衝之間於工作週期上逐步增加,直到電漿119密度於TCP RF功率的ON脈衝期間達到穩定態。 It should be understood that the closed loop feedback control method for the voltage generated on the top surface 105T of the substrate 105 as described with respect to FIG. 9 is also applicable to controlling the voltage generated on the top surface 315T of the edge ring 315, particularly when implementing the bias voltage supply system 333B of FIG. 3G. Specifically, the determined real-time edge ring 315 top surface 315T voltage ( Vedge ring top ) is used as a feedback signal to achieve a constant set point voltage on the top surface 315T of the edge ring 315, so that the feedback control bias voltage customized waveform supplied to the edge ring electrode 323 is gradually increased over the duty cycle between consecutive pulses of the feedback control bias voltage customized waveform supplied to the edge ring electrode 323 until the plasma 119 density reaches a steady state during the ON pulse of the TCP RF power.

由於基板支撐件301與邊緣環315之間的電容差異,於TCP RF功率之脈衝時維持小IADF可能係具挑戰性的。因為邊緣環315通常相較於基板支撐件301具有較小的表面積,故邊緣環315相較於基板支撐件301具有較小電容。邊緣環315的較小電容導致邊緣環315之頂面315T上較大的電壓變化。電壓幅度的回饋控制通常為了調節與目標電壓之較大偏差而需要更多時間。從而,因為邊緣環315相較於基板支撐件301具有較小電容,故邊緣環315相較於基板支撐件301需要更快的回饋控制。當基板105頂面105T電壓抑或邊緣環315頂面315T電壓脫離回饋控制時,在基板105的頂面105T與邊緣環315的頂面315T之間可能存在大電壓差,而可能造成大IADF以及相應不利的蝕刻傾斜。在某些實施例中,當實施圖3D的偏壓電壓供應系統333A時,偏壓電壓定制波形342之工作週期的閉迴路回饋控制提供對於基板105之頂面105T與邊緣環315之頂面315T間電壓差的限制,以便在基板105的邊緣附近維持小IDAF。在某些實施例中,當實施圖3G的偏壓電壓供應系統333B時,偏壓電壓定制波形342-1及342-2之每一者的獨立閉迴路回饋控制提供對於基板105之頂面105T與邊緣環315之頂面315T間電壓差的限制,以便在基板105的邊緣附近維持小IDAF。Maintaining a small IADF when pulsing TCP RF power can be challenging due to the capacitance difference between the substrate support 301 and the edge ring 315. Because the edge ring 315 typically has a smaller surface area than the substrate support 301, the edge ring 315 has a smaller capacitance than the substrate support 301. The smaller capacitance of the edge ring 315 results in a larger voltage variation on the top surface 315T of the edge ring 315. Feedback control of the voltage amplitude typically requires more time to adjust for larger deviations from the target voltage. Thus, because the edge ring 315 has a smaller capacitance than the substrate support 301, the edge ring 315 requires faster feedback control than the substrate support 301. When the voltage on the top surface 105T of the substrate 105 or the voltage on the top surface 315T of the edge ring 315 is out of feedback control, a large voltage difference may exist between the top surface 105T of the substrate 105 and the top surface 315T of the edge ring 315, which may cause a large IADF and a corresponding unfavorable etch tilt. In some embodiments, when the bias voltage supply system 333A of FIG. 3D is implemented, closed-loop feedback control of the duty cycle of the bias voltage custom waveform 342 provides a limit on the voltage difference between the top surface 105T of the substrate 105 and the top surface 315T of the edge ring 315 so as to maintain a small IDAF near the edge of the substrate 105. In some embodiments, when the bias voltage supply system 333B of FIG. 3G is implemented, independent closed-loop feedback control of each of the bias voltage customized waveforms 342-1 and 342-2 provides a limit on the voltage difference between the top surface 105T of the substrate 105 and the top surface 315T of the edge ring 315 so as to maintain a small IDAF near the edge of the substrate 105.

在某些實施例中,偏壓電壓供應系統333包括配置在基板支撐件301內的偏壓電極123以及配置在基板支撐件301內的中階電極302,使得基板支撐件301的下部303存在於偏壓電極123與中階電極302之間,並且使得基板支撐件301的上部305存在於中階電極302與基板支撐件301的頂面301T之間。偏壓電壓供應系統333亦包括連接以供應偏壓電壓定制射頻波形至偏壓電極123的電壓供應系統341、391。在某些實施例中,將偏壓電壓定制射頻波形定義為持續的脈衝循環系列,其中每一脈衝循環包括其中偏壓電壓定制射頻波形具有負電壓的on期間以及其中偏壓電壓定制射頻波形具有正電壓的off期間。偏壓電壓供應系統333亦包括連接以量測偏壓電極123上之第一電壓與中階電極302上之第二電壓的電壓量測系統。偏壓電壓供應系統333亦包括控制器351(或控制器351的部分),控制器351係配置以使用所量測第一電壓、所量測第二電壓、基板支撐件301之下部303之電容、及基板支撐件301之上部305之電容以判定當基板存在於基板支撐件301之頂面301T上時基板105之頂面105T上的電壓。控制器351係配置以將基板105之頂面105T上的電壓傳遞至電壓供應系統341、391。In some embodiments, the bias voltage supply system 333 includes a bias electrode 123 disposed in the substrate support 301 and an intermediate electrode 302 disposed in the substrate support 301, such that a lower portion 303 of the substrate support 301 is located between the bias electrode 123 and the intermediate electrode 302, and an upper portion 305 of the substrate support 301 is located between the intermediate electrode 302 and a top surface 301T of the substrate support 301. The bias voltage supply system 333 also includes voltage supply systems 341, 391 connected to supply a bias voltage customized RF waveform to the bias electrode 123. In some embodiments, the bias voltage customized RF waveform is defined as a continuous series of pulse cycles, wherein each pulse cycle includes an on period in which the bias voltage customized RF waveform has a negative voltage and an off period in which the bias voltage customized RF waveform has a positive voltage. The bias voltage supply system 333 also includes a voltage measurement system connected to measure a first voltage on the bias electrode 123 and a second voltage on the intermediate electrode 302. The bias voltage supply system 333 also includes a controller 351 (or a portion of the controller 351), which is configured to use the measured first voltage, the measured second voltage, the capacitance of the lower portion 303 of the substrate support 301, and the capacitance of the upper portion 305 of the substrate support 301 to determine the voltage on the top surface 105T of the substrate 105 when the substrate is present on the top surface 301T of the substrate support 301. The controller 351 is configured to communicate the voltage on the top surface 105T of the substrate 105 to the voltage supply systems 341, 391.

在某些實施例中,電壓供應系統341、391係配置以調整偏壓電壓定制射頻波形以最小化設定點電壓與基板105之頂面105T上電壓之間的差。在某些實施例中,電壓供應系統341、391係配置以在偏壓電壓定制射頻波形的一脈衝循環內調整偏壓電壓定制射頻波形。在某些實施例中,控制器351係配置以藉由計算第一項及第二項之和而判定基板105之頂面105T上的電壓,其中第一項等於中階電極302上的第二電壓,其中第二項等於一常數與差分電壓的乘積,其中該常數等於基板支撐件301之下部303之電容與基板支撐件301之上部305之電容的比值,且其中差分電壓等於中階電極302上的第二電壓減去偏壓電極123上的第一電壓。In some embodiments, the voltage supply system 341, 391 is configured to adjust the bias voltage customized RF waveform to minimize the difference between the set point voltage and the voltage on the top surface 105T of the substrate 105. In some embodiments, the voltage supply system 341, 391 is configured to adjust the bias voltage customized RF waveform within a pulse cycle of the bias voltage customized RF waveform. In some embodiments, the controller 351 is configured to determine the voltage on the top surface 105T of the substrate 105 by calculating the sum of a first term and a second term, wherein the first term is equal to the second voltage on the intermediate electrode 302, wherein the second term is equal to the product of a constant and a differential voltage, wherein the constant is equal to the ratio of the capacitance of the lower portion 303 of the substrate support 301 to the capacitance of the upper portion 305 of the substrate support 301, and wherein the differential voltage is equal to the second voltage on the intermediate electrode 302 minus the first voltage on the bias electrode 123.

在某些實施例中,偏壓電壓供應系統333亦包括配置在邊緣環315內的邊緣環電極323,邊緣環315係配置以侷限基板支撐件301。邊緣環電極323係配置以控制邊緣環315之頂面315T上的電壓。供應至基板支撐件301內偏壓電極123的偏壓電壓定制射頻波形係第一偏壓電壓定制射頻波形。邊緣環電極323係連接以接收來自電壓供應系統341、396的第二偏壓電壓定制射頻波形。在某些實施例中,將第二偏壓電壓定制射頻波形定義為持續的脈衝循環系列,其中每一脈衝循環包括其中第二偏壓電壓定制射頻波形具有負電壓的on期間以及其中第二偏壓電壓定制射頻波形具有正電壓的off期間。偏壓電壓供應系統333亦包括配置在邊緣環315內的邊緣環中階電極317,使得邊緣環315的下部319存在於邊緣環電極323與邊緣環中階電極317之間,並且使得邊緣環315的上部321存在於邊緣環中階電極317與邊緣環315的頂面315T之間。In some embodiments, the bias voltage supply system 333 also includes an edge ring electrode 323 configured within the edge ring 315, and the edge ring 315 is configured to confine the substrate support 301. The edge ring electrode 323 is configured to control the voltage on the top surface 315T of the edge ring 315. The bias voltage customized RF waveform supplied to the bias electrode 123 in the substrate support 301 is a first bias voltage customized RF waveform. The edge ring electrode 323 is connected to receive a second bias voltage customized RF waveform from the voltage supply system 341, 396. In some embodiments, the second bias voltage customized RF waveform is defined as a continuous series of pulse cycles, wherein each pulse cycle includes an on period in which the second bias voltage customized RF waveform has a negative voltage and an off period in which the second bias voltage customized RF waveform has a positive voltage. The bias voltage supply system 333 also includes an edge ring intermediate electrode 317 configured in the edge ring 315, so that the lower portion 319 of the edge ring 315 exists between the edge ring electrode 323 and the edge ring intermediate electrode 317, and the upper portion 321 of the edge ring 315 exists between the edge ring intermediate electrode 317 and the top surface 315T of the edge ring 315.

電壓量測系統係連接以量測邊緣環電極323上的第三電壓以及邊緣環中階電極317上的第四電壓。控制器351係配置以使用所量測之邊緣環電極323上第三電壓、所量測之邊緣環中階電極317上第四電壓、邊緣環315之下部319之電容、及邊緣環315之上部321之電容以判定邊緣環315之頂面315T上的電壓。在某些實施例中,控制器351係配置以藉由計算第一項及第二項之和而判定邊緣環315之頂面315T上的電壓,其中第一項等於邊緣環中階電極317上的第四電壓,其中第二項等於一常數與差分電壓的乘積,其中該常數等於邊緣環315之下部319之電容與邊緣環315之上部321之電容的比值,且其中差分電壓等於邊緣環中階電極317上的第四電壓減去邊緣環電極323上的第三電壓。控制器351係配置以將邊緣環315之頂面315T上的電壓傳遞至電壓供應系統。The voltage measurement system is connected to measure a third voltage on the edge ring electrode 323 and a fourth voltage on the edge ring intermediate electrode 317. The controller 351 is configured to use the measured third voltage on the edge ring electrode 323, the measured fourth voltage on the edge ring intermediate electrode 317, the capacitance of the lower portion 319 of the edge ring 315, and the capacitance of the upper portion 321 of the edge ring 315 to determine the voltage on the top surface 315T of the edge ring 315. In some embodiments, the controller 351 is configured to determine the voltage on the top surface 315T of the edge ring 315 by calculating the sum of a first term and a second term, wherein the first term is equal to the fourth voltage on the edge ring mid-stage electrode 317, wherein the second term is equal to the product of a constant and a differential voltage, wherein the constant is equal to the ratio of the capacitance of the lower portion 319 of the edge ring 315 to the capacitance of the upper portion 321 of the edge ring 315, and wherein the differential voltage is equal to the fourth voltage on the edge ring mid-stage electrode 317 minus the third voltage on the edge ring electrode 323. The controller 351 is configured to transmit the voltage on the top surface 315T of the edge ring 315 to the voltage supply system.

在某些實施例中,偏壓電壓供應系統333包括可變電容器359、361、363、365,可變電容器359、361、363、365係配置以相對於供應至偏壓電極123的第一偏壓電壓定制射頻波形個別地控制供應至邊緣環電極323的第二偏壓電壓定制射頻波形。在某些實施例中,電壓供應系統341、396係配置以調整供應至邊緣環電極323的第二偏壓電壓定制射頻波形以最小化設定點電壓與邊緣環315之頂面315T上電壓之間的差。在某些實施例中,電壓供應系統341、396係配置以在第二偏壓電壓定制射頻波形的一脈衝循環內調整供應至邊緣環電極323的第二偏壓電壓定制射頻波形。In some embodiments, the bias voltage supply system 333 includes variable capacitors 359, 361, 363, 365, which are configured to individually control the second bias voltage customized RF waveform supplied to the edge ring electrode 323 relative to the first bias voltage customized RF waveform supplied to the bias electrode 123. In some embodiments, the voltage supply system 341, 396 is configured to adjust the second bias voltage customized RF waveform supplied to the edge ring electrode 323 to minimize the difference between the set point voltage and the voltage on the top surface 315T of the edge ring 315. In some embodiments, the voltage supply system 341, 396 is configured to adjust the second bias voltage customized RF waveform supplied to the edge ring electrode 323 within a pulse cycle of the second bias voltage customized RF waveform.

在某些實施例中,揭示用於電漿處理系統300的基板支撐系統。基板支撐系統包括具有配置以支撐基板105之頂面301T的基板支撐件301。基板支撐系統包括配置在基板支撐件301內的偏壓電極123。偏壓電極123係配置以控制基板105之頂面105T上的電壓。偏壓電極123係連接以接收來自電壓供應系統341、391的偏壓電壓定制射頻波形。基板支撐系統亦包括配置在基板支撐件301內的中階電極302,使得基板支撐件301的下部303存在於偏壓電極123與中階電極302之間,並且使得基板支撐件301的上部305存在於中階電極302與基板支撐件301的頂面301T之間。基板支撐系統亦包括電連接至偏壓電極123的第一連接器313以用於量測偏壓電極123上的第一即時電壓。偏壓電極123係配置以電性接收第一連接器313以用於量測偏壓電極123上的第一即時電壓。基板支撐系統亦包括電連接至中階電極302的第二連接器309以用於量測中階電極302上的第二即時電壓。中階電極302係配置以電性接收第二連接器309以用於量測中階電極302上的第二即時電壓。基板支撐系統亦包括控制器351,控制器351係配置以使用所量測的偏壓電極123上之第一即時電壓、所量測的中階電極302上之第二即時電壓、基板支撐件301之下部303之電容、及基板支撐件301之上部305之電容以判定基板105之頂面105T上的即時電壓。In certain embodiments, a substrate support system for a plasma processing system 300 is disclosed. The substrate support system includes a substrate support 301 having a top surface 301T configured to support a substrate 105. The substrate support system includes a bias electrode 123 disposed within the substrate support 301. The bias electrode 123 is configured to control a voltage on a top surface 105T of the substrate 105. The bias electrode 123 is connected to receive a bias voltage customized RF waveform from a voltage supply system 341, 391. The substrate support system also includes an intermediate electrode 302 disposed within the substrate support 301 such that a lower portion 303 of the substrate support 301 is located between the bias electrode 123 and the intermediate electrode 302, and an upper portion 305 of the substrate support 301 is located between the intermediate electrode 302 and a top surface 301T of the substrate support 301. The substrate support system also includes a first connector 313 electrically connected to the bias electrode 123 for measuring a first real-time voltage on the bias electrode 123. The bias electrode 123 is configured to electrically receive the first connector 313 for measuring the first real-time voltage on the bias electrode 123. The substrate support system also includes a second connector 309 electrically connected to the intermediate electrode 302 for measuring a second real-time voltage on the intermediate electrode 302. The intermediate electrode 302 is configured to electrically receive the second connector 309 for measuring the second real-time voltage on the intermediate electrode 302. The substrate support system also includes a controller 351, which is configured to use the measured first real-time voltage on the bias electrode 123, the measured second real-time voltage on the intermediate electrode 302, the capacitance of the lower portion 303 of the substrate support 301, and the capacitance of the upper portion 305 of the substrate support 301 to determine the real-time voltage on the top surface 105T of the substrate 105.

在某些實施例中,揭示用於電漿處理系統300的邊緣環系統。邊緣環系統包括配置以侷限基板支撐件301的邊緣環315。邊緣環系統亦包括配置在邊緣環315內的邊緣環電極323。邊緣環電極323係配置以控制邊緣環315之頂面315T上的電壓。邊緣環電極323係連接以接收來自電壓供應系統341、396的偏壓電壓定制射頻波形。邊緣環系統亦包括配置在邊緣環315內的邊緣環中階電極317,使得邊緣環315的下部319存在於邊緣環電極323與邊緣環中階電極317之間,並且使得邊緣環315的上部321存在於邊緣環中階電極317與邊緣環315的頂面315T之間。邊緣環系統亦包括電連接至邊緣環電極323的第一連接器327以用於量測邊緣環電極323上的第一即時電壓。邊緣環電極323係配置以電性接收第一連接器327以用於量測邊緣環電極323上的第一即時電壓。邊緣環系統亦包括電連接至邊緣環中階電極317的第二連接器331以用於量測邊緣環中階電極317上的第二即時電壓。邊緣環中階電極317係配置以電性接收第二連接器331以用於量測邊緣環中階電極317上的第二即時電壓。控制器351係配置以使用所量測的邊緣環電極323上之第一即時電壓、所量測的邊緣環中階電極317上之第二即時電壓、邊緣環315之下部319之電容、及邊緣環315之上部321之電容以判定邊緣環315之頂面315T上的即時電壓。In certain embodiments, an edge ring system for a plasma processing system 300 is disclosed. The edge ring system includes an edge ring 315 configured to confine a substrate support 301. The edge ring system also includes an edge ring electrode 323 configured within the edge ring 315. The edge ring electrode 323 is configured to control a voltage on a top surface 315T of the edge ring 315. The edge ring electrode 323 is connected to receive a bias voltage custom RF waveform from a voltage supply system 341, 396. The edge ring system also includes an edge ring intermediate electrode 317 disposed in the edge ring 315 such that a lower portion 319 of the edge ring 315 exists between the edge ring electrode 323 and the edge ring intermediate electrode 317, and an upper portion 321 of the edge ring 315 exists between the edge ring intermediate electrode 317 and a top surface 315T of the edge ring 315. The edge ring system also includes a first connector 327 electrically connected to the edge ring electrode 323 for measuring a first real-time voltage on the edge ring electrode 323. The edge ring electrode 323 is configured to electrically receive the first connector 327 for measuring a first real-time voltage on the edge ring electrode 323. The edge ring system also includes a second connector 331 electrically connected to the edge ring intermediate electrode 317 for measuring a second real-time voltage on the edge ring intermediate electrode 317. The edge ring intermediate electrode 317 is configured to electrically receive the second connector 331 for measuring a second real-time voltage on the edge ring intermediate electrode 317. The controller 351 is configured to use the measured first real-time voltage on the edge ring electrode 323, the measured second real-time voltage on the edge ring middle electrode 317, the capacitance of the lower portion 319 of the edge ring 315, and the capacitance of the upper portion 321 of the edge ring 315 to determine the real-time voltage on the top surface 315T of the edge ring 315.

依據某些實施例,圖10A顯示用於控制基板105上電壓之方法的流程圖。方法包括操作1001,以用於操作電壓供應系統341、391以供應偏壓電壓定制射頻波形至基板支撐件301內的偏壓電極123。方法亦包括操作1003,以用於在給定時間量測偏壓電極123上的第一電壓。應理解的是,可使用其他相關參數來判定/計算例如電壓的諸多電性參數,例如,V=IR,其中V係電壓,I係電流,以及R係電阻。因而,應理解的是,可藉由直接電壓量測抑或間接電壓量測來進行本文所提及的諸多電壓量測,其中間接電壓量測包括與待量測電壓相關之一或更多參數的判定/量測以及使用與待量測電壓相關之一或更多參數對待量測電壓的後續判定/計算。方法亦包括操作1005,以用於在給定時間量測中階電極302上的第二電壓。方法亦包括操作1007,以用於使用在給定時間所量測之偏壓電極123上第一電壓、在給定時間所量測之中階電極302上第二電壓、基板支撐件301之下部303之電容、及基板支撐件301之上部305之電容以在給定時間判定當基板105存在於基板支撐件301之頂面301T上時基板105之頂面105T上的電壓。According to some embodiments, FIG. 10A shows a flow chart of a method for controlling voltage on a substrate 105. The method includes operation 1001 for operating a voltage supply system 341, 391 to supply a bias voltage customized RF waveform to a bias electrode 123 in a substrate support 301. The method also includes operation 1003 for measuring a first voltage on the bias electrode 123 at a given time. It should be understood that other related parameters may be used to determine/calculate a variety of electrical parameters such as voltage, for example, V=IR, where V is voltage, I is current, and R is resistance. Thus, it should be understood that the various voltage measurements mentioned herein can be performed by direct voltage measurement or indirect voltage measurement, wherein the indirect voltage measurement includes the determination/measurement of one or more parameters related to the voltage to be measured and the subsequent determination/calculation of the voltage to be measured using one or more parameters related to the voltage to be measured. The method also includes operation 1005 for measuring a second voltage on the intermediate electrode 302 at a given time. The method also includes an operation 1007 for using a first voltage on the bias electrode 123 measured at a given time, a second voltage on the intermediate electrode 302 measured at a given time, a capacitance of a lower portion 303 of the substrate support 301, and a capacitance of an upper portion 305 of the substrate support 301 to determine a voltage on a top surface 105T of the substrate 105 when the substrate 105 is present on a top surface 301T of the substrate support 301 at the given time.

依據某些實施例,圖10B顯示用於控制基板105上電壓的圖10A之方法之可選延續的流程圖。方法包括操作1009,以用於判定於給定時間之基板105之頂面105T上電壓與設定點電壓之間的差。方法亦包括操作1011,以用於判定對於偏壓電壓定制射頻波形的調整,所述調整將減小於給定時間之基板105之頂面105T上電壓與設定點電壓之間的差。方法亦包括操作1013,以用於操作電壓供應系統341、391以實施對於偏壓電壓定制射頻波形的調整。According to certain embodiments, FIG. 10B shows a flow chart of an optional continuation of the method of FIG. 10A for controlling a voltage on a substrate 105. The method includes an operation 1009 for determining a difference between a voltage on a top surface 105T of the substrate 105 at a given time and a set point voltage. The method also includes an operation 1011 for determining an adjustment to a bias voltage custom RF waveform that will reduce the difference between a voltage on a top surface 105T of the substrate 105 at a given time and the set point voltage. The method also includes an operation 1013 for operating a voltage supply system 341, 391 to implement the adjustment to the bias voltage custom RF waveform.

在某些實施例中,給定時間發生於偏壓電壓定制射頻波形之循環的負區段期間,且操作1013係執行以於偏壓電壓定制射頻波形之下一循環的負區段期間實施對於偏壓電壓定制射頻波形的調整。在某些實施例中,對於偏壓電壓定制射頻波形的調整係電壓變動作為於偏壓電壓定制射頻波形之下一循環的負區段期間中時間的函數。在某些實施例中,對於偏壓電壓定制射頻波形的調整係偏壓電壓定制射頻波形之下一循環的負區段期間之持續時間的變動。In some embodiments, the given time occurs during a negative portion of a cycle of the bias voltage customized RF waveform, and operation 1013 is performed to implement an adjustment to the bias voltage customized RF waveform during the negative portion of a cycle under the bias voltage customized RF waveform. In some embodiments, the adjustment to the bias voltage customized RF waveform is a change in voltage as a function of time during the negative portion of a cycle under the bias voltage customized RF waveform. In some embodiments, the adjustment to the bias voltage customized RF waveform is a change in the duration of the negative portion of a cycle under the bias voltage customized RF waveform.

依據某些實施例,圖10C顯示圖10A抑或圖10B之方法之可選延續的流程圖。方法亦包括操作1015,以用於操作電壓供應系統341、396以供應第二偏壓電壓定制射頻波形至侷限基板支撐件301之邊緣環315內的邊緣環電極323。在此實施例中,將供應至基板支撐件301內偏壓電極123的偏壓電壓定制射頻波形稱為第一偏壓電壓定制射頻波形。方法亦包括操作1017,以用於在給定時間量測邊緣環電極323上的第三電壓。方法亦包括操作1019,以用於在給定時間量測邊緣環中階電極317上的第四電壓。方法亦包括操作1021,以用於使用在給定時間所量測之邊緣環電極323上第三電壓、在給定時間所量測之邊緣環中階電極317上第四電壓、邊緣環315之下部319之電容、及邊緣環315之上部321之電容以在給定時間判定邊緣環315之頂面315T上的電壓。According to some embodiments, FIG. 10C shows a flow chart of an optional continuation of the method of FIG. 10A or FIG. 10B. The method also includes an operation 1015 for operating the voltage supply system 341, 396 to supply a second bias voltage customized RF waveform to the edge ring electrode 323 within the edge ring 315 of the confined substrate support 301. In this embodiment, the bias voltage customized RF waveform supplied to the bias electrode 123 in the substrate support 301 is referred to as the first bias voltage customized RF waveform. The method also includes an operation 1017 for measuring a third voltage on the edge ring electrode 323 at a given time. The method also includes an operation 1019 for measuring a fourth voltage on the edge ring intermediate electrode 317 at a given time. The method also includes an operation 1021 for using the third voltage on the edge ring electrode 323 measured at a given time, the fourth voltage on the edge ring intermediate electrode 317 measured at a given time, the capacitance of the lower portion 319 of the edge ring 315, and the capacitance of the upper portion 321 of the edge ring 315 to determine the voltage on the top surface 315T of the edge ring 315 at a given time.

依據某些實施例,圖10D顯示用於控制邊緣環315上電壓的圖10C之方法之可選延續的流程圖。方法包括操作1023,以用於判定於給定時間之邊緣環315之頂面315T上電壓與設定點電壓之間的差。方法亦包括操作1025,以用於判定對於第二偏壓電壓定制射頻波形的調整,所述調整將減小於給定時間之邊緣環315之頂面315T上電壓與設定點電壓之間的差。方法亦包括操作1027,以用於操作電壓供應系統341、396以實施對於第二偏壓電壓定制射頻波形的調整。在某些實施例中,給定時間發生於第二偏壓電壓定制射頻波形之循環的負區段期間,且操作1027係執行以於第二偏壓電壓定制射頻波形之下一循環的負區段期間實施對於第二偏壓電壓定制射頻波形的調整。在某些實施例中,對於第二偏壓電壓定制射頻波形的調整係電壓變動作為於第二偏壓電壓定制射頻波形之下一循環的負區段期間中時間的函數。在某些實施例中,對於第二偏壓電壓定制射頻波形的調整係第二偏壓電壓定制射頻波形之下一循環的負區段期間之持續時間的變動。According to certain embodiments, FIG. 10D shows a flow chart of an optional continuation of the method of FIG. 10C for controlling the voltage on the edge ring 315. The method includes an operation 1023 for determining the difference between the voltage on the top surface 315T of the edge ring 315 at a given time and the set point voltage. The method also includes an operation 1025 for determining an adjustment for the second bias voltage custom RF waveform that will reduce the difference between the voltage on the top surface 315T of the edge ring 315 at a given time and the set point voltage. The method also includes an operation 1027 for operating the voltage supply system 341, 396 to implement the adjustment for the second bias voltage custom RF waveform. In some embodiments, the given time occurs during a negative portion of a cycle of the second bias voltage customized RF waveform, and operation 1027 is performed to implement an adjustment to the second bias voltage customized RF waveform during the negative portion of a cycle under the second bias voltage customized RF waveform. In some embodiments, the adjustment to the second bias voltage customized RF waveform is a voltage change as a function of time during the negative portion of a cycle under the second bias voltage customized RF waveform. In some embodiments, the adjustment of the second bias voltage customized RF waveform is a change in the duration of a negative segment of a cycle under the second bias voltage customized RF waveform.

可結合諸多電腦系統配置來實踐本文所述的諸多實施例,電腦系統配置包括手持硬體單元、微處理器系統、基於微處理器的或可程式化的消費性電子產品、迷你電腦、大型電腦及其相似者。亦可結合經由電腦網路連接的遠端處理硬體單元執行任務所在的分散式計算環境來實踐本文所述的諸多實施例。亦應理解的是,本文所揭示的諸多實施例包括涉及儲存於電腦系統中之資料的諸多電腦實行操作之執行。這些電腦實行操作乃為操縱物理量的操作。在諸多實施例中,藉由通用電腦抑或特別用途電腦來執行電腦實行操作。在某些實施例中,藉由選擇性啟動的電腦來執行、及/或藉由儲存在電腦記憶體中或經由電腦網路獲取的一或更多電腦程式來指導電腦實行操作。當經由電腦網路獲取電腦程式及/或數位資料時,可藉由電腦網路上的其他電腦來處理數位資料,例如,計算資源雲。電腦程式及數位資料係儲存為非暫態電腦可讀取媒體上的電腦可讀編碼。非暫態電腦可讀取媒體係儲存資料的任何的資料儲存硬體單元,例如,記憶體裝置等等,而之後可藉由電腦系統讀取資料。非暫態電腦可讀取媒體的範例包括硬碟、網路附接儲存器(NAS)、ROM、RAM、光碟-ROMs (CD-ROMs)、可錄CD(CD-Rs)、可複寫CD(CD-RWs)、數位影像/光碟(DVD)、磁帶、及其他光學和非光學的資料儲存硬體單元。在某些實施例中,電腦程式及/或數位資料係分散在位於耦合電腦系統之網路內不同電腦系統中的多個電腦可讀取媒體之中,使得電腦程式及/或數位資料可以分散的形式被執行及/或儲存。The embodiments described herein may be practiced in conjunction with a variety of computer system configurations, including handheld hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, and the like. The embodiments described herein may also be practiced in conjunction with a distributed computing environment in which remote processing hardware units connected via a computer network perform tasks. It should also be understood that the embodiments disclosed herein include the execution of a variety of computer-implemented operations involving data stored in a computer system. These computer-implemented operations are operations that manipulate physical quantities. In many embodiments, the computer-implemented operations are performed by a general-purpose computer or a special-purpose computer. In some embodiments, the computer is operated by executing selectively activated computers and/or by directing one or more computer programs stored in the computer memory or obtained via a computer network. When the computer program and/or digital data are obtained via a computer network, the digital data can be processed by other computers on the computer network, for example, a computing resource cloud. The computer program and digital data are stored as computer-readable code on non-transitory computer-readable media. Non-transitory computer-readable media is any data storage hardware unit that stores data, such as a memory device, etc., and the data can then be read by a computer system. Examples of non-transitory computer-readable media include hard disks, network attached storage (NAS), ROM, RAM, compact disk-ROMs (CD-ROMs), recordable CDs (CD-Rs), rewritable CDs (CD-RWs), digital video/optical disks (DVDs), magnetic tapes, and other optical and non-optical data storage hardware units. In some embodiments, a computer program and/or digital data is distributed among multiple computer-readable media located in different computer systems in a network of coupled computer systems, so that the computer program and/or digital data can be executed and/or stored in a distributed form.

儘管以上揭示內容係為了清楚理解之目的而包括某些細節,但將顯見可在隨附申請專利範圍的範疇內實踐某些變化及修改。例如,應理解本文所揭示之任何實施例中的一或更多特徵可與本文所揭示之任何其他實施例的一或更多特徵相結合。因此,應將本文實施例視為說明性的而非限制性的,且所申請之專利範圍並不限於本文中給出的細節,而係可在所述實施例的範疇及同等範疇內進行修改。Although the above disclosure includes certain details for the purpose of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. For example, it is understood that one or more features of any embodiment disclosed herein may be combined with one or more features of any other embodiment disclosed herein. Therefore, the embodiments herein should be regarded as illustrative and not restrictive, and the scope of the claims is not limited to the details given herein, but may be modified within the scope of the embodiments and equivalents.

100,300:電漿處理系統 101:腔室 102:電漿處理區 103:基板支撐件 103T:基板支撐件103之頂面 104:參考接地電位 105:基板 105T:基板之頂面 107:窗口 109:線圈 111,127:阻抗匹配網路 113:TCP RF產生器 115,129,309,327,313,331,335,337,347,349:連接 117,121:箭號 119:電漿 123:偏壓電極 125:偏壓RF產生器 201:曲線V(輸出) 203:曲線V(基板頂部 1 Amp) 205:曲線V(基板頂部 0.5 Amp) 301:基板支撐件 301T:基板支撐件301之頂面 302:中階電極 303:基板支撐件301的下部 305:基板支撐件301的上部 307,311,325,329:電壓量測裝置 315:邊緣環 315T:邊緣環315之頂面 317:邊緣環中階電極 319:邊緣環315的下部319 321:邊緣環315的上部 323:邊緣環電極 333,333A,333B:偏壓電壓供應系統 341,391,396:電壓供應系統 342,342-1,342-2:指定偏壓電壓定制波形 342A:偏壓電壓階躍部分(Vstep) 342B:依時變化偏壓電壓部分(dV/dT) 342A1,342A2:階躍部分 342B1,342B2:斜坡部分 343,392,397:濾波器 344A:第一電壓供應器 344B:第二電壓供應器 345:偏壓電壓供應節點 351:控制器 353:分路電路 355:第一支路 357:第二支路 359,363:串聯電容器 360,362,369,371:切換裝置 361,365:並聯電容器 367:參考接地電位 372:在基板105之頂面105T上的相應偏壓電壓波形 372A:階躍部分 372B:斜坡部分 374:在邊緣環315之頂面315T上的相應偏壓電壓波形 374A:階躍部分 374B:斜坡部分 373,375,377:電壓感測器 379-1 … 379-N, 393-1 … 393-N, 398-1 … 398-N:RF產生器 381-1 … 381-N, 394-1 … 394-N, 399-1 … 399-N:阻抗匹配網路 383:電連接 385:脈衝電壓波形 387:依時變化脈衝電壓波形 390:第一電壓供應系統 395:第二電壓供應系統 401:輸入HU 403:輸入/輸出(I/O)介面 405:輸出HU 407:I/O介面 409:處理器 411:儲存硬體單元(HU) 413:資料通訊匯流排 415:網路介面控制器(NIC) 501,701:偏壓電壓定制波形 503,703,803,903:相應電壓波形 601,705,805,905:電壓波形 707,709:波形703的區域 711,811,911:恆定設定點電壓 801,901:回饋控制偏壓電壓定制波形 1001,1003,1005,1007,1009,1011,1013,1015,1017,1019,1021,1023,1025,1027:操作 100,300: Plasma processing system 101: Chamber 102: Plasma processing zone 103: Substrate support 103T: Top surface of substrate support 103 104: Reference ground potential 105: Substrate 105T: Top surface of substrate 107: Window 109: Coil 111,127: Impedance matching network 113: TCP RF generator 115,129,309,327,313,331,335,337,347,349: Connections 117,121: Arrows 119: Plasma 123: Bias electrode 125: Bias RF generator 201: Curve V (output) 203: Curve V (1 Amp at the top of the substrate) 205: Curve V (0.5 Amp at the top of the substrate) 301: Substrate support 301T: Top surface of substrate support 301 302: Intermediate electrode 303: Lower portion of substrate support 301 305: Upper portion of substrate support 301 307,311,325,329: Voltage measuring device 315: Edge ring 315T: Top surface of edge ring 315 317: Intermediate electrode of edge ring 319: Lower portion 319 of edge ring 315 321: Upper part of edge ring 315 323: Edge ring electrode 333,333A,333B: Bias voltage supply system 341,391,396: Voltage supply system 342,342-1,342-2: Custom waveform for specifying bias voltage 342A: Bias voltage step portion (Vstep) 342B: Time-dependent bias voltage portion (dV/dT) 342A1,342A2: Step portion 342B1,342B2: Slope portion 343,392,397: Filter 344A: First voltage supply 344B: second voltage supply 345: bias voltage supply node 351: controller 353: shunt circuit 355: first branch 357: second branch 359,363: series capacitor 360,362,369,371: switching device 361,365: parallel capacitor 367: reference ground potential 372: corresponding bias voltage waveform on the top surface 105T of the substrate 105 372A: step portion 372B: ramp portion 374: corresponding bias voltage waveform on the top surface 315T of the edge ring 315 374A: step portion 374B: ramp section 373,375,377: voltage sensor 379-1 … 379-N, 393-1 … 393-N, 398-1 … 398-N: RF generator 381-1 … 381-N, 394-1 … 394-N, 399-1 … 399-N: impedance matching network 383: electrical connection 385: pulse voltage waveform 387: time-dependent pulse voltage waveform 390: first voltage supply system 395: second voltage supply system 401: input HU 403: input/output (I/O) interface 405: output HU 407: I/O interface 409: Processor 411: Storage hardware unit (HU) 413: Data communication bus 415: Network interface controller (NIC) 501,701: Bias voltage custom waveform 503,703,803,903: Corresponding voltage waveform 601,705,805,905: Voltage waveform 707,709: Region of waveform 703 711,811,911: Constant set point voltage 801,901: Feedback control bias voltage custom waveform 1001,1003,1005,1007,1009,1011,1013,1015,1017,1019,1021,1023,1025,1027: Operation

依據某些實施例,圖1A顯示穿越電漿處理系統的垂直剖面圖。According to some embodiments, FIG. 1A shows a vertical cross-section through a plasma processing system.

依據某些實施例,參考圖1A中視面A-A,圖1B顯示配置在基板支撐件上之基板的俯視圖。According to some embodiments, referring to view A-A in FIG. 1A , FIG. 1B shows a top view of a substrate disposed on a substrate support.

依據某些實施例,圖2顯示基板之頂面上電壓,基板之頂面上電壓響應藉由偏壓RF產生器之固定振幅RF電壓至偏壓電極的供應,而具有出現於基板之頂面處的兩不同離子通量條件。2 shows the voltage on the top surface of the substrate in response to the supply of a fixed amplitude RF voltage to the bias electrode by the bias RF generator, with two different ion flux conditions occurring at the top surface of the substrate, according to some embodiments.

依據某些實施例,圖3A顯示穿越電漿處理系統的垂直剖面圖。According to some embodiments, FIG. 3A shows a vertical cross-section through a plasma processing system.

依據某些實施例,參考圖3A中視面A-A,圖3B顯示具有圍繞基板支撐件之邊緣環的配置在基板支撐件上之基板的俯視圖。According to some embodiments, referring to view A-A in FIG. 3A , FIG. 3B shows a top view of a substrate disposed on a substrate support having an edge ring surrounding the substrate support.

依據某些實施例,參考圖3A中視面B-B,圖3C顯示基板支撐件內中階電極以及邊緣環內邊緣環中階電極的俯視圖。According to some embodiments, referring to view plane B-B in FIG. 3A , FIG. 3C shows a top view of a mid-level electrode in a substrate support and a mid-level electrode in an edge ring in an edge ring.

依據某些實施例,圖3D顯示為圖3A之偏壓電壓供應系統之示例性實施方式的偏壓電壓供應系統。According to some embodiments, FIG. 3D shows a bias voltage supply system that is an exemplary implementation of the bias voltage supply system of FIG. 3A .

依據某些實施例,圖3E顯示在圖3D之偏壓電壓供應系統內之電壓供應系統的示例性實施方式。According to some embodiments, FIG. 3E shows an exemplary implementation of a voltage supply system within the bias voltage supply system of FIG. 3D .

依據某些實施例,圖3F顯示藉由圖3E之電壓供應系統產生的示例性偏壓電壓定制波形、以及在基板之頂面上的相應偏壓電壓波形、以及在邊緣環之頂面上的相應偏壓電壓波形。According to some embodiments, FIG. 3F shows an exemplary bias voltage customized waveform generated by the voltage supply system of FIG. 3E , and a corresponding bias voltage waveform on the top surface of the substrate, and a corresponding bias voltage waveform on the top surface of the edge ring.

依據某些實施例,圖3G顯示為圖3A之偏壓電壓供應系統之示例性實施方式的偏壓電壓供應系統。According to some embodiments, FIG. 3G shows a bias voltage supply system that is an exemplary implementation of the bias voltage supply system of FIG. 3A .

依據某些實施例,圖4顯示控制器的示例圖。FIG. 4 shows an example diagram of a controller according to some embodiments.

依據某些實施例,圖5顯示藉由圖3A之偏壓電壓供應系統供應至偏壓電極之偏壓電壓定制波形以及在基板之頂面上產出之相應電壓波形的範例。FIG. 5 shows an example of a bias voltage customized waveform supplied to a bias electrode by the bias voltage supply system of FIG. 3A and a corresponding voltage waveform generated on a top surface of a substrate, according to some embodiments.

依據某些實施例,圖6顯示對應於如圖5中顯示之藉由偏壓電壓供應系統供應至偏壓電極之偏壓電壓定制波形的基板支撐件內中階電極上的電壓波形。According to some embodiments, FIG. 6 shows a voltage waveform on an intermediate electrode in a substrate support corresponding to the customized waveform of the bias voltage supplied to the bias electrode by the bias voltage supply system as shown in FIG. 5 .

依據某些實施例,圖7顯示藉由圖3A之偏壓電壓供應系統供應至偏壓電極之偏壓電壓定制波形以及在基板之頂面上產生之相應電壓波形的範例。According to some embodiments, FIG. 7 shows an example of a bias voltage customized waveform supplied to a bias electrode by the bias voltage supply system of FIG. 3A and a corresponding voltage waveform generated on a top surface of a substrate.

依據某些實施例,圖8顯示藉由圖3A之偏壓電壓供應系統供應至偏壓電極的回饋控制偏壓電壓定制波形以及在基板之頂面上產生的相應電壓波形。According to some embodiments, FIG. 8 shows a feedback-controlled bias voltage customized waveform supplied to a bias electrode by the bias voltage supply system of FIG. 3A and a corresponding voltage waveform generated on a top surface of a substrate.

依據某些實施例,圖9顯示藉由圖3A之偏壓電壓供應系統供應至偏壓電極的另一回饋控制偏壓電壓定制波形以及在基板之頂面上產生的相應電壓波形。FIG. 9 illustrates another feedback-controlled bias voltage customized waveform supplied to a bias electrode by the bias voltage supply system of FIG. 3A and a corresponding voltage waveform generated on a top surface of a substrate, according to some embodiments.

依據某些實施例,圖10A顯示用於控制基板上電壓之方法的流程圖。According to some embodiments, FIG. 10A shows a flow chart of a method for controlling a voltage on a substrate.

依據某些實施例,圖10B顯示用於控制基板上電壓的圖10A之方法之可選延續的流程圖。According to some embodiments, FIG. 10B shows a flow chart of an optional continuation of the method of FIG. 10A for controlling a voltage on a substrate.

依據某些實施例,圖10C顯示圖10A抑或圖10B之方法之可選延續的流程圖。According to some embodiments, FIG. 10C is a flow chart showing an optional continuation of the method of either FIG. 10A or FIG. 10B .

依據某些實施例,圖10D顯示用於控制邊緣環上電壓的圖10C之方法之可選延續的流程圖。According to some embodiments, FIG. 10D shows a flow chart of an optional continuation of the method of FIG. 10C for controlling the voltage on the edge ring.

Claims (25)

一種控制一基板上的電壓的系統,包含: 一偏壓電極,配置在一基板支撐件內,該基板支撐件具有配置以支撐一基板的一頂面; 一中階電極,配置在該基板支撐件內使得該基板支撐件的一下部存在於該偏壓電極與該中階電極之間,並且使得該基板支撐件的一上部存在於該中階電極與該基板支撐件的該頂面之間; 一電壓供應系統,連接以供應一偏壓電壓定制射頻波形至該偏壓電極; 一電壓量測系統,連接以量測該偏壓電極上的一第一電壓以及該中階電極上的一第二電壓;及 一控制器,配置以使用所量測的該第一電壓、所量測的該第二電壓、該基板支撐件之該下部之電容、及該基板支撐件之該上部之電容以判定當該基板存在於該基板支撐件之該頂面上時該基板之一頂面上的一電壓,該控制器係配置以將關於該基板之該頂面上之該電壓的資訊傳遞至該電壓供應系統。 A system for controlling a voltage on a substrate comprises: a bias electrode disposed in a substrate support having a top surface configured to support a substrate; an intermediate electrode disposed in the substrate support such that a lower portion of the substrate support is located between the bias electrode and the intermediate electrode, and an upper portion of the substrate support is located between the intermediate electrode and the top surface of the substrate support; a voltage supply system connected to supply a bias voltage customized RF waveform to the bias electrode; a voltage measurement system connected to measure a first voltage on the bias electrode and a second voltage on the intermediate electrode; and a controller configured to use the measured first voltage, the measured second voltage, the capacitance of the lower portion of the substrate support, and the capacitance of the upper portion of the substrate support to determine a voltage on a top surface of the substrate when the substrate is present on the top surface of the substrate support, the controller being configured to transmit information about the voltage on the top surface of the substrate to the voltage supply system. 如請求項1之系統,其中該偏壓電壓定制射頻波形係定義為一持續的脈衝循環系列,其中每一脈衝循環包括其中該偏壓電壓定制射頻波形具有一負電壓的一開(on)期間以及其中該偏壓電壓定制射頻波形具有一正電壓的一關(off)期間。A system as in claim 1, wherein the bias voltage customized RF waveform is defined as a continuous series of pulse cycles, each pulse cycle including an on period in which the bias voltage customized RF waveform has a negative voltage and an off period in which the bias voltage customized RF waveform has a positive voltage. 如請求項2之系統,其中該電壓供應系統係配置以調整該偏壓電壓定制射頻波形以最小化一設定點電壓與該基板之該頂面上的該電壓之間的差。A system as in claim 2, wherein the voltage supply system is configured to adjust the bias voltage custom RF waveform to minimize a difference between a set point voltage and the voltage on the top surface of the substrate. 如請求項3之系統,其中該電壓供應系統係配置以在該偏壓電壓定制射頻波形的一脈衝循環內調整該偏壓電壓定制射頻波形。A system as in claim 3, wherein the voltage supply system is configured to adjust the bias voltage customized RF waveform within a pulse cycle of the bias voltage customized RF waveform. 如請求項1之系統,其中該控制器係配置以藉由計算一第一項及一第二項之和而判定該基板之該頂面上的該電壓,其中該第一項等於該第二電壓,其中該第二項等於一常數與一差分電壓的一乘積,其中該常數等於該基板支撐件之該下部之電容與該基板支撐件之該上部之電容的一比值,且其中該差分電壓等於該第二電壓減去該第一電壓。A system as in claim 1, wherein the controller is configured to determine the voltage on the top surface of the substrate by calculating the sum of a first term and a second term, wherein the first term is equal to the second voltage, wherein the second term is equal to a product of a constant and a differential voltage, wherein the constant is equal to a ratio of the capacitance of the lower portion of the substrate support to the capacitance of the upper portion of the substrate support, and wherein the differential voltage is equal to the second voltage minus the first voltage. 如請求項1之系統,進一步包含: 一邊緣環電極,配置在一邊緣環內,該邊緣環係配置以侷限該基板支撐件,該邊緣環電極係配置以控制該邊緣環之一頂面上的一電壓,其中供應至該基板支撐件內該偏壓電極的該偏壓電壓定制射頻波形係一第一偏壓電壓定制射頻波形,該邊緣環電極係連接以接收來自該電壓供應系統的一第二偏壓電壓定制射頻波形;及 一邊緣環中階電極,配置在該邊緣環內使得該邊緣環的一下部存在於該邊緣環電極與該邊緣環中階電極之間,並且使得該邊緣環的一上部存在於該邊緣環中階電極與該邊緣環的該頂面之間,其中該電壓量測系統係連接以量測該邊緣環電極上的一第三電壓以及該邊緣環中階電極上的一第四電壓, 其中該控制器係配置以使用所量測的該第三電壓、所量測的該第四電壓、該邊緣環之該下部之電容、及該邊緣環之該上部之電容以判定該邊緣環之該頂面上的該電壓,該控制器係配置以將關於該邊緣環之該頂面上之該電壓的資訊傳遞至該電壓供應系統。 The system of claim 1 further comprises: an edge ring electrode disposed in an edge ring, the edge ring being configured to confine the substrate support, the edge ring electrode being configured to control a voltage on a top surface of the edge ring, wherein the bias voltage customized RF waveform supplied to the bias electrode in the substrate support is a first bias voltage customized RF waveform, and the edge ring electrode is connected to receive a second bias voltage customized RF waveform from the voltage supply system; and An edge ring intermediate electrode is arranged in the edge ring so that a lower portion of the edge ring exists between the edge ring electrode and the edge ring intermediate electrode, and an upper portion of the edge ring exists between the edge ring intermediate electrode and the top surface of the edge ring, wherein the voltage measurement system is connected to measure a third voltage on the edge ring electrode and a fourth voltage on the edge ring intermediate electrode, The controller is configured to use the measured third voltage, the measured fourth voltage, the capacitance of the lower portion of the edge ring, and the capacitance of the upper portion of the edge ring to determine the voltage on the top surface of the edge ring, and the controller is configured to transmit information about the voltage on the top surface of the edge ring to the voltage supply system. 如請求項6之系統,進一步包含: 一可變電容器,配置以相對於該第一偏壓電壓定制射頻波形個別地控制該第二偏壓電壓定制射頻波形。 The system of claim 6 further comprises: A variable capacitor configured to individually control the second bias voltage customized RF waveform relative to the first bias voltage customized RF waveform. 如請求項6之系統,其中該第二偏壓電壓定制射頻波形係定義為一持續的脈衝循環系列,其中每一脈衝循環包括其中該第二偏壓電壓定制射頻波形具有一負電壓的一開(on)期間以及其中該第二偏壓電壓定制射頻波形具有一正電壓的一關(off)期間。A system as in claim 6, wherein the second bias voltage customized RF waveform is defined as a continuous series of pulse cycles, wherein each pulse cycle includes an on period in which the second bias voltage customized RF waveform has a negative voltage and an off period in which the second bias voltage customized RF waveform has a positive voltage. 如請求項8之系統,其中該電壓供應系統係配置以調整該第二偏壓電壓定制射頻波形以最小化一設定點電壓與該邊緣環之該頂面上的該電壓之間的差。A system as in claim 8, wherein the voltage supply system is configured to adjust the second bias voltage customized RF waveform to minimize a difference between a set point voltage and the voltage on the top surface of the edge ring. 請求項9之系統,其中該電壓供應系統係配置以在該第二偏壓電壓定制射頻波形的一脈衝循環內調整該第二偏壓電壓定制射頻波形。The system of claim 9, wherein the voltage supply system is configured to adjust the second bias voltage customized RF waveform within a pulse cycle of the second bias voltage customized RF waveform. 如請求項7之系統,其中該控制器係配置以藉由計算一第一項及一第二項之和而判定該邊緣環之該頂面上的該電壓,其中該第一項等於該第四電壓,其中該第二項等於一常數與一差分電壓的一乘積,其中該常數等於該邊緣環之該下部之電容與該邊緣環之該上部之電容的一比值,且其中該差分電壓等於該第四電壓減去該第三電壓。A system as in claim 7, wherein the controller is configured to determine the voltage on the top surface of the edge ring by calculating the sum of a first term and a second term, wherein the first term is equal to the fourth voltage, wherein the second term is equal to a product of a constant and a differential voltage, wherein the constant is equal to a ratio of the capacitance of the lower portion of the edge ring to the capacitance of the upper portion of the edge ring, and wherein the differential voltage is equal to the fourth voltage minus the third voltage. 一種用於一電漿處理系統的一基板支撐系統,包含: 一基板支撐件,具有配置以支撐一基板的一頂面; 一偏壓電極,配置在該基板支撐件內,該偏壓電極係配置以控制該基板之一頂面上的一電壓,該偏壓電極係連接以接收來自一電壓供應系統的一偏壓電壓定制射頻波形,其中該偏壓電極係配置以電性接收一第一連接器以用於量測該偏壓電極上的一第一電壓;及 一中階電極,配置在該基板支撐件內使得該基板支撐件的一下部存在於該偏壓電極與該中階電極之間,並且使得該基板支撐件的一上部存在於該中階電極與該基板支撐件的該頂面之間,其中該中階電極係配置以電性接收一第二連接器以用於量測該中階電極上的一第二電壓。 A substrate support system for a plasma processing system, comprising: a substrate support having a top surface configured to support a substrate; a bias electrode disposed in the substrate support, the bias electrode being configured to control a voltage on a top surface of the substrate, the bias electrode being connected to receive a bias voltage customized RF waveform from a voltage supply system, wherein the bias electrode is configured to electrically receive a first connector for measuring a first voltage on the bias electrode; and An intermediate electrode is disposed in the substrate support so that a lower portion of the substrate support is located between the bias electrode and the intermediate electrode, and an upper portion of the substrate support is located between the intermediate electrode and the top surface of the substrate support, wherein the intermediate electrode is configured to electrically receive a second connector for measuring a second voltage on the intermediate electrode. 如請求項12之用於該電漿處理系統的該基板支撐系統,進一步包含: 一控制器,配置以使用所量測的該第一電壓、所量測的該第二電壓、該基板支撐件之該下部之電容、及該基板支撐件之該上部之電容以判定該基板之該頂面上的該電壓。 The substrate support system for the plasma processing system of claim 12 further comprises: A controller configured to use the measured first voltage, the measured second voltage, the capacitance of the lower portion of the substrate support, and the capacitance of the upper portion of the substrate support to determine the voltage on the top surface of the substrate. 一種用於一電漿處理系統的邊緣環系統,包含: 一邊緣環,配置以侷限一基板支撐件; 一邊緣環電極,配置於該邊緣環內,該邊緣環電極係配置以控制該邊緣環之一頂面上的一電壓並用以接收來自一電壓供應系統的一偏壓電壓定制射頻波形,其中該邊緣環電極係配置以電性接收一第一連接器以用於量測該邊緣環電極上的一第一電壓;及 一邊緣環中階電極,配置於該邊緣環內使得該邊緣環的一下部存在於該邊緣環電極與該邊緣環中階電極之間,並且使得該邊緣環的一上部存在於該邊緣環中階電極與該邊緣環的該頂面之間,其中該邊緣環中階電極係配置以電性接收一第二連接器以用於量測該邊緣環中階電極上的一第二電壓。 An edge ring system for a plasma processing system, comprising: an edge ring, configured to confine a substrate support; an edge ring electrode, configured in the edge ring, the edge ring electrode being configured to control a voltage on a top surface of the edge ring and to receive a bias voltage customized RF waveform from a voltage supply system, wherein the edge ring electrode is configured to electrically receive a first connector for measuring a first voltage on the edge ring electrode; and An edge ring intermediate electrode is arranged in the edge ring so that a lower portion of the edge ring exists between the edge ring electrode and the edge ring intermediate electrode, and an upper portion of the edge ring exists between the edge ring intermediate electrode and the top surface of the edge ring, wherein the edge ring intermediate electrode is arranged to electrically receive a second connector for measuring a second voltage on the edge ring intermediate electrode. 如請求項14之用於該電漿處理系統的該邊緣環系統,進一步包含: 一控制器,配置以使用所量測的該第一電壓、所量測的該第二電壓、該邊緣環之該下部之電容、及該邊緣環之該上部之電容以判定該邊緣環之該頂面上的該電壓。 The edge ring system for the plasma processing system as claimed in claim 14 further comprises: A controller configured to use the measured first voltage, the measured second voltage, the capacitance of the lower portion of the edge ring, and the capacitance of the upper portion of the edge ring to determine the voltage on the top surface of the edge ring. 一種用於控制一基板上電壓的方法,包含: 操作一電壓供應系統以供應一偏壓電壓定制射頻波形至一基板支撐件內的一偏壓電極; 於一給定時間量測該偏壓電極上的一第一電壓; 於該給定時間量測一中階電極上的一第二電壓,該中階電極係配置在該基板支撐件內使得該基板支撐件的一下部存在於該偏壓電極與該中階電極之間,並且使得該基板支撐件的一上部存在於該中階電極與該基板支撐件的一頂面之間;以及 使用所量測的該第一電壓、所量測的該第二電壓、該基板支撐件之該下部之電容、及該基板支撐件之該上部之電容以於該給定時間判定當該基板存在於該基板支撐件之該頂面上時該基板之一頂面上的一電壓。 A method for controlling voltage on a substrate, comprising: Operating a voltage supply system to supply a bias voltage customized RF waveform to a bias electrode in a substrate support; Measuring a first voltage on the bias electrode at a given time; Measuring a second voltage on an intermediate electrode at the given time, the intermediate electrode being arranged in the substrate support so that a lower portion of the substrate support is between the bias electrode and the intermediate electrode, and so that an upper portion of the substrate support is between the intermediate electrode and a top surface of the substrate support; and The measured first voltage, the measured second voltage, the capacitance of the lower portion of the substrate support, and the capacitance of the upper portion of the substrate support are used to determine a voltage on a top surface of the substrate when the substrate is present on the top surface of the substrate support at the given time. 如請求項16之用於控制該基板上電壓的方法,進一步包含: 判定於該給定時間之該基板之該頂面上的該電壓與一設定點電壓之間的差; 判定對於該偏壓電壓定制射頻波形的一調整,該調整將減小於該給定時間之該基板之該頂面上的該電壓與該設定點電壓之間的差;以及 操作該電壓供應系統以實施對於該偏壓電壓定制射頻波形的該調整。 The method for controlling the voltage on the substrate as claimed in claim 16 further comprises: determining the difference between the voltage on the top surface of the substrate at the given time and a set point voltage; determining an adjustment to the bias voltage custom RF waveform that will reduce the difference between the voltage on the top surface of the substrate at the given time and the set point voltage; and operating the voltage supply system to implement the adjustment to the bias voltage custom RF waveform. 如請求項17之用於控制該基板上電壓的方法,其中該給定時間發生於該偏壓電壓定制射頻波形之一循環的一負區段期間,且其中於該偏壓電壓定制射頻波形之一下一循環的一負區段期間實施對於該偏壓電壓定制射頻波形的該調整。A method for controlling the voltage on the substrate as claimed in claim 17, wherein the given time occurs during a negative segment of a cycle of the bias voltage customized RF waveform, and wherein the adjustment of the bias voltage customized RF waveform is implemented during a negative segment of a next cycle of the bias voltage customized RF waveform. 如請求項18之用於控制該基板上電壓的方法,其中對於該偏壓電壓定制射頻波形的該調整係一電壓變動作為於該偏壓電壓定制射頻波形之該下一循環的該負區段期間中時間的一函數。A method for controlling voltage on the substrate as in claim 18, wherein the adjustment of the bias voltage customized RF waveform is a voltage change as a function of time during the negative segment of the next cycle of the bias voltage customized RF waveform. 如請求項18之用於控制該基板上電壓的方法,其中對於該偏壓電壓定制射頻波形的該調整係該偏壓電壓定制射頻波形之該下一循環的該負區段期間之一持續時間的一變動。A method for controlling the voltage on the substrate as in claim 18, wherein the adjustment of the bias voltage customized RF waveform is a change in the duration of the negative segment of the next cycle of the bias voltage customized RF waveform. 如請求項16之用於控制該基板上電壓的方法,進一步包含: 操作該電壓供應系統以供應一第二偏壓電壓定制射頻波形至侷限該基板支撐件之一邊緣環內的一邊緣環電極,其中供應至該基板支撐件內該偏壓電極的該偏壓電壓定制射頻波形係一第一偏壓電壓定制射頻波形; 於該給定時間量測該邊緣環電極上的一第三電壓; 於該給定時間量測一邊緣環中階電極上的一第四電壓,該邊緣環中階電極係配置在該邊緣環內使得該邊緣環的一下部存在於該邊緣環電極與該邊緣環中階電極之間,並且使得該邊緣環的一上部存在於該邊緣環中階電極與該邊緣環的一頂面之間;以及 使用所量測的該第三電壓、所量測的該第四電壓、該邊緣環之該下部之電容、及該邊緣環之該上部之電容以於該給定時間判定該邊緣環之該頂面上的一電壓。 The method for controlling the voltage on the substrate as claimed in claim 16 further comprises: Operating the voltage supply system to supply a second bias voltage customized RF waveform to an edge ring electrode confined within an edge ring of the substrate support, wherein the bias voltage customized RF waveform supplied to the bias electrode within the substrate support is a first bias voltage customized RF waveform; Measuring a third voltage on the edge ring electrode at the given time; Measuring a fourth voltage on a middle electrode of an edge ring at the given time, the middle electrode of the edge ring being arranged in the edge ring so that a lower portion of the edge ring exists between the edge ring electrode and the middle electrode of the edge ring, and an upper portion of the edge ring exists between the middle electrode of the edge ring and a top surface of the edge ring; and Using the measured third voltage, the measured fourth voltage, the capacitance of the lower portion of the edge ring, and the capacitance of the upper portion of the edge ring to determine a voltage on the top surface of the edge ring at the given time. 如請求項21之用於控制該基板上電壓的方法,進一步包含: 判定於該給定時間之該邊緣環之該頂面上的該電壓與一設定點電壓之間的差; 判定對於該第二偏壓電壓定制射頻波形的一調整,該調整將減小於該給定時間之該邊緣環之該頂面上的該電壓與該設定點電壓之間的差;以及 操作該電壓供應系統以實施對於該第二偏壓電壓定制射頻波形的該調整。 The method for controlling the voltage on the substrate as claimed in claim 21 further comprises: determining the difference between the voltage on the top surface of the edge ring at the given time and a set point voltage; determining an adjustment for the second bias voltage customized RF waveform that will reduce the difference between the voltage on the top surface of the edge ring at the given time and the set point voltage; and operating the voltage supply system to implement the adjustment for the second bias voltage customized RF waveform. 如請求項22之用於控制該基板上電壓的方法,其中該給定時間發生於該第二偏壓電壓定制射頻波形之一循環的一負區段期間,且其中於該第二偏壓電壓定制射頻波形之一下一循環的一負區段期間實施對於該第二偏壓電壓定制射頻波形的該調整。A method for controlling the voltage on the substrate as claimed in claim 22, wherein the given time occurs during a negative segment of a cycle of the second bias voltage customized RF waveform, and wherein the adjustment of the second bias voltage customized RF waveform is implemented during a negative segment of a next cycle of the second bias voltage customized RF waveform. 如請求項23之用於控制該基板上電壓的方法,其中對於該第二偏壓電壓定制射頻波形的該調整係一電壓變動作為於該第二偏壓電壓定制射頻波形之該下一循環的該負區段期間中時間的一函數。A method for controlling voltage on the substrate as in claim 23, wherein the adjustment of the second bias voltage customized RF waveform is a voltage change as a function of time during the negative segment of the next cycle of the second bias voltage customized RF waveform. 如請求項23之用於控制該基板上電壓的方法,其中對於該第二偏壓電壓定制射頻波形的該調整係該第二偏壓電壓定制射頻波形之該下一循環的該負區段期間之一持續時間的一變動。A method for controlling the voltage on the substrate as in claim 23, wherein the adjustment of the second bias voltage customized RF waveform is a change in the duration of the negative segment of the next cycle of the second bias voltage customized RF waveform.
TW112126858A 2022-07-21 2023-07-19 Precise feedback control of bias voltage tailored waveform for plasma etch processes TW202422628A (en)

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