TW202420073A - Instruction compression method, instruction decompression method and process compression method - Google Patents

Abstract

An instruction compression method, an instruction decompression method, and a process compression method are provided. The process compression method is used for compressing a process that includes a jump instruction. The process compression method includes the following steps: dividing the process into multiple blocks according to a position of the jump instruction in the process and a destination of the jump instruction; recording a jump relationship between these blocks; performing instruction compression on these blocks; updating a jump address of the jump instruction according to the jump relationship; determining multiple groups according to the sizes of the blocks and the jump relationship; and determining whether the jump instruction is a first type jump instruction or a second type jump instruction according to the relationship between the jump instruction and the groups.

Description

Instruction compression method, instruction decompression method and process compression method

The present invention relates to instruction compression and instruction decompression, and in particular to instruction compression and instruction decompression related to jump instructions (also called branch instructions).

Generally speaking, a process (e.g., an image processing process, a startup process, etc.) usually includes at least one jump instruction. However, existing platforms cannot enable variable-length instruction compression at the same time when processing jump logic, resulting in a larger space required for the instruction register, an increase in the number of long jump instructions, and a decrease in the execution efficiency of the process. Therefore, an instruction compression method, an instruction decompression method, and a process compression method are needed to reduce the space required for the instruction register and reduce the number of long jump instructions.

In view of the deficiencies of the prior art, one object of the present invention is to provide an instruction compression method, an instruction decompression method and a process compression method to improve the deficiencies of the prior art.

An embodiment of the present invention provides an instruction decompression method, which is applied to a hardware circuit. The hardware circuit decompresses an instruction and executes the instruction. The instruction includes a header, and the header includes a reference value. The method includes: when the reference value of the instruction is a default value, reading a first parameter of the instruction to obtain a number of different parameters; and setting a plurality of corresponding parameters of the hardware circuit with a plurality of second parameters of the instruction, and the number of the second parameters is equal to the number of different parameters.

Another embodiment of the present invention provides an instruction compression method for compressing an instruction to generate a compressed instruction, wherein the instruction includes a header and a plurality of parameters, wherein the header includes a reference value, and the method includes: comparing the instruction with a previous instruction to find a plurality of different parameters in the instruction that are different from those in the previous instruction; setting the reference value of the compressed instruction to a default value; setting a target parameter of the compressed instruction to the number of the different parameters; and setting other parameters of the compressed instruction to the different parameters.

Another embodiment of the present invention provides a process compression method for compressing a process, wherein the process includes a jump instruction, and the method includes: dividing the process into a plurality of blocks according to a position of the jump instruction in the process and a destination of the jump instruction; recording a jump relationship between the blocks; performing instruction compression on the blocks; recalculating a jump address of the jump instruction according to the jump relationship; determining a plurality of groups according to the sizes of the blocks and the jump relationship; and determining whether the jump instruction is a first type of jump instruction or a second type of jump instruction according to the relationship between the jump instruction and the groups.

The technical means embodied in the embodiments of the present invention can improve at least one of the shortcomings of the prior art. Therefore, compared with the prior art, the present invention can reduce the space required for the instruction register and/or reduce the number of long jump instructions.

The features, implementation and effects of the present invention are described in detail below with reference to the accompanying drawings.

The technical terms used in the following descriptions refer to the customary terms in this technical field. If this manual explains or defines some of the terms, the interpretation of those terms shall be based on the explanation or definition in this manual.

The disclosure of the present invention includes an instruction compression method, an instruction decompression method, and a process compression method. Since some of the components included in the intelligent processor of the present invention may be known components individually, the details of the known components will be omitted in the following description without affecting the full disclosure and feasibility of the device invention. In addition, part or all of the processes of the instruction compression method, instruction decompression method, and process compression method of the present invention may be in the form of software and/or firmware.

FIG1 is a functional block diagram of an embodiment of an intelligent processing unit (IPU) of the present invention. The intelligent processing unit 100 includes a decoder 110, a direct memory access (DMA) 120, a vector circuit 130, and a convolution circuit 140. The direct memory access 120, the vector circuit 130, and the convolution circuit 140 each include an instruction decompression circuit 122, 132, 142 and a calculation circuit 124, 134, 144. The instruction decompression circuits 122, 132 and 142 are used to decompress instructions (decompression instructions will be described in detail later with reference to FIG. 13), and the calculation circuits 124, 134 and 144 respectively perform the main functions of the direct memory access 120, the vector circuit 130 and the convolution circuit 140. Since the main functions of the direct memory access 120, the vector circuit 130 and the convolution circuit 140 are known to those skilled in the art, they will not be described in detail.

The decoder 110 includes a memory 112 (e.g., a static random access memory (SRAM)), an instruction prefetch circuit 114, an instruction delivery circuit 116, and a jump logic circuit 118. The memory 112 can store instructions to be executed by the intelligent processor 100. The instruction prefetch circuit 114 is used to obtain instructions from the memory 112, and then the instruction delivery circuit 116 delivers the instruction to the corresponding hardware circuit (i.e., direct memory access 120, vector circuit 130, or convolution circuit 140) according to the flag InstFlag of the instruction (see FIG. 7). The jump logic circuit 118 is used to determine whether the instruction is a jump instruction and/or the type of the jump instruction (long jump instruction or short jump instruction). When encountering a jump instruction, the jump logic circuit 118 determines the destination of the jump instruction, and then the instruction pre-fetch circuit 114 obtains the next instruction based on the destination.

In some embodiments, if the difference between the destination of a jump instruction (i.e., the address of the target instruction in the memory 112) and the address of the jump instruction itself in the memory 112 is less than a threshold value (e.g., the size of the instruction buffer of the memory 112), the jump instruction is a short jump instruction; otherwise, the jump instruction is a long jump instruction. In other words, the jump range of the short jump instruction is smaller than the jump range of the long jump instruction. When the decoder 110 processes the long jump instruction, direct memory access 120 is required to obtain more instructions from the external memory of the intelligent processor 100 (e.g., dynamic random access memory (DRAM), not shown), while short jump instructions do not require it; therefore, long jump instructions are more time-consuming and consume system resources than short jump instructions.

FIG. 2 is a flow chart of an embodiment of the process compression method of the present invention. In some embodiments, the steps of FIG. 2 are executed by a development tool (e.g., a general purpose computer) during the development stage of the intelligent processor 100. The process compression method of FIG. 2 can be used to compress a certain process (e.g., an image processing process, a startup process, etc.), and the process includes multiple instructions (e.g., process 310 of FIG. 3 includes 15 instructions such as instructions INST1 to INST15, which are variable-length instructions, and at least one of which is a jump instruction, FIG. 3 will be described in detail below). FIG. 2 includes the following steps.

Step S210: Divide the flow into a plurality of blocks according to the position of the jump instruction in a flow (e.g., the address of the jump instruction in the memory 112) and the destination of the jump instruction (e.g., the address of the destination in the memory 112). More specifically, step S210 scans the instructions in a flow and sets the block boundary BB to divide the flow into a plurality of blocks. The details of step S210 will be described in detail below with reference to FIG. 5. In the example of FIG. 3 , the process 310 is divided into four blocks (blocks BLK1 to BLK4, respectively including instructions INST1 to INST5, instructions INST6 to INST8, instructions INST9 to INST11, and instructions INST12 to INST15, where instructions INST5 and INST11 are jump instructions, and their destinations are instructions INST9 and INST6, respectively).

Step S220: Record the jump relationship between blocks. Please refer to FIG. 3. After step S210 is completed, the jump relationship 320 between blocks can be obtained: the target block of block BLK1 is block BLK3 (because block BLK3 contains the destination of instruction INST5 (i.e., instruction INST9)); the source block of block BLK2 is block BLK3 (because block BLK2 contains the destination of instruction INST11 (i.e., instruction INST6)); and the source block and target block of block BLK3 are block BLK1 and block BLK2 respectively. Please refer to FIG. 4 , which is a schematic diagram of the jump relationship between blocks, corresponding to the jump relationship 320 between blocks in FIG. 3 ; in other words, the jump relationship between blocks can also be represented or recorded in a graphical manner.

Step S230: perform command compression on the blocks one by one to obtain a plurality of compressed blocks. This step will be described in detail below with reference to FIG. 6 .

Step S240: Recalculate the jump address (i.e., the destination address of the jump instruction) according to the jump relationship between the blocks. Because the block has been compressed in step S230, the destination address of the jump instruction after compression is no longer the original address, so the jump address must be recalculated or updated. For example, please refer to Figure 3. Since almost every block becomes smaller after compression, the positions of instruction INST9 and instruction INST6 are changed, so the destination addresses of instruction INST5 and instruction INST11 must be updated or adjusted accordingly.

Step S250: Determine the group according to the block size and jump relationship. The purpose of this step is to divide multiple blocks into multiple groups. The details of step S250 will be explained below in conjunction with Figures 8 and 9.

Step S260: Determine whether the jump instruction is a first type of jump instruction (e.g., a short jump instruction) or a second type of jump instruction (e.g., a long jump instruction) based on the relationship between the jump instruction and the group. By dividing the blocks into a plurality of groups, the present invention can more accurately divide the short jump instructions and the long jump instructions to avoid errors during the execution of the process. Step S260 will be described below in conjunction with FIG. 11.

FIG5 is a detailed diagram of step S210, including steps S510 to S550. Please refer to FIG3 and FIG4 for the following description.

Step S510: Read an instruction.

Step S520: Determine whether the instruction is a jump instruction or a destination of a jump instruction. If not, execute step S510 to read the next instruction; if yes, execute step S530.

Step S530: Set block boundary BB to determine the block. More specifically, if the instruction is a jump instruction, step S530 sets block boundary BB after the instruction (e.g., between instruction INST5 and instruction INST6 and between instruction INST11 and instruction INST12 in FIG. 3 ); if the instruction is the destination of a jump instruction, step S530 sets block boundary BB before the instruction (e.g., between instruction INST5 and instruction INST6 and between instruction INST8 and instruction INST9 in FIG. 3 ).

Step S540: Determine whether there are still instructions to be processed in the process. If yes, execute step S510 to read the next instruction; if not, execute step S550.

Step S550: Set block boundary BB and then end.

Taking FIG. 3 as an example, the method of FIG. 5 divides the process 310 at instruction INST5 (i.e., sets block boundary BB) to generate block BLK1. Similarly, since instruction INST9 and instruction INST11 are destination and jump instructions respectively, block boundary BB will be set before instruction INST9 and after instruction INST11, thereby generating blocks BLK2 and BLK3 respectively. Block boundary BB will also be set at the end of the process 310 to generate block BLK4.

FIG6 is a flow chart of an embodiment of the instruction compression method of the present invention. FIG7 is a schematic diagram of the instruction structure before compression and the instruction structure after compression. As shown in FIG7, instruction INST_k-1 and instruction INST_k are uncompressed instructions (the two are consecutive instructions, and instruction INST_k-1 is before instruction INST_k). Instruction INST_k-1, instruction INST_k, and the compressed instruction INST_k' all include a header HD and at least one parameter (for example, instruction INST_k-1 and instruction INST_k each include n parameters P1~Pn, and the compressed instruction INST_k' includes 1 parameter P1'). In some embodiments, the size of the header HD and each parameter is a word. The header HD includes a flag InstFlag and a reference value HDLen. The flag InstFlag records the hardware circuit to which the instruction belongs. For uncompressed instructions, the reference value HDLen records the number of parameters (for example, the reference value HDLen of instruction INST_k-1 and instruction INST_k is n); for compressed instruction INST_k', the reference value HDLen is a default value (for example, 0). The compression method of Figure 6 is based on blocks and includes the following steps.

Step S610: Read an instruction of a block.

Step S620: Determine whether the instruction is the first instruction of the block. If yes, execute step S610 to read the next instruction of the block; if no, execute step S630. The first instruction of a block is not compressed (because there is no previous instruction as a reference).

Step S630: Compare the instruction with the previous instruction to find out the different parameters in the instruction that are different from the previous instruction. Taking FIG. 7 as an example, since the parameters P2 to Pn of the instruction INST_k-1 are respectively equal to the parameters P2 to Pn of the instruction INST_k, and only the parameter P1 is not equal to the parameter P1', the different parameter found in step S630 is the parameter P1'.

Step S640: Setting the reference value HDLen of the header HD of the compressed command to a default value, in order to mark the compressed command.

Step S650: Set the first parameter of the compressed instruction to the number of different parameters Nd. Taking FIG. 7 as an example, since the number of different parameters Nd between instruction INST_k-1 and instruction INST_k is 1, this step sets the first parameter of the compressed instruction INST_k' to 1 (ie, "Len=1").

Step S660: Set the other parameters of the compressed instruction to the one or more different parameters. In this step, the 2nd to xth (x=1+Nd) parameters of the compressed instruction INST_k' are set to the different parameters obtained in step S630. Taking Figure 7 as an example, since the only different parameter between instruction INST_k-1 and instruction INST_k is parameter P1' (i.e., the number of different parameters Nd is 1), this step sets the second parameter of the compressed instruction INST_k' to parameter P1'. After step S660 is completed, the compressed instruction INST_k' can be obtained.

Step S670: Determine whether there are instructions to be processed in the block. If yes, execute step S610 to read the next instruction in the block; if no, end the method of FIG. 6 (step S680).

FIG8 and FIG9 are details of an embodiment of step S250 of FIG2. Step S250 includes two main steps: first, determine the group according to the block size (FIG8), and then adjust the group according to the jump relationship (FIG9). Please refer to FIG10A and FIG10B for the following description. FIG10A and FIG10B are schematic diagrams of an embodiment of the present invention that divides multiple blocks of the process into multiple groups, corresponding to the process 310 of FIG3. FIG8 includes the following steps.

Step S810: Select a block and update the size of the current group according to the size of the block. The size of a group is the sum of the sizes of all the blocks it contains. This step is to update the size of the current group by adding the size of the block to the size of the current group. Taking Figure 10A as an example, assuming that the current group only contains block BLK1, the selected block is block BLK2, and the size of the current group after update is the sum of the size of block BLK1 and the size of block BLK2.

Step S820: Determine whether the size of the current group is greater than a threshold value. In some embodiments, the threshold value may be the size of the instruction buffer of the memory 112. If the determination result of step S820 is no, then execute step S830; otherwise, execute step S840 and step S850.

Step S830: Set the block as part of the current group. If the judgment result of step S820 is no, it means that adding the selected block to the current group will not make the current group too large (greater than the threshold value), so step S830 sets the block as part of the current group. Continuing with the above example, assuming that the sum of the size of block BLK1 and the size of block BLK2 does not exceed the threshold value SR, then in this step, block BLK2 is set to the same group as block BLK1.

Step S840: Set the block as part of the new group. The judgment result of step S820 is that adding the selected block to the current group will make the current group too large (greater than the threshold value), so step S840 determines the current group (i.e., sets the group boundary GB), and then sets the selected block as part of the new group (at this time, the new group only includes the block). Taking Figure 10A as an example, when the selected block is block BLK3, in step S840, the group boundary GB will be set first (i.e., group GRP1 will be determined), and then group GRP2 will be established (at this time, group GRP2 only includes block BLK3 and has not yet been determined).

Step S850: Set the size of the new group to the size of the block. In the above example, since group GRP2 only contains block BLK3, the size of the new group is equal to the size of block BLK3. It should be noted that the new group becomes the current group in the next round (i.e., when step S810 is executed again).

Step S860: Determine whether there are still blocks to be processed. If yes, execute step S810 to select the next block; if no, execute step S870.

Step S870: Set the group boundary, and then end. Taking FIG. 10A as an example, when the selected block is block BLK4, the judgment of step S860 is no, and then step S870 sets the group boundary GB after block BLK4 to determine group GRP2.

Please refer to FIG10A. After the method of FIG8 is completed, the four blocks of FIG4 are divided into two groups. However, because there is a destination of a jump instruction in the middle of group GRP1 (i.e., between the first block and the last block of a group) (i.e., the destination of instruction INST11 is block BLK2), this will cause a jump error during execution of the process, so the group must be further adjusted according to the method of FIG9. FIG9 includes the following steps.

Step S910: Select a group.

Step S920: Select a block of the group.

Step S930: Determine whether the following conditions are met: the block is not the first block of the group, and the block is the destination of the jump instruction of other groups. Taking Figure 10A as an example, if step S910 and step S920 select group GRP1 and block BLK1 respectively, the judgment result of step S830 is no (because block BLK1 is the first block of group GRP1); if step S910 and step S920 select group GRP1 and block BLK2 respectively, the judgment result of step S830 is yes (because block BLK2 is not the first block of group GRP1 and is the destination of instruction INST11).

Step S940: Determine whether the group still has blocks to be processed. If yes, execute step S920 to select the next block of the group; otherwise, execute step S960.

Step S950: Set the group boundary GB, that is, divide the current group into two groups. Taking Figures 10A and 10B as an example, step S950 sets the group boundary GB before block BLK2 (that is, the destination of instruction INST11), so that the original group GRP1 becomes group GRP1 and group GRP3.

Step S960: Determine whether there are still groups to be processed. If yes, execute step S910 to select the next group; if no, end the method of FIG. 9 (step S970).

FIG. 11 is a detailed diagram of an implementation example of step S260 of FIG. 2 , including the following steps.

Step S1110: Select a jump instruction. Taking FIG. 10B as an example, this step will select instruction INST5 or instruction INST11.

Step S1120: Determine whether the destination of the jump instruction is in the group to which the jump instruction belongs. Taking FIG. 10B as an example, for instruction INST5, since its destination (block BLK3) is not in the group to which instruction INST5 belongs (i.e., group GRP1), the determination result of step S1120 is no. Similarly, for instruction INST11, the determination result of step S1120 is also no.

Step S1130: Set the jump instruction as a long jump instruction.

Step S1140: Set the jump instruction as a short jump instruction.

Step S1150: Determine whether there are still jump instructions. If yes, execute step S1110 to select the next jump instruction; if no, end the method of FIG. 11 (step S1160).

In the example of FIG. 10B , instruction INST5 and instruction INST11 are both inter-group jump instructions (long jump instructions). Please refer to FIG. 12 , which is a schematic diagram of another embodiment of the present invention for dividing groups. As shown in FIG. 12 , group GRP1 includes block BLK1, block BLK2, and block BLK3, while group GRP2 only includes block BLK4. Since the jump instruction INST_n is in group GRP1 and its destination (block BLK3) is also in group GRP1, the jump instruction INST_n is an intra-group jump instruction; therefore, the jump instruction INST_n will be judged as a short jump instruction in the method of FIG. 11 (i.e., step S1120 is judged as yes).

FIG13 is a flow chart of an embodiment of the instruction decompression method of the present invention. FIG13 is executed by the instruction decompression circuit (i.e., the instruction decompression circuit 122, the instruction decompression circuit 132, or the instruction decompression circuit 142) of the hardware circuit (i.e., the direct memory access 120, the vector circuit 130, or the convolution circuit 140) of FIG1, and FIG13 includes the following steps.

Step S1310: Read or receive an instruction, for example, read an instruction from the memory, or receive an instruction distributed by the instruction distribution circuit 116.

Step S1320: Determine whether the reference value HDLen of the header HD of the instruction is a default value. If not (indicating that the instruction is not a compressed instruction), execute step S1330; if yes (indicating that the instruction is a compressed instruction), execute steps S1340 and S1350.

Step S1330: Set the corresponding parameters of the hardware circuit with all the parameters of the instruction (for example, set the temporary value of the register). Please refer to Figure 14, which is a schematic diagram of the hardware circuit of the present invention executing an uncompressed instruction. Assume that before executing the uncompressed instruction INST_y (including five parameters P1', P2', P3', P4' and P5'), the register group REGP of the hardware circuit stores five parameters P1, P2, P3, P4 and P5 (respectively the register values of register REG1, register REG2, register REG3, register REG4 and register REG5), then after the hardware circuit executes the instruction INST_y, the register group REGP stores the five parameters of the instruction INST_y (as shown in the register group REGP on the right side of Figure 14). That is, the purpose of step S1330 is to set the parameters of the hardware circuit with the parameters of instruction INST_y. After the parameters of the hardware circuit are set, the hardware circuit (more specifically, the computing circuit of the hardware circuit) can execute the instruction (step S1360).

Step S1340: Read the first parameter of the instruction to obtain the number of different parameters Nd. Please refer to Figure 15, which is a schematic diagram of the hardware circuit of the present invention executing the compression instruction. The instruction INST_z in Figure 15 is a compressed instruction, and its number of different parameters Nd is 2 (ie, "Len=2").

Step S1350: Set the corresponding parameters of the hardware circuit with the 2nd to Nd+1th parameters of the instruction (for example, set the temporary value of the register). In the example of FIG. 15 , the instruction decompression circuit obtains the parameters P1' and P2' of the compressed instruction INST_z according to the number of different parameters Nd, and then sets the register REG1 and the register REG2 with the parameters P1' and P2' respectively. The purpose of step S1350 is to set the parameters of the hardware circuit with the parameters of the compressed instruction INST_z. After the parameters of the hardware circuit are set, the hardware circuit can execute the instruction (step S1360).

In summary, the present invention reduces the space required for the instruction register (i.e., reduces the size of the memory 112) by compressing the instructions to save costs. In addition, because the instructions are compressed, the present invention can also reduce the number of long jump instructions to improve the execution efficiency of the process.

Although the above-mentioned embodiments are based on variable-length instructions and intelligent processors, this is not a limitation of the present invention. Those skilled in the art can appropriately apply the present invention to other types of instructions and control circuits based on the disclosure of the present invention.

Although the embodiments of the present invention are described above, these embodiments are not intended to limit the present invention. A person having ordinary knowledge in the technical field may modify the technical features of the present invention according to the explicit or implicit contents of the present invention. All such modifications may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be subject to the scope of the patent application defined in this specification.

100: Intelligent processor 110: Decoder 112: Memory 114: Instruction pre-fetch circuit 116: Instruction dispatch circuit 118: Jump logic circuit 120: Direct memory access (DMA) 130: Vector circuit 140: Convolution circuit 122,132,142: Instruction decompression circuit 124,134,144: Calculation circuit 310: Process INST1~INST15,INST_k-1,INST_k,INST_y: Instruction 320: Jump relationship between blocks BB: Block boundary BLK1,BLK2,BLK3,BLK4: Block INST_k',INST_z:Compressed instruction HD:Header InstFlag:Flag HDLen:Reference value P1,P2,P3,P4,P5,Pn,P1',P2',P3',P4',P5':Parameter Nd:Number of different parameters SR:Threshold value GB:Group boundary GRP1,GRP2,GRP3:Group INST_n:Jump instruction REGP:Register group REG1,REG2,REG3,REG4,REG5:Register S210,S220,S230,S240,S250,S260,S510,S520,S530,S540,S550,S610,S620,S630,S640,S650,S660,S670,S680,S810,S820,S830,S840,S850,S860,S870,S910,S920,S930,S940,S950,S960,S970,S1110,S1120,S1130,S1140,S1150,S1160,S1310,S1320,S1330,S1340,S1350,S1360: Steps

FIG1 is a functional block diagram of an embodiment of the intelligent processor of the present invention; FIG2 is a flow chart of an embodiment of the process compression method of the present invention; FIG3 shows a process including multiple instructions and the jump relationship between blocks of the process; FIG4 is a schematic diagram of the jump relationship between blocks; FIG5 is a detail of an embodiment of step S210 of FIG2; FIG6 is a flow chart of an embodiment of the instruction compression method of the present invention; FIG7 is a schematic diagram of the instruction structure before compression and the instruction structure after compression; FIG8 and FIG9 are details of an embodiment of step S250 of FIG2; FIG10A and FIG10B are schematic diagrams of an embodiment of the present invention in which multiple blocks of a process are divided into multiple groups; FIG. 11 is a detail of an embodiment of step S260 of FIG. 2; FIG. 12 is a schematic diagram of another embodiment of the present invention for dividing groups; FIG. 13 is a flow chart of an embodiment of the instruction decompression method of the present invention; FIG. 14 is a schematic diagram of the hardware circuit of the present invention executing an uncompressed instruction; and FIG. 15 is a schematic diagram of the hardware circuit of the present invention executing a compressed instruction.

S210, S220, S230, S240, S250, S260: Steps

Claims (18)

A method for decompressing an instruction is applied to a hardware circuit, the hardware circuit decompresses an instruction and executes the instruction, the instruction includes a header, the header includes a reference value, the method includes: when the reference value of the instruction is a default value, reading a first parameter of the instruction to obtain a number of different parameters; and setting a plurality of corresponding parameters of the hardware circuit with a plurality of second parameters of the instruction, the number of the second parameters being equal to the number of different parameters. The method of claim 1 further includes: when the reference value of the instruction is not the default value, setting the corresponding parameters of the hardware circuit with all the parameters of the instruction. As in the method of claim 1, wherein the hardware circuit comprises a plurality of registers, and the corresponding parameters are the stored values of the registers. The method of claim 1, wherein, when the number of different parameters is N, the second parameters are the second to N+1th parameters of the instruction. A method as claimed in claim 1, wherein the instruction is a variable length instruction. A method for compressing an instruction is provided for compressing an instruction to generate a compressed instruction, the instruction comprising a header and a plurality of parameters, the header comprising a reference value, the method comprising: comparing the instruction with a previous instruction to find a plurality of different parameters in the instruction that are different from the previous instruction; setting the reference value of the compressed instruction to a default value; setting a target parameter of the compressed instruction to the number of the different parameters; and setting other parameters of the compressed instruction to the different parameters. A method as claimed in claim 6, wherein the method is applied to a hardware circuit, the hardware circuit executes a process, the instruction and the previous instruction are consecutive instructions of the process, and the instruction is later than the previous instruction. A method as claimed in claim 7, wherein the process comprises a plurality of blocks, each block comprises a plurality of instructions, the instruction and the previous instruction belong to the same target block among the blocks, and the instruction is not the first instruction of the target block. The method of claim 6, wherein the target parameter is the first parameter of the compressed instruction. A method as claimed in claim 6, wherein the instruction is a variable length instruction. A flow compression method is used to compress a flow, wherein the flow includes a jump instruction, and the method includes: (A) dividing the flow into a plurality of blocks according to a position of the jump instruction in the flow and a destination of the jump instruction; (B) recording a jump relationship between the blocks; (C) performing instruction compression on the blocks; (D) recalculating a jump address of the jump instruction according to the jump relationship; (E) determining a plurality of groups according to the sizes of the blocks and the jump relationship; and (F) determining whether the jump instruction is a first type of jump instruction or a second type of jump instruction according to the relationship between the jump instruction and the groups. The method of claim 11, wherein the process further comprises a plurality of instructions, and the step (A) comprises: reading one of the instructions; and when the read instruction is the jump instruction or the destination of the jump instruction, setting a block boundary. A method as claimed in claim 12, wherein the instructions are a plurality of variable-length instructions. The method of claim 11, wherein step (E) comprises: selecting a block; updating the size of a current group according to the size of the block; setting the block as part of a new group when the size of the current group is greater than a threshold; and setting the block as part of the current group when the size of the current group is not greater than the threshold. The method of claim 14, wherein the step (E) further comprises: when the size of the current group is greater than the threshold value, setting the size of the new group to the size of the block. The method of claim 14, wherein the jump instruction is a first jump instruction, the destination is a first destination, and the step (E) further comprises: selecting a first group; selecting a target block of the first group; and setting a group boundary when the target block is not the first block of the first group and the target block is a second destination of a second jump instruction of a second group. The method of claim 11, wherein the step (F) comprises: selecting the jump instruction; When the destination of the jump instruction is located in a target group to which the jump instruction belongs, setting the jump instruction to a short jump instruction. The method of claim 17, wherein the step (F) further comprises: when the destination of the jump instruction is not within the target group, setting the jump instruction to a long jump instruction; wherein the jump range of the short jump instruction is smaller than the jump range of the long jump instruction.

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