TW202418953A - Semiconductor device including memory structure and method of manufacturing the same - Google Patents

Abstract

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a plurality of capacitors, a first supporting layer, and a plurality of isolation layers. The plurality of capacitors are disposed on the substrate. Each of the capacitors extends along a first direction. Each of the plurality of capacitors includes a first capacitor electrode, a second capacitor electrode, and a capacitor dielectric separating the first capacitor electrode from the second capacitor electrode. The first supporting layer is disposed on the substrate. The first supporting layer extends along a second direction different from the first direction. Each of the plurality of isolation layers extends along the first direction, and the plurality of isolation layers and the first capacitor electrode of the plurality of capacitors have a staggered arrangement. The first capacitor electrode of the plurality of capacitors is spaced apart from the substrate. The capacitor dielectric includes a first surface and a second surface which are disposed on two opposite sides along the first direction. The second surface is exposed by the first capacitor electrode. The first supporting layer is disposed between the first surface and the second surface of the capacitor dielectric.

Description

Semiconductor device including memory structure and method for preparing the same

This application is a division of application No. 112114118 filed on April 14, 2023. Application No. 112114118 claims priority and benefits to U.S. formal application No. 17/973,202 filed on October 25, 2022, the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor device and a method for preparing the same, and more particularly to a semiconductor device including a three-dimensional memory structure and a method for preparing the same.

With the rapid development of the electronics industry, integrated circuits (ICs) have also achieved high performance and miniaturization. The technological progress in materials and design of ICs has produced a new generation of ICs, which are smaller and more complex than the previous generation.

A dynamic random access memory (DRAM) device is a type of random access memory that stores each bit of data in a separate capacitor within an integrated circuit. Typically, DRAM is arranged in a square array of one capacitor and transistor per cell. Vertical transistors have been developed for 4F ² DRAM cells, where F represents the minimum feature width or critical dimension (CD) for photolithography. However, recently, as wordline pitch continues to shrink, DRAM manufacturers face significant challenges in minimizing the memory cell area.

The above “prior art” description is only to provide background technology, and does not admit that the above “prior art” description discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of the present case.

One aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a plurality of capacitors, a first support layer, and a plurality of isolation layers. The plurality of capacitors are disposed on the substrate. Each capacitor extends along a first direction. Each of the plurality of capacitors includes a first capacitor electrode, a second capacitor electrode, and a capacitor dielectric separating the first capacitor electrode from the second capacitor electrode. The first support layer is disposed on the substrate. The first support layer extends along a second direction different from the first direction. Each isolation layer in the plurality of isolations extends along the first direction, and the plurality of isolation layers and the first capacitor electrodes in the plurality of capacitors have a staggered arrangement. The first capacitor electrodes of the plurality of capacitors are spaced apart from the substrate. The capacitor dielectric includes a first surface and a second surface disposed on two opposite sides of the capacitor dielectric along the first direction. The second surface is exposed by the first capacitor electrode. The first supporting layer is disposed between the first surface and the second surface of the capacitor dielectric.

Another aspect of the present disclosure provides a method for preparing a semiconductor device. The method includes: providing a substrate; forming a plurality of isolation layers and a plurality of first conductive layers on the substrate, wherein the plurality of isolation layers and the plurality of first conductive layers are alternately stacked; patterning the plurality of isolation layers and the plurality of first conductive layers to form a plurality of island structures; removing a first portion of the plurality of isolation layers to expose the plurality of first conductive layers; forming a capacitor dielectric to cover the plurality of first conductive layers; and forming a second conductive layer to cover the capacitor dielectric.

Embodiments of the present disclosure provide a semiconductor element. The semiconductor element can define a three-dimensional memory element. For example, the capacitor can be arranged along a plane that is substantially perpendicular to the upper surface of the substrate, which reduces the overall thickness of the semiconductor element. In addition, the semiconductor element may include a support layer. The support layer can be configured to strengthen the intermediate structure during the manufacturing process. The support layer can be configured to increase the length of the first capacitor electrode of the capacitor and prevent the first capacitor electrode from collapsing, which can increase the number of capacitors.

The above has been a fairly broad overview of the technical features and advantages of the present disclosure so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the patent application scope of the present disclosure will be described below. Those with ordinary knowledge in the art to which the present disclosure belongs should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the art to which the present disclosure belongs should also understand that such equivalent constructions cannot deviate from the spirit and scope of the present disclosure as defined by the attached patent application scope.

The embodiments, or examples, of the present disclosure illustrated in the accompanying drawings will now be described in specific language. It should be understood that no limitation of the scope of the present disclosure is intended herein. Any changes or modifications to the described embodiments, and any further application of the principles described herein, should be considered as would be routinely made by one of ordinary skill in the art to which the present disclosure relates. Reference numerals may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment are applicable to another embodiment, even if they share the same reference numeral.

It will be understood that when an element or layer is referred to as being “connected to” or “coupled to” another element or layer, it can be directly connected or coupled to the other element or layer or intervening elements or layers may be present.

It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, or portions, these elements, components, regions, layers, or portions are not limited by these terms. Instead, these terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, the first element, component, region, layer, or portion discussed below may be referred to as the second element, component, region, layer, or portion without departing from the teachings of the present inventive concept.

The terms used herein are used only to describe specific embodiments and are not intended to limit the concepts of the present invention. As used herein, the singular forms "a", "an" and "the" also include the plural forms unless the context clearly indicates otherwise. It should be further understood that the terms "comprise" and "include", when used in this specification, indicate the presence of the features, integers, steps, operations, elements or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components or groups thereof.

It should be noted that the term "approximately" modifies the amount of an ingredient, component, or reactant employed to refer to variations in the numerical amount that may occur, for example, through typical measurements and liquid handling routines used to make concentrates or solutions. In addition, variations may occur due to inadvertent errors in measurement procedures, differences in the manufacture, source, or purity of the ingredients used to make the composition or perform the method, etc. In one aspect, the term "approximately" means within 10% of the reported value. In another aspect, the term "approximately" means within 5% of the reported value. However, in another aspect, the term "approximately" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

Referring to FIG. 1A , FIG. 1A is a perspective view illustrating a semiconductor device 100 a of some embodiments of the present disclosure. The semiconductor device 100 a may be included in a memory device. The memory device may include, for example, a dynamic random access memory (DRAM) device, a one-time programming (OTP) memory device, a static random access memory (SRAM) device, or other suitable memory devices.

As shown in FIG. 1A , the semiconductor device 100 a may include a substrate 110 , isolation layers 120 - 1 , 120 - 2 , 120 - 3 , 120 - 4 , and 120 - 5 , conductive layers 130 - 1 , 130 - 2 , 130 - 3 , 130 - 4 , and 130 - 5 , and support layers 140 - 1 and 140 - 2 , and capacitors 150 - 1 , 150 - 2 , 150 - 3 , 150 - 4 , 150 - 5 , 150 - 6 , 150 - 7 , 150 - 8 , 150 - 9 , and 150 - 10 .

The substrate 110 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, or the like. The substrate 110 may include an elementary semiconductor, including silicon or germanium in single crystal form, polycrystalline form, or amorphous form; a composite semiconductor material, including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium sulfide; an alloy semiconductor material, including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or a combination thereof. In some embodiments, the alloy semiconductor substrate may include a SiGe alloy having a gradient Ge feature, wherein the composition of Si and Ge changes from a ratio at one position of the gradient SiGe feature to a ratio at another position. In another embodiment, the SiGe alloy is formed on a silicon substrate. In some embodiments, the SiGe alloy may be mechanically stretched by another material in contact with the SiGe alloy. In some embodiments, the substrate 110 may have a multi-layer structure, or the substrate 110 may include a multi-layer compound semiconductor structure. The substrate 110 may have a surface 110s1 (or an upper surface). The normal direction of the surface 110s1 may be substantially parallel to the Z direction.

In some embodiments, the isolation layer 120-1 may be disposed on the surface 110s1 of the substrate 110. In some embodiments, the isolation layer 120-1 may be in contact with the substrate 110. The isolation layer 120-2 may be disposed on the isolation layer 120-1. In some embodiments, the isolation layer 120-2 may be separated from the isolation layer 120-1 by the conductive layer 130-1. The isolation layer 120-3 may be disposed on the isolation layer 120-2. In some embodiments, the isolation layer 120-3 may be separated from the isolation layer 120-2 by the conductive layer 130-2. The isolation layer 120-4 may be disposed on the isolation layer 120-3. In some embodiments, the isolation layer 120-4 may be separated from the isolation layer 120-3 by the conductive layer 130-3. The isolation layer 120-5 may be disposed on the isolation layer 120-4. In some embodiments, the isolation layer 120-5 may be separated from the isolation layer 120-4 by the conductive layer 130-4. In some embodiments, the isolation layers 120-1, 120-2, 120-3, 120-4, and 120-5 may be stacked along the Z direction. In some embodiments, the isolation layers 120-1, 120-2, 120-3, 120-4 and 120-5 may be located at different levels. Each isolation layer 120-1, 120-2, 120-3, 120-4 and 120-5 may include a dielectric material such as silicon oxide ( _SiOx ), silicon _nitride ( _SixNy ), silicon oxynitride (SiON) or other suitable materials.

In some embodiments, the conductive layer 130-1 may be disposed on the surface 110s1 of the substrate 110. In some embodiments, the conductive layer 130-1 may be disposed on the isolation layer 120-1. In some embodiments, the conductive layer 130-1 may be in contact with the isolation layer 120-1. In some embodiments, the conductive layer 130-2 may be disposed on the conductive layer 130-1. In some embodiments, the conductive layer 130-2 may be disposed on the isolation layer 120-2. In some embodiments, the conductive layer 130-3 may be disposed on the conductive layer 130-2. In some embodiments, the conductive layer 130-3 may be disposed on the isolation layer 120-3. In some embodiments, the conductive layer 130-4 may be disposed on the conductive layer 130-3. In some embodiments, the conductive layer 130-4 may be disposed on the isolation layer 120-4. In some embodiments, the conductive layer 130-5 may be disposed on the isolation layer 120-5. In some embodiments, the conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5 may be stacked along the Z direction. In some embodiments, each of the conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5 may extend along the X direction. In some embodiments, the conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5 may be located at different horizontal levels. In some embodiments, each of the conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5 may include a conductive material such as tungsten (W), copper (Cu), aluminum (Al), tantalum (Ta), molybdenum (Mo), tantalum nitride (TaN), titanium, titanium nitride (TiN), etc., and/or combinations thereof.

In some embodiments, each of the support layers 140-1 and 140-2 can extend along the Y direction. In some embodiments, each of the support layers 140-1 and 140-2 can be configured to support the capacitors 150-1, 150-2, 150-3, 150-4, 150-5, 150-6, 150-7, 150-8, 150-9, and 150-10. In some embodiments, each of the support layers 140-1 and 140-2 can help increase the length of the capacitors 150-1, 150-2, 150-3, 150-4, 150-5, 150-6, 150-7, 150-8, 150-9, and 150-10 along the X direction. In some embodiments, the support layers 140-1 and 140-2 may be arranged along the X direction. In some embodiments, each of the support layers 140-1 and 140-2 may extend continuously through, for example, the capacitors 150-1 and 150-6. In some embodiments, the support layer 140-1 may be separated from the support layer 140-2 by the capacitor dielectric 152. In some embodiments, the support layer 140-1 may be separated from the support layer 140-2 by the conductive layer 154. In some embodiments, the support layer 140-1 may be disposed, for example, between the conductive layers 130-2 and 130-3. In some embodiments, the material of the support layers 140-1 and 140-2 may be different from the material of the isolation layers 120-1, 120-2, 120-3, 120-4, and 120-5. In some embodiments, each of the support layers 140-1 and 140-2 may include silicon nitride (Si _x N _y ), silicon oxide (SiO _x ), silicon oxynitride (SiON), or other suitable materials.

In some embodiments, capacitors 150-1, 150-2, 150-3, 150-4, 150-5, 150-6, 150-7, 150-8, 150-9, and 150-10 may be arranged along the YZ plane. In some embodiments, capacitors 150-1, 150-2, 150-3, 150-4, and 150-5 may be stacked along the Z direction. In some embodiments, capacitors 150-1, 150-2, 150-3, 150-4, and 150-5 may be located at different horizontal levels. In some embodiments, capacitors 150-1, 150-2, 150-3, 150-4, 150-5, 150-6, 150-7, 150-8, 150-9, and 150-10 may extend along the X direction. In some embodiments, capacitor 150-1 may be disposed on substrate 110. In some embodiments, capacitor 150-2 may be disposed on capacitor 150-1. In some embodiments, capacitor 150-3 may be disposed on capacitor 150-2. In some embodiments, capacitor 150-4 may be disposed on capacitor 150-3. In some embodiments, capacitor 150-5 may be disposed on capacitor 150-4. In some embodiments, capacitors 150-1 and 150-6 may be disposed along the Y direction.

In some embodiments, each of capacitors 150-1, 150-2, 150-3, 150-4, 150-5, 150-6, 150-7, 150-8, 150-9, and 150-10 may include a first capacitor electrode, a capacitor dielectric, and a second capacitor electrode. In some embodiments, each of conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5 may serve as a first capacitor electrode. In some embodiments, capacitor dielectric 152 may serve as a capacitor dielectric. In some embodiments, conductive layer 154 may serve as a second capacitor electrode.

In some embodiments, the capacitor dielectric 152 may surround or enclose the conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5. In some embodiments, the capacitor dielectric 152 may have a ring-shaped profile in a cross-sectional view. In some embodiments, the capacitor dielectric 152 may contact the support layers 140-1 and 140-2. In some embodiments, the capacitor dielectric 152 may extend along the X direction. The capacitor dielectric 152 may include a high-k material. The high-k material may include ferrite (HfO ₂ ), zirconium (ZrO ₂ ), vanadium (La ₂ O ₃ ), yttrium (Y ₂ O ₃ ), aluminum (Al ₂ O ₃ ), titanium (TiO ₂ ) or other applicable materials. Other suitable materials are also within the scope of this disclosure.

In some embodiments, the conductive layer 154 may surround or enclose the capacitor dielectric 152. In some embodiments, the conductive layer 154 may surround or enclose the conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5. In some embodiments, the conductive layer 154 may be separated from the conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5 by the capacitor dielectric 152. In some embodiments, the conductive layer 154 may have a ring-shaped profile in a cross-sectional view. In some embodiments, the conductive layer 154 may extend along the X direction. In some embodiments, the material of the conductive layer 154 may be the same as the material of the conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5. In some embodiments, the conductive layer 154 may include a conductive material such as tungsten (W), copper (Cu), aluminum (Al), tantalum (Ta), molybdenum (Mo), tantalum nitride (TaN), titanium, titanium nitride (TiN), etc., and/or combinations thereof.

1B , which is a cross-sectional view illustrating a semiconductor device 100a along line AA′ in FIG. 1A according to some embodiments of the present disclosure.

In some embodiments, isolation layer 120-1, conductive layer 130-1, isolation layer 120-2, conductive layer 130-2, isolation layer 120-3, conductive layer 130-3, isolation layer 120-4, conductive layer 130-4, isolation layer 120-5 and conductive layer 130-5 may be located at horizontal layers E1, E2, E3, E4, E5, E6, E7, E8, E9 and E10, respectively.

The capacitor dielectric 152 may have a surface 152s1 and a surface 152s2. The surfaces 152s1 and 152s2 may be located on two opposite sides of the capacitor dielectric 152 along the X direction. The surface 152s1 of the capacitor dielectric may be exposed from the conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5. The surface 152s1 of the capacitor dielectric may be exposed from the conductive layer 154. In some embodiments, the support layer 140-1 may be disposed between the surfaces 152s1 and 152s2 of the capacitor dielectric 152. In some embodiments, the support layer 140-2 may be disposed between the surfaces 152s1 and 152s2 of the capacitor dielectric 152. In some embodiments, the support layer 140 - 1 may be disposed between two opposite side surfaces of the conductive layer 154 .

In some embodiments, each of the isolation layers 120-1, 120-2, 120-3, 120-4, and 120-5 may be in contact with the capacitor dielectric 152. In some embodiments, each of the isolation layers 120-1, 120-2, 120-3, 120-4, and 120-5 may be separated from the conductive layer 154 by the capacitor dielectric 152.

In some embodiments, each of the conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5 may have a portion 132 and a portion 134. In some embodiments, the portions 132 and 134 are monolithic. In some embodiments, the portion 132 may serve as a first capacitor electrode of the capacitors 150-1, 150-2, 150-3, 150-4, 150-5, 150-6, 150-7, 150-8, 150-9, and/or 150-10. In some embodiments, portion 134 may serve as an interconnect between capacitor 150-1, 150-2, 150-3, 150-4, 150-5, 150-6, 150-7, 150-8, 150-9, or 150-10 and a transistor (not shown in this figure).

1C , a semiconductor device 100a along line BB′ in FIG. 1A is illustrated according to some embodiments of the present disclosure.

In some embodiments, each of the conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5 may have a rectangular outline or other suitable outline. In some embodiments, the capacitor dielectric 152 may completely surround or enclose the conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5. In some embodiments, the conductive layer 154 may completely surround or enclose the capacitor dielectric 152.

1D , which is a cross-sectional view illustrating a semiconductor device along line CC′ in FIG. 1A according to some embodiments of the present disclosure.

In some embodiments, the support layer 140-2 (or 140-1) may contact the conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5. In some embodiments, the support layer 140-2 (or 140-1) may be connected to the conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5. In some embodiments, the support layer 140-2 (or 140-1) may contact the surface 110s1 of the substrate 110.

1E is a cross-sectional view illustrating a semiconductor device along line DD' in FIG. 1A according to some embodiments of the present disclosure.

In some embodiments, the semiconductor device 100a may include a plurality of island structures 180. Each island structure 180 may include isolation layers 120-1, 120-2, 120-3, 120-4, and 120-5, and conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5. Each island structure 180 may extend along the X direction. In some embodiments, portions 134 of each conductive layer 130-1, 130-2, 130-3, 130-4, and 130-5 may be separated from each other by the isolation layers 120-1, 120-2, 120-3, 120-4, and 120-5.

Embodiments of the present disclosure provide a semiconductor element. The semiconductor element can define a three-dimensional memory element. For example, the capacitor can be arranged along a plane that is substantially perpendicular to the upper surface of the substrate, which reduces the overall thickness of the semiconductor element. In addition, the semiconductor element may include a support layer. The support layer can be configured to strengthen the intermediate structure during the manufacturing process. The support layer can be configured to increase the length of the first capacitor electrode of the capacitor and prevent the first capacitor electrode from collapsing, which can increase the number of capacitors.

FIG. 2 is a cross-sectional view illustrating a semiconductor device 100 b according to some embodiments of the present disclosure.

The semiconductor device 100b may further include a transistor 160. In some embodiments, the transistor 160 may include a word line 161, a gate dielectric 162, a channel layer 163-1, 163-2, 163-3, 163-4, or 163-5, and a bit line 164-1, 164-2, 164-3, 164-4, or 164-5.

In some embodiments, the word line 161 may be disposed on the substrate 110. In some embodiments, the word line 161 may be disposed, for example, between the bit line 164-1 and the capacitor 150-1. In some embodiments, the word line 161 may penetrate a portion of the substrate 110. In some embodiments, the word line 161 may extend along the Z direction. In some embodiments, the word line 161 may penetrate the isolation layers 120-1, 120-2, 120-3, 120-4, and 120-5. In some embodiments, the word line 161 may include a conductive material, such as tungsten (W), copper (Cu), aluminum (Al), tantalum (Ta), molybdenum (Mo), tantalum nitride (TaN), titanium, titanium nitride (TiN), etc., and/or combinations thereof.

In some embodiments, the gate dielectric 162 may surround the word line 161. In some embodiments, the gate dielectric 162 may separate the word line 161 from the conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5. In some embodiments, the gate dielectric 162 may separate the word line 161 from the channel layers 163-1, 163-2, 163-3, 163-4, or 163-5. In some embodiments, the gate dielectric 162 may penetrate the conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5. In some embodiments, the gate dielectric 162 may penetrate the isolation layers 120-1, 120-2, 120-3, 120-4, and 120-5. In some embodiments, the gate dielectric 162 may include silicon oxide ( _SiOx ), silicon nitride (Si _x N _y ), silicon oxynitride (SiON), or a combination thereof. In some embodiments, the gate dielectric 162 may include a dielectric material, such as a high-k dielectric material. The high-k material may have a dielectric constant (k value) greater than 4. The high-k material may include ferrite (HfO ₂ ), zirconium oxide (ZrO ₂ ), lumen oxide (La ₂ O ₃ ), yttrium oxide (Y ₂ O ₃ ), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ), or other applicable materials. Other suitable materials are also within the scope of this disclosure.

In some embodiments, each of the channel layers 163-1, 163-2, 163-3, 163-4, or 163-5 may extend in the X direction. In some embodiments, each of the channel layers 163-1, 163-2, 163-3, 163-4, or 163-5 may be located on the same horizontal plane as the conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5, respectively. In some embodiments, the material of the channel layers 163-1, 163-2, 163-3, 163-4, or 163-5 may be different from the material of the conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5. In some embodiments, each of the channel layers 163-1, 163-2, 163-3, 163-4, or 163-5 may include a semiconductor material, such as silicon (Si), germanium (Ge), tin (Sn), antimony (Sb) in single crystal form, polycrystalline form, or amorphous form. In some embodiments, each of the channel layers 163-1, 163-2, 163-3, 163-4, or 163-5 may include a doping region (not shown). The doping region may have an n-type or p-type dopant doped therein. In some embodiments, the p-type dopant includes boron (B), other group III elements, or any combination thereof. In some embodiments, the n-type dopant includes arsenic (As), phosphorus (P), other group V elements, or any combination thereof.

In other embodiments, each of the channel layers 163-1, 163-2, 163-3, 163-4, or 163-5 may include a metal oxide. The metal oxide may include, but is not limited to: indium oxide; tin oxide; zinc oxide; a two-component metal oxide, such as In-Zn-based oxide, Sn-Zn-based oxide, Al-Zn-based oxide, Zn-Mg-based oxide, Sn-Mg-based oxide, In-Mg-based oxide, or In-Ga-based oxide; a three-component metal oxide, such as In-Ga-Zn-based oxide (also denoted as IGZO), In-Al-Zn-based oxide, In-S-based oxide (also denoted as ITO), In-Sn-Zn-based oxide, Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn-based oxide, In-La-Zn-based oxide, In-Co-Zn-based oxide, In-Pr- Zn-based oxide, In-Nd-Zn-based oxide, In-Sm-Zn-based oxide, In-Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide or In-Lu-Zn-based oxide; and a four-component metal oxide, such as In-Sn-Ga-Zn-based oxide, In-Hf-Ga-Zn-based oxide, In-Al-Ga-Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide or In-Hf-Al-Zn-based oxide, but the present disclosure is not limited to this.

In some embodiments, each of the bit lines 164-1, 164-2, 164-3, 164-4, and 164-5 may be disposed on the isolation layer 120-5. In some embodiments, each of the bit lines 164-1, 164-2, 164-3, 164-4, and 164-5 may extend along the Y direction. In some embodiments, each of the bit lines 164-1, 164-2, 164-3, 164-4, and 164-5 may be arranged along the X direction. In some embodiments, each of the bit lines 164-1, 164-2, 164-3, 164-4, and 164-5 may include a conductive material such as tungsten (W), copper (Cu), aluminum (Al), tungsten (Ta), molybdenum (Mo), tantalum nitride (TaN), titanium, titanium nitride (TiN), etc., and/or combinations thereof.

The semiconductor device 100b may further include conductive plugs 165-1, 165-2, 165-3 and 165-4. The conductive plugs 165-1, 165-2, 165-3 and 165-4 may include conductive materials such as tungsten (W), copper (Cu), aluminum (Al), tantalum (Ta), molybdenum (Mo), tantalum nitride (TaN), titanium, titanium nitride (TiN), etc., and/or combinations thereof.

In some embodiments, bit line 164-1 may be electrically connected to channel layer 163-1 through conductive plug 165-1. In some embodiments, bit line 164-2 may be electrically connected to channel layer 163-2 through conductive plug 165-2. In some embodiments, bit line 164-3 may be electrically connected to channel layer 163-3 through conductive plug 165-3. In some embodiments, bit line 164-4 may be electrically connected to channel layer 163-4 through conductive plug 165-4. Each conductive plug 165-1, 165-2, 165-3, and 165-4 may have a different height along the Z direction. For example, conductive plug 165-1 may have a different height than conductive plug 165-2 along the Z direction.

In some embodiments, transistor 160 may be electrically connected to capacitors 150-1, 150-2, 150-3, 150-4, and/or 150-5. In some embodiments, transistor 160 may be electrically connected to capacitors 150-1, 150-2, 150-3, 150-4, and/or 150-5 through portions 134 of conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5. In some embodiments, interconnect wires (e.g., 134) may be disposed between transistor 160 and capacitors 150-1, 150-2, 150-3, 150-4, and 150-5. In some embodiments, transistor 160 and capacitors 150-1, 150-2, 150-3, 150-4, and 150-5 are arranged horizontally. For example, capacitors 150-1, 150-2, 150-3, 150-4, and 150-5 and word lines occupy substantially the same height, from horizontal plane E1 to E10.

Embodiments of the present disclosure provide a semiconductor device. The semiconductor device can define a three-dimensional memory device. For example, capacitors and word lines can be located within a predetermined height, which reduces the overall thickness of the semiconductor device. In addition, the semiconductor device can include a support layer. The support layer can be configured to strengthen the intermediate structure during the manufacturing process. The support layer can be configured to increase the length of the first capacitor electrode of the capacitor and prevent the first capacitor electrode from collapsing, which can increase the number of capacitors.

FIG. 3 is a flow chart illustrating a method 200 for preparing a semiconductor device according to some embodiments of the present disclosure.

The preparation method 200 begins with operation 202, where a substrate is provided. The substrate may have an array region and an interconnect region. A plurality of isolation layers and a first conductive layer may be formed on the substrate. The plurality of isolation layers and the plurality of first conductive layers are alternately stacked.

The fabrication method 200 continues with operation 204, where a plurality of isolation layers and a plurality of first conductive layers are patterned to form a plurality of island structures.

The fabrication method 200 continues with operation 206 where a portion of the isolation layer over the array region is removed to form a first opening. A support layer may be formed to fill the first opening.

The fabrication method 200 continues with operation 208 where the remaining isolation layer on the array region is removed to expose the first conductive layer.

The fabrication method 200 continues with operation 210 where a capacitor dielectric and a second conductive layer are formed to surround the first conductive layer, thereby defining a plurality of capacitors.

The fabrication method 200 continues with operation 212 where the second conductive layer over the capacitor dielectric and interconnect regions is removed to expose the first conductive layer.

The preparation method 200 is merely an example and is not intended to limit the content of the present disclosure beyond the scope explicitly described in the scope of the application. Additional operations may be provided before, during, or after each operation of the preparation method 200, and some of the operations described may be replaced, eliminated, or reordered for other embodiments of the preparation method. In some embodiments, the preparation method 200 may include further operations not depicted in FIG. 3. In some embodiments, the preparation method 200 may include one or more operations described in FIG. 3.

FIG. 4A to FIG. 20A illustrate the preparation method of the semiconductor element 00a of some embodiments of the present disclosure. FIG. 4B to FIG. 20B are cross-sectional views along the AA' line of FIG. 4A to FIG. 20A, respectively. FIG. 4C to FIG. 20C are cross-sectional views along the BB' line of FIG. 4A to FIG. 20A, respectively. FIG. 4D to FIG. 20D are cross-sectional views along the CC' line of FIG. 4A to FIG. 20A, respectively. FIG. 4E to FIG. 20E are cross-sectional views along the DD' line of FIG. 4A to FIG. 20A, respectively.

4A, 4B, 4C, 4D, and 4E, a substrate 110 may be provided. In some embodiments, isolation layers 120-1, 120-2, 120-3, 120-4, and 120-5, and conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5 may be alternately formed on the substrate 110. The manufacturing technology of each isolation layer 120-1, 120-2, 120-3, 120-4 and 120-5, and the conductive layer 130-1, 130-2, 130-3, 130-4 and 130-5 may include chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD) or other suitable processes. In some embodiments, the isolation layers 120-1, 120-2, 120-3, 120-4 and 120-5 may include a dielectric material, such as silicon oxide. In some embodiments, the conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5 may include a conductive material such as titanium nitride or other suitable materials.

5A, 5B, 5C, 5D, and 5E, a mask layer 171 may be formed on the conductive layer 130-5. The mask layer 171 may include a negative tone photoresist (or negative photoresist) or a positive tone photoresist (or positive photoresist). The mask layer 171 may have an opening 171r exposed to the conductive layer 130-5. In some embodiments, the opening 171r may extend along the X direction.

6A, 6B, 6C, 6D, and 6E, the isolation layers 120-1, 120-2, 120-3, 120-4, and 120-5, and the conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5 may be patterned to form an island structure 180. A portion of the isolation layers 120-1, 120-2, 120-3, 120-4, and 120-5 may be removed. The mask layer 171 may be removed. A portion of the conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5 may be removed. Each island structure 180 may include isolation layers 120-1, 120-2, 120-3, 120-4, and 120-5, and conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5. Each island structure 180 may extend along the X direction. A first capacitor electrode of the capacitor may be defined at this stage.

7A, 7B, 7C, 7D, and 7E, a mask layer 172 may be formed to cover the island structure 180. The mask layer 172 may include a negative tone photoresist or a positive tone photoresist. The mask layer 172 may include an opening 172r that exposes the island structure 180. The opening 172r may extend along the Y direction. In some embodiments, portions 121 of the isolation layers 120-1, 120-2, 120-3, 120-4, and 120-5 may be exposed by the opening 172r.

8A, 8B, 8C, 8D, and 8E, the isolation layers 120-1, 120-2, 120-3, 120-4, and 120-5 exposed by the opening 172r may be removed. Portions 121 of the isolation layers 120-1, 120-2, 120-3, 120-4, and 120-5 may be removed. A plurality of openings 173r may be formed.

9A, 9B, 9C, 9D, and 9E, a dielectric layer 141 may be formed to fill the opening 173r. Support layers 140-1 and 140-2 may be formed. The support layer 140-1 may extend along the Y direction. In some embodiments, the support layer 140-1 may surround or enclose the conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5. In some embodiments, the support layers 140-1 and 140-2 may be inserted between, for example, two opposing side surfaces (not noted in the figure) of the isolation layers 120-1, 120-2, 120-3, 120-4, and 120-5. In some embodiments, the support layers 140-1 and 140-2 may be inserted, for example, between two opposing side surfaces (not noted in the figure) of the conductive layer 130-1, 130-2, 130-3, 130-4, or 130-5. In some embodiments, the support layers 140-1 and 140-2 may conform the intermediate structure in FIGS. 10A to 20A to one frame. In some embodiments, the dielectric layer 141 may include a dielectric material, such as silicon nitride. The material of the dielectric layer 141 may be different from the material of the isolation layers 120-1, 120-2, 120-3, 120-4, and 120-5. The manufacturing technology of the dielectric layer 141 may include CVD, PVD, ALD, LPCVD, PECVD, or other suitable processes.

10A, 10B, 10C, 10D, and 10E, a portion of the dielectric layer 141 may be removed to expose the dielectric layer. The dielectric layer 141 on the upper surface 180s1 (or an upper surface) of the island structure 180 may be removed. The dielectric layer 141 on the conductive layer 130-5 may be removed. The dielectric layer 141 on the mask layer 172 may be removed. Removal of the dielectric layer 141 may include, for example, a wet etching technique.

11A, 11B, 11C, 11D, and 11E, the mask layer 172 may be removed and the conductive layer 130-5 may be exposed.

12A, 12B, 12C, 12D, and 12E, a mask layer 173 may be formed to cover the isolation layers 120-1, 120-2, 120-3, 120-4, and 120-5, and a portion 122 of the conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5. The mask layer 173 may include a negative tone photoresist or a positive tone photoresist. In some embodiments, the mask layer 173 may be configured to define an array region 102 and an interconnect region 104 of a semiconductor element. The array region 102 may be a region on which a capacitor is formed. The interconnect region 104 may be a region on which an interconnection wire is formed. In some embodiments, the isolation layers 120-1, 120-2, 120-3, 120-4, and 120-5, and the conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5 of the array region 102 may be exposed from the mask layer 173. In some embodiments, the isolation layers 120-1, 120-2, 120-3, 120-4, and 120-5, and the conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5 of the interconnect region 104 may be covered by the mask layer 173.

13A, 13B, 13C, 13D, and 13E, an etching technique may be performed. The isolation layers 120-1, 120-2, 120-3, 120-4, and 120-5 exposed from the mask layer 173 may be removed. Portions 122 of the isolation layers 120-1, 120-2, 120-3, 120-4, and 120-5 may be removed. The conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5 may be exposed. The removal of the isolation layers 120-1, 120-2, 120-3, 120-4, and 120-5 may include, for example, a wet etching technique. The opening 120r may be defined. The supporting layers 140-1 and 140-2 may be configured to support the conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5, thereby preventing the conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5 from collapsing.

14A, 14B, 14C, 14D, and 14E, the mask layer 173 may be removed.

15A, 15B, 15C, 15D, and 15E, a capacitor dielectric 152 may be formed within the opening 120r. In some embodiments, the capacitor dielectric 152 may be conformally formed on the conductive layers 130-1, 130-2, 130-3, 130-4, and 130-5. In some embodiments, the capacitor dielectric 152 may be formed on the array region 102. In some embodiments, the capacitor dielectric 152 may be formed on the interconnect region 104. The fabrication techniques of the capacitor dielectric 152 may include, for example, ALD, CVD, PVD, LPCVD, PECVD, or other suitable processes. In some embodiments, the capacitor dielectric 152 may include a high-k material.

16A, 16B, 16C, 16D, and 16E, a conductive layer 154 may be conformally formed on the capacitor dielectric 152. Capacitors 150-1, 150-2, 150-3, 150-4, 150-5, 150-6, 150-7, 150-8, 150-9, and 150-10 may be formed. In some embodiments, the conductive layer 154 may be formed on the array region 102. In some embodiments, the conductive layer 154 may be formed on the interconnect region 104. The fabrication techniques of the conductive layer 154 may include, for example, ALD, CVD, PVD, LPCVD, PECVD, or other suitable processes. In some embodiments, the conductive layer 154 may include a conductive material such as titanium nitride or other suitable materials.

17A, 17B, 17C, 17D, and 17E, a mask layer 174 may be formed to cover portions of the isolation layers 120-1, 120-2, 120-3, 120-4, and 120-5. Portions of the isolation layers 120-1, 120-2, 120-3, 120-4, and 120-5 may correspond to the interconnection region 104. The mask layer 174 may include a negative tone photoresist or a positive tone photoresist. In some embodiments, the mask layer 174 may cover the array region 102. In some embodiments, the mask layer 174 may expose the interconnection region 104. The conductive layer 154 in the interconnection region 104 may be exposed by the mask layer 174.

18A, 18B, 18C, 18D, and 18E, the conductive layer 154 on the interconnect region 104 may be removed. The conductive layer 154 on the portion 123 of the isolation layers 120-1, 120-2, 120-3, 120-4, and 120-5 may be removed. The removal of the conductive layer 154 may include, for example, a wet etching technique.

19A, 19B, 19C, 19D, and 19E, the capacitor dielectric 152 on the interconnect region 104 may be removed. The capacitor dielectric 152 on the portion 123 of the isolation layers 120-1, 120-2, 120-3, 120-4, and 120-5 may be removed. The removal of the capacitor dielectric 152 may include, for example, a wet etching technique.

20A, 20B, 20C, 20D, and 20E, the mask layer 174 may be removed, and the conductive layer on the interconnects 104 of 130-1, 130-2, 130-3, 130-4, and 130-5 may be exposed, thereby manufacturing the semiconductor device 100a.

One aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a plurality of capacitors, a first support layer, and a plurality of isolation layers. The plurality of capacitors are disposed on the substrate. Each capacitor extends along a first direction. Each of the plurality of capacitors includes a first capacitor electrode, a second capacitor electrode, and a capacitor dielectric separating the first capacitor electrode from the second capacitor electrode. The first support layer is disposed on the substrate. The first support layer extends along a second direction different from the first direction. Each isolation layer in the plurality of isolations extends along the first direction, and the plurality of isolation layers and the first capacitor electrodes in the plurality of capacitors have a staggered arrangement. The first capacitor electrodes of the plurality of capacitors are spaced apart from the substrate. The capacitor dielectric includes a first surface and a second surface disposed on two opposite sides of the capacitor dielectric along the first direction. The second surface is exposed by the first capacitor electrode. The first supporting layer is disposed between the first surface and the second surface of the capacitor dielectric.

Another aspect of the present disclosure provides a method for preparing a semiconductor device. The method includes: providing a substrate; forming a plurality of isolation layers and a plurality of first conductive layers on the substrate, wherein the plurality of isolation layers and the plurality of first conductive layers are alternately stacked; patterning the plurality of isolation layers and the plurality of first conductive layers to form a plurality of island structures; removing a first portion of the plurality of isolation layers to expose the plurality of first conductive layers; forming a capacitor dielectric to cover the plurality of first conductive layers; and forming a second conductive layer to cover the capacitor dielectric.

Embodiments of the present disclosure provide a semiconductor element. The semiconductor element can define a three-dimensional memory element. For example, the capacitor can be arranged along a plane that is substantially perpendicular to the upper surface of the substrate, which reduces the overall thickness of the semiconductor element. In addition, the semiconductor element may include a support layer. The support layer can be configured to strengthen the intermediate structure during the manufacturing process. The support layer can be configured to increase the length of the first capacitor electrode of the capacitor and prevent the first capacitor electrode from collapsing, which can increase the number of capacitors.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements can be made without departing from the spirit and scope of the present disclosure defined by the scope of the patent application. For example, many of the above processes can be implemented in different ways, and other processes or combinations thereof can be used to replace many of the above processes.

Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, manufactures, material compositions, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of this disclosure that existing or future developed processes, machines, manufactures, material compositions, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Accordingly, such processes, machines, manufactures, material compositions, means, methods, or steps are included in the scope of the patent application of this application.

100a: semiconductor element 100b: semiconductor element 102: array region 110: substrate 110s1: surface 120-1: isolation layer 120-2: isolation layer 120-3: isolation layer 120-4: isolation layer 120-5: isolation layer 120r: opening 104: interconnection region 121: part 122: part 123: part 130-1: conductive layer 130-2: conductive layer 130-3: conductive layer 130-4: conductive layer 130-5: conductive layer 132: part 134: part 140-1: Support layer 140-2: Support layer 141: Dielectric layer 150-1: Capacitor 150-2: Capacitor 150-3: Capacitor 150-4: Capacitor 150-5: Capacitor 150-6: Capacitor 150-7: Capacitor 150-8: Capacitor 150-9: Capacitor 150-10: Capacitor 152: Capacitor dielectric 152s1: Surface 152s2: Surface 154: Conductive layer 160: Transistor 161: Word line 162: Gate dielectric 163-1: Channel layer 163-2: Channel layer 163-3: Channel layer 163-4: channel layer 163-5: channel layer 164-1: bit line 164-2: bit line 164-3: bit line 164-4: bit line 164-5: bit line 165-1: conductive plug 165-2: conductive plug 165-3: conductive plug 165-4: conductive plug 165-5: conductive plug 171: mask layer 171r: opening 172: mask layer 172r: opening 173: mask layer 173r: opening 174: mask layer 180: island structure 180s1: upper surface 200: preparation method 202: operation 204: Operation 206: Operation 208: Operation 210: Operation 212: Operation A-A': Line B-B': Line C-C': Line D-D': Line E1: Horizontal plane E2: Horizontal plane E3: Horizontal plane E4: Horizontal plane E5: Horizontal plane E6: Horizontal plane E7: Horizontal plane E8: Horizontal plane E9: Horizontal plane E10: Horizontal plane X: Direction Y: Direction Z: Direction

When referring to the embodiments and the scope of the patent application together with the drawings, a more comprehensive understanding of the disclosure of the present application can be obtained. The same element symbols in the drawings refer to the same elements, and: FIG. 1A is a perspective view, illustrating a semiconductor element of some embodiments of the present disclosure. FIG. 1B is a cross-sectional view, illustrating a semiconductor element along the A-A' line in FIG. 1A in some embodiments of the present disclosure. FIG. 1C is a cross-sectional view, illustrating a semiconductor element along the B-B' line in FIG. 1A in some embodiments of the present disclosure. FIG. 1D is a cross-sectional view, illustrating a semiconductor element along the C-C' line in FIG. 1A in some embodiments of the present disclosure. FIG. 1E is a cross-sectional view, illustrating a semiconductor element along the D-D' line in FIG. 1A in some embodiments of the present disclosure. FIG. 2 is a cross-sectional view, illustrating a semiconductor element of some embodiments of the present disclosure. FIG. 3 is a flow chart illustrating a method for preparing a semiconductor element according to some embodiments of the present disclosure. FIG. 4A, FIG. 4B, FIG. 4C, FIG. 4D, and FIG. 4E illustrate one or more stages of a method for preparing a semiconductor element according to some embodiments of the present disclosure. FIG. 5A, FIG. 5B, FIG. 5C, FIG. 5D, and FIG. 5E illustrate one or more stages of a method for preparing a semiconductor element according to some embodiments of the present disclosure. FIG. 6A, FIG. 6B, FIG. 6C, FIG. 6D, and FIG. 6E illustrate one or more stages of a method for preparing a semiconductor element according to some embodiments of the present disclosure. FIG. 7A, FIG. 7B, FIG. 7C, FIG. 7D, and FIG. 7E illustrate one or more stages of a method for preparing a semiconductor element according to some embodiments of the present disclosure. Figures 8A, 8B, 8C, 8D and 8E illustrate one or more stages of a method for preparing a semiconductor element of some embodiments of the present disclosure. Figures 9A, 9B, 9C, 9D and 9E illustrate one or more stages of a method for preparing a semiconductor element of some embodiments of the present disclosure. Figures 10A, 10B, 10C, 10D and 10E illustrate one or more stages of a method for preparing a semiconductor element of some embodiments of the present disclosure. Figures 11A, 11B, 11C, 11D and 11E illustrate one or more stages of a method for preparing a semiconductor element of some embodiments of the present disclosure. Figures 12A, 12B, 12C, 12D, and 12E illustrate one or more stages of a method for preparing a semiconductor device according to some embodiments of the present disclosure. Figures 13A, 13B, 13C, 13D, and 13E illustrate one or more stages of a method for preparing a semiconductor device according to some embodiments of the present disclosure. Figures 14A, 14B, 14C, 14D, and 14E illustrate one or more stages of a method for preparing a semiconductor device according to some embodiments of the present disclosure. Figures 15A, 15B, 15C, 15D, and 15E illustrate one or more stages of a method for preparing a semiconductor device according to some embodiments of the present disclosure. Figures 16A, 16B, 16C, 16D, and 16E illustrate one or more stages of a method for preparing a semiconductor element of some embodiments of the present disclosure. Figures 17A, 17B, 17C, 17D, and 17E illustrate one or more stages of a method for preparing a semiconductor element of some embodiments of the present disclosure. Figures 18A, 18B, 18C, 18D, and 18E illustrate one or more stages of a method for preparing a semiconductor element of some embodiments of the present disclosure. Figures 19A, 19B, 19C, 19D, and 19E illustrate one or more stages of a method for preparing a semiconductor element of some embodiments of the present disclosure. FIG. 20A, FIG. 20B, FIG. 20C, FIG. 20D, and FIG. 20E illustrate one or more stages of a method for preparing a semiconductor device according to some embodiments of the present disclosure.

100a:Semiconductor components

110: Base

110s1: Surface

120-1: Isolation Layer

120-2: Isolation Layer

120-3: Isolation Layer

120-4: Isolation Layer

120-5: Isolation Layer

130-1: Conductive layer

130-2: Conductive layer

130-3: Conductive layer

130-4: Conductive layer

130-5: Conductive layer

140-1: Support layer

140-2: Support layer

150-1: Capacitor

150-2: Capacitor

150-3: Capacitor

150-4: Capacitor

150-5: Capacitor

150-6: Capacitor

150-7: Capacitor

150-8: Capacitor

150-9: Capacitors

150-10: Capacitor

152:Capacitor dielectric

154: Conductive layer

A-A': line

B-B': line

C-C': line

D-D': line

X: Direction

Y: Direction

Z: Direction

Claims (16)

A semiconductor element comprises: a substrate; a plurality of capacitors disposed on the substrate, wherein each capacitor extends along a first direction, wherein each of the plurality of capacitors comprises a first capacitor electrode, a second capacitor electrode, and a capacitor dielectric separating the first capacitor electrode from the second capacitor electrode; a first supporting layer disposed on the substrate and extending along a second direction different from the first direction; and a plurality of isolation layers, each of which extends along the first direction, wherein the plurality of isolation layers and the first capacitor electrodes of the plurality of capacitors have a staggered arrangement, wherein the first capacitor electrodes of the plurality of capacitors are spaced apart from the substrate, The capacitor dielectric includes a first surface and a second surface, which are arranged on two opposite sides of the capacitor dielectric along the first direction, the second surface is exposed by the first capacitor electrode, and the first supporting layer is arranged between the first surface and the second surface of the capacitor dielectric. A semiconductor device as described in claim 1, wherein the first supporting layer is in contact with the substrate. The semiconductor device as described in claim 2 further includes: A second supporting layer, which is separated from the first supporting layer and extends along the second direction, wherein the second supporting layer is in contact with the substrate. The semiconductor device as described in claim 2 further includes: a transistor electrically connected to one of the plurality of capacitors; and an interconnection disposed between the transistor and one of the plurality of capacitors. A semiconductor device as described in claim 4, wherein the interconnection line and the first capacitor electrode of one of the plurality of capacitors are monolithic. A semiconductor device as described in claim 4, wherein the interconnection line extends along the first direction. A semiconductor device as described in claim 4, wherein the transistor includes a word line extending along a third direction different from the first direction and the second direction. A semiconductor device as described in claim 7, wherein the transistor includes a channel layer separated from the first capacitor electrode of one of the plurality of capacitors by the word line. A semiconductor device as described in claim 7, wherein the material of the channel layer is different from the material of the first capacitor electrode of one of the capacitors. A semiconductor device as described in claim 7, wherein the word line is in contact with the substrate. A method for preparing a semiconductor element comprises: providing a substrate; forming a plurality of isolation layers and a plurality of first conductive layers on the substrate, wherein the plurality of isolation layers and the plurality of first conductive layers are alternately stacked; patterning the plurality of isolation layers and the plurality of first conductive layers to form a plurality of island structures; removing a first portion of the plurality of isolation layers to expose the plurality of first conductive layers; forming a capacitor dielectric to cover the plurality of first conductive layers; and forming a second conductive layer to cover the capacitor dielectric. The preparation method as described in claim 11 further comprises: Before removing the first portion of the plurality of isolation layers, forming a first mask layer to cover a second portion of the plurality of isolation layers, wherein the first mask layer exposes the first portion of the plurality of isolation layers; and After removing the first portion of the plurality of isolation layers, removing the first mask layer. A preparation method as described in claim 12, wherein the capacitor dielectric is formed on the second portion of the plurality of isolation layers, and the preparation method further comprises: Removing the capacitor dielectric on the second portion of the plurality of isolation layers. The preparation method as described in claim 12, wherein the second conductive layer is formed on the second portion of the plurality of isolation layers, and the preparation method further comprises: Removing the second conductive layer on the second portion of the plurality of isolation layers. The preparation method as described in claim 11 further comprises: After forming the plurality of island structures, removing a third portion of the plurality of isolation layers to form an opening; and forming a support layer to fill the opening. The preparation method as described in claim 15 further comprises: Before removing the third portion of the plurality of isolation layers, forming a second mask layer on the island structures, wherein the second mask exposes the third portion of the plurality of isolation layers; Forming a dielectric layer to fill the opening, wherein the dielectric layer is further formed on an upper surface of each of the plurality of island structures; and Removing the dielectric layer from the upper surface of each of the plurality of island structures.