TW202418273A - Flash memory device and program method thereof - Google Patents
Flash memory device and program method thereof Download PDFInfo
- Publication number
- TW202418273A TW202418273A TW111139285A TW111139285A TW202418273A TW 202418273 A TW202418273 A TW 202418273A TW 111139285 A TW111139285 A TW 111139285A TW 111139285 A TW111139285 A TW 111139285A TW 202418273 A TW202418273 A TW 202418273A
- Authority
- TW
- Taiwan
- Prior art keywords
- leakage current
- current
- bit line
- common bit
- memory cells
- Prior art date
Links
- 238000004088 simulation Methods 0.000 claims abstract description 33
- 238000001514 detection method Methods 0.000 claims abstract description 26
- 238000012360 testing method Methods 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 23
- 238000012795 verification Methods 0.000 claims description 22
- 230000007704 transition Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 4
- 238000006731 degradation reaction Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 238000009966 trimming Methods 0.000 description 3
- 101001121408 Homo sapiens L-amino-acid oxidase Proteins 0.000 description 2
- 102100026388 L-amino-acid oxidase Human genes 0.000 description 2
- 101100012902 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) FIG2 gene Proteins 0.000 description 2
- 101100233916 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) KAR5 gene Proteins 0.000 description 2
- 238000007664 blowing Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 231100000989 no adverse effect Toxicity 0.000 description 1
Images
Landscapes
- Read Only Memory (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
Description
本發明是有關於一種記憶體的編程方法,且特別是有關於一種能夠針對漏電流進行補償的快閃記憶體裝置及其編程方法。The present invention relates to a memory programming method, and more particularly to a flash memory device capable of compensating for leakage current and a programming method thereof.
在針對快閃記憶體(flash memory)的編程操作中,為了確保臨限電壓(threshold voltage,Vt)已被編程到預定的目標電壓,編程驗證(Program-Verify,PV)是不可或缺的操作項目。在編程驗證中會對選中記憶胞施加讀取電壓,並且對所產生的胞電流進行偵測。胞電流必需被判定為足夠低才能通過驗證。In the programming operation of flash memory, in order to ensure that the threshold voltage (Vt) has been programmed to the predetermined target voltage, program verification (PV) is an indispensable operation item. In program verification, a read voltage is applied to the selected memory cell, and the cell current generated is detected. The cell current must be judged to be low enough to pass the verification.
除了選中記憶胞的胞電流之外,在共同位元線(global bit line)上還會有其他記憶胞所產生的漏電流。因此,實際上在編程驗證中與參考電流進行比較的是共同位元線上由胞電流以及漏電流相加而成的感測電流。當感測電流不夠低時就會對選中記憶胞所耦接的字元線再次施加編程脈衝以及進行編程驗證,並且重複操作直到感測電流被判定為足夠低為止。此外,對於反或型快閃記憶體(NOR flash memory)來說,由於劣化的關係漏電流還會隨著進行循環操作(即由編程操作及抹除操作構成的循環)的次數增加而逐漸增加,導致需要施加更多次的編程脈衝來將選中記憶胞的臨限電壓推動至更高,才能在編程驗證時使感測電流低於參考電流。同時,編程驗證的次數也會隨之增加。如此惡性循環之下,頁編程時間(page program time,tPP)就會隨著循環操作的次數增加而逐漸增加,導致快閃記憶體的效率下降,進而成為記憶體技術開發上的瓶頸。In addition to the cell current of the selected memory cell, there is also leakage current generated by other memory cells on the global bit line. Therefore, in programming verification, the reference current is actually compared with the sensed current formed by the sum of the cell current and the leakage current on the global bit line. When the sensed current is not low enough, the programming pulse will be applied again to the word line coupled to the selected memory cell and programming verification will be performed, and the operation will be repeated until the sensed current is judged to be low enough. In addition, for NOR flash memory, due to degradation, the leakage current will gradually increase with the number of cycles (i.e., cycles consisting of programming and erasing operations), resulting in the need to apply more programming pulses to push the critical voltage of the selected memory cell to a higher level so that the sense current can be lower than the reference current during programming verification. At the same time, the number of programming verifications will also increase. Under such a vicious cycle, the page program time (tPP) will gradually increase with the number of cycles, resulting in a decrease in the efficiency of the flash memory, which in turn becomes a bottleneck in the development of memory technology.
本發明提供一種快閃記憶體裝置及其編程方法,能夠盡量使頁編程時間在經過多次循環操作後仍維持不變。The present invention provides a flash memory device and a programming method thereof, which can keep the page programming time unchanged as much as possible after multiple cycle operations.
本發明的快閃記憶體裝置包括記憶體陣列、第一共同位元線以及感測放大裝置。記憶體陣列包括第一記憶體區塊。第一記憶體區塊包括多個第一記憶胞。第一共同位元線耦接第一記憶胞。感測放大裝置耦接第一共同位元線。在漏電流偵測操作中,感測放大裝置偵測第一記憶胞在第一共同位元線上產生的漏電流,以獲得漏電流模擬資訊。在編程操作中,感測放大裝置根據漏電流模擬資訊以提供參考電流,且對第一記憶胞中的選中記憶胞在第一共同位元線上產生的感測電流與參考電流進行比較,以進行編程驗證。The flash memory device of the present invention includes a memory array, a first common bit line, and a sense amplifier. The memory array includes a first memory block. The first memory block includes a plurality of first memory cells. The first common bit line is coupled to the first memory cells. The sense amplifier is coupled to the first common bit line. In a leakage current detection operation, the sense amplifier detects the leakage current generated by the first memory cell on the first common bit line to obtain leakage current analog information. In a programming operation, the sense amplifier provides a reference current based on the leakage current analog information, and compares the sense current generated by a selected memory cell among the first memory cells on the first common bit line with the reference current to perform programming verification.
本發明的快閃記憶體裝置的編程方法包括下列步驟:在漏電流偵測操作中,偵測第一記憶胞在第一共同位元線上產生的漏電流,以獲得漏電流模擬資訊;以及在編程操作中,根據漏電流模擬資訊以提供參考電流,且對第一記憶胞中的選中記憶胞在第一共同位元線上產生的感測電流與參考電流進行比較,以進行編程驗證。The programming method of the flash memory device of the present invention includes the following steps: in a leakage current detection operation, the leakage current generated by the first memory cell on the first common bit line is detected to obtain leakage current simulation information; and in a programming operation, a reference current is provided according to the leakage current simulation information, and the sensed current generated by the selected memory cell in the first memory cell on the first common bit line is compared with the reference current to perform programming verification.
基於上述,本發明的快閃記憶體裝置及其編程方法能夠在編程操作之前預先偵測記憶體區塊所產生的漏電流。並且,在編程操作中能夠根據漏電流的大小提供適當的參考電流來進行編程驗證。藉此,不會因漏電流的影響而需要在編程驗證時施加更多次的編程脈衝,不會對頁編程時間產生不良的影響,避免快閃記憶體的效率下降。Based on the above, the flash memory device and programming method of the present invention can detect the leakage current generated by the memory block before the programming operation. In addition, during the programming operation, it can provide an appropriate reference current according to the leakage current to perform programming verification. In this way, it is not necessary to apply more programming pulses during programming verification due to the influence of the leakage current, and it will not have a negative impact on the page programming time, thereby avoiding the reduction of the efficiency of the flash memory.
請參照圖1,圖1繪示本發明一實施例的快閃記憶體裝置的示意圖。快閃記憶體裝置100包括記憶體陣列110、感測放大裝置120以及第一共同位元線GBL1。記憶體陣列110包括第一記憶體區塊112。第一記憶體區塊112包括多個第一記憶胞MC1~MCn+i-1。第一記憶胞MC1~MCn+i-1分別耦接至字元線WL[0]~WL[n+i-1]。第一記憶胞MC1~MCn+i-1的源極端共同耦接至接地電壓GND。第一記憶體區塊112還可區分為多個分部11~1n,多個分部11~1n共用的第一共同位元線GBL1。Please refer to FIG. 1 , which shows a schematic diagram of a flash memory device according to an embodiment of the present invention. The
第一共同位元線GBL1耦接第一記憶胞MC1~MCn+i-1。感測放大裝置120耦接第一共同位元線GBL1。在漏電流偵測操作中,感測放大裝置120可偵測第一記憶胞MC1~MCn+i-1在第一共同位元線GBL1上產生的漏電流IL,以獲得漏電流模擬資訊。The first common bit line GBL1 is coupled to the first memory cells MC1-MCn+i-1. The
具體來說,在漏電流偵測操作中,將與第一記憶胞MC1~MCn+i-1對應的所有字元線WL[0]~WL[n+i-1]均控制為禁能的狀態。如此一來,第一記憶體區塊112中的記憶胞皆為非存取的狀態,感測放大裝置120可接收第一共同位元線GBL1上所產生的漏電流IL。在此同時,感測放大裝置120可接收測試電流Itest,並根據設定比例來調整測試電流Itest以產生複製漏電流ILR。感測放大裝置120使複製漏電流ILR與第一共同位元線GBL1上的漏電流IL來進行比較來產生比較結果,並透過調整設定比例來找出最接近漏電流IL的複製漏電流ILR,藉以產生漏電流模擬資訊。Specifically, in the leakage current detection operation, all word lines WL[0]~WL[n+i-1] corresponding to the first memory cells MC1~MCn+i-1 are controlled to be disabled. In this way, the memory cells in the
在漏電流偵測操作完成之後的編程操作中,感測放大裝置120可根據漏電流模擬資訊以提供參考電流Iref,且對第一記憶胞MC1~MCn+i-1中的選中記憶胞MCT在第一共同位元線GBL1上產生的感測電流Isen與參考電流Iref進行比較,以進行編程驗證。In the programming operation after the leakage current detection operation is completed, the
具體來說,在編程操作中,將與選中記憶胞MCT對應的字元線WL[i-1]控制為致能的狀態,將與其餘的第一記憶胞(第一記憶胞MC1~MCn+i-1中除了選中記憶胞MCT以外的記憶胞)對應的字元線控制為禁能的狀態。如此一來,選中記憶胞MCT會在第一共同位元線GBL1上產生胞電流Icell,感測放大裝置120在第一共同位元線GBL1可接收由胞電流Icell以及漏電流IL相加而成感測電流Isen。在此同時,感測放大裝置120還會根據之前獲得的漏電流模擬資訊來調整測試電流Itest以產生參考電流Iref。感測放大裝置120使感測電流Isen與參考電流Iref進行比較,以進行編程驗證。Specifically, in the programming operation, the word line WL[i-1] corresponding to the selected memory cell MCT is controlled to be enabled, and the word lines corresponding to the remaining first memory cells (the memory cells other than the selected memory cell MCT in the first memory cells MC1~MCn+i-1) are controlled to be disabled. In this way, the selected memory cell MCT will generate a cell current Icell on the first common bit line GBL1, and the
需說明的是,基於與參考電流Iref是根據漏電流模擬資訊所產生的,因此,在感測放大裝置120針對感測電流Isen以及參考電流Iref進行比較時,感測電流Isen中的漏電流IL的部分可以被消除。如此一來,在進行編程驗證時,不需要因為漏電流的關係而施加更多次的編程脈衝即可通過驗證,不會對頁編程時間造成不良的影響,從而能夠盡量使頁編程時間在經過多次循環操作後仍維持不變。It should be noted that, since the reference current Iref is generated according to the leakage current simulation information, when the
圖2繪示本發明一實施例的感測放大裝置的示意圖。請參照圖2,感測放大裝置200包括第一感測放大器210以及比例控制器220。第一感測放大器210具有第一輸入端以耦接第一共同位元線GBL1。比例控制器220可以為具備運算能力的處理器。或者,比例控制器220可以是透過硬體描述語言(Hardware Description Language, HDL)或是其他任意本領域具通常知識者所熟知的數位電路的設計方式來進行設計,並透過現場可程式邏輯門陣列(Field Programmable Gate Array, FPGA)、複雜可程式邏輯裝置(Complex Programmable Logic Device, CPLD)或是特殊應用積體電路(Application-specific Integrated Circuit, ASIC)的方式來實現的硬體電路。比例控制器220耦接第一感測放大器210的第二輸入端。比例控制器接收測試電流Itest,且在漏電流偵測操作中,根據設定比例調整測試電流Itest以產生複製漏電流ILR。FIG2 is a schematic diagram of a sensing amplifier device according to an embodiment of the present invention. Referring to FIG2 , the
在漏電流偵測操作中,第一感測放大器210對第一共同位元線GBL1上的漏電流IL與複製漏電流ILR進行比較,以產生比較結果CR。比例控制器220接收比較結果CR,當比較結果CR維持為第一邏輯準位時比例控制器220調整設定比例。並且,第一感測放大器210及比例控制器220重複進行第一共同位元線GBL1上的漏電流IL與複製漏電流ILR的比較以及設定比例的調整,直到比較結果CR由第一邏輯準位轉態為第二邏輯準位為止。In the leakage current detection operation, the
當比較結果CR由第一邏輯準位轉態為第二邏輯準位時,表示此時的設定比例所產生的複製漏電流ILR最接近於漏電流IL,因此感測放大裝置200可儲存對應的設定比例來作為漏電流模擬資訊。When the comparison result CR changes from the first logic level to the second logic level, it means that the replica leakage current ILR generated by the setting ratio at this time is closest to the leakage current IL. Therefore, the
附帶一提的,在其他實施例中,感測放大裝置200也可直接儲存目前的複製漏電流ILR來作為漏電流模擬資訊。Incidentally, in other embodiments, the
在本實施例中,測試電流Itest可以預設為一個具有相對高數值的信號,在此條件下,比例控制器220可逐步調低設定比例來進行複製漏電流ILR與漏電流IL的比較動作。在初始階段,複製漏電流ILR可大於漏電流IL,並使比較結果CR為第一邏輯準位。而隨著設定比例的調低,複製漏電流ILR可被調整為小於或等於漏電流IL,第一感測放大器210可產生為第二邏輯準位的比較結果CR。此時的複製漏電流ILR為最接近於漏電流IL的狀態。或者,測試電流Itest也可以預設為一個具有相對低數值的信號,在此條件下,比例控制器220可逐步調高設定比例來進行複製漏電流ILR與漏電流IL的比較動作。在初始階段,複製漏電流ILR可小於漏電流IL,並使比較結果CR為第一邏輯準位。而隨著設定比例的調高,複製漏電流ILR可被調整為大於或等於漏電流IL,第一感測放大器210可產生為第二邏輯準位的比較結果CR。此時的複製漏電流ILR同樣可以為最接近於漏電流IL的狀態。此外,上述的第一邏輯準位可以為邏輯1或邏輯0,上述的第二邏輯準位則可以為與第一邏輯準位互補的邏輯0或1。In this embodiment, the test current Itest can be preset as a signal with a relatively high value. Under this condition, the
圖3繪示本發明一實施例的編程操作的參考電流與感測電流的示意圖。請參照圖3,在漏電流偵測操作完成之後的編程操作中所使用的參考電流Iref會由比較電流Icmp以及補償電流Icps相加而成,感測電流Isen則會由胞電流Icell以及漏電流IL相加而成。感測放大裝置200可根據之前獲得的漏電流模擬資訊以提供補償電流Icps,使補償電流Icps相當於與所儲存的設定比例對應的複製漏電流ILR。比較電流Icmp則例如是一般情況下進行編程驗證時用來驗證是否編程成功的電流。因此,在第一感測放大器210針對感測電流Isen以及參考電流Iref進行比較時,感測電流Isen中的漏電流IL的部分可以與參考電流Iref中的補償電流Icps的部分互相抵消。如此一來,在進行編程驗證時,不需要因為漏電流的關係而施加更多次的編程脈衝即可通過驗證,不會對頁編程時間造成不良的影響,從而能夠盡量使頁編程時間在經過多次循環操作後仍維持不變,避免快閃記憶體的效率下降。FIG3 is a schematic diagram of the reference current and the sense current of the programming operation of an embodiment of the present invention. Referring to FIG3 , the reference current Iref used in the programming operation after the leakage current detection operation is completed is formed by adding the comparison current Icmp and the compensation current Icps, and the sense current Isen is formed by adding the cell current Icell and the leakage current IL. The
需說明的是,快閃記憶體的效率下降例如可以反應在編程失敗、記憶胞本質劣化以及不符合技術規格三個方面上。通常快閃記憶體裝置的內部會限制施加編程脈衝以及進行編程驗證的重複次數,避免頁編程時間的過久,因此當漏電流過高而持續無法通過編程驗證時就會導致編程失敗。漏電流會導致施加更多次的編程脈衝,以便將選中記憶胞編程到更高的臨限電壓的狀態以進行補償,然而這意味著會更多的電子注入氧化層區域,增加氧化層劣化的可能性,並導致有關記憶胞本質劣化的可靠性問題。並且,頁編程時間過長則會不符合技術規格所規定的時間長度。本發明的快閃記憶體裝置能夠盡量使頁編程時間在經過多次循環操作後仍維持不變,藉此避免上述問題的發生。It should be noted that the decline in the efficiency of flash memory can be reflected in three aspects, for example, programming failure, degradation of the memory cell nature, and non-compliance with technical specifications. Usually, the internal part of the flash memory device will limit the application of programming pulses and the number of repetitions of programming verification to avoid too long page programming time. Therefore, when the leakage current is too high and the programming verification fails continuously, it will lead to programming failure. The leakage current will cause more programming pulses to be applied in order to program the selected memory cell to a higher threshold voltage state for compensation. However, this means that more electrons will be injected into the oxide layer area, increasing the possibility of oxide layer degradation and causing reliability issues related to the degradation of the memory cell nature. In addition, if the page programming time is too long, it will not meet the time length specified by the technical specifications. The flash memory device of the present invention can keep the page programming time as constant as possible after multiple cycle operations, thereby avoiding the occurrence of the above problems.
以下請參照圖4,圖4繪示本發明一實施例的漏電流偵測操作的流程圖。在步驟S410中,測試電流Itest的數值可以在晶圓測試時,透過測試流程的調整(trim)機制來完成設定。測試電流Itest可以設定為具有一個相對大的數值的電流值。關於測試流程的調整(trim)機制,可以透過熔斷(或不熔斷)電子熔絲的方式,或者利用本領域具通常知識者熟知的測試流程的調整技術來進行,沒有特別的限制。Please refer to FIG. 4 below, which is a flow chart of the leakage current detection operation of an embodiment of the present invention. In step S410, the value of the test current Itest can be set by the trimming mechanism of the test process during the wafer test. The test current Itest can be set to a current value with a relatively large value. Regarding the trimming mechanism of the test process, it can be performed by blowing (or not blowing) an electronic fuse, or by using the trimming technology of the test process that is familiar to those skilled in the art, without any special restrictions.
在步驟S420中,則進行設定比例的調整動作。在本實施例中,初始的設定比例可以等於100%。透過測試電流Itest以及設定比例,本實施例的感測放大裝置可產生複製漏電流ILR並與共同位元線上的漏電流IR進行比較,並在步驟S430中產生比較結果CR。In step S420, the setting ratio is adjusted. In this embodiment, the initial setting ratio can be equal to 100%. Through the test current Itest and the setting ratio, the sensing amplifier of this embodiment can generate a replica leakage current ILR and compare it with the leakage current IR on the common bit line, and generate a comparison result CR in step S430.
在步驟S440中,判斷比較結果CR是否等於初始值(例如為邏輯0)?若判斷結果為是,則重新執行步驟S420以進一步調低設定比例。若判斷結果為否,則可儲存設定比例來作為漏電流模擬資訊(步驟S450)。In step S440, is it determined whether the comparison result CR is equal to the initial value (e.g., logical 0)? If the determination result is yes, then step S420 is re-executed to further reduce the setting ratio. If the determination result is no, then the setting ratio can be stored as leakage current simulation information (step S450).
附帶一提的,本實施例中的步驟S410也可透過測試流程的調整機制,來調整出一個相對小的測試電流Itest。在此情況下,步驟S420中初始的設定比例為一個小於100%的比值。並在步驟S440的判斷結果為是後,步驟S420可進一步調高設定比例。Incidentally, step S410 in this embodiment can also be adjusted to a relatively small test current Itest through the adjustment mechanism of the test process. In this case, the initial setting ratio in step S420 is a ratio less than 100%. And after the judgment result of step S440 is yes, step S420 can further increase the setting ratio.
圖5A及圖5B繪示本發明一實施例的快閃記憶體裝置的示意圖。在圖5A及圖5B中,快閃記憶體裝置500包括記憶體陣列510、感測放大裝置520、第一共同位元線GBL1以及第二共同位元線GBL21~GBL2m。記憶體陣列510包括第一記憶體區塊5140以及第二記憶體區塊5141~514m。第一記憶體區塊5140耦接第一共同位元線GBL1。第二記憶體區塊5141~514m分別耦接第二共同位元線GBL21~GBL2m。在第一記憶體區塊5140以及第二記憶體區塊5141~514m內分別包括多個記憶胞。第一記憶體區塊5140以及第二記憶體區塊5141~514m所包括的多個記憶胞分別耦接對應的共同位元線。5A and 5B are schematic diagrams of a flash memory device according to an embodiment of the present invention. In FIG5A and 5B, the
感測放大裝置520包括第一感測放大器5240、第二感測放大器5241~524m、比例控制器526以及電流鏡5280~528m。第一感測放大器5240的第一輸入端耦接第一共同位元線GBL1。每個第二感測放大器5241~524m的第一輸入端耦接第二共同位元線GBL21~GBL2m中對應的第二共同位元線。電流鏡5280~528m分別耦接第一感測放大器5240的第二輸入端以及第二感測放大器5241~524m的第二輸入端。The
如圖5A所示,在漏電流偵測操作中,透過比例控制器526以使設定比例與設定信號Itest相乘所產生的複製漏電流ILR。複製漏電流ILR可透過電流鏡5280~528m的鏡射動作來分別產生鏡射複製漏電流ILR0~ILRm以傳送至第一感測放大器5240以及第二感測放大器5241~524m。如此一來,透過第一感測放大器5240以及第二感測放大器5241~524m的比較結果,以及配合比例控制器526逐步的調整設定比例,可以逐一的計算出第一共同位元線GBL1及第二共同位元線GBL21~GBL2m對應的多個記憶胞區塊的電流模擬資訊,以快速地的完成漏電流偵測操作。此時,電流鏡5280~528m可具有相同的鏡射比,僅透過調整設定比例來獲得每個記憶胞區塊所對應的電流模擬資訊。As shown in FIG5A, in the leakage current detection operation, the
如圖5B所示,在漏電流偵測操作完成之後的編程操作中,電流鏡5280~528m可分別具有不同的鏡射比,多個鏡射比分別等同多個權重值,並分別對應第一記憶體區塊5140及第二記憶體區塊5141~514m的電流模擬資訊。此時,比例控制器526可以將設定比例固定於100%,並且將相等於測試電流Itest的電流傳送至每個電流鏡5280~528m。如此一來,每個電流鏡5280~528m可根據對應的漏電流模擬資訊鏡射測試電流Itest以分別產生補償電流Icps0~Icpsm。感測電流Isen0~Isem中的漏電流的部分可以分別與參考電流Iref0~Irefm中的補償電流Icps0~Icpsm的部分互相抵消。As shown in FIG. 5B , in the programming operation after the leakage current detection operation is completed, the
圖6繪示繪示本發明一實施例的快閃記憶體裝置的編程方法的流程圖。請同時參照圖1及圖6,本實施例的方法可適用於圖1的快閃記憶體裝置100。在步驟S610中,在漏電流偵測操作中,偵測第一記憶胞MC1~MCn+i-1在第一共同位元線GBL1上產生的漏電流IL,以獲得漏電流模擬資訊。在步驟S620中,感測放大裝置120根據漏電流模擬資訊以提供參考電流Iref,且對第一記憶胞MC1~MCn+i-1中的選中記憶胞MCT在第一共同位元線GBL1上產生的感測電流Isen與參考電流Iref進行比較,以進行編程驗證。關於上述步驟的實施細節,在前述的多個實施例中已有詳盡的說明,在此恕不多贅述。FIG6 is a flow chart showing a programming method of a flash memory device according to an embodiment of the present invention. Please refer to FIG1 and FIG6 simultaneously. The method of the present embodiment can be applied to the
綜上所述,本發明的快閃記憶體裝置及其編程方法能夠在編程操作之前預先偵測記憶體區塊所產生的漏電流以作為漏電流模擬資訊。並且,在編程操作中能夠漏電流模擬資訊提供適當的參考電流來與感測電流進行比較,以抵消感測電流中的漏電流的部分。藉此,不會因漏電流的影響而需要在編程驗證時施加更多次的編程脈衝,不會對頁編程時間產生不良的影響,避免快閃記憶體的效率下降。In summary, the flash memory device and programming method of the present invention can detect the leakage current generated by the memory block in advance before the programming operation to serve as leakage current simulation information. Moreover, during the programming operation, the leakage current simulation information can provide an appropriate reference current to compare with the sensed current to offset the leakage current portion of the sensed current. In this way, it is not necessary to apply more programming pulses during programming verification due to the influence of the leakage current, and it will not have a negative impact on the page programming time, thereby avoiding a decrease in the efficiency of the flash memory.
100、500:快閃記憶體裝置
110、510:記憶體陣列
112、5140:第一記憶體區塊
120、200、520:感測放大裝置
210、5240:第一感測放大器
220、526:比例控制器
11~1n:分部
5141~514m:第二記憶體區塊
5241~524m:第二感測放大器
5280~528m:電流鏡
CR:比較結果
GBL1:第一共同位元線
GBL21~GBL2m:第二共同位元線
GND:接地電壓
IL:漏電流
ILR:複製漏電流
ILR0~ILRm:鏡射複製漏電流
Icell:胞電流
Icmp:比較電流
Icps、Icps0~Icpsm:補償電流
Iref、Iref0~Irefm:參考電流
Isen、Isen0~Isem:感測電流
Itest:測試電流
MC1~MCn+i-1:第一記憶胞
MCT:選中記憶胞
WL[0]~WL[n+i-1]:字元線
S410~S450、S610~S620:步驟
100, 500:
圖1繪示本發明一實施例的快閃記憶體裝置的示意圖。 圖2繪示本發明一實施例的感測放大裝置的示意圖。 圖3繪示本發明一實施例的編程操作的參考電流與感測電流的示意圖。 圖4繪示本發明一實施例的漏電流偵測操作的流程圖。 圖5A及圖5B繪示本發明一實施例的快閃記憶體裝置的示意圖。 圖6繪示繪示本發明一實施例的快閃記憶體裝置的編程方法的流程圖。 FIG. 1 is a schematic diagram of a flash memory device according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a sensing amplifier according to an embodiment of the present invention. FIG. 3 is a schematic diagram of a reference current and a sensing current of a programming operation according to an embodiment of the present invention. FIG. 4 is a flow chart of a leakage current detection operation according to an embodiment of the present invention. FIG. 5A and FIG. 5B are schematic diagrams of a flash memory device according to an embodiment of the present invention. FIG. 6 is a flow chart of a programming method of a flash memory device according to an embodiment of the present invention.
100:快閃記憶體裝置 100: Flash memory device
110:記憶體陣列 110:Memory array
112:第一記憶體區塊 112: First memory block
120:感測放大裝置 120: Sensing amplifier
11~1n:分部 11~1n: Division
GBL1:第一共同位元線 GBL1: First common bit line
GND:接地電壓 GND: Ground voltage
IL:漏電流 IL: Leakage current
Isen:感測電流 Isen: Sense current
Itest:測試電流 Itest: test current
MC1~MCn+i-1:第一記憶胞 MC1~MCn+i-1: first memory cell
MCT:選中記憶胞 MCT: Select memory cells
WL[0]~WL[n+i-1]:字元線 WL[0]~WL[n+i-1]: character line
Claims (15)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW111139285A TWI822395B (en) | 2022-10-17 | 2022-10-17 | Flash memory device and program method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW111139285A TWI822395B (en) | 2022-10-17 | 2022-10-17 | Flash memory device and program method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI822395B TWI822395B (en) | 2023-11-11 |
TW202418273A true TW202418273A (en) | 2024-05-01 |
Family
ID=89722562
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW111139285A TWI822395B (en) | 2022-10-17 | 2022-10-17 | Flash memory device and program method thereof |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI822395B (en) |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10475510B2 (en) * | 2017-12-21 | 2019-11-12 | Macronix International Co., Ltd. | Leakage compensation read method for memory device |
US10566072B2 (en) * | 2018-03-06 | 2020-02-18 | Winbond Electronics Corp. | Detection methods for NOR flash memory |
-
2022
- 2022-10-17 TW TW111139285A patent/TWI822395B/en active
Also Published As
Publication number | Publication date |
---|---|
TWI822395B (en) | 2023-11-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10163526B2 (en) | Circuit and method for detecting time dependent dielectric breakdown (TDDB) shorts and signal-margin testing | |
US6411549B1 (en) | Reference cell for high speed sensing in non-volatile memories | |
JPH09128983A (en) | Method for setting of threshold voltage of reference memory cell for memory device | |
US20060274594A1 (en) | Implementation of a fusing scheme to allow internal voltage trimming | |
US5699295A (en) | Current detection circuit for reading a memory in integrated circuit form | |
US9105357B2 (en) | Semiconductor memory device and defective judging method thereof | |
US7260004B2 (en) | Method and apparatus for increasing yield in a memory circuit | |
JP2023523493A (en) | SENSE AMPLIFIER, MEMORY AND CONTROL METHOD | |
US7394698B1 (en) | Method and apparatus for adjusting a read reference level under dynamic power conditions | |
JPWO2006082619A1 (en) | Storage device and reference cell adjustment method for the storage device | |
TW202418273A (en) | Flash memory device and program method thereof | |
US11538549B2 (en) | Test circuit and semiconductor memory system including the test circuit | |
US20030002342A1 (en) | Method and apparatus for sen-ref equalization | |
US20240153569A1 (en) | Flash memory device and program method thereof | |
CN117976019A (en) | Flash memory device and programming method thereof | |
US20080062767A1 (en) | Method of fixing a read evaluation time or the difference between a read charge voltage and a read discriminating voltage in a non-volatile nand type memory device | |
JP7146114B2 (en) | Memory system that can reduce read time | |
TWI615851B (en) | Sensing circuit and method for non-volatile memory device | |
US20230290416A1 (en) | Memory and reading method thereof | |
TWI783869B (en) | Memory and reading method thereof | |
US20150055423A1 (en) | Semiconductor memory apparatus | |
US11501841B2 (en) | Memory device and control method thereof | |
US20240331783A1 (en) | Semiconductor memory device and method of operating the same | |
US20230176750A1 (en) | Semiconductor memory device and write method thereof | |
JP7301237B2 (en) | SENSE AMPLIFIER, MEMORY AND CONTROL METHOD |