TW202418273A - Flash memory device and program method thereof - Google Patents

Abstract

A flash memory device and a program method thereof are provided. The flash memory device includes a memory array, a first common bit line and a sense amplifier device. The memory array includes a first memory block having a plurality of first memory cells. In a leakage current detection operation, the sense amplifier device detects a leakage current generated by the first memory cells on the first common bit line to obtain leakage current simulation information. In a program operation, the sense amplifying device provides a reference current according to the leakage current simulation information, and compares a sense current, which is generated by a selected memory cell of the first memory cells on the first common bit line, with the reference current to perform a program verification.

Description

Flash memory device and programming method thereof

The present invention relates to a memory programming method, and more particularly to a flash memory device capable of compensating for leakage current and a programming method thereof.

In the programming operation of flash memory, in order to ensure that the threshold voltage (Vt) has been programmed to the predetermined target voltage, program verification (PV) is an indispensable operation item. In program verification, a read voltage is applied to the selected memory cell, and the cell current generated is detected. The cell current must be judged to be low enough to pass the verification.

In addition to the cell current of the selected memory cell, there is also leakage current generated by other memory cells on the global bit line. Therefore, in programming verification, the reference current is actually compared with the sensed current formed by the sum of the cell current and the leakage current on the global bit line. When the sensed current is not low enough, the programming pulse will be applied again to the word line coupled to the selected memory cell and programming verification will be performed, and the operation will be repeated until the sensed current is judged to be low enough. In addition, for NOR flash memory, due to degradation, the leakage current will gradually increase with the number of cycles (i.e., cycles consisting of programming and erasing operations), resulting in the need to apply more programming pulses to push the critical voltage of the selected memory cell to a higher level so that the sense current can be lower than the reference current during programming verification. At the same time, the number of programming verifications will also increase. Under such a vicious cycle, the page program time (tPP) will gradually increase with the number of cycles, resulting in a decrease in the efficiency of the flash memory, which in turn becomes a bottleneck in the development of memory technology.

The present invention provides a flash memory device and a programming method thereof, which can keep the page programming time unchanged as much as possible after multiple cycle operations.

The flash memory device of the present invention includes a memory array, a first common bit line, and a sense amplifier. The memory array includes a first memory block. The first memory block includes a plurality of first memory cells. The first common bit line is coupled to the first memory cells. The sense amplifier is coupled to the first common bit line. In a leakage current detection operation, the sense amplifier detects the leakage current generated by the first memory cell on the first common bit line to obtain leakage current analog information. In a programming operation, the sense amplifier provides a reference current based on the leakage current analog information, and compares the sense current generated by a selected memory cell among the first memory cells on the first common bit line with the reference current to perform programming verification.

The programming method of the flash memory device of the present invention includes the following steps: in a leakage current detection operation, the leakage current generated by the first memory cell on the first common bit line is detected to obtain leakage current simulation information; and in a programming operation, a reference current is provided according to the leakage current simulation information, and the sensed current generated by the selected memory cell in the first memory cell on the first common bit line is compared with the reference current to perform programming verification.

Based on the above, the flash memory device and programming method of the present invention can detect the leakage current generated by the memory block before the programming operation. In addition, during the programming operation, it can provide an appropriate reference current according to the leakage current to perform programming verification. In this way, it is not necessary to apply more programming pulses during programming verification due to the influence of the leakage current, and it will not have a negative impact on the page programming time, thereby avoiding the reduction of the efficiency of the flash memory.

Please refer to FIG. 1 , which shows a schematic diagram of a flash memory device according to an embodiment of the present invention. The flash memory device 100 includes a memory array 110, a sense amplifier device 120, and a first common bit line GBL1. The memory array 110 includes a first memory block 112. The first memory block 112 includes a plurality of first memory cells MC1 to MCn+i-1. The first memory cells MC1 to MCn+i-1 are respectively coupled to word lines WL[0] to WL[n+i-1]. The source terminals of the first memory cells MC1 to MCn+i-1 are commonly coupled to a ground voltage GND. The first memory block 112 can be further divided into a plurality of sub-divisions 11-1n, and the plurality of sub-divisions 11-1n share a first common bit line GBL1.

The first common bit line GBL1 is coupled to the first memory cells MC1-MCn+i-1. The sense amplifier 120 is coupled to the first common bit line GBL1. In the leakage current detection operation, the sense amplifier 120 can detect the leakage current IL generated by the first memory cells MC1-MCn+i-1 on the first common bit line GBL1 to obtain leakage current analog information.

Specifically, in the leakage current detection operation, all word lines WL[0]~WL[n+i-1] corresponding to the first memory cells MC1~MCn+i-1 are controlled to be disabled. In this way, the memory cells in the first memory block 112 are all in a non-access state, and the sense amplifier 120 can receive the leakage current IL generated on the first common bit line GBL1. At the same time, the sense amplifier 120 can receive the test current Itest and adjust the test current Itest according to the set ratio to generate the replica leakage current ILR. The sense amplifier 120 compares the replica leakage current ILR with the leakage current IL on the first common bit line GBL1 to generate a comparison result, and finds the replica leakage current ILR closest to the leakage current IL by adjusting the setting ratio to generate leakage current simulation information.

In the programming operation after the leakage current detection operation is completed, the sense amplifier 120 can provide a reference current Iref according to the leakage current simulation information, and compare the sense current Isen generated on the first common bit line GBL1 of the selected memory cell MCT among the first memory cells MC1~MCn+i-1 with the reference current Iref to perform programming verification.

Specifically, in the programming operation, the word line WL[i-1] corresponding to the selected memory cell MCT is controlled to be enabled, and the word lines corresponding to the remaining first memory cells (the memory cells other than the selected memory cell MCT in the first memory cells MC1~MCn+i-1) are controlled to be disabled. In this way, the selected memory cell MCT will generate a cell current Icell on the first common bit line GBL1, and the sense amplifier 120 can receive the sense current Isen formed by the addition of the cell current Icell and the leakage current IL on the first common bit line GBL1. At the same time, the sense amplifier 120 will also adjust the test current Itest according to the previously obtained leakage current simulation information to generate a reference current Iref. The sense amplifier 120 compares the sense current Isen with the reference current Iref for programming verification.

It should be noted that, since the reference current Iref is generated according to the leakage current simulation information, when the sensing amplifier 120 compares the sensing current Isen with the reference current Iref, the leakage current IL in the sensing current Isen can be eliminated. In this way, when performing programming verification, it is not necessary to apply more programming pulses due to the leakage current to pass the verification, and there will be no adverse effect on the page programming time, so that the page programming time can be kept unchanged as much as possible after multiple cycles.

FIG2 is a schematic diagram of a sensing amplifier device according to an embodiment of the present invention. Referring to FIG2 , the sensing amplifier device 200 includes a first sensing amplifier 210 and a proportional controller 220. The first sensing amplifier 210 has a first input terminal coupled to a first common bit line GBL1. The proportional controller 220 may be a processor with computing capabilities. Alternatively, the proportional controller 220 may be a hardware circuit designed by a hardware description language (HDL) or any other digital circuit design method known to a person skilled in the art, and implemented by a field programmable gate array (FPGA), a complex programmable logic device (CPLD), or an application-specific integrated circuit (ASIC). The ratio controller 220 is coupled to the second input terminal of the first sense amplifier 210. The ratio controller receives the test current Itest, and in the leakage current detection operation, adjusts the test current Itest according to a set ratio to generate a replica leakage current ILR.

In the leakage current detection operation, the first sense amplifier 210 compares the leakage current IL on the first common bit line GBL1 with the replica leakage current ILR to generate a comparison result CR. The ratio controller 220 receives the comparison result CR and adjusts the setting ratio when the comparison result CR maintains the first logic level. Furthermore, the first sense amplifier 210 and the ratio controller 220 repeatedly compare the leakage current IL on the first common bit line GBL1 with the replica leakage current ILR and adjust the setting ratio until the comparison result CR changes from the first logic level to the second logic level.

When the comparison result CR changes from the first logic level to the second logic level, it means that the replica leakage current ILR generated by the setting ratio at this time is closest to the leakage current IL. Therefore, the sensing amplifier 200 can store the corresponding setting ratio as leakage current simulation information.

Incidentally, in other embodiments, the sensing amplifier 200 may also directly store the current replica leakage current ILR as the leakage current simulation information.

In this embodiment, the test current Itest can be preset as a signal with a relatively high value. Under this condition, the ratio controller 220 can gradually reduce the setting ratio to perform the comparison operation of the replica leakage current ILR and the leakage current IL. In the initial stage, the replica leakage current ILR can be greater than the leakage current IL, and the comparison result CR is the first logic level. As the setting ratio is reduced, the replica leakage current ILR can be adjusted to be less than or equal to the leakage current IL, and the first sensing amplifier 210 can generate a comparison result CR of the second logic level. At this time, the replica leakage current ILR is the state closest to the leakage current IL. Alternatively, the test current Itest can also be preset as a signal with a relatively low value. Under this condition, the ratio controller 220 can gradually increase the setting ratio to perform the comparison operation of the replica leakage current ILR and the leakage current IL. In the initial stage, the replica leakage current ILR can be less than the leakage current IL, and the comparison result CR is made to be the first logic level. As the setting ratio is increased, the replica leakage current ILR can be adjusted to be greater than or equal to the leakage current IL, and the first sensing amplifier 210 can generate a comparison result CR of the second logic level. At this time, the replica leakage current ILR can also be the state closest to the leakage current IL. In addition, the first logic level may be logic 1 or logic 0, and the second logic level may be logic 0 or 1 complementary to the first logic level.

FIG3 is a schematic diagram of the reference current and the sense current of the programming operation of an embodiment of the present invention. Referring to FIG3 , the reference current Iref used in the programming operation after the leakage current detection operation is completed is formed by adding the comparison current Icmp and the compensation current Icps, and the sense current Isen is formed by adding the cell current Icell and the leakage current IL. The sensing amplifier 200 can provide the compensation current Icps according to the leakage current simulation information obtained previously, so that the compensation current Icps is equivalent to the replica leakage current ILR corresponding to the stored setting ratio. The comparison current Icmp is, for example, the current used to verify whether the programming is successful when performing programming verification under normal circumstances. Therefore, when the first sense amplifier 210 compares the sense current Isen and the reference current Iref, the leakage current IL in the sense current Isen can cancel out the compensation current Icps in the reference current Iref. In this way, when performing programming verification, it is not necessary to apply more programming pulses due to the leakage current to pass the verification, and the page programming time will not be adversely affected, so that the page programming time can be kept unchanged after multiple cycle operations as much as possible to avoid the efficiency of the flash memory from decreasing.

It should be noted that the decline in the efficiency of flash memory can be reflected in three aspects, for example, programming failure, degradation of the memory cell nature, and non-compliance with technical specifications. Usually, the internal part of the flash memory device will limit the application of programming pulses and the number of repetitions of programming verification to avoid too long page programming time. Therefore, when the leakage current is too high and the programming verification fails continuously, it will lead to programming failure. The leakage current will cause more programming pulses to be applied in order to program the selected memory cell to a higher threshold voltage state for compensation. However, this means that more electrons will be injected into the oxide layer area, increasing the possibility of oxide layer degradation and causing reliability issues related to the degradation of the memory cell nature. In addition, if the page programming time is too long, it will not meet the time length specified by the technical specifications. The flash memory device of the present invention can keep the page programming time as constant as possible after multiple cycle operations, thereby avoiding the occurrence of the above problems.

Please refer to FIG. 4 below, which is a flow chart of the leakage current detection operation of an embodiment of the present invention. In step S410, the value of the test current Itest can be set by the trimming mechanism of the test process during the wafer test. The test current Itest can be set to a current value with a relatively large value. Regarding the trimming mechanism of the test process, it can be performed by blowing (or not blowing) an electronic fuse, or by using the trimming technology of the test process that is familiar to those skilled in the art, without any special restrictions.

In step S420, the setting ratio is adjusted. In this embodiment, the initial setting ratio can be equal to 100%. Through the test current Itest and the setting ratio, the sensing amplifier of this embodiment can generate a replica leakage current ILR and compare it with the leakage current IR on the common bit line, and generate a comparison result CR in step S430.

In step S440, is it determined whether the comparison result CR is equal to the initial value (e.g., logical 0)? If the determination result is yes, then step S420 is re-executed to further reduce the setting ratio. If the determination result is no, then the setting ratio can be stored as leakage current simulation information (step S450).

Incidentally, step S410 in this embodiment can also be adjusted to a relatively small test current Itest through the adjustment mechanism of the test process. In this case, the initial setting ratio in step S420 is a ratio less than 100%. And after the judgment result of step S440 is yes, step S420 can further increase the setting ratio.

5A and 5B are schematic diagrams of a flash memory device according to an embodiment of the present invention. In FIG5A and 5B, the flash memory device 500 includes a memory array 510, a sense amplifier 520, a first common bit line GBL1, and second common bit lines GBL21-GBL2m. The memory array 510 includes a first memory block 5140 and second memory blocks 5141-514m. The first memory block 5140 is coupled to the first common bit line GBL1. The second memory blocks 5141-514m are respectively coupled to the second common bit lines GBL21-GBL2m. The first memory block 5140 and the second memory blocks 5141-514m include a plurality of memory cells respectively. The plurality of memory cells included in the first memory block 5140 and the second memory blocks 5141-514m are respectively coupled to corresponding common bit lines.

The sensing amplifier device 520 includes a first sensing amplifier 5240, second sensing amplifiers 5241-524m, a proportional controller 526, and current mirrors 5280-528m. The first input terminal of the first sensing amplifier 5240 is coupled to the first common bit line GBL1. The first input terminal of each second sensing amplifier 5241-524m is coupled to the corresponding second common bit line among the second common bit lines GBL21-GBL2m. The current mirrors 5280-528m are respectively coupled to the second input terminal of the first sensing amplifier 5240 and the second input terminal of the second sensing amplifiers 5241-524m.

As shown in FIG5A, in the leakage current detection operation, the ratio controller 526 is used to multiply the setting ratio with the setting signal Itest to generate the replica leakage current ILR. The replica leakage current ILR can generate the mirrored replica leakage currents ILR0~ILRm through the mirroring action of the current mirrors 5280~528m to transmit to the first sense amplifier 5240 and the second sense amplifier 5241~524m. In this way, through the comparison results of the first sense amplifier 5240 and the second sense amplifier 5241~524m, and the ratio controller 526 gradually adjusts the setting ratio, the current simulation information of the multiple memory cell blocks corresponding to the first common bit line GBL1 and the second common bit line GBL21~GBL2m can be calculated one by one to quickly complete the leakage current detection operation. At this time, the current mirrors 5280-528m may have the same mirroring ratio, and the current simulation information corresponding to each memory cell block can be obtained only by adjusting the setting ratio.

As shown in FIG. 5B , in the programming operation after the leakage current detection operation is completed, the current mirrors 5280 to 528m may have different mirroring ratios, and the multiple mirroring ratios are respectively equivalent to multiple weight values, and respectively correspond to the current simulation information of the first memory block 5140 and the second memory block 5141 to 514m. At this time, the ratio controller 526 may fix the setting ratio at 100%, and transmit a current equal to the test current Itest to each current mirror 5280 to 528m. In this way, each current mirror 5280 to 528m may mirror the test current Itest according to the corresponding leakage current simulation information to generate compensation currents Icps0 to Icpsm respectively. The leakage current portion of the sensing current Isen0~Isem can be offset by the compensation current portion Icps0~Icpsm of the reference current Iref0~Irefm.

FIG6 is a flow chart showing a programming method of a flash memory device according to an embodiment of the present invention. Please refer to FIG1 and FIG6 simultaneously. The method of the present embodiment can be applied to the flash memory device 100 of FIG1. In step S610, in the leakage current detection operation, the leakage current IL generated by the first memory cells MC1~MCn+i-1 on the first common bit line GBL1 is detected to obtain leakage current simulation information. In step S620, the sensing amplifier device 120 provides a reference current Iref according to the leakage current simulation information, and compares the sensing current Isen generated by the selected memory cell MCT among the first memory cells MC1~MCn+i-1 on the first common bit line GBL1 with the reference current Iref to perform programming verification. The implementation details of the above steps have been fully described in the aforementioned embodiments and will not be elaborated here.

In summary, the flash memory device and programming method of the present invention can detect the leakage current generated by the memory block in advance before the programming operation to serve as leakage current simulation information. Moreover, during the programming operation, the leakage current simulation information can provide an appropriate reference current to compare with the sensed current to offset the leakage current portion of the sensed current. In this way, it is not necessary to apply more programming pulses during programming verification due to the influence of the leakage current, and it will not have a negative impact on the page programming time, thereby avoiding a decrease in the efficiency of the flash memory.

100, 500: flash memory device 110, 510: memory array 112, 5140: first memory block 120, 200, 520: sensing amplifier device 210, 5240: first sensing amplifier 220, 526: proportional controller 11~1n: division 5141~514m: second memory block 5241~524m: second sensing amplifier 5280~528m: current mirror CR: comparison result GBL1: first common bit line GBL21~GBL2m: second common bit line GND: ground voltage IL: leakage current ILR: replica leakage current ILR0~ILRm: mirrored replica leakage current Icell: cell current Icmp: comparison current Icps, Icps0~Icpsm: compensation current Iref, Iref0~Irefm: reference current Isen, Isen0~Isem: sense current Itest: test current MC1~MCn+i-1: first memory cell MCT: selected memory cell WL[0]~WL[n+i-1]: word line S410~S450, S610~S620: steps

FIG. 1 is a schematic diagram of a flash memory device according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a sensing amplifier according to an embodiment of the present invention. FIG. 3 is a schematic diagram of a reference current and a sensing current of a programming operation according to an embodiment of the present invention. FIG. 4 is a flow chart of a leakage current detection operation according to an embodiment of the present invention. FIG. 5A and FIG. 5B are schematic diagrams of a flash memory device according to an embodiment of the present invention. FIG. 6 is a flow chart of a programming method of a flash memory device according to an embodiment of the present invention.

100: Flash memory device

110:Memory array

112: First memory block

120: Sensing amplifier

11~1n: Division

GBL1: First common bit line

GND: Ground voltage

IL: Leakage current

Isen: Sense current

Itest: test current

MC1~MCn+i-1: first memory cell

MCT: Select memory cells

WL[0]~WL[n+i-1]: character line

Claims (15)

A flash memory device comprises: a memory array comprising a first memory block, the first memory block comprising a plurality of first memory cells; a first common bit line coupled to the first memory cells; and a sensing amplifier coupled to the first common bit line, wherein in a leakage current detection operation, the sensing amplifier detects leakage currents generated by the first memory cells on the first common bit line to obtain leakage current analog information, In a programming operation, the sense amplifier device provides a reference current according to the leakage current simulation information, and compares a sense current generated by a selected memory cell among the first memory cells on the first common bit line with the reference current to perform a programming verification. A flash memory device as described in claim 1, wherein the sense amplifier device comprises: a first sense amplifier having a first input terminal coupled to the first common bit line; and a proportional controller coupled to a second input terminal of the first sense amplifier, the proportional controller receiving a test current and, in the leakage current detection operation, adjusting the test current according to a set ratio to generate a replica leakage current. A flash memory device as described in claim 2, wherein in the leakage current detection operation, the first sense amplifier compares the leakage current on the first common bit line with the replica leakage current to generate a comparison result, and when the comparison result remains at a first logic level, the proportional controller adjusts the set ratio, and the first sense amplifier and the proportional controller repeatedly compare the leakage current on the first common bit line with the replica leakage current and adjust the set ratio until the comparison result transitions from the first logic level to a second logic level. The flash memory device as described in claim 3, wherein when the comparison result changes from the first logic level to the second logic level, the sensing amplifier stores the corresponding setting ratio as the leakage current simulation information. A flash memory device as described in claim 2, wherein the reference current is formed by adding a comparison current and a compensation current, and in the programming operation, the sensing amplifier device provides the compensation current according to the leakage current simulation information, and the compensation current is equivalent to the replica leakage current corresponding to the stored setting ratio. The flash memory device as described in claim 1, wherein in the leakage current detection operation, all word lines corresponding to the first memory cells are in a disabled state. The flash memory device as described in claim 1, wherein in the programming operation, the word line corresponding to the selected memory cell is in an enabled state, and the word lines corresponding to the remaining first memory cells are in a disabled state. The flash memory device as described in claim 1 further includes a plurality of second common bit lines, the memory array further includes a plurality of second memory blocks, each of the second memory blocks includes a plurality of second memory cells, each of the second memory cells is coupled to the corresponding second common bit line, the sensing amplifier device further includes a plurality of second sensing amplifiers and a plurality of current mirrors, the first input end of each of the second sensing amplifiers is coupled to the corresponding second common bit line, the current mirrors are respectively coupled to the second input end of the first sensing amplifier and the second input end of the second sensing amplifiers, and in the programming operation, each of the current mirrors mirrors a test current according to the corresponding leakage current simulation information to generate a respective compensation current. A programming method for a flash memory device, the flash memory device includes a memory array, the memory array includes a first memory block having a plurality of first memory cells, each of the first memory cells is coupled to a first common bit line, wherein the programming method includes the following steps: In a leakage current detection operation, the leakage current generated by the first memory cells on the first common bit line is detected to obtain a leakage current simulation information; and In a programming operation, a reference current is provided according to the leakage current simulation information, and a sensed current generated by a selected memory cell among the first memory cells on the first common bit line is compared with the reference current to perform a programming verification. A programming method for a flash memory device as described in claim 9, wherein in the leakage current detection operation, the step of detecting the leakage current generated by the first memory cells on the first common bit line to obtain the leakage current simulation information includes: Receiving a test current, and in the leakage current detection operation, adjusting the test current according to a set ratio to generate a replica leakage current. The programming method of the flash memory device as described in claim 10, wherein in the leakage current detection operation, the step of detecting the leakage current generated by the first memory cells on the first common bit line to obtain the leakage current simulation information further includes: In the leakage current detection operation, the leakage current on the first common bit line is compared with the replica leakage current to generate a comparison result; When the comparison result maintains a first logic level, the setting ratio is adjusted; and Repeating the comparison step and the step of adjusting the setting ratio until the comparison result is converted from the first logic level to a second logic level. The programming method of the flash memory device as described in claim 11, wherein in the leakage current detection operation, the step of detecting the leakage current generated by the first memory cells on the first common bit line to obtain the leakage current simulation information further includes: When the comparison result is converted from the first logic level to the second logic level, the corresponding setting ratio is stored as the leakage current simulation information. A programming method for a flash memory device as described in claim 10, wherein the reference current is formed by adding a comparison current and a compensation current, and in the programming operation, the step of providing the reference current according to the leakage current simulation information includes: Providing the compensation current according to the leakage current simulation information, the compensation current being equal to the replica leakage current corresponding to the stored setting ratio. A programming method for a flash memory device as described in claim 9, wherein in the leakage current detection operation, all word lines corresponding to the first memory cells are in a disabled state, wherein in the programming operation, the word line corresponding to the selected memory cell is in an enabled state, and the word lines corresponding to the remaining first memory cells are in a disabled state. A programming method for a flash memory device as described in claim 9, wherein the memory array further includes a plurality of second memory blocks, each of the second memory blocks includes a plurality of second memory cells, each of the second memory cells is coupled to the corresponding second common bit line, and the programming method further includes: In the programming operation, a test current is mirrored by a plurality of current mirrors according to the corresponding leakage current simulation information to generate a respective compensation current.

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