TW202416274A - Memory card device - Google Patents

Abstract

The present invention discloses a memory card device. The memory card device comprises a data storage unit, a first pin group, a second pin group and a control unit. The data storage unit storages a data base. The first pin group comprises a plurality of data transmission pin electrically connected with the data storage unit for transmitting the data base. The second pin group comprises a plurality of operation pins. One of the plurality of operation pins receives and transmits a trigger signal selectively provided from a host. The control unit is electrically connected with the data storage unit and the second pin group. The control unit controls the data storage unit to execute a read and write operation to the data base, or the control unit receives the trigger signal to execute a data erase operation to the data base.

Description

Memory card device

This case pertains to the field of data storage, and in particular to a memory card device.

Memory card devices are used to store data. There are two types of memory card devices. The first type is a memory card device that has only a bus with a single transmission speed standard, and the memory card device uses the bus with a single transmission speed standard to transmit data. When a user wants to use a different transmission speed, he can only choose another memory card device with a bus with a different transmission speed, which makes the applicability of the memory card device lower. In order to improve the applicability of the memory card device, the second type is a memory card device having two transmission speed standard buses at the same time, so that the memory card device can only use the bus of one of the two transmission speed standards for data transmission. Since this method only uses one of the two sets of buses, the efficiency of the bus usage on this memory card device will be reduced. In addition, when the above two types of memory card devices want to delete the data stored inside, in addition to using the software erase method, an additional pin can be set on the memory card device, and then a removal signal can be received through this pin to physically destroy the data on the memory device. However, the above methods will reduce the convenience of setting up the memory card device.

Therefore, how to develop a memory card device that overcomes the above-mentioned shortcomings is currently an urgent need.

The purpose of the present invention is to provide a memory card device, comprising two groups of pins, namely a first group of pins and a second group of pins. At least one of the plurality of data transmission pins of the first group of pins is used to transmit data in a data storage unit, and any one of the plurality of operation pins of the second group of pins is used to transmit a trigger signal provided by a host device. The control unit performs a data removal operation on the data storage unit by providing a signal, or provides a high voltage signal to destroy the NAND flash memory to perform a data removal operation on the data, which means that the two group pins with different transmission speed standards have the data transmission function and the data removal function respectively, so the memory card device of this case has a higher usage efficiency. And the memory card device of this case uses the existing pins to perform the data removal function without the need for additional pins, so the memory card device of this case is more convenient.

To achieve the above-mentioned purpose, one embodiment of the present case is a memory card device, comprising a data storage unit, a first group of pins, a second group of pins and a control unit. The data storage unit is used to store data. The first group of pins includes a plurality of data transmission pins, which are electrically connected to the data storage unit for transmitting data. The second group of pins includes a plurality of operation pins, one of which receives and transmits a trigger signal selectively provided by a host device. The control unit is electrically connected to the data storage unit and the second group of pins, wherein the control unit controls the data storage unit to perform read and write operations on the data, or the control unit receives the trigger signal and performs a data removal operation on the data.

To achieve the above-mentioned purpose, another embodiment of the present case is a memory card device, comprising a data storage unit, a first group of pins and a second group of pins. The data storage unit is used to store data. The first group of pins includes a plurality of data transmission pins, which are electrically connected to the data storage unit and used to transmit data. The second group of pins includes a plurality of operation pins, which are electrically connected to the data storage unit, wherein one of the plurality of operation pins receives and transmits a selectively provided high voltage signal, wherein when the operation pin transmits the high voltage signal, the data storage unit performs a physical destruction operation.

Some typical embodiments that embody the features and advantages of the present invention will be described in detail in the following description. It should be understood that the present invention can have various variations in different aspects without departing from the scope of the present invention, and the descriptions and drawings are essentially for illustrative purposes rather than for limiting the present invention.

Please refer to FIG. 1 and FIG. 2, where FIG. 1 is a schematic diagram of the structure of the memory card device of the first embodiment of the present invention, and FIG. 2 is a schematic diagram of the circuit structure of the memory card device shown in FIG. As shown in FIG. 1 and FIG. 2, the memory card device 1 of the present embodiment can be but is not limited to a secure digital card (SD Card), and includes a body 2, a data storage unit 3, a first group of pins 4, a second group of pins 5, and a control unit 6. The body 2 includes a first surface 21, a second surface, a first side 22, a second side 23, a third side 24 and a fourth side 25, wherein the first surface 21 is opposite to the second surface, the first side 22 is opposite to the third side 24, the second side 23 is opposite to the fourth side 25, the second side 23 is connected between the first side 22 and the third side 24, and the fourth side 25 is connected between the first side 22 and the third side 24. The first side 22 is a long side, and the second side 23 is a wide side. The data storage unit 3 is disposed in the body 2 to store data. The first group of pins 4 is disposed on the main body 2 and includes a plurality of data transmission pins 41, wherein each data transmission pin 41 is at least partially exposed to the first surface 21, and the transmission speed of each data transmission pin 41 can be but is not limited to being defined according to the SD transmission speed standard, and the plurality of data transmission pins 41 are substantially arranged along the first row L1 of the main body 2, wherein the first row L1 is parallel to the second side 23. At least one data transmission pin 41 among the plurality of data transmission pins 41 is electrically connected to the data storage unit 3, wherein FIG. 2 takes one of the plurality of data transmission pins 41 as an example in which the data transmission pin 41 is electrically connected to the data storage unit 3. Of course, the number and position of the data transmission pins 41 electrically connected to the data storage unit 3 are not limited to those shown in FIG. 2.

The function of each of the plurality of root data transmission pins 41 may be the same as or different from the functions of other root data transmission pins 41. In some embodiments, at least one of the plurality of root data transmission pins 41 is electrically connected between the data storage unit 3 and a host device (not shown), such as but not limited to a computer, and the data transmission pin 41 is used to transmit data between the data storage unit 3 and the host device. In one embodiment, the first group of pins 4 includes nine data transmission pins 41, which are numbered as pin 1, pin 2, pin 3, pin 4, pin 5, pin 6, pin 7, pin 8 and pin 9. From the first side 22 to the third side 24, the plurality of data transmission pins 41 of the first group of pins 4 are arranged in the order of pin 9, pin 1, pin 2, pin 3, pin 4, pin 5, pin 6, pin 7 and pin 8, wherein the description or definition of each pin is recorded in the following Table 1. Pin Number Data transmission pins defined by the SD transmission standard Name Type describe Pin 1 CD/DAT3 I/O/PP Card detection/data line [bit 3] Pin 2 CMD PP Command/Response Pin 3 VSS1 S Supply voltage ground Pin 4 VDD S Supply voltage Pin 5 CLK I Pulse Pin 6 VSS2 S Supply voltage ground Pin 7 DAT0 I/O/PP Data line [bit 0] Pin 8 DAT1 I/O/PP Data line [bit 1] Pin 9 DAT2 I/O/PP Data line [bit 2] Table I

The second group of pins 5 is disposed on the body 2 and includes a plurality of operating pins 51, wherein each operating pin 51 is at least partially exposed to the first surface 21. The transmission speed provided by the plurality of operating pins 51 of the second group of pins 5 is different from the transmission speed provided by the plurality of data transmission pins 41 of the first group of pins 4. For example, the transmission speed of the plurality of operating pins 51 of each second group of pins 5 may be but is not limited to that defined according to the UHS-II transmission speed standard, and the plurality of operating pins 51 are substantially arranged along the second row L2 of the body 2, wherein the second row L2 is parallel to the second side 23 and the first row L1.

The function of each of the plurality of root operation pins 51 may be the same as or different from the functions of other root operation pins 51, wherein any one of the plurality of root operation pins 51 is electrically connected to the host device, wherein the host device may selectively provide a trigger signal as required, for example, providing a trigger signal when data in the data storage unit 3 is to be deleted, and the operation pin 51 may receive and transmit the trigger signal provided by the host device. In one embodiment, the second group pin 5 includes eight data transmission pins 51, which are numbered as pin 10, pin 11, pin 12, pin 13, pin 14, pin 15, pin 16, and pin 17. From the first side 22 to the third side 24, the plurality of pins 51 of the second group pin 5 are arranged in the order of pin 10, pin 11, pin 12, pin 13, pin 14, pin 15, pin 16, and pin 17. Pin Number Based on the operation pins defined by the UHS-II transmission standard Name Type describe Pin 10 Hi-V_GND S High voltage ground Pin 11 D0+ LVDS without Pin 12 D0- LVDS without Pin 13 Hi-V_GND S High voltage ground Pin 14 Hi-Vin S Supply high voltage Pin 15 D1- LVDS without Pin 16 D1+ LVDS without Pin 17 QE I Trigger signal Table II

The control unit 6 is electrically connected to the data storage unit 3 and the second group pin 5, wherein FIG. 2 takes one of the plurality of operation pins 51 as an example of being electrically connected to the control unit 6. Of course, the number and position of the operation pins 51 electrically connected to the control unit 6 are not limited to those shown in FIG. 2. In one embodiment, the 17th pin is connected to the control unit 6.

The control unit 6 controls the data storage unit 3 to perform a read/write operation on the data to identify the data or write new data. When the operation pin 51 transmits a trigger signal provided by the host device, the control unit 6 receives the trigger signal transmitted by the operation pin 51 and performs a data removal operation on the data. The data removal operation may include a data erase operation. The control unit 6 removes the data in the data storage unit 3 according to the data erase operation. Alternatively, in other embodiments, the transmission speed of the first group of pins 4 may be defined according to the UHS-II transmission speed standard, and the transmission speed of the second group of pins 5 may be defined according to the SD transmission speed standard.

Specifically, when the first group of pins 4 is a pin defined by the current UHS-II transmission standard (i.e., the 10th to 17th pins mentioned above), the second group of pins 5 is a pin defined by the current SD transmission standard (i.e., the 1st to 9th pins mentioned above). Generally speaking, when the host device uses the UHS-II communication protocol to transmit data with the memory device 1, the trigger signal can be received through the pin defined by the current SD transmission standard. Conversely, when the host device uses the SD communication protocol to transmit data with the memory device 1, the trigger signal can be received through the pin defined by the current UHS-II transmission standard, thereby increasing the flexibility of use of the memory device.

As can be seen from the above, the memory card device 1 of the present case includes two group pins, namely the first group pin 4 and the second group pin 5. At least one of the plurality of data transmission pins 41 of the first group pin 4 is used to transmit data in the data storage unit 3, and any one of the plurality of operation pins 51 of the second group pin 5 is used to transmit data from the host. The trigger signal provided by the device enables the control unit 6 to perform a data removal operation on the data of the data storage unit 3, which means that the two group pins with different transmission speed standards have the data transmission function and the data removal function respectively. Therefore, compared with the traditional memory card device that only has one bus to operate, the memory card device 1 of this case has a higher utilization efficiency. In addition, the memory card device 1 of this case uses the existing pins to perform the data removal function without the need for additional pins, so the memory card device 1 of this case is more convenient.

Please refer to FIG. 3, which is a schematic diagram of the circuit structure of the memory card device of the second embodiment of the present invention. As shown in the figure, compared with the memory card device 1 of FIG. 2, the memory card device 1a of the present embodiment further includes a general-purpose input/output pin (GPIO) 7. The general-purpose input/output pin 7 is electrically connected between the control unit 6 and one of the operating pins 51 of the second group of pins 5, for example, between the control unit 6 and the 17th pin, wherein the general-purpose input/output pin 7 can be set to be exposed on the first surface 21 or embedded in the body 2. The universal input output pin 7 receives the trigger signal transmitted by the operation pin 51 of the second group pin 5 and transmits it to the control unit 6, so that the control unit 6 performs a data removal operation on the data of the data storage unit 3 according to the trigger signal. In some embodiments, the universal input output pin 7 further communicates with the host device, so that the host device can control the operation state of the universal input output pin 7 and further control whether the trigger signal of the operation pin 51 can be transmitted to the control unit 6, for example, the host device controls the universal input output pin 7 to be turned on so that the trigger signal of the operation pin 51 is transmitted to the control unit 6, or the host device controls the universal input output pin 7 to be turned off so that the trigger signal of the operation pin 51 cannot be transmitted to the control unit 6. The data storage unit 3 of the present embodiment may be further constituted by a NAND flash memory, wherein the data erasure operation may include a NAND destroying action, and the control unit 6 destroys the NAND flash memory constituting the data storage unit 3 according to the NAND destroying action in the data erasure operation, thereby erasing the data in the data storage unit 3. In some embodiments, the control unit 6 further receives a vendor command provided by the host device, and the control unit 6 sets the original function of each operation pin 51 in the second group of pins 5 to be disabled according to the vendor command, and controls any one of the plurality of operation pins 51 to transmit a trigger signal, thereby specifying the position of the operation pin 51 that transmits the trigger signal.

Please refer to FIG. 4, which is a schematic diagram of the circuit structure of the memory card device of the third embodiment of the present invention. As shown in the figure, the memory card device 1b of the present embodiment includes a body 2, a data storage unit 3, a first group of pins 4, a second group of pins 5, a control unit 6, a first switch unit 91 and a second switch unit 92. The body 2, the data storage unit 3, the first group of pins 4 and the second group of pins 5 of the memory card device 1b of the present embodiment are similar to the body 2, the data storage unit 3, the first group of pins 4 and the second group of pins 5 shown in FIG. 2, so they are not described in detail here. The first switch unit 91 may be, but is not limited to, a diode. One end of the first switch unit 91 is electrically connected to at least one data transmission pin 41, such as the fourth pin, among the plurality of data transmission pins 41 for providing a supply voltage. The other end of the first switch unit 91 is electrically connected to the control unit 6 and the data storage unit 3. The first switch unit 91 further communicates with the host device so that the host device can control the operation state of the first switch unit 91. It further controls whether the supply voltage provided by the data transmission pin 41 can be transmitted to the control unit 6 and the data storage unit 3. For example, the host device controls the first switch unit 91 to be turned on so that the control unit 6 and the data storage unit 3 can receive the supply voltage provided by the data transmission pin 41, or the host device controls the first switch unit 91 to be turned off so that the control unit 6 and the data storage unit 3 cannot receive the supply voltage provided by the data transmission pin 41.

The second switch unit 92 may be, but is not limited to, a diode and/or a fuse. One end of the second switch unit 92 is electrically connected to one of the plurality of operation pins 51, such as the 14th pin. The other end of the second switch unit 92 is electrically connected to the data storage unit 3, wherein the 14th pin is further electrically connected to the host device. The host device or an external person may selectively provide a high voltage signal according to demand. The following is based on the host device. For example, when the device selectively provides a high-voltage signal, when the host device does not provide a high-voltage signal and the 14th pin cannot transmit a high-voltage signal, the second switch unit 92 is turned on and the data storage unit 3 can operate normally. When the operation pin 51 provides a high-voltage signal and the 14th pin transmits a high-voltage signal, the second switch unit 92 is closed and the data storage unit 3 performs a physical destruction operation, causing the data in the data storage unit 3 to perform a data removal operation.

In summary, the memory card device of the present invention comprises two groups of pins, namely a first group of pins and a second group of pins. At least one of the plurality of data transmission pins of the first group of pins is used to transmit data in the data storage unit, and any one of the plurality of operation pins of the second group of pins transmits a trigger signal provided by the host device. The control unit performs a data removal operation on the data of the data storage unit, or provides a high voltage signal to destroy the NAND flash memory and then performs a data removal operation on the data, which means that the two groups of pins with different transmission speed standards have data transmission functions and data removal functions respectively, so the memory card device of this case has a higher usage efficiency. In addition, the memory card device of this case uses the existing pins to perform the data removal function without the need for additional pins, so the memory card device of this case is more convenient.

1, 1a, 1b: memory card device 2: body 21: first surface 22: first side 23: second side 24: third side 25: fourth side L1: first row L2: second row 3: data storage unit 4: first group pin 41: data transmission pin 5: second group pin 51: operation pin 6: control unit 7: general input and output pin 91: first switch unit 92: second switch unit

FIG. 1 is a schematic diagram of the structure of the memory card device of the first embodiment of the present invention. FIG. 2 is a schematic diagram of the circuit structure of the memory card device shown in FIG. 1. FIG. 3 is a schematic diagram of the circuit structure of the memory card device of the second embodiment of the present invention. FIG. 4 is a schematic diagram of the circuit structure of the memory card device of the third embodiment of the present invention.

1: Memory card device

2: Body

21: First surface

22: First side

23: Second side

24: The third side

25: Fourth side

L1: First column

L2: Second column

3: Data storage unit

4: The first group of pins

41: Data transmission pin

5: Second group of pins

51: Operation pin

6: Control unit

Claims (10)

A memory card device comprises: a data storage unit for storing data; a first group of pins comprising a plurality of data transmission pins electrically connected to the data storage unit for transmitting the data; a second group of pins comprising a plurality of operation pins, wherein one of the plurality of operation pins receives and transmits a trigger signal selectively provided by a host device; and a control unit electrically connected to the data storage unit and the second group of pins, wherein the control unit controls the data storage unit to perform a read/write operation on the data, or the control unit receives the trigger signal and performs a data removal operation on the data. A memory card device as described in claim 1, wherein the transmission speed of each of the data transmission pins in the first group of pins is defined according to the SD transmission speed standard, and the transmission speed of each of the operation pins in the second group of pins is defined according to the UHS-II transmission speed standard. A memory card device as described in claim 1, wherein the transmission speed of each of the data transmission pins in the first group of pins is defined according to the UHS-II transmission speed standard, and the transmission speed of each of the operation pins in the second group of pins is defined according to the SD transmission speed standard. A memory card device as described in claim 1, wherein the memory card device includes a universal input/output pin electrically connected between the control unit and the second group of pins, wherein the universal input/output pin is used to communicate with the host device, and the universal input/output pin receives the trigger signal to transmit to the control unit so that the control unit performs the data removal operation on the data according to the trigger signal. A memory card device as described in claim 1, wherein the data removal operation includes a data erase action, and the control unit removes the data in the data storage unit according to the data erase action. A memory card device as described in claim 1, wherein the control unit further receives a supplier instruction provided by the host device, and the control unit sets the original function of each of the operating pins in the second group of pins to be disabled according to the supplier instruction, and controls any one of the plurality of operating pins to send the trigger signal. A memory card device comprises: a data storage unit for storing data; a first group of pins comprising a plurality of data transmission pins electrically connected to the data storage unit for transmitting the data; and a second group of pins comprising a plurality of operation pins electrically connected to the data storage unit, wherein one of the plurality of operation pins receives and transmits a selectively provided high voltage signal, wherein when the operation pin transmits the high voltage signal, the data storage unit performs a physical destruction operation. A memory card device as described in claim 7, wherein the memory card device includes a second switch unit, one end of the second switch unit is electrically connected to an operating pin electrically connected to a host device, and the other end of the second switch unit is electrically connected to the data storage unit, wherein when the host device does not provide the high-voltage signal and the operating pin cannot transmit the high-voltage signal, the second switch unit is turned on and the data storage unit can operate normally, and when the host device provides the high-voltage signal and the operating pin transmits the high-voltage signal, the second switch unit is closed and the data storage unit performs the physical destruction operation. A memory card device as described in claim 7, wherein the transmission speed of each of the data transmission pins in the first group of pins is defined according to the SD transmission speed standard, and the transmission speed of each of the operating pins in the second group of pins is defined according to the UHS-II transmission speed standard. A memory card device as described in claim 7, wherein the transmission speed of each data transmission pin in the first group of pins is defined according to the UHS-II transmission speed standard, and the transmission speed of each operation pin in the second group of pins is defined according to the SD transmission speed standard.

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