TW202414853A - Light-emitting device and manufacturing method thereof - Google Patents

Abstract

A light-emitting device includes: a semiconductor stack, including: a first semiconductor layer with a first conductivity type; an intermediate structure formed on the first semiconductor layer; an active region formed on the intermediate structure and having an upper surface; a second semiconductor with a second conductivity type different from the first conductivity type formed on the active region; and a plurality of recesses formed in the active region, and wherein each of the recess has an opening on the upper surface of the active region and a width of the opening is between 20 nm and 100 nm; a distribution density of the plurality of recesses on the upper surface is less than 2×10 ⁸cm ^-2; and the light-emitting device has a hot/cold factor (85°C to 25°C) of light output power greater than or equal to 95% when operated under a current density of 75A/cm ²or more.

Description

Light emitting element and method for manufacturing the same

The present application relates to a light-emitting element and a manufacturing method thereof, and in particular to a light-emitting element and a manufacturing method thereof with improved thermal light-emitting efficiency.

Solid-state semiconductor components such as light-emitting diodes (LEDs) have the advantages of low power consumption, low heat generation, long service life, shock resistance, small size, fast response speed and good photoelectric properties, such as stable luminous wavelength. Therefore, LEDs are widely used in household appliances, equipment indicator lights, and optoelectronic products. Generally speaking, in the method of manufacturing light-emitting diodes, a III-V semiconductor stack is formed on a growth substrate by using methods such as epitaxial growth. However, when the selected growth substrate material and the III-V semiconductor material are heterogeneous materials, defects may be generated in the semiconductor stack due to the lattice mismatch between the materials.

A light-emitting element comprises: a semiconductor stack, comprising: a first semiconductor layer having a first conductivity type; an intermediate structure located on the first semiconductor layer; an active region located on the intermediate structure and comprising an upper surface; a second semiconductor layer located on the active region and having a second conductivity type different from the first conductivity type; and a plurality of concave portions in the active region, each having an opening on the upper surface of the active region; wherein the width of the opening is between 20 nm and 100 nm; the distribution density of the plurality of concave portions on the upper surface is less than 2×10 ⁸ cm ^-2 ; and the ratio of the hot luminous efficiency of the light-emitting element at 85°C to the cold luminous efficiency at 25°C is greater than or equal to 95% at an operating current density of more than ⁷⁵ A/cm 2.

The following embodiments will be accompanied by drawings and descriptions, in which similar or identical parts are labeled with the same reference numerals, and in the drawings, the shape or thickness of the components may be enlarged or reduced. It should be noted that components not shown in the drawings or described in the description may be in forms known to those skilled in the art. In addition, other layers/structures or steps may be incorporated in the following embodiments. For example, the description of "forming a second layer/structure on a first layer/structure" may include an embodiment in which the first layer/structure directly contacts the second layer/structure, or an embodiment in which the first layer/structure indirectly contacts the second layer/structure, that is, other layers/structures exist between the first layer/structure and the second layer/structure. In addition, the spatial relative relationship between the first layer/structure and the second layer/structure may change according to the operation or use of the device. The first layer/structure itself is not limited to a single layer or a single structure. The first layer may include multiple sub-layers, and the first structure may include multiple sub-structures.

In addition, for the spatially related descriptive terms mentioned in this application, such as "under", "low", "below", "above", "upper", "lower", "top", "bottom" and similar terms, for the convenience of description, their usage is to describe the relative relationship between one element or feature and another element or feature in the drawings. In addition to the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientations of the semiconductor stack and the light-emitting element during use and operation. As the orientation of the semiconductor element is different (rotated 90 degrees or other orientations), the spatially related statements used to describe its orientation should also be interpreted in a similar manner.

In this application, if there is no special explanation, the general formula AlGaN series represents Al _a Ga _(1-a) N, where 0≤a≤1; the general formula InGaN series represents In _b Ga _(1–b) N, where 0≤b≤1; the general formula AlInGaN series represents Al _c In _d Ga _{(1 - cd)} N, where 0≤c≤1, 0≤d≤1. Adjusting the content of the elements can achieve different purposes, such as but not limited to adjusting the energy level or adjusting the main emission wavelength of the light-emitting element.

The composition and doping of each layer included in the light-emitting device disclosed in this application can be analyzed by any suitable method, such as secondary ion mass spectrometer (SIMS).

The thickness of each layer included in the light-emitting element disclosed in this application can be analyzed by any suitable method, such as transmission electron microscopy (TEM) or scanning electron microscope (SEM), so as to match the depth position of each layer on the SIMS spectrum, for example.

FIG1 shows a light emitting device 1 according to the first embodiment of the present application. The light emitting device 1 comprises a substrate 10 and a semiconductor stack 12 located on the substrate 10. The semiconductor stack 12 comprises a buffer structure 40, a first semiconductor contact layer 121, an intermediate structure 50, an active region 123, an electron blocking region 70 and a second semiconductor contact layer 122 in order from the substrate 10 upward, that is, in the thickness direction thereof. The first semiconductor contact layer 121 includes a first conductive type impurity, and the second semiconductor contact layer 122 includes a second conductive type impurity, wherein the first conductive type impurity and the second conductive type impurity make the first semiconductor contact layer 121 and the second semiconductor contact layer 122 have different conductivity types, electrical properties, polarities, or are used to provide electrons or holes respectively. In one embodiment, the first conductive type impurity includes a Group IV element, such as silicon, and the second conductive type impurity includes a Group II element, such as magnesium. The first semiconductor contact layer 121 and the second semiconductor contact layer 122 may also contain impurities of more than one element, such as carbon, hydrogen, oxygen, or a combination thereof. A plurality of recesses 11 are located in the active region 123, and each has an opening on the upper surface 123a of the active region 123. In one embodiment, the opening width of the recess 11 on the upper surface 123a of the active region is between 20 nm and 100 nm, and the distribution density of the plurality of V-shaped recesses 11 on the upper surface 123a of the active region is less than 2×10 ⁸ cm ^-2 , thereby improving the thermal luminous efficiency of the light-emitting element 1, and the details will be described later. The first electrode 20 is electrically connected to the first semiconductor contact layer 121, and the second electrode 30 is electrically connected to the second semiconductor contact layer 122.

In one embodiment, the semiconductor stack 12 can be formed on the substrate 10 by epitaxial growth. The substrate 10 includes a sapphire (Al ₂ O ₃ ) substrate, a gallium nitride (GaN) substrate, a silicon (Si) substrate, a silicon carbide (SiC) substrate, and an aluminum nitride (AlN) substrate. In one embodiment, the substrate 10 can be a patterned substrate, that is, the substrate 10 has a patterned structure (not shown) on the surface where the semiconductor stack 12 is located. The light emitted from the semiconductor stack 12 can be refracted, scattered or reflected by the patterned structure of the substrate 10, thereby improving the brightness of the light-emitting element.

In any embodiment of the present application, the method of performing epitaxial growth includes but is not limited to metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), physical vapor deposition (PVD), and liquid-phase epitaxy (LPE).

The wavelength of light emitted by the light-emitting element 1 is adjusted by changing the physical and chemical composition of one or more layers in the semiconductor stack 12. The material of the epitaxial stack includes III-V semiconductor materials, such as InGaN series materials, AlGaN series materials or AlInGaN series materials. When the material of the active region 123 is InGaN series materials, blue light with a wavelength between 400 nm and 490 nm, cyan light with a wavelength between 490 nm and 530 nm, or green light with a wavelength between 530 nm and 570 nm can be emitted. When the material of the active region 123 is AlGaN series or AlInGaN series materials, ultraviolet light with a wavelength between 400 nm and 250 nm can be emitted.

The buffer structure 40 can reduce the dislocation caused by lattice mismatch between the substrate 10 and the semiconductor stack 12, thereby improving the epitaxial quality. The buffer structure 40 includes a single layer, or includes multiple layers (not shown). In one embodiment, the buffer structure 40 includes Al _i Ga _(1–i) N, where 0≤i≤1. In one embodiment, the material of the buffer structure 40 includes GaN. In another embodiment, the material of the buffer structure 40 includes AlN. The buffer structure 40 can be formed by MOCVD, MBE, HVPE or PVD. PVD includes sputtering or electron beam evaporation. When the buffer structure 40 includes multiple layers (not shown), each layer includes the same material or different materials. In one embodiment, the buffer structure 40 includes two layers, wherein the first layer is grown by sputtering and the second layer is grown by MOCVD. In one embodiment, the buffer structure 40 further includes a third layer. The third layer is grown by MOCVD, and the growth temperature of the second layer is higher or lower than the growth temperature of the third layer. In one embodiment, the first, second and third layers include the same material, such as AlN, or different materials, such as a combination of AlN, GaN and AlGaN. In other embodiments, PVD-aluminum nitride (PVD-AlN) is used as the buffer layer, and the target material for forming PVD-aluminum nitride is composed of aluminum nitride, or a target material composed of aluminum is used and aluminum nitride is reactively formed in a nitrogen source environment.

In one embodiment, the buffer structure 40 may be undoped (i.e., not intentionally doped). In another embodiment, the buffer structure 40 may include dopants such as silicon, carbon, hydrogen, oxygen, or a combination thereof. In some embodiments, when the buffer structure 40 includes multiple layers and includes first conductive type impurities, the concentration of the first conductive type impurities in a layer close to the first semiconductor contact layer 121 is greater than the concentration of the first conductive type impurities in a layer far from the first semiconductor contact layer 121. For example, the concentration of the first conductive type impurities in a layer close to the first semiconductor contact layer 121 is greater than 1×10 ¹⁸ /cm ³ , and the concentration of the first conductive type impurities in a layer far from the first semiconductor contact layer 121 is less than 1×10 ¹⁷ /cm ³ . The buffer structure 40 can reduce the chance of defects D caused by lattice mismatch between the substrate 10 and the semiconductor stack 12 propagating upward to the active region 123. When the buffer structure 40 does not include the first conductive type impurities, the excellent crystallinity of the buffer structure 40 can be maintained. In addition, when the buffer structure 40 does not include the first conductive type impurities, the difference in thermal expansion coefficient between it and the substrate 10 can be reduced, thereby reducing the stress caused by the high temperature process of epitaxy and reducing the probability of dislocation generation. Therefore, it is preferred that the buffer structure 40 does not include the first conductive type impurities, and the defects in the buffer structure 40 are reduced by increasing the thickness of the buffer structure 40. However, if the thickness of the buffer structure 40 is increased to a certain extent, the effect of the increase in the thickness of the buffer structure 40 corresponding to the reduction of its defects is saturated. Therefore, the thickness of the buffer structure 40 is preferably greater than or equal to 2 μm and less than or equal to 8 μm, preferably less than or equal to 6 μm, and more preferably less than or equal to 4 μm. In one embodiment, when the substrate 10 includes a patterned structure, the thickness of the buffer structure 40 is preferably thicker than the height of the patterned structure to completely cover the patterned structure and form a flat surface.

The material of the first semiconductor contact layer 121 includes _{AlxInyGa (1 - xy)} N _, where 0≦x≦1, 0≦y≦1. In one embodiment, the first semiconductor contact layer 121 includes AlGaN series materials and does not include indium (In). The first semiconductor contact layer 121 and the buffer structure 40 may be the same or different materials and have different doping concentrations. The first semiconductor contact layer 121 may be an n-type semiconductor layer. The first conductivity type impurity concentration of the first semiconductor contact layer 121 is greater than the first conductivity type impurity concentration of the buffer structure 40. The first conductivity type impurity concentration of the first semiconductor contact layer 121 is greater than 1×10 ¹⁸ /cm ³ , preferably greater than 1×10 ¹⁹ /cm ³ , and more preferably between 1×10 ¹⁹ /cm ³ and 5×10 ²² /cm ³ (both inclusive). The first semiconductor contact layer 121 may be a single layer, or a plurality of regions may be formed by a plurality of growth steps. The plurality of regions may have the same or different material compositions, and the plurality of regions may have the same thickness or different thicknesses. In one embodiment, the first semiconductor contact layer 121 may include a first contact sublayer (not shown) and a second contact sublayer (not shown) alternately stacked 5-40 times. The first contact sublayer comprises Al _x Ga _{(1 − x)} N, wherein 0 x 1; _the second contact sublayer comprises _{AlyGa1 - yN} , where 0 y 1 and y≠x. For example, the material of the first contact sublayer is gallium nitride (GaN), and the second contact sublayer is aluminum gallium nitride (AlGaN). The first contact sublayer has a higher first conductivity type impurity concentration, and the second contact sublayer has a lower first conductivity type impurity concentration, thereby improving the lateral current dispersion, thereby improving the anti-electrostatic discharge (ESD) damage ability and light-emitting efficiency of the light-emitting element 1. The thickness of the first contact sublayer and the second contact sublayer is 10 nm-100 nm. In another embodiment, in the process of growing the first semiconductor contact layer 121, growth condition parameters such as doping concentration, temperature or pressure can be adjusted. The modulation method may be periodic or non-periodic to form a plurality of periodic or non-periodic regions. In one embodiment, the first semiconductor contact layer 121 may include a first contact region (not shown) and a second contact region (not shown) alternately stacked multiple times, wherein the first contact region and the second contact region include different first conductivity type impurity concentrations, or other different impurity concentrations, such as carbon concentrations.

As shown in FIG1 , the intermediate structure 50 is located between the first semiconductor contact layer 121 and the active region 123. The intermediate structure 50 includes, from bottom to top, a second intermediate layer 50a, a stress buffer layer 50c, and a first intermediate layer 50b. In one embodiment, the growth conditions of the first semiconductor contact layer 121, such as temperature, pressure, ratio and flow rate of the organic metal reaction source, are different from those of the active region 123. Therefore, in order to reduce the instability of the growth environment caused by the difference in growth conditions between the first semiconductor contact layer 121 and the active region 123 and avoid the generation of new differences therein, thereby affecting the epitaxial quality, the intermediate structure 50 can be used as a conversion structure between the first semiconductor contact layer 121 and the active region 123 to maintain good epitaxial quality. In one embodiment, the buffer structure 40 and the first semiconductor contact layer 121 grow at a first growth rate under a first temperature condition. The intermediate structure 50 grows at a second growth rate under a second temperature condition. The active region 123 grows at a third growth rate under a third temperature condition. The first temperature is higher than the second temperature, and the second temperature is higher than or equal to the third temperature. In one embodiment, the first temperature is a high temperature between 1000 degrees and 1300 degrees. Before growing the active region 123, the growth temperature can be adjusted to a lower temperature environment to gently connect the growth of the active region 123 and maintain the epitaxial quality of the active region 123. In one embodiment, the intermediate structure 50 can be used as a transition region for the conversion of the growth temperature of the first semiconductor contact layer 121 and the active region 123. The growth temperature of the intermediate structure 50 is 150-350 degrees lower than the growth temperature of the buffer structure 40 or the first semiconductor contact layer 121, for example, between 700-950 degrees. In one embodiment, the growth temperature of the intermediate structure 50 is similar to or the same as the growth temperature of the active region 123; for example, the difference between the highest growth temperature of the intermediate structure 50 and the highest growth temperature of the active region 123 does not exceed 100 degrees, and the difference between the lowest growth temperature of the intermediate structure 50 and the lowest growth temperature of the active region 123 does not exceed 100 degrees. In another embodiment, there are many dislocations in the buffer structure 40 due to the mismatch of lattice constants between the buffer structure 40 and the substrate 10, and some of the dislocations will extend into the first semiconductor contact layer 121 when it is subsequently grown. In addition, during the subsequent epitaxial layer growth, due to differences in growth conditions, materials, or doping concentrations, stress is accumulated in the epitaxial stack. After a certain amount of stress is accumulated, a V-shaped recess is gradually formed in the epitaxial layer. The V-shaped recess of the bottom layer will extend to the upper layer, such as the plurality of recesses 11 in the active region 123. When there are too many V-shaped recesses in the semiconductor stack and/or the size of the V-shaped recesses is too large, the V-shaped recesses may form leakage paths, and the light-emitting efficiency of the light-emitting element is likely to decrease as the operating temperature increases under high current operation, and the light-emitting efficiency loss is more serious as the operating current density increases. However, the V-shaped recesses can also serve as carrier discharge paths when the element is subjected to electrostatic surges or large current injection. When there are too few or no V-shaped recesses in the semiconductor stack and/or the size of the V-shaped recesses is too small, the reliability of the element will be affected. Therefore, by adjusting the stress in the dislocation and/or epitaxial layer, the generation of V-shaped recesses, as well as the number and size of V-shaped recesses, can be further controlled. In one embodiment, in order to suppress and slow down the formation of V-shaped recesses and reduce the size and number of V-shaped recesses, the first growth rate is greater than the second growth rate and the third growth rate. In another embodiment, the first growth rate is greater than the second growth rate, and the second growth rate is greater than or equal to the third growth rate. By growing the intermediate structure 50 at a lower rate, the dislocation between the buffer structure 40 and the first semiconductor contact layer 121 caused by the high-speed growth is filled or reduced. In one embodiment, the growth rate of the intermediate structure 50 is no more than 50Å/min, in one embodiment, no more than 30Å/min; in one embodiment, no more than 10Å/min.

The material of the intermediate structure 50 includes _{AlxInyGa (1-xy)} N, wherein 0≦x≦1, 0≦y≦1. The intermediate structure 50 further includes first conductivity type impurities, _and the first conductivity type impurity concentration of the intermediate structure 50 is less than the first conductivity type impurity concentration of the first semiconductor contact layer 121. In one embodiment, the material of the second intermediate layer _50a includes _{AlxInyGa (1-xy)} N, wherein 0≦x≦1, 0≦y≦1; in one embodiment, the first conductivity type impurity concentration in the second intermediate layer 50a is less than 1×10 ¹⁹ /cm ³ , and includes the same material as the first semiconductor contact layer 121. The stress buffer layer 50c may include a first sublayer (not shown) and a second sublayer (not shown) alternately stacked multiple times, wherein the first sublayer and the second sublayer have different lattice constants, and the energy gap of the first sublayer is higher than the energy gap of the second sublayer. The first sublayer includes Al _x1 In _y1 Ga _(1-x1-y1) N, and the second sublayer includes Al _x2 In _y2 Ga _(1-x2-y2) N, wherein 0≦x1, x2, y1, y2＜1, and y1＜y2. For example, the material of the first sublayer is gallium nitride (GaN), and the second sublayer is indium gallium nitride (InGaN), and in one embodiment, the material is alternately stacked 5-40 times. By alternately stacking the first sublayer and the second sublayer of different lattice constants, the stress generated by epitaxy during the growth of the self-buffer structure 40 can be alleviated. In one embodiment, the first sublayer and the second intermediate layer 50a include the same material. In addition, the stress buffer layer 50c has a lower first conductivity type impurity concentration or is not intentionally doped with the first conductivity type impurity, which can reduce stress and further inhibit the generation of new dislocations. In one embodiment, the first conductivity type impurity of the stress buffer layer 50c is less than 1×10 ¹⁷ /cm ³ , and in one embodiment, it is less than 5×10 ¹⁶ /cm ³ . In one embodiment, the first sublayer and the second sublayer of the stress buffer layer 50c are not intentionally doped with the first conductivity type impurities. In another embodiment, the first sublayer contains the first conductivity type impurities, and its first conductivity type impurity concentration is less than 1×10 ¹⁷ /cm ³ , and the second sublayer is not intentionally doped with the first conductivity type impurities. In another embodiment, the first sublayer and the second sublayer both contain the first conductivity type impurities, and the first conductivity type impurity concentration in the second sublayer is lower than the first conductivity type impurity concentration in the first sublayer. In one embodiment, the thickness of the first sublayer and the second sublayer is not greater than 20 nm, and in one embodiment, it is between 0.5 nm and 10 nm. If the dislocation generated from the substrate side in the semiconductor stack triggers a V-shaped recess in the second intermediate layer 50a, the size of the V-shaped recess can be controlled by, for example, adjusting the thickness of the stress buffer layer 50c or its growth conditions. In one embodiment, when the stress buffer layer 50c includes a first sublayer and a second sublayer, the size of the V-shaped recess can be determined by adjusting the thickness of the first sublayer and the second sublayer. In one embodiment, the thickness of the first sublayer and the second sublayer is set to 0.5 nm-10 nm as described above, and the size of the V-shaped recess can be controlled within a specific range. In other embodiments, the stress buffer layer 50c may also be composed of a semiconductor stack composed of multiple layers of different materials with the same function, such as a multi-layer structure with a gradient composition of group III elements.

The material of the first intermediate layer 50b includes _{AlxInyGa (1-xy)} N, wherein 0≦x≦1, 0≦y≦1; the first intermediate layer 50b includes first conductivity type impurities, and the first conductivity type impurity concentration _thereof is between 1× ¹⁰¹⁸ / ^cm3 and 1× ¹⁰²⁰ / ^cm3 , and in one embodiment, is less than 1× ¹⁰¹⁹ / ^cm3 , and includes the same material as the first semiconductor contact layer 121. By adjusting the doping concentration of the first intermediate layer 50b, the overall energy band can be changed, thereby improving the hole overflow in the semiconductor stack 12, and the thickness of the first intermediate layer 50b is set to 0.1nm to 2nm, which can suppress the generation of the V-shaped recess. In one embodiment, the thickness of the first intermediate layer 50b and the thickness of the first sublayer and/or the second sublayer in the stress buffer layer 50c are of the same order of magnitude, that is, the ratio of the thicknesses of the two is greater than or equal to 1, but not greater than 10. In another embodiment, the first conductivity type impurity concentration of the first intermediate layer 50b is more than 100 times the first conductivity type impurity concentration of the first sublayer and/or the second sublayer in the stress buffer layer 50c. The thickness of the second intermediate layer 50a is more than five times the thickness of the first intermediate layer 50b. In another embodiment, the semiconductor stack 12 further includes one or more other structures located between the intermediate structure 50 and the first semiconductor contact layer 121, for example, includes a low-doped layer (not shown) located between the intermediate structure 50 and the first semiconductor contact layer 121. The first conductivity type impurity concentration of the low-doped layer is less than the first conductivity type impurity concentration of the first semiconductor contact layer 121, which can reduce the forward voltage and improve the anti-static ability of the light-emitting element 1. In one embodiment, the first conductivity type impurity concentration in the low-doped layer is at least one order of magnitude less than the first conductivity type impurity concentration of the first semiconductor contact layer 121. In one embodiment, the first conductivity type impurity concentration in the low-doped layer is not less than 1×10 ¹⁷ /cm ³ , and preferably, not more than 5×10 ¹⁸ /cm ³ . In one embodiment, the first conductivity type impurity concentration in the low-doped layer is less than the first conductivity type impurity concentration in the second intermediate layer 50a. In some embodiments, the low-doped layer has a thickness of not less than 50 nm and/or not more than 1000 nm; in one embodiment, between 100 nm and 500 nm (including the end values). If the thickness of the low-doped layer is less than 50 nm, the antistatic ability of the light-emitting element 1 will be deteriorated, and the forward voltage of the light-emitting element 1 will be increased. In one embodiment, the opening width of the V-shaped recess 11 on the upper surface 123a of the active region can be adjusted to a smaller size and a smaller distribution density, for example, the opening width is between 20 nm and 100 nm, and the distribution density is less than 2×10 ⁸ cm ^-2 . Then, by combining the above-mentioned low-doped layer with the highly doped second intermediate layer 50a and the highly doped first semiconductor contact layer 121, the effect of reducing the forward voltage of the light-emitting element and improving the anti-static ability of the light-emitting element can be achieved even with the V-shaped recess 11 of a small size and a smaller distribution density.

The active region 123 includes a plurality of quantum well layers (not shown) and a plurality of barrier layers (not shown) alternately stacked, wherein the energy gap of the barrier layer is greater than the energy gap of the quantum well layer. The quantum well layer includes indium (In), such as Al _x1 In _y1 Ga _(1-x1-y1) N, wherein 0≤x1≤1 and 0＜y1≤1, and in one embodiment, In _y1 Ga _(1-y1) N, wherein 0＜y1＜0.25. The barrier layer includes a nitride layer having an indium (In) composition ratio lower than the indium (In) composition ratio of the quantum well layer, such as Al _x2 In _y2 Ga _(1-x2-y2) N, wherein 0≤x2≤0.1, 0≤y2≤0.1, preferably 0≤x2≤0.08, and more preferably 0≤x2≤0.05. The number of cycles of the quantum well layer and the barrier layer alternately stacked may be, for example, 2 to 20, preferably 3 to 15, and more preferably 4 to 12. If the number of cycles is too large, the thickness of the active region will be too thick, the quality of the epitaxial layer will be reduced, and the luminous efficiency of the light-emitting element will be reduced. In addition, a large number of cycles will cause the thickness of the epitaxial layer to be too thick, which will increase the probability of the opening of the V-shaped recess 11 being formed, and the opening of the V-shaped recess 11 that already exists will increase due to the thickness of the active region 123, making the opening of the V-shaped recess 11 too large. If the number of cycles is too small, the thickness of the active junction region is too thin, and the recombination of electrons and holes cannot be effectively achieved, thereby reducing the luminous efficiency of the light-emitting element.

In order to suppress and slow down the formation of the V-shaped recess 11 and reduce the size and number of the V-shaped recess 11, in this embodiment, the active region 123 grows at a low speed. Specifically, the growth rate of the active region 123 is lower than the growth rate of the buffer structure 40 and the first semiconductor contact layer 121. In one embodiment, the growth rate of the active region 123 is no more than 30Å/min, and in one embodiment, no more than 10Å/min. In addition, the active region 123 has a lower first conductivity type impurity concentration or is not intentionally doped with the first conductivity type impurity, which can reduce the generation of defects caused by impurities and further suppress the generation of new dislocations. In one embodiment, the first conductivity type impurity in the active region 123 is less than 1×10 ¹⁷ /cm ³ , and in one embodiment, less than 5×10 ¹⁶ /cm ³ . In one embodiment, the quantum well layer and the barrier layer are not intentionally doped with the first conductivity type impurity. In another embodiment, the barrier layer includes the first conductivity type impurity, and its first conductivity type impurity concentration is less than 1×10 ¹⁷ /cm ³ , and the quantum well layer is not intentionally doped with the first conductivity type impurity. In another embodiment, the quantum well layer and the barrier layer both include the first conductivity type impurity, and the first conductivity type impurity concentration in the quantum well layer is lower than the first conductivity type impurity concentration in the barrier layer. In another embodiment, the first conductivity type impurity concentration in the quantum well layer and the barrier layer is less than 0.01 times the first conductivity type impurity concentration in the first intermediate layer 50b. On the basis that the active region 123 has a lower first conductivity type impurity concentration or is not intentionally doped with the first conductivity type impurity, the thickness of a quantum well layer and a barrier layer is less than 10 nm, and in one embodiment, between 1 nm and 5 nm, so that the generation of new dislocations can be further suppressed.

According to the light emitting element and the manufacturing method thereof of the embodiment of the present application, after the active region 123 is grown, a plurality of V-shaped recesses 11 can be formed in the active region, and the V-shaped recesses 11 each have an opening on the upper surface 123a of the active region 123. In a cross-sectional view, the V-shaped recess 11 is V-shaped, and the V-shaped recess 11 includes a bottom located in the active region 123. The V-shaped recess 11 has a continuous inclined surface, and the thickness of the barrier layer and the quantum well layer located below the inclined surface is thinner than the thickness on the plane outside the V-shaped recess 11. Taking the growth substrate as a sapphire substrate as an example, the surface of the growth substrate epitaxially grown semiconductor stack 12 is a polar surface (C surface), and the inclined surface of the V-shaped recess 11 is a semipolar surface, which makes it easier for holes to tunnel through the barrier layer and the quantum well layer, so the injection of holes can be increased to improve the luminescence efficiency. Furthermore, the formation of the V-shaped recess 11 increases the path of current conduction dispersion, thereby improving the ability of the semiconductor stack to resist electrostatic discharge. In addition, the appropriate number and size of V-shaped recesses 11 can reduce the probability of carriers falling into defects, thereby reducing the conductivity and activity of defects to reduce the probability of non-radiative recombination. However, when the size of the V-shaped recess 11 is large and/or the distribution density is high, too many current conduction dispersion paths cause leakage effects, resulting in carrier loss or poor carrier confinement capability of the light-emitting element in the hot state, leading to a decrease in the hot state light-emitting efficiency of the light-emitting element. Therefore, according to the light-emitting element 1 and the manufacturing method thereof of the embodiment of the present application, the opening width of the V-shaped recess 11 formed on the upper surface 123a of the active region is between 20 nm and 100 nm, and the distribution density of the plurality of V-shaped recesses 11 on the upper surface 123a of the active region is less than 2×10 ⁸ cm ^-2 , thereby improving the hot state light-emitting efficiency of the light-emitting element 1. FIG2A shows a scanning electron microscope (SEM) image of a comparative light-emitting element, and FIG2B shows a scanning electron microscope image of the light-emitting element 1 of the embodiment of the present application. Both FIG2A and FIG2B are taken from the upper surface 123a of the active region after the active region has grown. Compared with the comparative example of FIG2A, the V-shaped recess 11 captured in FIG2B has a smaller size and a lower distribution density.

The electron blocking region 70 is located between the active region 123 and the second semiconductor contact layer 122. The electron blocking region 70 can block the electrons injected from the first semiconductor contact layer 121 into the active region 123, and reduce the situation where the electrons flow out into the second semiconductor contact layer 122 before combining with the holes in the quantum well layer in the active region 123. In one embodiment, the electron blocking region 70 may have a higher energy gap than the barrier layer in the active region 123. The electron blocking region 70 may include a single layer, multiple sub-layers, or a plurality of alternating first sub-layers and second sub-layers. In one embodiment, the electron blocking region 70 is a superlattice structure composed of a plurality of alternating first sub-layers and second sub-layers. The electron blocking region 70 may be a p-type, n-type or i-type semiconductor layer. In one embodiment, the electron blocking region 70 includes a second conductivity type impurity, and the second conductivity type impurity concentration is greater than 1×10 ¹⁷ /cm ³ , and in one embodiment, greater than or equal to 1×10 ¹⁹ /cm ³ and not more than 1×10 ²¹ /cm ³ . In one embodiment, the electron blocking region 70 includes a second conductivity type impurity and a first conductivity type impurity co-doped, wherein the second conductivity type impurity concentration is greater than 1×10 ¹⁸ /cm ³ , and the first conductivity type impurity concentration is less than 1×10 ¹⁸ /cm ³ . In one embodiment, the growth rate of the electron blocking region 70 is no more than 30Å/min, and in another embodiment, no more than 10Å/min. By controlling the growth rate of the electron blocking region 70 to be no more than the growth rate of the active region 123, the V-shaped concave portion 11 formed in the active region 123 can be slowed down and gradually filled up during the growth of the electron blocking region 70. In one embodiment, the electron blocking region 70 can be epitaxially grown in a hydrogen environment, which is beneficial to the two-dimensional epitaxial growth of the electron blocking region 70 and filling up the V-shaped concave portion 11.

The second semiconductor contact layer 122 is located on the electron blocking region 70. In some embodiments, the doping concentration of the second type dopant in the second semiconductor contact layer 122 is not less than 1×10 ¹⁸ /cm ³ , preferably, not less than 1×10 ¹⁹ /cm ³ , and more preferably, between 1×10 ¹⁹ /cm ³ and 1×10 ²¹ /cm ³ (including the end values). In one embodiment, the second semiconductor contact layer 122 comprises Al _x1 In _x2 Ga _(1–x1-x2) N, wherein 0≦x1≦1, 0≦x2≦1. In one embodiment, x2=0, 0＜x1≦0.1, and preferably, 0＜x1≦0.05, so as to improve the luminous efficiency. In another embodiment, the second semiconductor contact layer 122 includes GaN. The second semiconductor contact layer 122 has a thickness not exceeding 15 nm, and preferably, exceeds 3 nm. In one embodiment, the second semiconductor contact layer 122 further includes a first conductivity type impurity, such as silicon, wherein the second conductivity type impurity concentration is greater than the first conductivity type impurity concentration. In some embodiments, the second semiconductor contact layer 122 includes a multi-layer structure, such as a superlattice structure. By adjusting the multi-layer structure, the doping concentration or material composition from the electron blocking region 70 to the outermost layer of the second semiconductor contact layer 122 is gradually adjusted, so that the epitaxial quality of the second semiconductor contact layer 122 is improved. In another embodiment, the second semiconductor contact layer 122 includes a lower contact layer (not shown) and an upper contact layer (not shown), wherein the lower contact layer is located between the upper contact layer and the electron blocking region 70. The upper contact layer is undoped or includes the first type dopant, and is used to contact the transparent conductive layer described below. In one embodiment, the concentration of the first type dopant in the upper contact layer is not less than 1×10 ¹⁸ /cm ³ , preferably, not less than 1×10 ¹⁹ /cm ³ , and more preferably, between 1×10 ¹⁹ /cm ³ and 1×10 ²¹ /cm ³ (including the end values). The thickness of the upper contact layer is less than that of the lower contact layer. In one embodiment, the thickness of the upper contact layer is not more than 10 nm; in one embodiment, the thickness of the upper contact layer is between 0.1 nm and 3 nm. In one embodiment, in addition to the electron blocking region 70, one or more other layer structures may be included between the active region 123 and the second semiconductor contact layer 122. For example, a diffusion prevention layer (not shown) is located between the electron blocking region 70 and the active region 123. The diffusion prevention layer is used to prevent the second semiconductor contact layer 122 or the second type dopant of the electron blocking region 70 from diffusing into the active region 123, thereby avoiding degradation of epitaxial quality or efficiency of the active region 123.

In the present application, after epitaxially growing the semiconductor stack 12, the light-emitting element 1 of any embodiment removes part of the semiconductor stack 12 by an etching process to expose the surface 121a of the first semiconductor contact layer 121. A first electrode 20 is formed on the surface 121a to be electrically connected to the first semiconductor contact layer 121, and a second electrode 30 is formed on the second semiconductor contact layer 122 to be electrically connected thereto. The first electrode 20 and the second electrode 30 are used to connect to an external power source or other electronic components and conduct current therebetween. The materials of the first electrode 20 and the second electrode 30 include metal materials. The metal material includes chromium (Cr), gold (Au), aluminum (Al), copper (Cu), silver (Ag), tin (Sn), nickel (Ni), rhodium (Rh), platinum (Pt), titanium (Ti), aluminum (Al), tungsten (W), etc. or alloys of the above materials. In some embodiments, the first electrode 20 and the second electrode 30 are a single layer, or a structure including multiple layers such as Ti/Au layer, Ti/Al layer, Ti/Pt/Au layer, Cr/Au layer, Cr/Pt/Au layer, Ni/Au layer, Ni/Pt/Au layer, Ti/Al/Ti/Au layer, Cr/Ti/Al/Au layer, Cr/Al/Ti/Au layer, Cr/Al/Ti/Pt layer or Cr/Al/Cr/Ni/Au layer, or a combination thereof. In one embodiment, the light-emitting element 1 is further provided with a transparent conductive layer (not shown) between the second electrode 30 and the second semiconductor contact layer 122. The material of the transparent conductive layer includes a transparent conductive oxide or a light-transmitting thin metal. The transparent conductive material may be, for example, indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), zinc oxide (ZnO), or indium zinc oxide (IZO).

In another embodiment (not shown), after the semiconductor stack 12 is epitaxially grown in the light-emitting element 1 of any embodiment, a wafer transfer process can be used to fix one side of the second semiconductor contact layer 122 in the semiconductor stack 12 to a transfer substrate, and then the substrate 10 is separated from the semiconductor stack 12. The transfer substrate includes a conductive material and can be used as a second electrode electrically connected to the second semiconductor contact layer 122. A first electrode 20 is formed on one side of the first semiconductor contact layer 121 in the semiconductor stack 12, and the first electrode 20 and the second electrode 30 are respectively located on opposite sides of the transfer substrate to form a vertical light-emitting element. In another embodiment (not shown), the substrate 10 includes a conductive material, and the first electrode 20 and the second electrode 30 are respectively located on opposite sides of the substrate 10 to form a vertical light emitting device.

FIG3 is a schematic diagram of a light emitting device 2 according to an embodiment of the present invention. The light emitting element 1 in the above embodiment is mounted on a carrier 101 in the form of a flip-chip. In order to simplify the diagram, FIG3 does not show all semiconductor layers in the semiconductor stack 12. The first electrode 20 and the second electrode 30 of the light emitting element 1 can be bonded to the electrode pad 80 on the carrier 101 using a metal bonding layer, such as a eutectic layer or solder 90. In addition, an insulating layer 26 is disposed between the first electrode 20, the second electrode 30 and the semiconductor stack 12, and the insulating layer includes openings 261 and 262. The first electrode 20 and the second electrode 30 are respectively filled in the openings 261 and 262 to be electrically connected to the first semiconductor contact layer 121 and the second semiconductor contact layer 122. The light of the light-emitting element 1 can be extracted through the surface of the substrate 10 opposite to the semiconductor stack 12 and/or the side surface of the substrate 10. In one embodiment, the light-emitting device 2 further includes a packaging material (not shown) covering the light-emitting element 1, wherein the packaging material includes epoxy, acrylic and silicone.

The temperature characteristics of a light-emitting element can be measured by the ratio of the hot luminous efficiency to the cold luminous efficiency. Generally speaking, the higher the operating temperature of the light-emitting element, the lower the hot luminous efficiency of the light-emitting element. The light-emitting element according to the embodiment of the present application can maintain good temperature characteristics even at a large current density, such as an operating current density of more than 75 A/ ^cm2 , that is, its hot/cold factor (H/C factor) can be maintained at least above 95%. Taking Table 1 as an example, it shows the experimental data measured at an operating current of 1 ampere for the light-emitting element 1 according to the embodiment of the present application, wherein the H/C factor represents the ratio of the hot luminous efficiency of the light-emitting element 1 measured at a high temperature of 85°C to the cold luminous efficiency measured at a room temperature of 25°C. In addition, generally speaking, when the light-emitting element works at low temperature, the forward voltage (Vf) becomes higher and the current decreases, and the required light intensity may not be achieved in constant voltage operation. According to the light-emitting element 1 of the embodiment of the present application, in addition to the above-mentioned good temperature characteristics, the difference between the forward voltage of the light-emitting element 1 at -40 ℃ and the forward voltage at 25 ℃ is ≤ 0.21 V, which means that even under low temperature operation, the start-up state of the light-emitting element 1 can maintain almost the same photoelectric characteristics as under room temperature operation. [Table 1] Embodiment Component size Po@450 nm Vf@25℃ Vf@-40℃ ∆ Vf H/C factor The first batch 45×45 mil ² 1456 mW 3.07 V 3.33 V 0.15 V 97% Second batch 45×45 mil ² 1473 mW 3.08 V 3.34 V 0.21 V 97%

FIG4 is a schematic diagram of a light-emitting device 4 according to an embodiment of the present invention. In one embodiment, the light-emitting device 4 is an LED bulb for automobiles, which can be plugged and fixed in a mounting through hole on the rear housing of the automobile headlight assembly. The light-emitting device 4 includes a first LED chip 4100 for low beam light emission or a second LED chip 4200 for high beam light emission, a long columnar lamp post 4300, a driving power circuit board 4400, a heat dissipation fin for heat dissipation (not shown), a fan for heat dissipation (not shown), a fan cover for protecting the fan (not shown), a power cord for electrical connection with a vehicle battery (not shown), and a plug disposed at the end of the power cord (not shown). The first LED chip 4100 or the second LED chip 4200 in the light-emitting device 4 may include any one or more of the light-emitting element 1 and the light-emitting device 2 described above.

FIG5 is a schematic diagram of a light-emitting device 5 according to an embodiment of the present invention. In one embodiment, the light-emitting device 5 may be a vehicle lighting lamp 500, which may be applied to daytime running lights, headlights, taillights, or turn signals. The main lighting lamp 510 may be a main lighting lamp in the vehicle lighting lamp 500. For example, when the vehicle lighting lamp 500 is used as a headlight, the main lighting lamp 510 may have the function of a headlight that illuminates the front of the vehicle. The combination lighting lamp 520 may have at least two functions. For example, when the vehicle lighting lamp is used as a headlight, the combination lighting lamp 520 may perform the functions of a daytime running light (DRL) and a turn signal lamp. The main lighting lamp 510 or the combination lighting lamp 520 may include any one or more of the aforementioned light-emitting element 1, light-emitting device 2 and light-emitting device 4.

It should be noted that the various embodiments listed in the present invention are only used to illustrate the present invention and are not used to limit the scope of the present invention. Any obvious modifications or changes made to the present invention by anyone do not deviate from the spirit and scope of the present invention. The same or similar components in different embodiments, or components with the same labels in different embodiments all have the same physical or chemical properties. In addition, the above-mentioned embodiments of the present invention can be combined or replaced with each other under appropriate circumstances, and are not limited to the specific embodiments described. The connection relationship between a specific component and other components described in detail in one embodiment can also be applied to other embodiments, and all fall within the scope of the scope of protection of the present invention as described below.

1: light-emitting element 2, 4, 5: light-emitting device 10: substrate 101: carrier 11: V-shaped recess 12: semiconductor stack 121: first semiconductor contact layer 121a: surface 122: second semiconductor contact layer 123: active region 123a: surface 20: first electrode 30: second electrode 40: buffer structure 50: intermediate structure 50a: second intermediate layer 50b: first intermediate layer 50c: stress buffer layer 70: electron blocking region 26: insulating layer 261, 262: opening 80: electrode pad 90: Solder 4100: First LED chip 4200: Second LED chip 4300: Light column 4400: Drive power circuit board 500: Car lighting 510: Main lighting 520: Combination lighting D: Defect

﹝Figure 1﹞shows a light-emitting element 1 of an embodiment of the present application. ﹝Figure 2A﹞shows a scanning electron microscope (SEM) image of a comparative light-emitting element. ﹝Figure 2B﹞shows a scanning electron microscope (SEM) image of a light-emitting element 1 of an embodiment of the present application. ﹝Figure 3﹞shows a schematic diagram of a light-emitting device 2 according to an embodiment of the present application. ﹝Figure 4﹞shows a schematic diagram of a light-emitting device 4 according to an embodiment of the present application. ﹝Figure 5﹞shows a schematic diagram of a light-emitting device 5 according to an embodiment of the present application.

1: Light-emitting element

10: Substrate

11: V-shaped concave part

12: Semiconductor stacking

121: First semiconductor contact layer

121a: Surface

122: Second semiconductor contact layer

123: Active area

123a: Surface

20: First electrode

30: Second electrode

40: Buffer structure

50: Middle structure

50a: Second middle layer

50b: First middle layer

50c: Stress buffer layer

70:Electron blocking area

D: Defect

Claims (10)

A light-emitting element comprises: a semiconductor stack, comprising: a first semiconductor layer having a first conductivity type; an intermediate structure located on the first semiconductor layer; an active region located on the intermediate structure and comprising an upper surface; a second semiconductor layer located on the active region and having a second conductivity type different from the first conductivity type; and a plurality of recessed portions in the active region, each having an opening on the upper surface of the active region; wherein the width of the opening is between 20 nm and 100 nm; a distribution density of the plurality of recessed portions on the upper surface is less than 2×10 ⁸ cm ^-2 ; and the light-emitting element has a ratio of a hot luminous efficiency at 85°C to a cold luminous efficiency at 25°C greater than or equal to 95% at an operating current density of more than ⁷⁵ A/cm 2. The light-emitting element of claim 1, wherein the intermediate structure comprises a stress buffer layer located on the first semiconductor layer and a first intermediate layer located between the stress buffer layer and the active region; wherein the stress buffer layer comprises a first conductive type impurity, and a concentration of the first conductive type impurity is less than 1×10 ¹⁷ cm ^-3 . A light-emitting element as claimed in claim 2, wherein the stress buffer layer comprises a plurality of first sublayers and a plurality of second sublayers alternately stacked, an energy gap of one of the plurality of first sublayers is higher than an energy gap of one of the plurality of second sublayers, the plurality of first sublayers comprise the first conductive type impurity; and the plurality of second sublayers are not doped with the first conductive type impurity or a concentration of the first conductive type impurity of the plurality of second sublayers is lower than a concentration of the first conductive type impurity of the plurality of first sublayers. The light-emitting device of claim 1, wherein the active region comprises the first conductivity type impurity, and a concentration of the first conductivity type impurity in the active region is less than 1×10 ¹⁷ cm ^-3 . The light-emitting device of claim 4, wherein the active region comprises a plurality of quantum well layers and a plurality of barrier layers, and a thickness of one of the plurality of quantum well layers and a thickness of one of the plurality of quantum well layers are between 1 nm and 5 nm. The light-emitting element of claim 2, wherein the thickness of the first intermediate layer is between 0.1 nm and 2 nm. The light-emitting device of claim 6, wherein the first intermediate layer comprises the first conductive type impurity, and the concentration of the first conductive type impurity is between 1×10 ¹⁸ cm ^-3 and 1×10 ²⁰ cm ^-3 . As in claim 2, the intermediate structure further comprises a second intermediate layer located between the stress buffer layer and the first semiconductor layer, and the thickness of the second intermediate layer is more than five times the thickness of the first intermediate layer. A light-emitting element as claimed in claim 1, wherein the difference between the forward voltage (Vf) of the light-emitting element at -40°C and the forward voltage at 25°C is ≤ 0.21 V at an operating current of 1 A. A light-emitting element as claimed in claim 1, wherein in a cross-sectional view, the recess is V-shaped, and the V-shape includes a bottom located in the active region.

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