TW202414774A - Semiconductor device,wafer-level structure and forming method thereof - Google Patents

Abstract

An array of dies is formed over a substrate. Each of the dies contains a plurality of functional transistors. A plurality of first seal rings each surround a respective one of the dies in a top view. The first seal rings define a plurality of corner regions that are disposed outside of the first seal rings and between corners of respective subsets of the dies. A plurality of structures is disposed within the corner regions. The structures include test structures, dummy structures, process monitor patterns, alignment marks, or overlay marks. Electrical interconnection elements are disposed between each pair of adjacent dies in the array of dies in the top view. The electrical interconnection elements electrically interconnect the dies in the array with one another. A second seal ring surrounds the array of dies, the first seal rings, and the structures in the top view.

Description

Semiconductor device, wafer-level structure, and method for forming the same

The disclosed embodiments relate to semiconductor devices, wafer-level structures, and methods of forming the same.

The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological improvements in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (the number of interconnected devices per chip area) has generally increased as geometric size (the smallest component or line that can be created using a manufacturing process) has decreased. This process of miniaturization generally improves manufacturing efficiency and reduces associated costs.

However, despite advances in semiconductor manufacturing, existing manufacturing systems and methods may still have shortcomings. For example, at the wafer level, existing manufacturing methods may still leave too much wasted space between dies. If the wasted space between dies is fully utilized, it can provide additional functionality to the manufactured die, or enhance its versatility.

Thus, while conventional methods of fabricating semiconductor devices are often adequate, they are not satisfactory in all respects.

The disclosed embodiment provides a semiconductor device, including a die array of a plurality of dies formed on a substrate, wherein each of the dies in the die array includes a plurality of functional transistors; a plurality of first sealing rings, each surrounding a corresponding one of the dies in a top view, wherein the first sealing ring defines a plurality of corner regions, which are disposed outside the first sealing ring and between corners of a corresponding subset of the dies; a plurality of structures, which are disposed in the corner regions; A first sealing ring is provided for enclosing a first die array and a second sealing ring. The first sealing ring is provided for enclosing a first die array and a second sealing ring. The first sealing ring is provided for enclosing a first die array and a second sealing ring. The first sealing ring is provided for enclosing a first die array and a second sealing ring. The first sealing ring is provided for enclosing a first die array and a second sealing ring.

The disclosed embodiment provides a wafer-level structure, including a plurality of integrated circuit dies formed on a substrate, wherein the integrated circuit dies have substantially the same integrated circuit layout; a plurality of first sealing rings, each surrounding a corresponding one of the integrated circuit dies in a top view, wherein each of the first sealing rings includes a plurality of first openings; a plurality of first structures, disposed between adjacent integrated circuit dies outside the first sealing rings, wherein the first structures include test structures, dummy structures, process monitoring patterns, alignment marks, or cover marks; a plurality of electrical interconnect elements, extending through the first sealing rings; An opening is used to electrically interconnect integrated circuit grains to form a multi-grain integrated circuit, the multi-grain integrated circuit including a first structure; a second sealing ring, which surrounds the multi-grain integrated circuit in a top view, wherein the first sealing ring is surrounded by the second sealing ring together, and each of the first sealing ring and the second sealing ring includes a plurality of metal wires and a plurality of through holes vertically arranged between the metal wires; and one or more second structures are formed in a plurality of regions of the substrate, the regions are located outside the second sealing ring in a top view, wherein the one or more second structures are not surrounded by more than one sealing ring in a top view.

The disclosed embodiment provides a method for forming a semiconductor device, comprising performing a multi-step lithography process to form a plurality of first integrated circuit dies on a substrate, wherein the first integrated circuit dies are substantially identical to each other and are arranged in an array having a plurality of rows and a plurality of columns; forming a plurality of first sealing rings to surround each of the first integrated circuit dies in a top view, wherein each of the first sealing rings has a plurality of spacings therein; forming a plurality of sets of conductive elements extending through the spacings of the first sealing rings to electrically interconnect the first integrated circuit dies to form a multi-die structure, wherein the plurality of conductive elements are electrically connected to each other through the first sealing rings to form a multi-die structure; The method comprises forming a second sealing ring which surrounds the first integrated circuit die, the first sealing ring, and the conductive elements in a top view; forming one or more test structures, one or more dummy structures, one or more process monitoring patterns, one or more alignment marks, or one or more cover marks in a plurality of regions of the multi-die structure, the regions being located in the second sealing ring but outside the first sealing ring; and performing a segmentation process along a plurality of scribe lines outside the second sealing ring, wherein the regions in the second sealing ring are not segmented.

Many different implementation methods or examples are disclosed below to implement different features of the subject matter provided. The following describes specific components and their arrangement embodiments to illustrate the present disclosure. Of course, these embodiments are only for illustration and do not limit the scope of the present disclosure. For example, in the specification, it is mentioned that the first feature component is formed on the second feature component, which includes an embodiment in which the first feature component and the second feature component are in direct contact, and also includes an embodiment in which there are other features between the first feature component and the second feature component, that is, the first feature component and the second feature component are not in direct contact.

In addition, repeated reference numerals or labels may be used in different embodiments, and such repetition is only for the purpose of simply and clearly describing the present disclosure, and does not represent a specific relationship between the different embodiments and/or structures discussed. In addition, in the present disclosure, forming on, connecting to and/or coupling to another feature component may include embodiments in which the feature components are formed to be in direct contact, and may also include embodiments in which additional feature components may be formed to be inserted into the above-mentioned feature components, so that the above-mentioned feature components may not be in direct contact. In addition, spatially related terms such as "vertical", "above", "up", "below", "bottom" and similar terms (such as "downwardly", "upwardly", etc.) may be used. These spatially related terms are for the convenience of describing the relationship between one (or some) elements or features and another (or some) elements or features in the diagram. These spatially related terms are intended to cover different orientations of the device including the features. In addition, when "about", "approximately", etc. are used to describe quantities or ranges of quantities, such terms are intended to cover numbers within the variations that occur due to natural variations in the manufacturing process, which is understood by those of ordinary skill in the art. For example, the term "about 5nm" includes a size range of 4.5nm to 5.5nm, where the allowable deviation of the manufacturing material layer is known to be +/-10%.

The present disclosure relates generally to semiconductor devices, and more particularly to IC dies including semiconductor devices, including field-effect transistors (FETs), planar FETs, three-dimensional fin-line FETs (FinFETs), or gate-all-around (GAA) devices. One aspect of the present disclosure relates to forming wafer-level structures including connected IC dies and seal rings surrounding the IC dies, and forming IC-related structures to utilize empty (or wasted) space on a wafer. Thus, chip area utilization can be improved, as discussed in more detail below.

1A and 1B show a three-dimensional perspective view and a top view, respectively, of a portion of an integrated circuit (IC) device 90. The IC device 90 may be an intermediate device or a portion thereof fabricated during the processing of an IC die, and may include static random-access memory (SRAM) and/or other logic circuits, passive components (e.g., resistors, capacitors, and inductors), and active components, such as p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), FinFETs, metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) field effect transistors, bipolar transistors, high voltage transistors, high frequency transistors, and/or other storage cells. Unless otherwise stated, the present disclosure is not limited to any particular number of devices or device regions, or any particular device configuration. For example, although the IC device 90 shown is a three-dimensional FinFET device, the concepts of the present disclosure may also be applied to planar field effect transistor devices or GAA devices.

1A , IC device 90 includes substrate 110. Substrate 110 may include elemental (single element) semiconductors (e.g., silicon, germanium, and/or other suitable materials), compound semiconductors (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium uranide, and/or other suitable materials), alloy semiconductors (e.g., SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and/or other suitable materials). Substrate 110 may be a single layer of material having a uniform composition. Alternatively, substrate 110 may include multiple material layers having similar or different compositions suitable for IC device manufacturing. In one example, substrate 110 may be a silicon-on-insulator (SOI) substrate having a semiconductor silicon layer formed on a silicon oxide layer. In another example, the substrate 110 may include a conductive layer, a semiconductive layer, a dielectric layer, other layers, or a combination thereof. Various doped regions, such as source/drain regions, may be formed in or on the substrate 110. The doped regions may be doped with n-type dopants (e.g., phosphorus or arsenic) and/or p-type dopants (e.g., boron), depending on the design requirements. The doped regions may be formed directly on the substrate 110, in a p-type well structure, in an n-type well structure, in a double well structure, or using a raised structure. The doped regions may be formed by implantation of dopant atoms, in-situ doping epitaxial growth, and/or other suitable techniques.

A three-dimensional active region 120 is formed on the substrate 110. The active region 120 is an elongated fin-like structure that protrudes upward from the substrate 110. Therefore, the active region 120 may be interchangeably referred to as a fin structure 120 or fin 120 hereinafter. The fin structure 120 may be fabricated using a suitable process including lithography and etching processes. The lithography process may include forming a photoresist layer covering the substrate 110, exposing the photoresist to a pattern, performing a post-exposure baking process, and developing the photoresist to form a mask element (not shown) including the photoresist. The mask element is then used to etch a groove in the substrate 110 to leave the fin structure 120 on the substrate 110. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes. In some embodiments, the fin structure 120 can be formed by a double patterning or multiple patterning process. Typically, the double patterning or multiple patterning process combines lithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than can be obtained using a single direct lithography process. As an example, a layer can be formed over a substrate and patterned using a lithography process. Spacers are formed next to the patterned layer using a self-alignment process. This layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fin structure 120.

The IC device 90 also includes a source/drain feature 122 formed above the fin structure 120. The source/drain feature 122 may include an epitaxial layer epitaxially grown on the fin structure 120. The IC device 90 also includes an isolation structure 130 formed on the substrate 110. The isolation structure 130 electrically separates the various components of the IC device 90. The isolation structure 130 may include silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a low-k dielectric material, and/or other suitable materials. In some embodiments, the isolation structure 130 may include a shallow trench isolation (STI) feature. In some embodiments, the isolation structure 130 is formed by etching a trench in the substrate 110 during the formation of the fin structure 120. The trench may then be filled with the isolation material described above, followed by a chemical mechanical planarization (CMP) process. Other isolation structures such as field oxide, local oxidation of silicon (LOCOS) and/or other suitable structures may also be used as the isolation structure 130. Alternatively, the isolation structure 130 may include a multi-layer structure, such as having one or more thermal oxide liners.

The IC device 90 further includes a gate structure 140 formed on three sides in the channel region of each fin structure 120 and bonding the fin structure 120. The gate structures 140 may be dummy gate structures (e.g., including an oxide gate dielectric and a polysilicon gate electrode), or they may be HKMG structures including a high-k gate dielectric and a metal gate, wherein the HKMG structure is formed by replacing the dummy gate structure. In some embodiments, the HKMG structures may each include a high-k gate dielectric and a metal gate. Example materials of high-k gate dielectrics include bismuth oxide, zirconium oxide, aluminum oxide, bismuth dioxide-aluminum oxide alloys, bismuth silicon oxide, bismuth silicon oxynitride, bismuth tantalum oxide, bismuth titanium oxide, bismuth zirconium oxide, or combinations thereof. The metal gate may include one or more work function metal layers and one or more fill metal layers. The work function metal layer may be configured to adjust the work function of the corresponding transistor. Example materials for the work function metal layer may include titanium nitride (TiN), titanium aluminide (TiAl), tantalum nitride (TaN), titanium carbide (Tic), tantalum carbide (TaC), tungsten carbide (WC), titanium aluminum nitride (TiAlN), zirconium aluminum (ZrAl), tungsten aluminum (WAl), tantalum aluminum (TaAl), halogenated aluminum (HfAl), or a combination thereof. The fill metal layer may serve as the main conductive portion of the gate layer. Although not depicted here, the gate structure 140 may include additional material layers, such as an interface layer above the fin structure 120, a capping layer, other suitable layers, or a combination thereof.

1B , the plurality of fin structures 120 are oriented longitudinally along the X direction, and the plurality of gate structures 140 are oriented longitudinally along the Y direction, i.e., substantially perpendicular to the fin structures 120. In many embodiments, the IC device 90 includes additional features, such as gate spacers disposed along the sidewalls of the gate structures 140, a hard mask layer disposed over the gate structures 140, and many other features.

It should also be understood that the various aspects of the present disclosure discussed below can be applied to multi-channel devices, such as gate-all-around (GAA) devices. FIG. 1C illustrates a three-dimensional perspective view of an example GAA device 150. For clarity and consistency, similar numbers in FIG. 1C and FIG. 1A and FIG. 1B will be represented by the same numbers. For example, the active area of the fin structure 120 rises vertically upward out of the substrate 110 in the Z direction. The isolation structure 130 provides electrical isolation between the fin structures 120. The gate structure 140 is located above the fin structure 120 and above the isolation structure 130. The mask 155 is located over the gate structure 140, and the gate spacer 160 is located on the sidewalls of the gate structure 140. A capping layer 165 is formed over the fin structure 120 to protect the fin structure 120 from oxidation during the formation of the isolation structure 130.

A plurality of nanostructures 170 are disposed above each fin structure 120. The nanostructures 170 may include nanosheets, nanotubes, or nanowires, or some other type of nanostructure extending horizontally in the X direction. The portion of the nanostructure 170 below the gate structure 140 may be used as a channel for the GAA device 150. Dielectric interspacers 175 may be disposed between the nanostructures 170. In addition, although not shown for simplicity, each nanostructure 170 may be circumferentially surrounded by a gate dielectric and a gate. In the illustrated embodiment, the portion of the nanostructure 170 outside the gate structure 140 may be used as a source/drain feature of the GAA device 150. However, in some embodiments, a continuous source/drain feature may be epitaxially grown over a portion of the GAA device 150. The fin structure 120 is located outside the gate structure 140. Regardless, a conductive source/drain contact 180 may be formed over the source/drain feature to provide an electrical connection thereto. An interlayer dielectric (ILD) 185 is formed over the isolation structure 130 and around the gate structure 140 and the source/drain contact 180.

FIG. 2 shows a top view of a wafer-level structure 200 and an enlarged view of a portion of the wafer-level structure 200. The top view is a viewing angle observed along a horizontal plane defined by an X-axis (or X-direction) and a Y-axis (or Y-direction). The wafer-level structure 200 may be a semiconductor wafer 205 or a portion thereof. As shown in the simplified example of FIG. 2 , the wafer-level structure 200 may include a plurality of IC dies, such as IC dies 210 , 211 , 220 , and 221 . Each of these IC dies 210 , 211 and 220 , 221 includes a plurality of IC devices (such as the IC device 90 or the GAA device 150 described above), other types of transistors, or other forms of active and/or passive integrated circuit microelectronic components (such as vias and metal lines). In some embodiments, IC dies 210, 211, 220, 221 have the same IC design and layout. In other words, they are implemented as the same device. For example, IC dies 210, 211, 220, 221 can each be implemented as a computer processor or a core thereof. In other embodiments, IC dies 210, 211, 220, 221 can each be implemented as an electronic memory storage device, such as a static random access memory (SRAM) or a dynamic random access memory (DRAM) or a portion thereof.

Some of these IC dies (e.g., IC dies 210, 211) are each implemented as an independent IC die. In other words, IC die 210 and IC die 211 can function independently of each other, and no electrical connection is made on the wafer-level structure 200 to connect them together. After the manufacture of these independent IC dies 210 and 211 is completed, the wafer-level structure 200 can separate the independent IC dies 210, 211 from each other along a plurality of saw lanes 240 (which extend along the X-axis and the Y-axis, as shown in FIG. 2). This is called a singulation process. Each of the independent IC dies 210, 211 can then be packaged to form an IC die.

At the same time, some IC dies (e.g., IC dies 220, 221) are electrically interconnected to form an interconnected IC die (e.g., interconnected IC die 250). Unlike the individual IC dies 210, 211, which are cut at four rectangular boundaries around each individual IC die, the cutting of the interconnected IC die 250 occurs around the common boundaries of the interconnected IC die 250, which may or may not be rectangular (although they are rectangular in the embodiment shown in FIG. 2). For example, there is no scribe line between IC die 220 and IC die 221, so no cutting occurs between IC die 220 and 221. Details of the interconnected IC die 250 are shown in the enlarged portion of FIG. 2.

The interconnected IC die 250 provides enhanced performance or functionality compared to the independent IC die 210, 211. For example, in an embodiment where the independent IC die 210, 211 each corresponds to a single-core computer processor, the interconnected IC die 250 corresponds to a dual-core computer processor, which can provide twice the speed or processing/computing power of the single-core computer processor. Similarly, in an embodiment where the independent IC die 210, 211 each corresponds to computer memory (e.g., SRAM or DRAM), the interconnected IC die 250 corresponds to a computer memory having twice the memory capacity of the independent IC die. Because an interconnected IC die (e.g., interconnected IC die 250) can be implemented simply by interconnecting any number of other desired independent IC dies together, the functionality and/or performance of the interconnected IC die can be flexibly configured, e.g., based on customer needs or design/manufacturing requirements. In many real-world scenarios, this may be preferable to having to separately design and manufacture an IC die (as an independent IC die) with performance or functionality comparable to that of interconnected IC die 250, since doing so would require additional design and/or manufacturing resources (e.g., requiring another set of lithography masks).

According to various aspects of the present disclosure, a dual seal ring structure is implemented to protect interconnected IC dies. In more detail, a seal ring 270 is implemented to circumferentially surround the four sides of each IC die 210, 211, 220, 221 in the top view, and another seal ring 280 is implemented to circumferentially surround the interconnected IC die 250 in the top view. Therefore, the seal ring 280 also circumferentially surrounds the seal ring 270 of the IC die 220 and 221. In the embodiment shown in FIG. 2, the shapes of the seal rings 270 and 280 are both rectangular, but it should be understood that in other embodiments, their shapes may be different.

FIG. 3 shows additional details of the sealing ring 270 and the sealing ring 280. In this regard, FIG. 3 is a side cross-sectional view of a portion of the wafer-level structure 200 taken along the scribe line A-A'. Since the scribe line A-A' extends along the Y direction, the side cross-sectional view of FIG. 3 is a cross-sectional view in the Y-Z plane.

The wafer-level structure 200 includes the above-mentioned substrate 110, on which a plurality of semiconductor devices 290 (for example, including the above-mentioned FinFET transistors or GAA transistors) are formed. These semiconductor devices 290 may also be referred to as active layers, or alternatively, the transistors of the semiconductor devices 290 are formed in the active layers. The wafer-level structure 200 also includes a multi-layer interconnect structure 300 formed on the semiconductor devices 290 and electrically coupled to the semiconductor devices 290. The multi-layer interconnect structure 300 includes a plurality of metal layers (for example, Metal-0, Metal-0, Metal-1, ..., Metal-N), each layer including a plurality of conductive interconnect elements (for example, metal wires 310). The metal wires 310 from different metal layers are vertically interconnected through conductive vias or contacts (for example, vias 320). The metal lines 310 and the vias 320 are embedded in or surrounded by an electrically insulating material, such as an interlayer dielectric (ILD) 330. A plurality of conductive pads 340 (e.g., comprising aluminum or copper or a combination thereof) are also formed on the multi-layer interconnect structure 300 and electrically coupled to the multi-layer interconnect structure 300. In some embodiments, the conductive pads 340 may also be considered to be part of the multi-layer interconnect structure 300. In addition to providing electrical connection to the multi-layer interconnect structure 300, the conductive pads 340 also prevent unwanted oxidation of components thereunder. Electrical connection to various components of the semiconductor device 290 is made possible by the conductive pads 340, the metal lines 310, and the vias 320.

It should be understood that FIG. 3 shows only a simplified arrangement of semiconductor device 290 and multi-layer interconnect structure 300. In other words, semiconductor device 290, metal line 310, and via 320 are only shown at a conceptual level, and their actual arrangement in IC die 220, 221 is much more complex than what is roughly shown in FIG. 3 (or subsequent top view or cross-sectional view).

The first sealing ring layer (seal ring 270 and seal ring 280) is composed of a vertical stack of metal lines 310 and vias 320 and conductive pads 340 of the multi-layer interconnect structure 300. For example, in the side cross-sectional view of FIG. 3, the seal ring 270 for the IC die 220 includes a vertical stack of metal lines 310, vias 320, and conductive pads 340 on the "left side" of the interconnected IC die 250, and a vertical stack of metal lines 310, vias 320, and conductive pads 340 on the "right side" of the interconnected IC die 250. Similarly, IC die 221 also has a seal ring 270, which includes a vertical stack of metal wires 310, vias 320, and conductive pads 340 disposed on their sides. The second seal ring layer (seal ring 280) is also composed of a vertical stack of metal wires 310, vias 320, and conductive pads 340. Compared with seal ring 270, seal ring 280 is disposed farther from IC die 220/221. In other words, seal ring 270 is disposed between its corresponding IC die 220/221 and seal ring 280.

The sealing rings 270 and 280 protect the IC dies 220 and 221 from unwanted factors in semiconductor manufacturing, such as moisture, water vapor, contaminant particles, or even pressure applied to the IC dies 220 and 221 by the separation/sawing tools during the singulation process. This is because the sealing rings 270 and 280 each form a closed barrier around the IC dies 220/221, so that the above-mentioned unwanted elements cannot penetrate the barrier and have an adverse effect on the components within the IC dies 220/221. The sealing rings 270 each provide a first layer of protection for the individual IC dies 220 and 221. The sealing rings 280 provide a second layer of protection for the individual IC dies 220 and 221 and the interconnected IC die 250 as a whole.

In the interconnected IC die 250, a gap region 350 is located between the different seal rings 270 surrounding the IC dies 220 and 221. The gap region 350 exists because the interconnected IC die 250 and the independent IC dies 210, 211 are formed on the same wafer. In more detail, a similar gap exists between the independent IC dies 210, 211 because the gap corresponds to the scribe line region used to divide the wafer to separate the independent IC dies 210, 211. At the same time, for ease of manufacturing, the size and spacing of the IC dies 220, 221 of the interconnected IC die 250 are configured similarly to the independent IC dies 210, 211. In this manner, the interconnected IC die 250 "inherits" the gap (corresponding to the scribe line region) between the individual IC dies 210, 211. In contrast to the individual IC dies 210, 211 (where the scribe line region would be segmented/divided), the gap region 350 would be retained (because segmentation would not occur between the two IC dies 220, 221 that would be interconnected together) and would exist on the final structure of the interconnected IC die 250.

Although the gap region 350 does not necessarily degrade the electrical performance of the interconnected IC die 250, it is not considered to be the best use of valuable chip space, especially when the IC device is scaled down. To address this problem, the present disclosure forms various useful structures in the gap region 350, such as a plurality of conductive elements 370 (see the enlarged view of the interconnected IC die 250 in FIG. 2). One of the conductive elements 370 is also shown in FIG. 4, which shows a side view cross-sectional view of another portion of the wafer-level structure 200 taken along the cut line BB' (shown in FIG. 2), in which a conductive element 370 is implemented. The cut line BB' also extends in the Y direction, so the side view cross-sectional view of FIG. 4 is also a cross-sectional view in the Y-Z plane.

In more detail, conductive element 370 (e.g., a metal wire comprising copper, aluminum, cobalt, or a combination thereof) is implemented to electrically interconnect IC die 220 and IC die 221. Conductive element 370 may carry or allow transmission of power signals (e.g., Vcc or Vdd), and/or carry or allow transmission of other suitable electrical signals, such as control signals (e.g., READ or WRITE signals for SRAM devices).

Each conductive element 370 extends in the Y direction and spans across the gap region 350. For example, as shown in FIG. 4 , the “leftmost” end of the conductive element 370 is connected to the “rightmost” end of one of the metal lines 310 of the IC die 220, and the “rightmost” end of the conductive element 370 is connected to the “leftmost” end of one of the metal lines 310 of the IC die 221, thereby electrically interconnecting the semiconductor devices 290 of the IC dies 220, 221. Therefore, the gap region 350 is effectively used as an area for establishing electrical interconnections within the interconnected IC die 250, and it is no longer just a waste of valuable chip space.

Note that in order for conductive elements 370 to interconnect IC die 220 and 221, their respective seal rings 270 must be broken or contain discontinuities. For example, the vertical stack (of seal rings 270) located on the "right side" of IC die 220 is broken by removing (or not implementing) one of the metal lines (e.g., a metal line in a Metal-5 layer) and the vias above and below the metal line. Similarly, the vertical stack (of seal rings 270) located on the "left side" of IC die 221 is broken by removing (or not implementing) one of the metal lines (e.g., a metal line in a Metal-5 layer) and the vias above and below the metal line. This arrangement prevents undesirable electrical shorts between the conductive element 370 and the sealing ring 270, which would increase undesirable electrical parasitics (e.g., parasitic capacitance). It should be appreciated that because the components of the interconnected IC die 250 (including the conductive element 370) are still annularly surrounded and protected by the sealing ring 280, discontinuities within the sealing ring 270 do not adversely affect the sealing of the interconnected IC die 250 from undesirable external components, but remain intact.

Referring back to the top view of FIG. 2 , the conductive element 370 may have different size and spacing requirements than the rest of the metal lines 310 of the IC die 220 , 221 . For example, the IC design and/or layout rules may specify that the metal lines 310 of the IC die 220 , 221 may have a width 400 (in either the X-direction or the Y-direction) and a spacing 410 between adjacently disposed metal lines 310 . In this regard, the width 400 and the spacing 410 are both measured in a direction perpendicular to the direction in which the metal lines 310 extend. In other words, if the metal line 310 extends in the X-direction, its width is the dimension of the metal line 310 measured in the Y-direction, and the spacing between the metal line 310 and its nearest metal line is also measured in the Y-direction, and vice versa.

As shown in FIG. 2 , each conductive element 370 has a width 420 that exceeds the width 400 of the metal line 310, regardless of whether the widths 400 and 420 are measured in the same direction. In addition, each conductive element 370 has a spacing 430 from an adjacent conductive element 370 that exceeds the spacing 410 of the adjacent metal line 310, regardless of whether the spacing 410 and 430 are measured in the same direction. The conductive elements 370 are configured to have larger widths and spacings, at least in part, because of pattern or topography uniformity issues. In more detail, as semiconductor feature sizes continue to scale down, it is undesirable for semiconductor wafers to have relatively large amounts of empty space, as this may result in process failures of semiconductor devices. Instead, it is preferred to achieve relative feature pattern uniformity across the wafer, for example by ensuring that there are no large blank areas on the die. Having greater pattern uniformity across the wafer also helps reduce undesirable loading effects in semiconductor manufacturing.

If the conductive elements 370 were not implemented, the gap region 350 would have been considered a large empty area. However, the electrical interconnect between the IC dies 220, 221 may not require a large number of individual conductive elements. Therefore, if the conductive elements 370 are implemented as the same width 400 as the rest of the metal lines 310, then the total area of the conductive elements 370 may still not be as large as desired for better pattern uniformity with the rest of the IC dies 220, 221. Therefore, the present disclosure proportionally increases the width 420 of the conductive elements 370 to improve pattern uniformity. The spacing 430 between the conductive elements 370 is also greater than the spacing 410 between the metal lines 310, so there is less risk of electrical bridging (e.g., an accidental electrical short between IC components) occurring in the gap region 350. In other words, the spacing 410 between metal lines 310 cannot be made too large, because doing so will limit the number of metal lines that can be implemented in each metal layer. In contrast, the number of conductive elements 370 required to electrically connect IC dies 220 and 221 together may not be that large, so a larger spacing 430 between adjacent pairs of conductive elements 370 is acceptable.

In some embodiments, the ratio of width 420 to width 400 is greater than 1:1 and is within a range between about 2:1 and about 4:1, and the ratio of spacing 430 to spacing 410 is greater than 1:1 and is within a range between about 2:1 and about 4:1. It should be understood that the above ranges are not randomly selected, but are specifically configured to maximize the likelihood of achieving relative pattern or topography uniformity and reduce the chance of bridging.

Note that for simplicity, FIG. 2 does not specifically illustrate the electrical and/or physical connections between the conductive elements 370 and their corresponding metal lines 310 of the IC die 220, 221, but it should be understood that such connections exist to ensure that the relevant circuits of the IC die 220 are electrically coupled to the relevant circuits of the IC die 221.

FIG. 5 shows a top view of another embodiment of the wafer-level structure 200, including an enlarged top view of the interconnected IC die 250. For reasons of clarity and consistency, similar components appearing in FIG. 2 and FIG. 5 will have the same reference numerals. Similar to the embodiment of FIG. 2, the interconnected IC die 250 shown in the embodiment of FIG. 5 also utilizes a plurality of conductive elements 370A, 370B to electrically couple the IC die 220 and 221 together. The conductive elements 370A, 370B are similar to the conductive elements 370 described above in that they are conductive and electrically connected to the metal lines of the IC die 220, 221 (not specifically shown here for simplicity). The conductive elements 370A, 370B also extend or span across the gap region 350, which is an efficient use of chip space that would otherwise be considered wasted. In addition, implementing conductive elements 370A, 370B helps improve semiconductor manufacturing itself, such as by improving pattern uniformity and reducing loading effects. The dimensions of conductive elements 370A, 370B can also be similar to conductive element 370 described above, such as in terms of their respective widths and spacings.

The difference between the conductive elements 370A, 370B and the conductive element 370 described above is that not all of the conductive elements 370A, 370B are straight. For example, at least one of the conductive elements 370B includes one or more turns (e.g., 90 degrees). As shown in FIG. 5 , the conductive element 370B initially extends from the IC die 220 toward the IC die 221 in the Y direction. The conductive element 370B then makes a substantially 90 degree turn in the gap region 350, thereby extending in the X direction. The conductive element 370B then makes another substantially 90 degree turn in the gap region 350, thereby extending again in the Y direction toward the IC die 221. The reason why the outline of the conductive element 370B is not straight in the top view may be to facilitate electrical routing (e.g., bypassing or avoiding certain microelectronic components), or it may be for pattern uniformity or loading purposes. It should be understood that other shapes or top view configurations may also be implemented for the conductive elements 370A, 370B, although they are not specifically shown in this specification for simplicity.

FIG. 6 shows a top view of yet another embodiment of the wafer-level structure 200, including an enlarged top view of the interconnected IC die 250. Again, for clarity and consistency, similar components appearing in FIG. 2 and FIGS. 5-6 have the same reference numerals. Similar to the embodiments of FIGS. 2 and 5, the interconnected IC die 250 shown in the embodiment of FIG. 6 also utilizes a plurality of conductive elements 370C, 370D to electrically couple the IC dies 220 and 221 together. However, at least some portions of the conductive elements 370C, 370D are implemented to be located between the sealing ring 270 and the sealing ring 280 in the X direction. In other words, the sealing ring 270 and the sealing ring 280 each have a section extending in the Y direction, and at least some portions of the conductive elements 370C, 370D are disposed between the sections extending in the Y direction of the sealing ring 270 and the sealing ring 280. For example, the conductive element 370C extends out of the IC die 220 in the X direction, then turns substantially 90 degrees to extend in the Y direction, and then turns substantially 90 degrees again to extend in the X direction into the IC die 221. Meanwhile, the conductive element 370D extends out of the IC die 220 in the X direction, then turns substantially 90 degrees to extend in the Y direction, then turns substantially 90 degrees again to extend in the X direction into the gap region 350, and finally turns 90 degrees again to extend in the Y direction into the IC die 221.

FIG. 7 shows a top view of another embodiment of wafer-level structure 200, including an enlarged top view of interconnected IC die 250. Again, for clarity and consistency, similar components appearing in FIG. 2 and FIG. 5-7 have the same reference numerals. In addition to implementing conductive elements 370 in interstitial region 350 to electrically couple IC die 220 and 221 together, the embodiment of FIG. 7 implements a number of other structures in interstitial region 350 to more efficiently utilize precious wafer area.

For example, the embodiment of FIG. 7 can implement multiple dummy structures 450 in the gap region 350. The dummy structures 450 can include dielectric materials or metal materials. For example, the dummy structures 450 can include dummy fin structures, dummy gate structures, dummy metal lines, dummy vias, etc. Although the dummy structures 450 are not used as microelectronic components of the IC die 220, 221, they are implemented in this specification to improve pattern uniformity or reduce loading, such as by increasing the pattern density of the gap region 350 to make it less empty. Therefore, the manufacturing of the wafer-level structure 200 can be improved by the presence of the dummy structures 450.

In one example, the embodiment of FIG. 7 may implement one or more test structures 460. Each test structure 460 may be designed and configured for electrical testing of semiconductor circuit elements or components (e.g., transistors or resistors). Thus, the test structures 460 may each include one of the semiconductor elements or components, and a conductive pad for establishing an electrical connection between a terminal of the test structure 460 and an external device. A current or voltage may be applied to the test structure 460.

In another example, the embodiment of FIG. 7 may implement one or more patterns 470. Pattern 470 is a pattern formed on a wafer to monitor the state of the wafer and/or the efficacy or accuracy of one or more manufacturing processes as the wafer undergoes one or more manufacturing processes. In some embodiments, pattern 470 may include a process monitoring pattern to measure the efficacy of a particular manufacturing process. In other embodiments, pattern 470 may include alignment marks and/or overlay marks, which may be features used for system calibration and/or for aligning subsequently formed patterns with previously formed patterns, such as patterns in different layers. In various embodiments, pattern 470 may include dielectric features or metal features.

It should be understood that each of the dummy structure 450, the test structure 460, and the pattern 470 can be implemented not only in the top layer of the wafer-level structure 200. For example, the dummy structure 450, the test structure 460, and the pattern 470 (e.g., as metal lines and/or vias) can be implemented in any metal layer of the multi-layer interconnect structure 300. The dummy structure 450, the test structure 460, and the pattern 470 can also be implemented in a layer below the multi-layer interconnect structure 300, for example, as a component in the substrate 110.

Regardless of what types of structures are implemented in the gap region 350, the fact that they are implemented in the gap region 350 means that valuable chip space within the IC die 220, 221 is saved or preserved. In other words, while conventional manufacturing methods may have to form structures (such as dummy structures 450, test structures 460, or monitoring patterns 470) within the IC die 220, 221, which consumes valuable chip area, the present disclosure frees up valuable chip area that would otherwise be wasted by forming the dummy structures 450, test structures 460, and monitoring patterns 470 outside the IC die 220, 221 and in the gap region 350. As a result, IC manufacturing efficiency can be improved and manufacturing costs can be reduced.

FIG. 8 shows a top view of other embodiments of interconnected IC die 250A and 250B. Although the interconnected IC die 250 described above includes two IC die 220, 221 that are electrically interconnected and surrounded by a sealing ring 280 (as an outer sealing ring layer) at 360 degrees, the interconnected IC die 250A and 250B each include more than two IC die. For example, the interconnected IC die 250A includes four individual IC die 222, 223, 224, 225 that are electrically interconnected. In the illustrated embodiment, the IC die 222, 223, 224, 225 can be arranged in a row extending in the Y direction. The IC die 222, 223 are electrically interconnected through a set of conductive elements 370. The IC dies 223, 224 are electrically interconnected through another set of conductive elements 370. The IC dies 224, 225 are electrically interconnected through another set of conductive elements 370. Each IC die 222, 223, 224, 225 is surrounded 360 degrees by its own sealing ring 270 (as an inner sealing ring layer). The four IC dies 222, 223, 224, 225 are then surrounded 360 degrees by a sealing ring 280 (as an outer sealing ring layer). The structures 450, 460, 470 discussed above with reference to FIG. 7 can be implemented in the gap region 350 between the IC dies 222, 223, 223-224, and 224-225.

In another example, interconnected IC die 250B includes four individual IC die 226, 227, 228, and 229 that are electrically interconnected together. In the illustrated embodiment, IC die 226, 227, 228, 229 may be arranged in a 2×2 matrix (e.g., having two rows and two columns). IC die 226 is electrically interconnected to IC die 227 in the X direction and to IC die 228 in the Y direction. IC die 227 is electrically interconnected to IC die 226 in the X direction and to IC die 229 in the Y direction. IC die 228 is electrically interconnected to IC die 229 in the X direction and to IC die 226 in the Y direction. IC die 229 is electrically interconnected to IC die 228 in the X direction and to IC die 227 in the Y direction. This connection method also uses a different subset of conductive elements 370 to complete the electrical connection. Each of the IC dies 226, 227, 228, and 229 is surrounded by a corresponding sealing ring 270 (as an inner sealing ring layer) at 360 degrees. The four IC dies 226, 227, 228, and 229 are then surrounded by a sealing ring 280 (as an outer sealing ring layer) at 360 degrees. The structure discussed above with reference to FIG. 7 can be implemented in the gap area 350 between the IC dies 226-227, 227-228, 228-229, and 226-228.

Other embodiments of interconnected IC die are also contemplated, but for the sake of brevity, these embodiments are not specifically described in this specification. For example, the interconnected IC die may include a row of interconnected IC die extending in the X direction. In another example, the interconnected IC die may include less than or more than four die (e.g., three or five). In addition, the individual IC die in the interconnected IC die need not be substantially identical to each other. In other words, the interconnected IC die may include IC die that are different types of ICs (e.g., containing different types of circuits or configured for different functions).

Another aspect of the present disclosure relates to the fabrication of "super grains," which are wafer-level structures that include most, if not all, of the IC die on a wafer. For example, in some embodiments, the IC die formed as part of a "super grain" structure may comprise between 50%-100% of all IC die formed on a single wafer. For example, as shown in FIG. 9 , in the case where the sealing ring 280 is rectangular, the above ratio may be between about 65% and about 75%. However, in embodiments where the sealing ring 280 is cross-shaped, also as shown in FIG. 9 , the above ratio may be higher than 75%.

FIG. 10 shows a simplified top view of a wafer 600 including a multi-die structure 610 as an example embodiment of such a “super-die.” As shown in FIG. 10 , the multi-die structure 610 includes a plurality of IC dies, such as IC dies 620 , 621 , 622 , 623 , arranged in an array having M rows and N columns. M and N are integers greater than 2. In some embodiments, M and N may each be in a range between 7 and 16. For simplicity and clarity, the multi-die structure 610 in FIG. 10 has 2 rows and 2 columns (and thus has 4 IC dies), thereby forming a 2×2 array, although it should be understood that the multi-die structure 610 as an actually manufactured structure may include a greater number of rows and/or columns (and thus has hundreds or thousands of IC dies). In some embodiments, all IC dies formed on wafer 600 are located within multi-die structure 610. In other embodiments, wafer 600 may include a small number of other IC dies that are not part of multi-die structure 610 (e.g., less than 10% of the number of IC dies in multi-die structure 610), but for simplicity, these other IC dies are not specifically shown in the embodiment of FIG. 10 .

Similar to the above-mentioned IC dies 220-229, each of the IC dies 620, 621, 622, 623 includes a circuit, which can be implemented using multiple transistors (e.g., FinFET devices or GAA devices) formed on a substrate. Also similar to the IC dies 220-229, each of the IC dies 620, 621, 622, 623 is surrounded by a corresponding sealing ring 270 in the top view, and the sealing ring 270 can be considered as an inner sealing ring layer to protect the corresponding IC die from moisture or other contaminants.

Each sealing ring 270 includes one or more openings 640 that allow conductive elements 370 to extend therethrough. As described above, since each sealing ring 270 may be comprised of a vertical stack of metal lines 310, vias 320 (disposed between metal lines 310), and conductive pads 340 (see, e.g., FIG. 4 ) disposed above the metal lines 310, each of the openings 640 may correspond to (or be defined by) a discontinuity in such a vertical stack. For example, a metal line 310 in one of the metal layers may have a break, or one of the conductive pads 340 may have a break, which forms an opening 640 that allows a conductive element 370 to extend therethrough. A first subset of horizontally extending conductive elements 370 electrically couples together the circuits of two adjacent die in a given row. A second subset of vertically extending conductive elements 370 electrically couples together the circuits of two adjacent die in a given column. When this is repeated over multiple rows and columns, all of the IC die of the multi-die structure 610 are electrically interconnected. In some embodiments, the IC die 620, 621, 622, 623 are substantially identical to one another. For example, the IC die 620, 621, 622, 623 use the same IC layout design and are manufactured using the same manufacturing process (e.g., using the same set of lithography masks). By electrically interconnecting all of the IC die 620, 621, 622, 623, their collective processing power and/or storage capacity can allow the multi-die structure 610 to be used as an enhanced computer tool, such as a supercomputer or component thereof.

The multi-die structure 610 also includes a sealing ring 280 that surrounds all of the IC dies 620, 621, 622, 623, the sealing ring 270, and the conductive elements 370 in a top view. The sealing ring 270 serves as an outer sealing ring layer to protect the IC dies 620, 621, 622, 623, the sealing ring 270, and the conductive elements 370 from moisture or other contaminants, or to buffer them from mechanical stresses applied to the multi-die structure 610 during the singulation process. As shown in FIG. 10 , the sealing ring 280 may also include a plurality of openings 650 that allow a subset of the conductive elements 370 to extend therethrough. Similar to the opening 640 of the sealing ring 270 , the opening 650 of the sealing ring 280 is also defined by a discontinuity or gap in the metal wires or conductive pads that together constitute the sealing ring 280 .

In some embodiments, other structures (e.g., other IC dies, not shown herein) may be electrically interconnected to the IC dies within the multi-die structure 610 via the conductive elements 370 extending through the openings 650. In some embodiments, there are no IC dies outside the seal ring 280 on the wafer 600. In other words, all IC dies are implemented within the multi-die structure 610 and are surrounded/protected by the seal ring 280. In such embodiments, the conductive elements 370 do not have to extend through the openings 650 to the outside of the seal ring 280 because there are no electrical components interconnected outside of the seal ring 280. However, the openings 650 and a subset of the conductive elements 370 extending through the openings 650 may still be maintained. This is because it is easier to repeat the manufacturing process between rows and columns for each IC die and its respective seal ring 270 and conductive elements 370 (extending from the four sides of the IC die) to form the components of the multi-die structure 610 (including IC dies at the edges or dies directly adjacent to the seal ring 280). It would be more complicated and expensive to design a different set of lithography masks to take into account that the IC dies at the edges of the multi-die structure 610 do not need to form some of the conductive elements that would extend beyond the seal ring 280. Therefore, even though these conductive elements 370 (even though they are not electrically coupled to any other IC die) extend beyond the seal ring 280, they are considered a byproduct of the manufacturing process in this case because they do not serve any useful purpose in the scenario.

The ends of these conductive elements can be sawed off or separated during a singulation process performed along the scribe lines outside the sealing ring 280 to separate the multi-die structure 610 from the rest of the wafer. Therefore, the extent to which the conductive elements 370 extend outside the sealing ring 280 depends on the distance between the scribe lines and the sealing ring 280.

FIG. 11 shows another top view of a wafer 600 including an embodiment of a multi-die structure 610, including an enlarged top view of the multi-die structure 610. The multi-die structure 610 includes an array of IC die R ₁₁ -R _mn arranged in M rows (rows R1-Rm) and N columns (columns C1-Cn). A portion of the conductive elements 370 extending in the X direction electrically interconnects the IC dies (e.g., dies R ₁₁ -R _1n ) in each row. Another portion of the conductive elements 370 extending in the Y direction electrically interconnects the IC dies (e.g., dies R ₁₁ -R _m1 ) in each column.

As described above, the conductive elements extend into their respective interconnected IC dies through the openings in the seal ring 270 surrounding each IC die. However, depending on design requirements, some IC dies within the multi-die structure 610 may not need to be interconnected. For example, IC die R ₂₂ and IC die R ₂₃ do not need to be electrically coupled together, so there is no conductive element 370 between IC die R ₂₂ and IC die R _23. In some embodiments, IC dies R ₁₁ -R _mn are substantially identical to each other, which can enhance the overall processing capability and/or storage capability of the multi-die structure 610.

FIG. 11 also shows scribe lines 670, 671, 672, and 673 on four sides of the multi-die structure 610. Specifically, the scribe lines 670, 671, 672, and 673 are located in a region of the multi-die structure 610. The wafer 600 is outside the sealing ring 280. In the singulation process, wafer separation or sawing equipment is used to separate or saw along the scribe lines 670, 671, 672, and 673 to separate the multi-die structure 610 from the rest of the wafer 600. Because the sealing ring 280 is located within the scribe lines 670, 671, 672, and 673, the sealing ring 280 is retained for the multi-die structure 610. Thus, the sealing ring 280 can help protect the microelectronic components within the multi-die structure 610 from mechanical forces (eg, deformation forces) generated by the singulation or sawing process, and can also protect the microelectronic components from moisture or other contaminant particles.

In the embodiment shown in FIG. 11 , other structures may be implemented on areas of wafer 600 outside of multi-die structure 610. For example, structure 680 may be implemented on the “left side” of wafer 600 and/or the “right side” of multi-die structure 610. For example, structure 680 may include another IC die that may or may not have the same IC design layout or functionality as IC die R ₁₁ -R _m1 in multi-die structure 610. In another example, structure 680 may include a test structure or a measurement structure that includes electronic circuitry for testing or measuring the performance or status of components within multi-die structure 610. Therefore, in some embodiments, it may be desirable to establish electrical connections between structure 680 and multi-die structure 610, at least while multi-die structure 610 is still in the manufacturing process and before singulation. For example, a subset of conductive elements 370A may be used to establish electrical connections between one of structures 680 and IC die R _1n within multi-die structure 610. As shown in FIG. 11 , opening 650 of seal ring 280 allows conductive element 370A to extend through seal ring 280 to electrically interconnect structure 680 and IC die R _1n .

It should be understood that after the fabrication of the multi-grain structure 610 is completed and in embodiments where electrical connections between the multi-grain structure 610 and external devices are no longer required, the singulation process may remove portions of the conductive elements (e.g., conductive elements 370A) extending beyond the scribe line (e.g., beyond the scribe line 671). Therefore, the final device of the multi-grain structure 610 may include the conductive elements 370 having sawn-off or separated ends.

Some IC dies within the multi-die structure 610 do not need to be connected to any device outside the multi-die structure 610. For example, the dies R11-Rm1 do not need to establish any connection between them and the structures 680 on the "left side" of the multi-die structure 610. For example, these structures 680 can be dummy features implemented for pattern uniformity purposes, or they can be alignment marks or overlay marks. In any case, since these structures 680 do not need to be electrically interconnected to the IC dies R ₁₁ -R _m1 , there is no need to form the conductive elements 370 on the "left side" of the IC dies R ₁₁ -R _m1 . Alternatively, even if the conductive elements 370 are formed on the "left side" of the IC dies R ₁₁ -R _m1 , their ends may be cut off along the sawing lines 673 during the above-mentioned singulation process.

Note that the conductive elements 370 may be implemented using any suitable shape or configuration, such as the shapes or configurations shown in FIGS. 5-6. For example, the conductive elements 370 need not be straight, but may include one or more corners, and they may also be implemented directly between the seal rings 270 and 280 (see FIG. 6). However, in most embodiments (such as the embodiment shown in FIG. 11), it may be easier to implement the conductive elements 370 as straight rectangular features directly between each pair of adjacently disposed IC dies within the multi-die structure 610. Such embodiments may leave the corner regions 700 empty, where the corner regions 700 refer to the regions of the multi-die structure 610 located between the corners of four adjacent IC dies. To further utilize these empty spaces, dummy structures 450, test structures 460, and/or patterns 470 (e.g., alignment marks or overlay marks) may be implemented in the corner regions 700. As described above, when the IC die of the multi-die structure 610 is fabricated, the dummy structures 450, test structures 460, and/or patterns 470 in the corner regions 700 may improve pattern uniformity or other manufacturing process-related metrics, and/or may free up valuable chip space that can be used within the IC die to implement equivalent or similar structures/patterns.

Another benefit achieved by implementing the multi-die structure 610 at the wafer level is that more dies can be packaged on a given wafer. In more detail, traditional wafer manufacturing can form multiple IC dies on a given wafer, but at some point, these IC dies will need to be separated from each other (for example, by a singulation process) and packaged individually before they can be sold as finished products. In order to ensure that the singulation process does not accidentally damage the IC die (for example, by sawing into the IC die, or even if the mechanical separation/sawing tool does not directly saw into the IC die, it will cause excessive mechanical stress on the IC die), traditional wafer manufacturing requires that a sufficiently large spacing be maintained between adjacent IC dies. This can be referred to as the inter-die spacing. Because no functional microelectronic components of the IC die are placed in such spaces, the wafer area corresponding to the inter-die pitch can be considered as wasted space. As semiconductor device processes continue to scale down, the available space on the wafer becomes more valuable, so there is a need to reduce the die-to-die pitch so that more IC dies can be formed on a given wafer. Unfortunately, with conventional wafers, it is difficult to further reduce the die-to-die pitch because the die-to-die pitch should exceed the width of the singulation/sawing tool (e.g., blade), which may have a fixed size.

However, IC dies formed as part of the multi-die structure 610 can be packed more closely together because they do not need to be packaged individually, which means that there is no need to use a singulation/sawing tool to cut in the area between adjacent IC dies. In other words, because there is no need to implement scribe lines within the multi-die structure 610, and because there are very few other structures (if any) that need to be formed on the wafer 600 outside of the multi-die structure 610, the IC dies in the multi-wafer structure can be closer to nearby IC dies than in a conventional wafer. The closer proximity between IC dies here can be represented by the ratio between the inter-die spacing 710 and the size 715 of one of the IC dies. As a simplified example, the example inter-die spacing 710 shown in FIG. 11 is the Y-direction distance between IC die _R12 and IC die _R22 , and dimension 715 is the Y-direction dimension of IC die _R22 (which may be substantially the same for all IC dies in multi-die structure 610). It is understood that similar inter-die spacing and IC die dimensions may also be achieved in the X-direction.

In any case, the ratio between the die spacing 710 and the dimension 715 of the multi-die structure 610 is smaller than the corresponding ratio in a conventional wafer. For example, in a conventional wafer with IC dies having the same dimensions as the IC dies R ₁₁ -R _mn of the present specification, the die spacing can be 2 to 4 times larger than the die spacing 710 of the present specification, and the ratio between the die spacing 710 and the dimension 715 can be about 2 to 4 times smaller than the corresponding ratio in a conventional wafer with IC dies of the same dimensions (for like products). Again, the smaller ratio is possible because substantially all of the IC dies on the wafer 600 are formed in the multi-die structure 610 and therefore do not need to be singulated and packaged individually. Thus, the inter-die spacing 710 may even be smaller than the width of a singulation/saw tool used to perform the singulation process (in the case of a multi-die structure 610, only used to cut the outer portion of the seal ring 280). Thus, even though the overall size of wafer 600 is the same as a conventional wafer, the number of IC dies that can be formed thereon may exceed the number of IC dies formed on a conventional wafer of the same size, at least in part because the IC dies may be more densely packed. Thus, the multi-die structure 610 may increase yield and/or reduce manufacturing costs.

FIG. 12 shows a top view of a portion of a multi-die structure 610 undergoing a manufacturing process according to an embodiment of the present disclosure. In step 720, IC die 620 is formed along with its seal ring 270 and the “left” portion of conductive element 370A using a first set of lithography processes (e.g., exposure and development processes). The “left” portion of conductive element 370A extends through opening 640 of seal ring 270 surrounding IC die 620. In step 730, IC die 621 (located on the “right side” of IC die 620 in the X direction) is formed along with its seal ring 270 and the “right” portion of conductive element 370B using a second set of lithography processes (e.g., exposure and development processes). The “right” portion of conductive element 370B extends through opening 640 of seal ring 270 surrounding IC die 621 .

The "left" portion of the conductive element 370A and the "right" portion of the conductive element 370B merge with each other in the X direction at region 740 to jointly form a conductive element 370, which is electrically interconnected with the IC dies 620 and 621. In order to ensure the merging of the "left" portion of the conductive element 370A and the "right" portion of the conductive element 370B, the "left" portion of the conductive element 370A and the "right" portion of the conductive element 370B are each initially configured to have a sufficiently long length in the X direction. For example, it is assumed that the conductive element 370 finally formed has a length of 750 in the X direction. In this case, the "left" portion of the conductive element 370A and the "right" portion of the conductive element 370B are configured so that they each have an initial length 760, wherein the initial length 760 is greater than 1/2 of the length 750. This configuration provides a safety margin so that the “left” portion conductive element 370A and the “right” portion conductive element 370B can be merged even if defects in the manufacturing process cause the “left” portion conductive element 370A and the “right” portion conductive element 370B to drift relative to each other.

As mentioned above, one of the problems with conventional devices and their manufacture is that even though multiple dies can be formed on the same wafer, the connection between the dies is made after each die has been formed (e.g., after the die has been separated). This results in additional masks and processes. If two or more different types of dies need to be interconnected, because the dies to be interconnected are formed by different processes, it will increase the manufacturing cost and processing time, and it may be necessary to break the existing sealing ring formed around these individual dies and reconnect them.

To overcome these problems, another aspect of the present disclosure is to form and interconnect different types of die on the same wafer (each die has its own seal ring), and to form the seal ring to surround the interconnected die, wherein the interconnection can be performed using the same mask or photomask. Thus, the manufacturing time and cost will be reduced. For example, FIG. 13 shows a top view of an embodiment of a wafer-level structure 200 that helps illustrate the above concepts. For clarity and consistency, similar components appearing in FIG. 13 and previous figures (e.g., FIG. 2) will have the same reference numerals.

As shown in FIG. 13 , the interconnected IC die 250 shown in the embodiment of FIG. 5 includes interconnected IC die 250 and 251 formed on wafer 205. The interconnected IC die 250 includes individual IC die 220 and 221, which are circumferentially surrounded by respective sealing rings 270 in the top view. In the top view, the interconnected IC die 250 itself is circumferentially surrounded by sealing ring 280. In the illustrated embodiment, IC die 220 and 221 are the same type of die. For example, they can each be a central processing unit (CPU). At the same time, the interconnected IC die 251 includes individual IC die 222 and 223, which are also circumferentially surrounded by respective sealing rings 270 in the top view. In the top view, interconnected IC die 251 is circumferentially surrounded by another sealing ring 280. However, unlike interconnected IC die 250, IC die 222 and 223 are not uniform because they are different types of die and/or have different functions. For example, IC die 222 may be a CPU, and IC die 223 may be a storage device, such as a dynamic random-access memory (DRAM) device.

Although IC dies 222 and 223 are different types of devices, they can be manufactured substantially simultaneously, such as on the same wafer and using the same process tools (although the transistors and interconnects formed on each IC die 222 and 223 may be different). Therefore, compared to a conventional process in which IC dies 222 and 223 must be manufactured separately, process cost and time are greatly reduced.

It should be understood that implementing IC die 222 as a CPU and IC die 223 as a DRAM device is merely a non-limiting example, and IC die 222 and 223 may be flexibly implemented as other different types of devices and/or have different functions, depending on design requirements. In addition, whether or not they are the same type of IC die, IC die 222 and 223 may be implemented to have different sizes. For example, IC die 222 and 223 may each be a memory device, but IC die 222 may have a larger or smaller area than IC die 223 in a top view.

It should also be understood that there is still an interstitial region 350 for interconnected IC die 250 and interconnected IC die 251. Useful structures can be formed in the interstitial region 350. In the embodiment shown, the useful structures can include conductive elements 370 that extend in the Y direction to electrically interconnect IC die 220, 221 together, or to interconnect IC die 222, 223 together. In other embodiments, dummy structures 450, test structures 460, and patterns 470 (discussed above with reference to FIG. 7) can also be implemented in the interstitial region 350.

FIG. 14 shows a top view of another embodiment of a wafer-level structure 200 according to aspects of the present disclosure. For clarity and consistency, similar components appearing in FIG. 2 and previous figures will have the same reference numerals. As shown in FIG. 14, an interconnected IC die 250C formed on a wafer 205 includes four IC dies 220, 221, 222, and 223 electrically interconnected. IC dies 220, 221 are electrically interconnected through a first set of conductive elements 370, and IC dies 222, 223 are electrically interconnected through a second set of conductive elements 370. In addition, IC dies 220 and 223 are electrically interconnected through conductive element 371, and IC dies 222 and 221 are electrically interconnected through conductive element 372. Conductive elements 371 and 372 extend in a diagonal direction because IC dies 220 and 223 are placed diagonally to each other, as are IC dies 221 and 222. In some embodiments, the diagonal direction is 45 degrees to the X-direction or the Y-direction. This is a more efficient way to electrically interconnect diagonally arranged IC dies 220, 221, 222, 223 (or diagonally arranged IC dies 221, 222). It will be appreciated that although only a single conductive element 371 and a single element 372 are shown for simplicity, conductive element 371 may include multiple conductive elements, as may conductive element 372.

FIG. 15 shows a top view of another embodiment of a wafer-level structure 200 according to aspects of the present disclosure. For clarity and consistency, similar components appearing in FIG. 14 and previous figures will have the same reference numerals. As shown in FIG. 15, an interconnected IC die 250C formed on a wafer 205 includes four IC die 220, 221, 222, and 223 electrically interconnected together. The IC die 220, 221 are electrically interconnected together through a first set of conductive elements 370, and the IC die 222, 223 are electrically interconnected together through a second set of conductive elements 370. In addition, the IC die 220 and 223 are electrically interconnected together through diagonally arranged conductive elements 371 (e.g., extending partially in the X direction and partially in the Y direction). In other embodiments, the conductive element 371 may extend at any sharp angle (eg, any angle between 0 degrees and 90 degrees) as long as the process variation is controlled within an acceptable range.

The IC dies 222 and 221 are electrically interconnected via another conductive element 373. The conductive element 373 includes a plurality of segments, some of which extend in the Y direction and others extend in the X direction. By electrically interconnecting the diagonally disposed IC dies 221, 222 using a conductive element 373 that extends in the X direction and the Y direction but not in the diagonal direction, the embodiments of the present specification can avoid chip stress release (CSR) regions. In this regard, an enlarged view of the CSR region is also shown in FIG. 15, which can include any corner regions of the IC dies 220, 221, 222, 223. The CSR region includes a reinforced portion of the sealing ring for better protecting the corners of the IC dies 220, 221, 222, 223. By avoiding the CSR region, the embodiments herein can reduce the difficulty of forming the conductive element 373 (and/or other interconnect metals).

FIG. 16 shows a top view of another embodiment of a wafer-level structure 200 according to aspects of the present disclosure. For clarity and consistency, similar components appearing in FIG. 16 and previous figures will have the same reference numbers. As shown in FIG. 16, the wafer-level structure 200 includes a multi-die structure similar to the multi-die structure 610 discussed above with reference to FIG. 11. For example, the wafer-level structure 200 includes an array of IC dies A ₁₁ -A _nn formed on the same wafer. The IC dies A ₁₁ -A _nn are arranged in a plurality of rows Y ₁ -Y _n and a plurality of columns X ₁ -X _n . In the top view, each of the IC dies A ₁₁ -A _nn is circumferentially surrounded by a corresponding sealing ring 270, and in the top view, the IC die array is collectively circumferentially surrounded by a sealing ring 280.

Conductive element 370 extends into IC dies _A11 - _Ann to electrically interconnect them together. In addition, conductive elements 374, 375, and 376 are implemented to further interconnect IC dies that are not adjacent to each other in the X direction or the Y direction. For example, conductive element 374 extends in a diagonal direction to electrically interconnect IC dies _A12 and _A21 that are arranged diagonally adjacent to each other. As another example, conductive element 375 extends in another diagonal direction to electrically interconnect IC _{dies A21} and _{A32 ,} which are also arranged diagonally adjacent to each other. As a further example, the conductive element 376 has multiple segments and extends in both the X-direction and the Y-direction to electrically interconnect the IC dies A _n2 and A _3n , which are arranged diagonally to each other (but not adjacent) because the IC dies A _n2 and A _3n are separated by multiple rows in the Y-direction. In some embodiments, some of the IC dies A ₁₁ -A _nn may also be of different types or have different functions. For example, the IC die A ₁₁ may be a CPU, while the IC die A _nn may be a DRAM device. The IC dies A ₁₁ -A _nn may also have different sizes.

FIG. 17 is a flow chart showing a method 500 for manufacturing a semiconductor device according to an embodiment of the present disclosure. The method 500 includes a step 510 of forming an active layer of a first integrated circuit (IC) die and a second IC die in a substrate. Please note that at this point, the first IC die and the second IC die are not yet fully formed.

The method 500 includes step 520 to form an internal connection structure of the first IC die and the second IC die above the active layer. The internal connection structure includes a first sealing ring, a second sealing ring, and a third sealing ring. In the top view, the first sealing ring and the second sealing ring surround the first IC die and the second IC die, respectively. The third sealing ring surrounds the first IC die, the second IC die, the first sealing ring, and the second sealing ring in the top view. The internal connection structure also includes a plurality of conductive elements extending into the first IC die and the second IC die and electrically coupling the first IC die and the second IC die together.

The method 500 includes step 530 of forming one or more test structures, one or more dummy structures, one or more process monitoring patterns, one or more alignment marks, or one or more cover marks in a region outside the first sealing ring and the second sealing ring, but still surrounded by the third sealing ring.

In some embodiments, the step 510 of forming the active layer is performed so that the first IC die and the second IC die are different types of IC die or have different functions. For example, the first IC die may be a CPU and the second IC die may be a DRAM.

In some embodiments, the first IC die and the second IC die are located diagonally relative to each other, and the step 520 of forming the interconnect structure is performed such that the conductive element extends diagonally into the first IC die or into the second IC die.

It should be understood that method 500 may include additional steps performed before, during, or after steps 510 to 530. For example, method 500 may include wafer testing, singulation, and packaging processes. For simplicity, these additional steps are not discussed in detail in this specification.

FIG. 18 is a flow chart showing a method 800 for manufacturing a semiconductor device according to an embodiment of the present disclosure. The method 800 includes a step 810 of forming an active layer of a plurality of first integrated circuit (IC) dies above a substrate.

The method 800 includes step 820 of forming an interconnect structure of the first IC die above the active layer. The interconnect structure includes: a plurality of first sealing rings surrounding each first IC die in a top view; a plurality of conductive elements extending through gaps of the first sealing rings to electrically interconnect the first IC dies together to form a multi-die structure, and a second sealing ring surrounding the first IC die, the first sealing rings, and the conductive elements in a top view.

The method 800 includes step 830 of forming one or more test structures, one or more dummy structures, one or more process monitoring patterns, one or more alignment marks, or one or more cover mark structures within the second seal ring but outside each first seal ring in the region of the multi-die.

The method 800 includes step 840 of performing a singulation process along the scribe line outside the second seal ring. The area inside the second seal ring is not singulated.

In some embodiments, the first sealing ring includes metal lines forming a plurality of vertical stacks and vias disposed between the metal lines.

In some embodiments, each conductive element has a first length, and wherein each group of conductive elements is formed by: performing a first exposure process to define a first segment of each conductive element in each group, the first segment having a second length greater than 50% of the first length; performing a second exposure process to define a second segment of each conductive element in each group, the second segment having a third length greater than 50% of the first length. Portions of the first segment and the second segment overlap and merge with each other. It should be understood that method 800 may include additional steps performed before, during, or after steps 810 to 840. For example, method 800 may include the steps of testing and packaging the first IC die. For simplicity, these additional steps are not discussed in detail in this specification.

FIG. 19 illustrates an integrated circuit manufacturing system 900 according to an embodiment of the present disclosure. The manufacturing system 900 includes a plurality of entities 902, 904, 906, 908, 910, 912, 914, 916 ..., N connected by a communication network 918. The network 918 may be a single network or may be a plurality of different networks, such as a local area network and the Internet, and may include wired and wireless communication channels.

In some embodiments, entity 902 represents a service system for manufacturing protocols; entity 904 represents a user, such as a product engineer who monitors a product of interest; entity 906 represents an engineer, such as a process engineer who controls a process and associated recipes, or an equipment engineer who monitors or adjusts conditions and settings of a process tool; entity 908 represents a metrology tool used for IC testing and measurement; entity 910 represents a semiconductor processing tool, such as an EUV tool used to perform a lithography process to define gate spacers for SRAM devices; entity 912 represents a virtual metrology module associated with processing tool 910; entity 914 represents an advanced process control module associated with processing tool 910 and other processing tools; entity 916 represents a sampling module associated with processing tool 910.

Each entity may interact with other entities and may provide integrated circuit manufacturing, process control and/or computing capabilities to other entities and/or receive capabilities from other entities. Each entity may also include one or more computer systems for performing calculations and performing automation. For example, the high-level processing control module of entity 914 may include a plurality of computer hardware having software instructions encoded therein. The computer hardware may include hard drives, flash drives, CD-ROMs, RAM memory, display devices (e.g., screens), input/output devices (e.g., mice and keyboards). The software instructions may be written in any suitable programming language and may be designed to perform specific tasks.

The integrated circuit manufacturing system 900 implements interaction between entities and integrated circuit (IC) manufacturing and advanced process control of IC manufacturing. In some embodiments, the advanced process control includes adjusting process conditions, settings and/or processes of process tools applied to related wafers based on measurement results.

In other embodiments, the metrology results are measured from a subset of processed wafers at an optimal sampling rate determined based on process quality and/or product quality. In still other embodiments, the metrology results are measured from specific areas and points selected from a subset of processed wafers, which are optimal sampling areas/points determined based on various characteristics of process quality and/or product quality.

One of the capabilities provided by the IC manufacturing system 900 is to enable collaboration and information access in areas such as design, engineering, process, metrology, and advanced process control. Another function provided by the IC manufacturing system 900 is to enable system integration between facilities, such as between metrology tools and processing tools. This integration enables the facilities to coordinate their activities. For example, integrating metrology tools and processing tools can more effectively incorporate manufacturing information into manufacturing processes or automatic program control modules, and can also enable wafer data measured online or in the field to be integrated with metrology tools.

The above-described advanced lithography processes, methods, and materials can be used in many applications, including fin field effect transistors (FinFETs). For example, fins can be patterned to produce relatively tight spacing between features, and the present disclosure is well suited for this. In addition, spacers (also known as mandrels) used in forming FinFET fins can be processed according to the above disclosure. At the same time, various aspects of the present disclosure can also be applied to multi-channel devices, such as gate-all-around (GAA) devices. To the extent that the present disclosure discusses fin structures or FinFET devices, these discussions are equally applicable to GAA devices.

The present disclosure may have advantages over conventional devices. However, it should be understood that not all advantages are discussed herein, different embodiments may have different advantages, and no embodiment requires a particular advantage. One advantage is improved chip area utilization. This is achieved by forming different structures in various areas of the wafer that would otherwise be considered wasted space. For example, a wafer may include multiple first sealing rings, each of which surrounds a respective IC die in a top view, and these first sealing rings are collectively surrounded by another second sealing ring. Within the second sealing rings, various structures are formed in areas between the first sealing rings that would otherwise constitute wasted space. These structures may include conductive elements used to interconnect adjacent IC dies, dummy features used to improve pattern uniformity or other manufacturing metrics, test structures used to test circuit performance on the wafer, or alignment marks or overlay marks used to measure lithography accuracy/precision, etc. By forming these structures in otherwise wasted areas of the wafer, they no longer need to be formed inside the IC die, freeing up valuable chip real estate for forming other functional circuit elements therein.

Another advantage is that the multi-grain structure can be formed as a wafer-level structure. For example, most (if not all) of the IC dies on a wafer (each surrounded by its own first sealing ring) can be electrically interconnected and then surrounded by a second sealing ring. This results in a "super-grain" structure (or more generally a multi-grain structure). Such a multi-grain structure can provide superior performance and/or capabilities compared to traditional IC dies. For example, in an embodiment where the multi-grain structure is formed by electrically interconnecting multiple computer processor dies (which can be substantially identical to each other), such a multi-grain structure can provide much faster processing speeds or greater processing capabilities than traditional computer processor dies. The multi-grain structure can even be used as a component of a supercomputer. In another example, as another example, in an embodiment where multiple electronic storage dies (such as SRAM or DRAM) are electrically interconnected to form a multi-die structure, such a multi-die structure can provide greater storage capacity than traditional electronic storage dies. In addition, because the multi-die structure is formed and interconnected at the wafer level, they can be packaged more tightly together because they do not need to be divided and packaged into separate ICs. In this way, the number of IC dies (as part of a multi-die structure) that can be formed on a wafer of a given area is increased compared to traditional wafers where IC dies must be packaged individually. This can further improve the performance of the final structure and/or reduce manufacturing costs. Other advantages may include compatibility with existing manufacturing processes (including FinFET and GAA processes) and ease and low cost of implementation.

The disclosed embodiment provides a semiconductor device, including a die array of a plurality of dies formed on a substrate, wherein each of the dies in the die array includes a plurality of functional transistors; a plurality of first sealing rings, each surrounding a corresponding one of the dies in a top view, wherein the first sealing ring defines a plurality of corner regions, which are disposed outside the first sealing ring and between corners of a corresponding subset of the dies; a plurality of structures, which are disposed in the corner regions; A first sealing ring is provided for enclosing a first die array and a second sealing ring. The first sealing ring is provided for enclosing a first die array and a second sealing ring. The first sealing ring is provided for enclosing a first die array and a second sealing ring. The first sealing ring is provided for enclosing a first die array and a second sealing ring. The first sealing ring is provided for enclosing a first die array and a second sealing ring.

In some embodiments, there are no functional transistors in the corner area. In some embodiments, each of the first sealing rings includes a plurality of first openings; and the electrical interconnect elements extend through the first openings to electrically connect the die in the die array. In some embodiments, the second sealing ring includes a second opening; each of the first sealing ring and the second sealing ring includes a corresponding plurality of metal wires and a vertical stack of a plurality of vias, the vias being vertically disposed between the metal wires; each of the first sealing ring and the second sealing ring includes a corresponding set of conductive pads disposed above the vertical stack of metal wires and vias; and the first opening and the second opening correspond to an opening of one of the metal wires or an opening of one of the conductive pads. In some embodiments, the second sealing ring includes a second opening, and a subset of the electrical interconnect elements extend through the second opening and a corresponding one of the first openings. In some embodiments, a subset of the electrical interconnect elements extends through the second opening and extends outside the second sealing ring; and the subset of the electrical interconnect elements has a segmented end. In some embodiments, the semiconductor device further includes a circuit formed on the substrate, wherein in a top view, the circuit is located outside the second sealing ring; and the subset of the electrical interconnect elements electrically couples the circuit to the die array. In some embodiments, the die array includes M rows extending in a first direction and N columns extending in a second direction, and M and N are integers greater than 2. In some embodiments, a first group of electrical interconnect elements extends in the first direction to electrically interconnect the die in each row; and a second group of electrical interconnect elements extends in the second direction to electrically interconnect the die in each column. In some embodiments, the device is a wafer-level structure; and the wafer-level structure has no other die except the die array. In some embodiments, the device is a wafer-level structure including a plurality of dies outside a second sealing ring; and the dies surrounded by the second sealing ring account for more than 50% of all dies formed on the wafer-level structure. In some embodiments, in a top view, each of the dies outside the second sealing ring is surrounded by at most one sealing ring. In some embodiments, the dies in the die array have the same integrated circuit layout.

The disclosed embodiment provides a wafer-level structure, including a plurality of integrated circuit dies formed on a substrate, wherein the integrated circuit dies have substantially the same integrated circuit layout; a plurality of first sealing rings, each surrounding a corresponding one of the integrated circuit dies in a top view, wherein each of the first sealing rings includes a plurality of first openings; a plurality of first structures, disposed between adjacent integrated circuit dies outside the first sealing rings, wherein the first structures include test structures, dummy structures, process monitoring patterns, alignment marks, or cover marks; a plurality of electrical interconnect elements, extending through the first sealing rings; An opening is used to electrically interconnect integrated circuit grains to form a multi-grain integrated circuit, the multi-grain integrated circuit including a first structure; a second sealing ring, which surrounds the multi-grain integrated circuit in a top view, wherein the first sealing ring is surrounded by the second sealing ring together, and each of the first sealing ring and the second sealing ring includes a plurality of metal wires and a plurality of through holes vertically arranged between the metal wires; and one or more second structures are formed in a plurality of regions of the substrate, the regions are located outside the second sealing ring in a top view, wherein the one or more second structures are not surrounded by more than one sealing ring in a top view.

In some embodiments, the one or more second structures include a plurality of additional IC dies; the second seal ring includes one or more second openings; and the additional IC dies are electrically coupled to the multi-die IC via a subset of electrical interconnects, the subset of electrical interconnects also extending through the one or more second openings. In some embodiments, the wafer-level structure of claim 15, wherein the IC dies of the multi-die IC account for at least 50% of all IC dies on the wafer-level structure.

The disclosed embodiment provides a method for forming a semiconductor device, comprising performing a multi-step lithography process to form a plurality of first integrated circuit dies on a substrate, wherein the first integrated circuit dies are substantially identical to each other and are arranged in an array having a plurality of rows and a plurality of columns; forming a plurality of first sealing rings to surround each of the first integrated circuit dies in a top view, wherein each of the first sealing rings has a plurality of spacings therein; forming a plurality of sets of conductive elements extending through the spacings of the first sealing rings to electrically interconnect the first integrated circuit dies to form a multi-die structure, wherein the plurality of conductive elements are electrically connected to each other through the first sealing rings to form a multi-die structure; The method comprises forming a second sealing ring which surrounds the first integrated circuit die, the first sealing ring, and the conductive elements in a top view; forming one or more test structures, one or more dummy structures, one or more process monitoring patterns, one or more alignment marks, or one or more cover marks in a plurality of regions of the multi-die structure, the regions being located in the second sealing ring but outside the first sealing ring; and performing a segmentation process along a plurality of scribe lines outside the second sealing ring, wherein the regions in the second sealing ring are not segmented.

In some embodiments, forming the first sealing ring includes forming a plurality of vertical stacks of a plurality of metal lines and a plurality of vias disposed between the metal lines. In some embodiments, each of the conductive elements has a first length, and each group of conductive elements is formed by: performing a first exposure process to define a first segment of each of the group of conductive elements, the first segment having a second length, the second length being greater than 50% of the first length; and performing a second exposure process to define a second segment of each of the group of conductive elements, the second segment having a third length, the third length being greater than 50% of the first length, and a portion of the first segment and the second segment overlap and merge with each other. In some embodiments, the semiconductor device forming method further includes forming a plurality of second integrated circuit dies outside the second sealing ring, wherein the number of the first integrated circuit dies accounts for at least 50% of the total number of the first integrated circuit dies and the second integrated circuit dies.

The above content summarizes the features of many embodiments, so that anyone with ordinary knowledge in the art can better understand the various aspects of the present disclosure. Anyone with ordinary knowledge in the art may have no difficulty in designing or modifying other processes and structures based on the present disclosure to achieve the same purpose and/or obtain the same advantages as the embodiments of the present disclosure. Anyone with ordinary knowledge in the art should also understand that making different changes, substitutions and modifications without departing from the spirit and scope of the present disclosure does not exceed the spirit and scope of the present disclosure.

90: IC device 110: substrate 120: active area/fin structure/fin 122: source/drain features 130: isolation structure 140: gate structure 150: GAA device 155: mask 160: gate spacer 165: cap layer 170: nanostructure 175: dielectric interspacer 180: source/drain contact 185: interlayer dielectric 200: wafer level structure 205: wafer 210,211,220,221,222,223,224,225,226,227,228,229,620, 621,622,623: IC die 240: sawing line 250,250A,250B,250C,251: interconnect IC die 270,280: sealing ring 290: semiconductor device 300: multi-layer interconnect structure 310: metal line 320: through hole 330: interlayer dielectric 340: conductive pad 350: gap region 370,370A,370B,370C,370D,371,372,373,374,375,376: conductive element 400,420: width 410,430,710: spacing 450: dummy structure 460: test structure 470: pattern 500,800: method 510,520,530, 720,730,810,820,830,840: Step 600: Wafer 610: Multi-die structure 640,650: Opening 670,671,672,673: Slice 680: Structure 700: Corner region 715: Dimension 740: Region 750: Length 760: Initial length 900: Manufacturing system 902,904,906,908,910,912,914,916,918: Entity A ₁₁ -A _nn : IC die C1-Cn, X1-Xn: Rows R1-Rm, Y1-Yn: Rows R ₁₁ -R _mn : IC die array

The following will be described in detail with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are only used for illustration. In fact, the size of the components may be arbitrarily enlarged or reduced to clearly show the features of the present disclosure. FIG. 1A is a perspective view of a FinFET-type IC device according to various aspects of the present disclosure. FIG. 1B is a plan view of a FinFET-type IC device according to various aspects of the present disclosure. FIG. 1C is a perspective view of a GAA device-type IC device according to various aspects of the present disclosure. FIG. 2 shows a top view of a wafer-level structure according to various aspects of the present disclosure. FIG. 3 to FIG. 4 are side cross-sectional views of an IC device according to various aspects of the present disclosure. FIG. 5 to FIG. 11 show top views of wafer-level structures according to various aspects of the present disclosure. FIG. 12 illustrates a top view of an IC die at different stages of fabrication according to various aspects of the present disclosure. FIGs. 13 to 16 illustrate top views of wafer-level structures and portions thereof according to various aspects of the present disclosure. FIGs. 17 to 18 each illustrate a flow chart of a method according to various aspects of the present disclosure. FIG. 19 is a block diagram of a fabrication system according to various aspects of the present disclosure.

without

200: Wafer-level structure

205: Wafer

210,211,220,221: IC chips

240: Cutting Road

250: Interconnected IC chips

270,280: Sealing ring

310:Metal wire

350: Gap area

370: Conductive element

400,420:Width

410,430: Spacing

Claims (20)

A semiconductor device, comprising: A die array of a plurality of dies, formed on a substrate, wherein each of the dies in the die array comprises a plurality of functional transistors; A plurality of first sealing rings, each surrounding a corresponding one of the dies in a top view, wherein the first sealing rings define a plurality of corner regions, disposed outside the first sealing rings and between corners of corresponding subsets of the dies; A plurality of structures, disposed in the corner regions, wherein the structures are not part of any functional transistor, and the structures comprise test structures, dummy structures, process monitoring patterns, alignment marks, or cover marks; A plurality of electrical interconnect elements, disposed between a pair of adjacent die in the die array in a top view, wherein the electrical interconnect elements electrically connect the die in the die array to each other; and a second sealing ring, surrounding the die array, the first sealing rings, and the structures in a top view. A semiconductor device as claimed in claim 1, wherein there are no functional transistors in the corner regions. A semiconductor device as claimed in claim 1, wherein: Each of the first sealing rings includes a plurality of first openings; and The electrical interconnect elements extend through the first openings to electrically connect the dies in the die array. A semiconductor device as claimed in claim 3, wherein: the second sealing ring includes a second opening; each of the first sealing rings and the second sealing ring includes a corresponding plurality of metal wires and a vertical stack of a plurality of through holes, the through holes being vertically disposed between the metal wires; each of the first sealing rings and the second sealing ring includes a corresponding set of conductive pads disposed above the vertical stack of the metal wires and the through holes; and the first openings and the second openings correspond to an opening of one of the metal wires or an opening of one of the conductive pads. A semiconductor device as claimed in claim 3, wherein the second sealing ring includes a second opening, and a subset of the electrical interconnect elements extend through the second opening and a corresponding one of the first openings. A semiconductor device as claimed in claim 5, wherein: the subset of the electrically interconnected elements extends through the second opening and extends outside the second sealing ring; and the subset of the electrically interconnected elements has segmented ends. The semiconductor device of claim 5 further includes a circuit formed on the substrate, wherein: In the top view, the circuit is located outside the second sealing ring; and The subset of the electrical interconnect elements electrically couples the circuit to the die array. A semiconductor device as claimed in claim 1, wherein the die array includes M rows extending in a first direction and N columns extending in a second direction, and M and N are integers greater than 2. A semiconductor device as claimed in claim 8, wherein: a first group of the electrical interconnect elements extend in the first direction to electrically interconnect the grains in each row; and a second group of the electrical interconnect elements extend in the second direction to electrically interconnect the grains in each column. A semiconductor device as claimed in claim 1, wherein: the device is a wafer-level structure; and the wafer-level structure has no other dies besides the die array. A semiconductor device as claimed in claim 1, wherein: the device is a wafer-level structure including a plurality of dies located outside the second sealing ring; and the dies surrounded by the second sealing ring account for more than 50% of all dies formed on the wafer-level structure. A semiconductor device as claimed in claim 11, wherein in a top view, each of the die outside the second sealing ring is surrounded by at most one sealing ring. A semiconductor device as claimed in claim 1, wherein the dies in the die array have the same integrated circuit layout. A wafer-level structure, comprising: A plurality of integrated circuit dies, formed on a substrate, wherein the integrated circuit dies have substantially the same integrated circuit layout; A plurality of first sealing rings, each surrounding a corresponding one of the integrated circuit dies in a top view, wherein each of the first sealing rings comprises a plurality of first openings; A plurality of first structures, disposed between adjacent integrated circuit dies outside the first sealing rings, wherein the first structures comprise test structures, dummy structures, process monitoring patterns, alignment marks, or cover marks; A plurality of electrical interconnect elements extending through the first openings to electrically interconnect the integrated circuit dies to form a multi-die integrated circuit, the multi-die integrated circuit comprising the first structures; a second sealing ring surrounding the multi-die integrated circuit in a top view, wherein the first sealing rings are surrounded by the second sealing ring together, and each of the first sealing rings and the second sealing ring comprises a plurality of metal wires and a plurality of through holes vertically disposed between the metal wires; and one or more second structures formed in a plurality of regions of the substrate, the regions being outside the second sealing ring in a top view, wherein the one or more second structures are not surrounded by more than one sealing ring in a top view. The wafer-level structure of claim 14, wherein: the one or more second structures include a plurality of additional integrated circuit dies; the second seal ring includes one or more second openings; and the additional integrated circuit dies are electrically coupled to the multi-die integrated circuit via a subset of the electrical interconnect elements, the subset of the electrical interconnect elements also extending through the one or more second openings. The wafer-level structure of claim 15, wherein the integrated circuit dies of the multi-die integrated circuit account for at least 50% of all integrated circuit dies on the wafer-level structure. A method for forming a semiconductor device, comprising: Performing a multi-pass lithography process to form a plurality of first integrated circuit grains on a substrate, wherein the first integrated circuit grains are substantially identical to each other and are arranged in an array having a plurality of rows and a plurality of columns; Forming a plurality of first sealing rings to surround each of the first integrated circuit grains in a top view, wherein each of the first sealing rings has a plurality of spacings; Forming a plurality of sets of conductive elements extending through the spacings of the first sealing rings to electrically interconnect the first integrated circuit grains to form a multi-grain structure, wherein each set of the conductive elements is electrically coupled to two adjacent first integrated circuit grains; Forming a second sealing ring, which surrounds the first integrated circuit dies, the first sealing rings, and the conductive elements in a top view; Forming one or more test structures, one or more dummy structures, one or more process monitoring patterns, one or more alignment marks, or one or more cover marks in a plurality of regions of the multi-die structure, the regions being located in the second sealing ring but outside the first sealing rings; and Performing a segmentation process along a plurality of cutting paths outside the second sealing ring, wherein the region within the second sealing ring is not segmented. A method for forming a semiconductor device as claimed in claim 17, wherein forming the first sealing rings includes forming a plurality of vertical stacks of a plurality of metal wires and a plurality of through holes disposed between the metal wires. A method for forming a semiconductor device as claimed in claim 17, wherein each of the conductive elements has a first length, and each group of the conductive elements is formed by: Performing a first exposure process to define a first segment of each of the conductive elements in the group, the first segment having a second length, the second length being greater than 50% of the first length; and Performing a second exposure process to define a second segment of each of the conductive elements in the group, the second segment having a third length, the third length being greater than 50% of the first length, and a portion of the first segments and the second segments overlap and merge with each other. The semiconductor device forming method of claim 17 further includes forming a plurality of second integrated circuit grains outside the second sealing ring, wherein the number of the first integrated circuit grains accounts for at least 50% of the total number of the first integrated circuit grains and the second integrated circuit grains.