TW202414412A - Memory device having switching device of page buffer and erase method thereof - Google Patents

Abstract

A memory device having a switching device for a page buffer is provided, and includes a plurality of switching units coupled between a memory cell array having a plurality of bit lines and a sense amplification circuit of the page buffer. Each of the plurality of switching units further comprising: a high voltage element and a low voltage element that are connected in series to each other. A first end of the high voltage element is coupled to the sense amplification circuit, and a first end of the low voltage element is coupled to a common source line of the memory cell array. A second end of the high voltage element and a second end of the low voltage element are connected to each other and coupled to a corresponding bit line of the memory cell array. The common source line coupled to each of the plurality of switching units shares a common active region.

Description

Switch device of page buffer, memory device having the switch device and erasing method thereof

The present invention relates to a switch device of a page buffer, a memory device having the switch device and an erasing method thereof.

As memory devices develop, the number of memory cells inside them increases, causing the area of the memory devices to also increase.

The memory device mainly includes a memory array and its related circuits. A page buffer is connected between the bit lines of the memory array and the internal data output lines. Generally speaking, the page buffer may include a switch device, which is composed of a high-voltage device with a thin gate oxide layer and a deep junction to perform an erase operation. Therefore, these high-voltage devices will occupy more area.

Therefore, how to provide a structure of a switch device of a page buffer that can achieve the existing function and reduce the memory area is a topic that requires efforts.

Based on the above description, the present invention provides a switch device of a page buffer, a memory device having the switch device, and an erasing method thereof.

According to an embodiment of the present invention, a memory device having a switch device of a page buffer is provided. The memory device having a switch device of a page buffer includes: a plurality of switch units coupled between a memory cell array and a sense amplifier circuit of the page buffer. Each of the plurality of switch units further includes: a high-voltage element and a low-voltage element, and the high-voltage element and the low-voltage element are connected in series with each other. The first end of the high-voltage element is coupled to the sense amplifier circuit, and the first end of the low-voltage element is coupled to the common source line of the memory cell array. The second end of the high-voltage element and the second end of the low-voltage element are connected to each other and coupled to the corresponding bit line of the memory cell array. The common source line coupled to each of the plurality of switch units shares a common active region.

According to another embodiment of the present invention, a memory device having a switching device of a page buffer is provided. The memory device having a switching device of a page buffer includes: a memory cell array and a page buffer. The memory cell array includes a plurality of bit lines, a plurality of word lines and a plurality of memory cells, and each of the plurality of memory cells is arranged at a position where the plurality of word lines and the plurality of bit lines intersect respectively. The page buffer is coupled to the plurality of bit lines of the memory cell array. The page buffer further includes a switching device and a sensing amplifier circuit. The switching device further includes: a plurality of switch units coupled between the memory cell array and the sensing amplifier circuit. Each of the plurality of switch units further comprises: a high voltage component and a low voltage component, wherein the high voltage component and the low voltage component are connected in series with each other. A first end of the high voltage component is coupled to the sensing amplifier circuit, and a first end of the low voltage component is coupled to a common source line of the memory cell array. A second end of the high voltage component and a second end of the low voltage component are connected to each other and coupled to a corresponding bit line of the memory cell array. The common source lines coupled to each of the plurality of switch units share a common active region.

According to another embodiment of the present invention, a method for erasing a memory device is provided, wherein the memory device has a memory cell array and a page buffer, and the page buffer includes a switch device composed of multiple switch units. Each of the multiple switch elements includes a first transistor as a high-voltage element and a second transistor as a low-voltage element. The first transistor and the second transistor are connected in series with each other. The first end of the first transistor is coupled to the sensing amplifier circuit of the page buffer, and the first end of the second transistor is coupled to the common source line of the memory cell array. The second end of the first transistor and the second end of the second transistor are connected to each other and coupled to the corresponding bit line of the memory cell array, and the common source line coupled to each of the multiple switch units shares a common active region. For each of the plurality of switch units, the erasing method includes: turning off the first transistor; applying a first voltage to the gate of the second transistor to turn on the second transistor; applying an erase voltage to the common source line after the first voltage applied to the gate of the second transistor remains stable for a specified time; boosting the gate voltage of the gate of the second transistor to the sum of the erase voltage and the first voltage by the erase voltage, and boosting the bit line voltage of the corresponding bit line to the erase voltage; and performing bilateral erasing on the memory cell on the corresponding bit line.

FIG1 is a block diagram showing a circuit architecture of a memory device. The memory device 100 basically includes a memory cell array 102, a row decoder 104a, a column decoder 104b, a page buffer 106, a high voltage generator 108, a control circuit 110, a command register 112a, an address register 112b, a status register 112c, an output buffer 114a, a control buffer 114b, a data buffer 114c, a column pre-decoder 116a, and a column pre-decoder 116b.

The memory cell array 102 may be composed of a plurality of memory cells. The memory cell array 102 may include a plurality of bit lines BL and a plurality of word lines WL, and the plurality of memory cells are respectively disposed at the intersections of the plurality of bit lines BL and the plurality of word lines WL. The address signal may be decoded by the row decoder 104a and the column decoder 104b, thereby specifying a specific memory cell in the memory cell array 102 for writing (programming), erasing or reading.

The high voltage generator 108 can generate the high voltage required for memory operation to the memory cell array 102 and the page buffer 106. The control circuit 110 can control all operations of the memory cell array 102 and the peripheral circuits. Other registers and buffers can be used for temporary storage and buffering of various data, signals or commands. The present invention does not limit the structure of the memory device 100. Those skilled in the art can change the design and modification of the internal circuit of the memory device 100 according to the design requirements without affecting the implementation of the present invention.

FIG2 is a circuit diagram of a switch device of a page buffer. As shown in FIG2 , a memory cell array 102 may include a plurality of blocks Block[1]~Block[k], each of which may include a plurality of pages, such as page 1~page i. As shown in FIG2 , each block (such as Block[1]) includes a plurality of bit lines BL0~BLi. Each bit line (such as BL0) may be interlaced with a plurality of word lines WL1~WLi, a string select line (SSL) and a gate select line (GSL). The page buffer 106 includes a sense amplifier circuit 106a and a switch device 106b. The sense amplifier circuit 106a may include a plurality of sense amplifiers SA0~SAi, each of which is coupled to corresponding bit lines BL0~BLi.

In addition, the switch device 106b may include a plurality of switch units, each of which includes a first transistor MN1 and a second transistor MN2. The first transistor MN1 and the second transistor MN2 are connected in series, and the connection point between the first transistor MN1 and the second transistor MN2 is coupled to a corresponding bit line (such as BL0). The gate of the first transistor MN1 receives a bit line selection signal BLS. One of the sources/drains of the first transistor MN1 is coupled to a sense amplifier SA0 corresponding to the bit line BL0 in the sense amplifier circuit 106a, and the other source/drain is coupled to the corresponding bit line BL0. The gate of the second transistor MN2 receives the bias selection signal Bias_select, one of its source/drain is coupled to a common source line CSL, and the other of its source/drain is coupled to the corresponding bit line BL0.

In the switch device 106b, the gate of the first transistor MN1 of each switch unit is coupled together, and the gate of the second transistor MN2 of each switch unit is also coupled together. In addition, in the present embodiment, the first transistor MN1 is a high-voltage component and the second transistor MN2 is a low-voltage component. That is, according to the embodiment of the present invention, each switch unit of the switch device 106b is composed of a transistor as a high-voltage component and a transistor as a low-voltage component. Here, the first transistor MN1 and the second transistor MN2 are, for example, MOS transistors. The first transistor MN1 and the second transistor MN2 may have the same structure but different gate lengths.

Fig. 3A is a schematic circuit diagram of a switch unit of a switch device in a page buffer according to an embodiment of the present invention, and Fig. 3B is a schematic diagram of a layout structure of a switch device of a page buffer according to an embodiment of the present invention. Fig. 3C is a portion of an equivalent circuit of a switch unit of a switch device corresponding to the layout structure of Fig. 3B.

As shown in FIG. 2A , the switch device 106 b is coupled between the memory cell array 102 and the sense amplifier circuit 106 a of the page buffer 106 , and the switch device 106 b is coupled to all the bit lines BL0 ˜BLi of the memory cell array 102 .

The switch device 106b includes a plurality of switch units 200, each of which is shown in FIG3A , and is connected to a corresponding bit line BLj (j=0~i, BL0 in this example) in the memory cell array 102. One end of the switch unit 200 is connected to the sense amplifier SA of the corresponding bit line BL0, and the other end of the switch unit 200 is connected to the common source line CSL of the memory cell array 102. As shown in FIG3A , the switch unit 200 is composed of a high voltage element 202 and a low voltage element 204 connected in series. The first end of the high voltage element 202 is coupled to the sense amplifier circuit SA, and the first end of the low voltage element 204 is coupled to the common source line CSL of the memory cell array 102. The second end of the high voltage element 202 and the second end of the low voltage element 204 are connected to each other (node N0) and coupled to the corresponding bit line BL0 among the plurality of bit lines BL0-BLi. The nodes of the common source lines CSL of the plurality of switch units 200 share a common active region 212 (see FIG. 3B ). The high voltage element 202 and the low voltage element 204 are controlled by the bit line selection signal BLS0 and the bias selection signal Bias_select0, respectively.

Specifically, the high voltage element 202 and the low voltage element 204 may be formed by MOS transistors MN1 and MN2, respectively; that is, the switch unit 200 may include a first transistor MN1 as the high voltage element 202 and a second transistor MN2 as the low voltage element 204, and the first transistor MN1 and the second transistor MN2 are connected in series to each other at the node N0. The gate of the first transistor MN1 may receive the bit line selection signal BLS0, the first source/drain is coupled to the sense amplifier SA corresponding to the bit line BL0, and the second source/drain is coupled to the bit line BL0 via the node N0. The gate of the second transistor MN2 can receive the bias selection signal Bias_select0, the first source/drain is also coupled to the bit line BL0 via the node N0, and the second source/drain is coupled to the common source line CSL.

In addition, the gate length L2 of the second transistor MN2 is smaller than the gate length L1 of the first transistor MN1. In one embodiment, the ratio L1/L2 of the gate length L1 of the first transistor MN1 to the gate length L2 of the second transistor MN2 may be 3-4. In addition, in one embodiment, the thickness T2 of the gate oxide layer of the second transistor MN2 is smaller than the thickness T1 of the gate oxide layer of the first transistor MN1. For example, the ratio T1/T2 of the gate oxide layer thickness T1 of the first transistor MN1 to the gate oxide layer thickness T2 of the second transistor MN2 may be 5-6.

In addition, FIG. 3C is a portion of an equivalent circuit diagram of a switch device corresponding to a layout structure described later. As shown in FIG. 3A , the second source/drain of the second transistor of each switch unit 200 of the switch device 106b is connected to the common source line CSL, so part of the circuit of the switch device 106b is composed of a plurality of switch units 200 shown in FIG. 3A . In FIG. 3C , basically two switch units 200 shown in FIG. 3A are connected in series. The upper switch device 200 connected to the bit line BL0 includes a first transistor MN1 and a second transistor MN2. Similarly, the lower switch device 200 connected to the bit line BL1 includes a first transistor MN4 and a second transistor MN3. Here, the connection method of the first transistor MN1 (MN4) and the second transistor MN2 (MN3) is the same as that of FIG. 3A , and will not be described in detail here. In addition, the gates of the first transistors MN1 and MN4 receive the bit line selection signals BLS0 and BLS1, respectively. Furthermore, the gates of the second transistors MN2 and MN3 receive the bias selection signals Bias_select0 and Bias_select1, respectively.

As shown in the layout structure diagram of the switch device shown in FIG3B , a plurality of switch units 200 are illustrated in the figure, and the number of the switch units 200 is basically equal to the number of the bit lines BL0 to BLi of the memory cell array 102. As shown in FIG3B , the switch device 106b includes a plurality of first active regions 210 extending along the first direction X; and a second active region 212 extending along the second direction Y and being arranged approximately along the middle of each first active region 210. The first direction X and the second direction Y intersect with each other, for example, the first direction X is approximately perpendicular to the second direction Y. The second active region 212 divides each first active region into a first region and a second region. Taking FIG3B as an example, each first active region 210 located above the second active region 212 can be referred to as a first region, and each first active region 210 located below the second active region 212 can be referred to as a second region. Here, above or below the second active area 212 is only used for explanation relative to FIG. 3B and is not used to limit the implementation of the present invention.

The switch device 106b further includes a first gate 202a and a second gate 204a, which are disposed in each of the first region and the second region. For example, in the first region of each first active region 210, the first gate 202a and the second gate 204a extend along the second direction Y and are located on the first active region 210. The first gate 202a and the second gate 204a are substantially perpendicular to the first region of each first active region 210. The second gate 204a is closer to the second active region 212 than the first gate 202a. The first gate 202a and the first region of each first active region 210 together form the plurality of first transistors MN1 (i.e., the high voltage element 202) mentioned above. The second gate 204a and the first region of each first active region 210 together form a plurality of second transistors MN2 (i.e., low voltage elements 204). In addition, the region between the first gate 202a and the second gate 204a in the first region of each first active region 210 can be electrically coupled to a corresponding bit line (e.g., bit line BL0, etc.) through a connection structure such as a contact window.

Similarly, in the second region of each first active region 210, the first gate 202a and the second gate 204a extend along the second direction Y and are located on the first active region 210. The first gate 202a and the second gate 204a are substantially perpendicular to the first region of each first active region 210. The second gate 204a is closer to the second active region 212 than the first gate 202a. The first gate 202a and the second region of each first active region 210 together form the above-mentioned multiple first transistors MN4 (i.e., the high voltage element 202). The second gate 204a and the second region of each first active region 210 together form the above-mentioned multiple second transistors MN3 (i.e., the low voltage element 204). In addition, the region between the first gate 202a and the second gate 204a in the second region of each first active region 210 can be electrically connected to a corresponding bit line (such as the bit line BL1) through a connection structure such as a contact window.

In addition, as described above, the gate length L2 of the gate of the second transistor MN2 (MN3) (i.e., the second gate 204a) is smaller than the gate length L1 of the gate of the first transistor MN1 (MN4) (i.e., the first gate 202a). In addition, the second active region 212 is used as a common active region to connect to the common source line CSL. Thus, the active region 212 coupled to the node of the common source line CSL of each switch unit 200 of the switch device is shared.

Regarding the operation method, the switch unit 200 connected to the bit line BL0 in FIG. 3C is used as an example to explain the operation of the switch devices connected to other bit lines. When reading, the memory cell specified by the specific bit line and word line is selected by the column decoder 104a and the row decoder 104b as shown in FIG. 1. At this time, the bias selection signal Bias_select0 can turn off the second transistor MN2 of the switch unit, and the bit line selection signal BLS0 turns on the first transistor MN1 of the switch unit.

In this way, when the bit line BL0 is selected, the data stored in the memory cells on the bit line BL0 and a selected word line WL can be transmitted to the corresponding sense amplifier SA through the selected bit line BL0 for reading. The reading of other bit lines is also carried out in the same way.

In addition, when erasing, the bias selection signal Bias_select0 can turn on the transistor MN2, and the bit line selection signal BLS0 can turn off the transistor MN1. In this way, the erase voltage applied to the common source line CSL can be applied to the bit line BL0 through the transistor MN2 to erase all the memory cells on the bit line BL0. Because the flash memory uses block erase when erasing, the memory cells on other bit lines will also be erased in the same way at the same time. Meanwhile, referring to the voltage application path shown by the bold line in FIG. 2 , taking the bit line BL0 as an example, the erase voltage applied to the common source line CSL can erase each memory cell from the top of the memory cell string through the bit line BL0, and can also erase each memory cell from the bottom of the memory cell string. That is, this erase operation is a double-end erase method, one end of which is from the bit line side and the other end is from the source line side. When the number of memory cells on the memory cell string increases, this double-end erase method can speed up the erase speed.

4A to 4J are schematic diagrams showing the manufacturing process of the switch device of the page buffer according to the present invention. The cross-sectional view is taken along the line A-A' of FIG3B.

As shown in FIG4A, a substrate 300 is first provided, and a pad oxide layer 302 and a silicon nitride layer 304 are sequentially formed on the substrate 300. Then, as shown in FIG4B, the silicon nitride layer 304 is patterned into a silicon nitride layer 304a. Implantation is performed using the patterned nitride layer 304a as a mask. A structure 300b having a well region is formed on the substrate 300a by an implantation process. In one example, the N well or a similar structure of the structure 300b can be on a P-type substrate.

In FIG. 4C , the pad oxide layer 302 not covered by the silicon nitride layer 304 a is removed. A thicker oxide portion is formed at the same location by thermal oxidation. An oxide layer 306 including the thicker oxide portion is formed on the restructure 300 b. Next, in FIG. 4D , the patterned silicon nitride layer 304 a is removed. The oxide layer 306 is then exposed.

Next, in FIG. 4E , the oxide layer 306 is etched back for cleaning, and the thickness of a portion of the oxide layer 306 is reduced. Thereafter, a thin oxide layer is grown to finally form a gate oxide layer 306a. The gate oxide layer 306a includes a thicker portion with a thickness of T1 and a thinner portion with a thickness of T2. The thickness T1 is greater than the thickness T2. Next, in FIG. 4F , a conductor layer 310 is formed on the gate oxide layer 306a by a deposition method. The conductor layer 310, for example, includes polysilicon and metal silicide. The metal silicide can be, for example, tungsten silicide. Next, in FIG. 4G , a mask layer 312 is formed on the conductive layer 310. The mask layer 312 has a gate pattern and is used to pattern the conductive layer 310 to form gates 310-1, 310-2, 310-3, and 310-4. In one example, the conductive layer 310 can be patterned by etching to form gates 310-1, 310-2, 310-3, and 310-4.

In FIG. 4H, the mask layer 312 is removed to expose each gate 310-1, 310-2, 310-3, 310-4. A plurality of LDD regions 320 are formed in the well region 300b. Next, in FIG. 4I, a spacer 314 is formed on the sidewalls of each gate 310-1, 310-2, 310-3, 310-4. In addition, a plurality of doped regions 322 are formed in the well region 300b. Here, each doped region 322 serves as a source/drain of a transistor. Each doped region 322 together with each gate 310-1, 310-2, 310-3, 310-4 constitutes a transistor, which is equivalent to the transistors MN1, MN2, MN3 and MN4 in FIG. 3C.

Next, an interlayer dielectric layer 330 is formed on the gates 310-1, 310-2, 310-3, and 310-4. Then, a contact window opening is formed in the interlayer dielectric layer 330 at a position aligned with each doped region 322, and then a metal material is filled into the contact window opening to form a contact window 340.

Among the transistors MN1, MN2, MN3, and MN4 formed in the above manner, the transistors MN2 and MN3 are low voltage components and their gate length is L2. The gates of the transistors MN2 and MN3 can represent the gates 310-2 and 310-3 illustrated in FIG. 4I, respectively. The transistors MN1 and MN4 are high voltage components and their gate length is L1, wherein the length L1 is greater than the length L2. The gates of the transistors MN1 and MN4 can represent the gates 310-1 and 310-4 illustrated in FIG. 4I, respectively. In one example, the length L1 can be 1 μm, and the length L2 is approximately 0.35 μm. In addition, the gate oxide layer thickness T2 of transistors MN2 and MN3 may be approximately 70Å, and the gate oxide layer thickness T1 of transistors MN1 and MN4 may be approximately 400Å.

The above description is only an exemplary example of forming the transistors MN1, MN2, MN3 and MN4 of the switch device. The present invention is not limited to the specific method of forming these transistors, and any method that can form the switch device of the present invention can be used.

FIG5 is a schematic diagram showing the structure of a 3D flash memory using the switch device of the page buffer of the present invention. The switch device of the page buffer of the present invention is not only used in a two-dimensional memory structure, but also can be applied to a three-dimensional memory structure.

As shown in FIG5 , a schematic diagram of a structure of a three-dimensional NAND flash memory is illustrated. In this example, the page buffer 410 is disposed below the memory cell array 420. As shown in FIG5 , the page buffer 410 includes an amplifier circuit 412 and a switch device 414. The amplifier circuit 412 further includes a first sense amplifier circuit 412a and a second sense amplifier circuit 412b, each of which has a plurality of sense amplifiers SA. The structure of the switch device 414 can be, for example, the structure shown in FIGS. 3B to 3C .

In the example of FIG. 5 , the memory cell array 420 includes a plurality of vertical channel pillars. Each vertical channel pillar includes a string of memory cells and is coupled to bit lines BL0 to BLi. The vertical channel pillars penetrate through a plurality of interlaced objects of a conductive layer (gate layer and word line layer) and an insulating layer. The insulating layer can be made of a dielectric material such as silicon oxide. The conductive layer can be made of a metal such as tungsten (W). The conductive layer can form one or more string select lines (SSLs), one or more word lines (WLs) and one or more string select ground select lines (GSLs). The outer surface of the vertical channel column contacts the conductive layer and serves as a gate of the memory cell. The vertical channel column may include multiple layers, including a tunneling layer, a charge trapping layer, and a blocking layer. The tunneling layer may include silicon oxide, or a silicon oxide/silicon nitride combination (e.g., oxide/nitride/oxide or ONO). The charge trapping layer may include silicon nitride or other materials that can capture charges. The blocking layer includes silicon oxide, aluminum oxide, and/or a combination of these materials. Multiple layers may be formed on the inner surface of the vertical channel column, and polysilicon may be filled in the middle of the vertical channel column. Filling materials (e.g., multiple layers and polysilicon) in each vertical channel column that intersects with the conductive layer may form a memory cell string along a vertical direction (e.g., Z direction).

In the example shown in FIG. 5 , the memory cell array 420 may include a first sub-array 420a and a second sub-array 420b. The first sub-array 420a and the second sub-array 420b both include bit lines BL0 to BLi, and the bit lines BL0 to BLi of the first sub-array 420a and the second sub-array 420b are electrically connected to each other. The first sub-array 420a and the second sub-array 420b respectively have corresponding first sensing amplifier circuits 412a and second sensing amplifier circuits 412b, and the first sensing amplifier circuits 412a and the second sensing amplifier circuits 412b may be respectively disposed below the first sub-array 420a and the second sub-array 420b. That is, the first sensing amplifier circuit 412a and the second sensing amplifier circuit 412b are disposed below the plurality of vertical channel columns of the first sub-array 420a and the second sub-array 420b.

In the example shown in FIG5 , the switch device 414 may be disposed below the first sub-array 420a and the second sub-array 420b. As described above, in the switch device 414, the node between the transistors MN1 and MN2 may be coupled upward to the bit line BL0 of the first sub-array 420a and the second sub-array 420b using, for example, a metal wire or a metal connection structure. Similarly, the other bit lines BL1 to BLi are also coupled to the switch device 414 in the same manner.

In addition, the method of using the switch device 414 of the page buffer 410 to read, write and erase the memory cell array 420 is as described above, and will not be repeated here. In addition, the above-mentioned setting method of the memory cell array 420 is only an example, and the setting method of the memory cell array 420 can be changed arbitrarily, which does not affect the setting and operation concept of the switch device 414 of the present invention.

FIG6 is a schematic diagram showing a voltage waveform of a switch device of a page buffer according to an embodiment of the present invention when performing an erase operation. Here, the first transistor MN1 and the second transistor MN2 of FIG3C are used as an example to illustrate that the operation timing of the first transistor MN4 and the second transistor MN3 is also the same.

In addition, for the sake of simplicity, the following description is based on one bit line BL0, but in fact, the erasing operation is performed in a block erasing manner. In addition, the following description will use an erasing voltage of 21V as an example, but the specific erasing voltage is not particularly limited by the present invention. In addition, the erasing method described here can be applied to the above-mentioned two-dimensional or three-dimensional memory cell array.

As shown in FIG6 , during the erase operation, the first transistor MN1 is turned off and the second transistor MN2 is turned on, thereby applying the erase voltage to the bit line BL0 via the common source line CSL. Initially, a power supply having a voltage (first voltage) V1 for the gate is provided from the power supply end (i.e., the power supply for supplying the gate voltage) between time t1 and t2, and then the power supply is turned off at time t2. At this time, the gate of the second transistor MN2 is raised to the voltage V1, and after time t2, the gate voltage of the second transistor MN2 continues to be maintained at the voltage V1. At this time, the channel of the second transistor MN2 is turned on, and it can be regarded as a capacitor, and the gate is in a floating state.

Then, after the voltage applied to the gate of the second transistor MN2 is stabilized at the voltage V1 for a specified time, for example, at time t3, the erase voltage is applied to the common source CSL. In this example, in order to prevent the gate of the second transistor MN2 from receiving an excessively high voltage all at once, the erase voltage can be applied to the common source CSL in a phased manner. By utilizing the conduction of the channel of the second transistor MN2, the erase voltage applied to the common source CSL can further increase the voltage of the gate of the second transistor MN2 to the erase voltage (for example, 21V).

In this embodiment, the erase voltage is applied to the common source CSL in three stages. For example, a voltage of 7V is applied for a period of time at first, then the voltage is increased to 14V and applied for a period of time, and finally the voltage is increased to 21V. In addition, when the erase voltage is applied to the common source CSL, the gate voltage of the gate of the second transistor MN2 is further increased to 7V+V1, 14V+V1 and 21V+V1 respectively. At the same time, the bit line voltage applied to the bit line BL0 is also gradually increased from 0V to 7V, 14, and 20V. The voltage applied to the bit line BL0 will close the channel due to the bulk effect, causing the voltage of the bit line BL0 to be slightly lower than the erase voltage of 21V.

In addition, the erase voltage applied to the common source line CSL is performed in a staged manner, but the erase voltage 21V can also be applied directly at one time. In addition, in the above example, the erase voltage applied to the common source line CSL is performed in a manner of 7V, 14V, and 21V, that is, the increment of the erase voltage each time is equal, but the increment of the voltage applied in each stage can also be unequal. In addition, the time for applying the voltage in each stage can be equal or unequal. The method of applying the erase voltage to the common source line CSL can be varied in various ways, and the method of application is determined by the actual application.

According to the embodiment of the present invention, when erasing a block of a memory cell array, in addition to applying an erase voltage from the bit line BL side, an erase voltage can also be applied from the common source line CSL side (source line side). That is, when erasing a block of a memory cell array based on the switch device of the page buffer of at least one embodiment of the present invention, an erase voltage can be applied from both ends of each string of memory cells to accelerate the erasing speed.

FIG. 7 is a schematic diagram showing the area reduction effect of the switch device of the page buffer according to an embodiment of the present invention.

As can be seen from FIG. 7 , the compression ratio of the gate of the second transistor MN2 of the present invention is reduced by about 34% compared to the gate of the second transistor MN2 of the existing structure. The area compression ratio of the active region between the gate of the first transistor MN1 and the gate of the second transistor MN2 of at least one embodiment of the present invention is reduced by about 68% compared to the existing structure. In addition, the active region used for the common source line CSL of at least one embodiment of the present invention is shared, so its compression ratio can be reduced by about 37%.

Therefore, through the switch device of the page buffer of at least one embodiment of the present invention, a high voltage transistor element is replaced by a low voltage transistor element (such as the second transistor MN2, MN3), and its gate length is smaller than that of the first transistor MN1, MN4 as the high voltage transistor element, and the active region corresponding to the node of the common source line CSL is shared. Through the structure of this switch device, the layout area of the switch device can be further reduced, and then the layout area of the memory device can also be reduced.

100: memory device 102: memory cell array 104a: row decoder 104b: row decoder 106: page buffer 106a: sense amplifier circuit 106b: switch device 1018: high voltage generator 110: control circuit 112a: command register 112b: address register 112c: status register 114a: output buffer 114b: control buffer 114c: data buffer 116a: row pre-decoder 116b: row pre-decoder 200: switch unit 202, MN1, MN4: first transistor 204, MN2, MN3: second transistor 202a: first gate 204a: second gate 210: first active region 212: second active region 300: substrate 300a: substrate 300b: structure 302: pad oxide layer 304: silicon nitride layer 304a: patterned silicon nitride layer 306: pad oxide layer 306a: gate oxide layer 310: conductor layer 310-1, 310-2, 310-3, 310-4: gate 312: mask layer 314: spacer 320: lightly doped region 322: doping region 330: interlayer dielectric layer 340: contact window 410: page buffer 412: sense amplifier circuit 412a: first sense amplifier circuit 412b: second sense amplifier circuit 414: switch device 420: memory cell array 420a: first sub-array 420b: second sub-array BL0, BL1, BLi: bit line CSL: common source line SA, SA0, SAi: sense amplifier BLS0, BLS1: Bias_select0, Bias_select1: L1: gate length of the first transistor L2: gate length of the second transistor T1: The thickness of the gate oxide layer of the first transistor T2: The thickness of the gate oxide layer of the second transistor

FIG. 1 is a block diagram of a circuit structure of a memory device. FIG. 2 is a circuit diagram of a switch device of a page buffer. FIG. 3A is a circuit diagram of a switch unit of a switch device in a page buffer according to an embodiment of the present invention. FIG. 3B is a schematic diagram of a layout structure of a switch device of a page buffer according to an embodiment of the present invention. FIG. 3C is a diagram of a portion of an equivalent circuit of a switch unit of a switch device corresponding to the layout structure of FIG. 3B. FIG. 4A to FIG. 4J are schematic diagrams of a manufacturing process of a switch device of a page buffer according to the present invention. FIG. 5 is a schematic diagram of a structure of a 3D flash memory using a switch device of a page buffer according to the present invention. FIG6 is a schematic diagram showing a voltage waveform when the switch device of the page buffer according to the embodiment of the present invention performs an erase operation. FIG7 is a schematic diagram showing an area reduction effect of the switch device of the page buffer according to the embodiment of the present invention.

106: Page buffer

106b: Sensing amplifier circuit

200: Switch unit

202, MN1, MN4: first transistor

204, MN2, MN3: second transistor

202a: First gate

204a: Second gate

210: First active zone

212: Second active zone

BL0, BL1: bit line

CSL: Common Source Line

SA: Sense Amplifier

L1: Gate length of the first transistor

L2: Gate length of the second transistor

Claims (20)

A memory device with a switch device of a page buffer, comprising: A plurality of switch units, coupled between a memory cell array and a sense amplifier circuit of the page buffer, wherein each of the plurality of switch units further comprises: a high voltage element and a low voltage element, wherein the high voltage element and the low voltage element are connected in series with each other; a first end of the high voltage element is coupled to the sense amplifier circuit, and a first end of the low voltage element is coupled to a common source line of the memory cell array; a second end of the high voltage element and a second end of the low voltage element are connected to each other and coupled to corresponding bit lines in the memory cell array, wherein the common source line coupled to each of the plurality of switch units shares a common active region. A memory device with a switch device having a page buffer as described in claim 1, wherein the high voltage element and the low voltage element are a first transistor and a second transistor respectively, the first transistor has a first source/drain and a second source/drain, the first source/drain is coupled to a sense amplifier corresponding to the corresponding bit line, and the second source/drain is coupled to the corresponding bit line, the second transistor has a first source/drain and a second source/drain, the first source/drain is coupled to the corresponding bit line, and the second source/drain is coupled to a common source line, the gate length of the second transistor is less than the gate length of the first transistor. A memory device with a switch device of a page buffer as described in claim 2, wherein the layout structure of the switch device includes: A plurality of first active regions extending along a first direction; A second active region extending along a second direction and connected to the plurality of first active regions, and dividing each of the plurality of first active regions into a first region and a second region, wherein the first direction and the second direction intersect each other; and A first gate and a second gate extending along the second direction, disposed in each of the first region and the second region and located on each of the plurality of first active regions, wherein the second gate is closer to the second active region than the first gate. A memory device having a switch device with a page buffer as described in claim 3, wherein in each of the plurality of first active regions in the first region, the first gate and each of the plurality of first active regions together form the first transistor, and the second gate and each of the plurality of first active regions together form the second transistor, and In each of the plurality of first active regions in the second region, the first gate and each of the plurality of first active regions together form the first transistor, and the second gate and each of the plurality of first active regions together form the second transistor, and The gate length of the second transistor in the first direction of the second gate is less than the gate length of the first transistor in the first direction of the first gate. A memory device having a switch device with a page buffer as described in claim 2, wherein the ratio of the gate length of the first transistor to the gate length of the second transistor is 3-4. A memory device having a switch device with a page buffer as described in claim 2, wherein a thickness of a gate oxide layer of the gate of the second transistor is smaller than a thickness of a gate oxide layer of the first transistor. A memory device having a switch device with a page buffer as described in claim 1, wherein the memory cell array is a three-dimensional structure, and the page buffer is arranged under the memory cell array. A memory device having a switch device of a page buffer as described in claim 7, wherein the memory cell array further includes a first sub-array and a second sub-array, and the sense amplifier circuit of the page buffer further includes a first sense amplifier circuit and a second sense amplifier circuit, the first sense amplifier circuit and the second sense amplifier circuit are respectively arranged below the first sub-array and the second sub-array, and the switch device is arranged below the memory cell array between the first sub-array and the second sub-array. A memory device having a switch device with a page buffer, comprising: A memory cell array, comprising a plurality of bit lines, a plurality of word lines and a plurality of memory cells, each of the plurality of memory cells being arranged at a position where the plurality of word lines and the plurality of bit lines intersect respectively; and A page buffer, coupled to the plurality of bit lines of the memory cell array, the page buffer further comprising a switch device and a sensing amplifier circuit, wherein the switch device further comprises: A plurality of switch units, coupled between the memory cell array and the sensing amplifier circuit, wherein each of the plurality of switch units further comprises: a high voltage element and a low voltage element, the high voltage element and the low voltage element being connected in series with each other; The first end of the high voltage element is coupled to the sensing amplifier circuit, and the first end of the low voltage element is coupled to the common source line of the memory cell array; and the second end of the high voltage element and the second end of the low voltage element are connected to each other and coupled to the corresponding bit line in the memory cell array, wherein the common source line coupled to each of the plurality of switch units shares a common active region. A memory device with a switch device having a page buffer as described in claim 9, wherein the high voltage element and the low voltage element are a first transistor and a second transistor respectively, the first transistor has a first source/drain and a second source/drain, the first source/drain is coupled to a sense amplifier corresponding to the corresponding bit line, and the second source/drain is coupled to the corresponding bit line, the second transistor has a first source/drain and a second source/drain, the first source/drain is coupled to the corresponding bit line, and the second source/drain is coupled to a common source line, the gate length of the second transistor is less than the gate length of the first transistor. A memory device with a switch device of a page buffer as described in claim 10, wherein the layout structure of the switch device includes: a plurality of first active regions extending along a first direction; a second active region extending along a second direction and connected to the plurality of first active regions, and dividing each of the plurality of first active regions into a first region and a second region, wherein the first direction and the second direction intersect each other; and a first gate and a second gate extending along the second direction, disposed in each of the first region and the second region and located on each of the plurality of first active regions, wherein the second gate is closer to the second active region than the first gate. A memory device having a switch device with a page buffer as described in claim 11, wherein in each of the plurality of first active regions in the first region, the first gate and each of the plurality of first active regions together form the first transistor, and the second gate and each of the plurality of first active regions together form the second transistor, and In each of the plurality of first active regions in the second region, the first gate and each of the plurality of first active regions together form the first transistor, and the second gate and each of the plurality of first active regions together form the second transistor, and The gate length of the second transistor in the first direction of the second gate is less than the gate length of the first transistor in the first direction of the first gate. A memory device having a switch device with a page buffer as described in claim 10, wherein the ratio of the gate length of the first transistor to the gate length of the second transistor is 3-4. A memory device having a switch device with a page buffer as described in claim 10, wherein the ratio of the thickness of the gate oxide layer of the second transistor to the thickness of the gate oxide layer of the first transistor is 5-6. A memory device having a switch device with a page buffer as described in claim 9, wherein the memory cell array is the three-dimensional structure, and the page buffer is arranged under the memory cell array. A memory device with a switch device of a page buffer as described in claim 15, wherein the memory cell array further includes a first memory cell array and a second memory cell array, and the sense amplifier circuit of the page buffer further includes a first sense amplifier circuit and a second sense amplifier circuit, the first sense amplifier circuit and the second sense amplifier circuit are respectively arranged below the first memory cell array and the second memory cell array, and the switch device is arranged below the memory cell array between the first memory cell array and the second memory cell array. A method for erasing a memory device, wherein the memory device has a memory cell array and a page buffer, wherein the page buffer includes a switch device composed of a plurality of switch units, wherein each of the plurality of switch units includes a first transistor as a high voltage element and a second transistor as a low voltage element, wherein the first transistor and the second transistor are connected in series with each other, wherein a first end of the first transistor is coupled to a first terminal of the page buffer. The sensing amplifier circuit, the first end of the second transistor is coupled to the common source line of the memory cell array, the second end of the first transistor and the second end of the second transistor are connected to each other and coupled to the corresponding bit line of the plurality of bit lines in the memory cell array, and the common source line coupled to each of the plurality of switch units shares a common active region, and for each of the plurality of switch units, the erasing method includes: Turning off the first transistor; Applying a first voltage to the gate of the second transistor to turn on the second transistor; After the first voltage applied to the gate of the second transistor remains stable for a specified time, applying an erase voltage to the common source line; Using the erase voltage, boosting the gate voltage of the gate of the second transistor to the sum of the erase voltage and the first voltage, and boosting the bit line voltage of the corresponding bit line to the erase voltage; and Performing bilateral erasing on the memory cell on the corresponding bit line. An erase method as described in claim 17, wherein the common voltage of the common source line is applied to the erase voltage in a multi-stage manner. An erasing method as described in claim 18, wherein the increment of each stage of the multi-stage method is the same or different. An erasing method as described in claim 18, wherein the application time of each stage of the multi-stage method is the same or different.

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