TW202411990A - Control circuit and semiconductor memory - Google Patents

Abstract

Embodiments of the disclosure provide a control circuit and a semiconductor memory. The control circuit is connected to a sensitive amplifier circuit, and the control circuit includes a pre-charge control module and a power supply control module. The pre-charge control module includes a pre-charge driver module and a pre-charge module, and the pre-charge driver module is connected to a first power supply for providing a pre-charge drive signal to the pre-charge module via the pre-charge driver module, the pre-charge drive signal being used to control the pre-charge module to pre-charge the sensitive amplifier circuit. The power supply control module includes a power supply driver module and a reference power supply module, and the power supply driver module is connected to the second power supply for providing a power supply drive signal to the reference power supply module via the power supply driver module, and controlling, according to the power supply drive signal, the reference power supply module to provide a reference voltage to the sensitive amplifier circuit. In this way, the first power supply is different from the second power supply, which can effectively suppress the power supply noise at different stages, improve the reading and writing speed, thereby improving the performance of the sensitive amplifier.

Description

Control circuit and semiconductor memory

The present invention relates to the field of semiconductor technology, and in particular to a control circuit and a semiconductor memory.

Dynamic Random Access Memory (DRAM) is a commonly used semiconductor storage device in computers, consisting of many duplicate storage units. During the data read process, the read data signal of each storage unit is read out through the local data line, the global data line and the data bus in sequence; conversely, during the data write process, the write data signal is written to the storage unit through the data bus, the global data line and the local data line in sequence.

Currently, a sense amplifier (SA) is set between the storage unit and the local data line. In order to improve the signal quality of the storage unit content, the storage data needs to be amplified by the sense amplifier before being read or written. However, the sense amplifier is prone to introduce noise at different working stages, making the data signal amplification process in related technologies still insufficient, resulting in the need to improve the performance of the sense amplifier.

The present invention provides a control circuit and a semiconductor memory, which can effectively suppress power supply noise at different stages, increase the reading and writing speed, and thus improve the performance of the sensing amplifier.

In a first aspect, an embodiment of the present invention provides a control circuit, which is connected to a sensing amplifier circuit, and the control circuit includes a pre-charge control module and a power control module, wherein:

The pre-charge control module includes a pre-charge drive module and a pre-charge module, and the pre-charge drive module is connected to the first power source, and is used to provide a pre-charge drive signal to the pre-charge module through the pre-charge drive module, and the pre-charge drive signal is used to control the pre-charge module to perform pre-charge processing for the sensing amplifier circuit;

The power control module includes a power drive module and a reference power module, and the power drive module is connected to a second power source, and is used to provide a power drive signal to the reference power module through the power drive module, and control the reference power module to provide a reference voltage for the sensing amplifier circuit according to the power drive signal; wherein the first power source is different from the second power source.

In some embodiments, the control circuit further includes a power switch module, and the power switch module is connected to a third power source, wherein: the power switch module is used to receive a power enable signal, and control the state of a switch tube inside the power switch module according to the power enable signal to provide a second power to the power drive module through the third power source, and the first power source is different from the third power source.

In some embodiments, the third power supply includes a first working power supply and a second working power supply, the first working power supply and the second working power supply are in different voltage domains and/or have different temperature characteristics, and the power enable signal includes a first power enable sub-signal and a second power enable sub-signal; the power switch module includes a first switching tube and a second switching tube, wherein: the first end of the first switching tube is connected to the first working power supply, the control end of the first switching tube is connected to the first power enable sub-signal, the first end of the second switching tube is connected to the second working power supply, the control end of the second switching tube is connected to the second power enable sub-signal, the second end of the first switching tube is connected to the second end of the second switching tube, and the first switching tube and the second switching tube are selectively turned on to provide a second power supply for the power drive module.

In some embodiments, when the sensing amplifier circuit operates in the bias elimination stage, the first switch tube is turned on to provide the second power to the power drive module through the first working power; and when the sensing amplifier circuit operates in the signal amplification stage, the second switch tube is turned on to provide the second power to the power drive module through the second working power.

In some embodiments, the power switch module includes at least one of the following: a pull-up power switch module and a pull-down power switch module; wherein the first switch tube and the second switch tube included in the pull-up power switch module are PMOS tubes, and the first switch tube and the second switch tube included in the pull-down power switch module are NMOS tubes, and the first working power supply connected to the pull-up power switch module is different from the first working power supply connected to the pull-down power switch module, and the second working power supply connected to the pull-up power switch module is different from the second working power supply connected to the pull-down power switch module.

In some embodiments, when the number of the power switch modules is at least one, the control circuit further includes a power switch control module, wherein: the power switch control module is used to receive a bias elimination enable signal and a target power enable signal, and generate at least one group of power enable signals according to the bias elimination enable signal and the target power enable signal; wherein each group of power enable signals includes a first power enable sub-signal and a second power enable sub-signal, and at least one group of power enable signals has a corresponding relationship with at least one power switch module.

In some embodiments, the target power enable signal includes a first target power enable signal and a second target power enable signal, and the power switch control module includes a first logic control module and a second logic control module, wherein: the first logic control module is used to receive the bias elimination enable signal and the second target power enable signal, and output at least one first power enable sub-signal; the second logic control module is used to receive the bias elimination enable signal and the first target power enable signal, and output at least one second power enable sub-signal; wherein the first target power enable signal and the first power enable sub-signal have the same valid state, and the second target power enable signal and the second power enable sub-signal have the same valid state.

In some embodiments, the first logic control module includes a first inverter, a first inverter, a first level conversion module, and a second inverter, wherein: the input end of the first inverter is used to receive the second target power enable signal, the output end of the first inverter is connected to the first input end of the first inverter, the second input end of the first inverter is used to receive the bias elimination enable signal, the output end of the first inverter is connected to the input end of the first level conversion module, the output end of the first level conversion module is connected to the input end of the second inverter, and the output end of the second inverter is used to output at least one first power enable signal. sub-signal; the second logic control module includes a first NOR gate, a third NOR gate, a second level switching module and a fourth NOR gate, wherein: the first input end of the first NOR gate is used to receive the bias elimination enable signal, the second input end of the first NOR gate is used to receive the first target power enable signal, the output end of the first NOR gate is connected to the input end of the third NOR gate, the output end of the third NOR gate is connected to the input end of the second level conversion module, the output end of the second level conversion module is connected to the input end of the fourth NOR gate, and the output end of the fourth NOR gate is used to output at least one second power enable sub-signal.

In some embodiments, the power switch control module further includes a fifth gate, wherein: the input terminal of the fifth gate is used to receive the bias elimination inverted signal, and the output terminal of the fifth gate is used to output the bias elimination enable signal.

In some embodiments, the pre-charge module includes a pre-charge switch tube, wherein: the first end of the pre-charge switch tube is connected to the pre-charge power supply, the control end of the pre-charge switch tube is used to receive a pre-charge drive signal, and the second end of the pre-charge switch tube is connected to the read bit line.

In some embodiments, the pre-charge module includes a pre-charge switch tube, wherein: the first end of the pre-charge switch tube is connected to the read bit line, the control end of the pre-charge switch tube is used to receive the pre-charge drive signal, and the second end of the pre-charge switch tube is connected to the complementary read bit line.

In some embodiments, the pre-charge drive module includes a pre-charge inverter, wherein: the input end of the pre-charge inverter is used to receive a pre-charge enable signal, the control end of the pre-charge inverter is connected to the first power source, and the output end of the pre-charge inverter is used to output a pre-charge drive signal.

In a second aspect, an embodiment of the present invention provides a semiconductor memory, which includes a control circuit, a plurality of storage blocks, and a sensitive amplifier module disposed between two adjacent storage blocks, a switch module is disposed between the two adjacent sensitive amplifier modules, the control circuit includes a pre-charge control module and a power control module, the sensitive amplifier module includes a sensing amplifier circuit and a pre-charge control module, and the switch module includes a power control module, wherein:

The pre-charge control module includes a pre-charge drive module and a pre-charge module, and the pre-charge drive module is connected to the first power source, and is used to provide a pre-charge drive signal to the pre-charge module through the pre-charge drive module, and control the pre-charge module to perform pre-charge processing for the sensing amplifier circuit according to the pre-charge drive signal;

The power control module includes a power drive module and a reference power module, and the power drive module is connected to a second power source, and is used to provide a power drive signal to the reference power module through the power drive module, and control the reference power module to provide a reference voltage for the sensing amplifier circuit according to the power drive signal; wherein the first power source is different from the second power source.

In some embodiments, the semiconductor memory further includes a power switch module as in the first aspect and a power switch control module as in the first aspect, wherein: the power switch module and the power switch control module are both located in the switch module; or, the power switch module is located in the switch module, and the power switch control module is located in a peripheral area of the semiconductor memory; or, the power switch module and the power switch control module are both located in a peripheral area of the semiconductor memory.

An embodiment of the present invention provides a control circuit and a semiconductor memory, wherein the control circuit is connected to a sensing amplifier circuit, and the control circuit includes a pre-charge control module and a power control module, wherein: the pre-charge control module includes a pre-charge drive module and a pre-charge module, and the pre-charge drive module is connected to a first power source, and is used to provide a pre-charge drive signal to the pre-charge module through the pre-charge drive module, and the pre-charge drive signal is used to control the pre-charge module to perform pre-charge processing for the sensing amplifier circuit; the power control module includes a power drive module and a reference power module, and the power drive module is connected to a second power source, and is used to provide a power drive signal to the reference power module through the power drive module, and control the reference power module according to the power drive signal to provide a reference voltage for the sensing amplifier circuit; wherein the first power source is different from the second power source. In this way, since the pre-charge driver module and the power driver module use different power supplies, the power supply noise at different stages can be isolated, so that the SA noise suppression and read/write speed are effectively improved, and the signal amplification process of the sensing amplifier circuit can be optimized, thereby improving the performance of the sensing amplifier.

The following will be combined with the attached drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. It is understood that the specific embodiments described here are only used to explain the relevant application, rather than to limit the application. It should also be noted that, for the convenience of description, only the parts related to the relevant application are shown in the attached drawings.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art belonging to the present invention. The terms used herein are only for the purpose of describing embodiments of the present invention and are not intended to limit the present invention.

In the following description, reference is made to “some embodiments” which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

It should be pointed out that the terms "first\second\third" involved in the embodiments of the present invention are only used to distinguish similar objects and do not represent a specific order of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or precedence where permitted, so that the embodiments of the present invention described here can be implemented in an order other than that illustrated or described here.

It should also be noted that the high level and low level used for the signal involved in the embodiments of the present invention refer to the logical level of the signal. There is a difference between a signal having a high level and a signal having a low level. For example, a high level may correspond to a signal having a first voltage, and a low level may correspond to a signal having a second voltage. In some embodiments, the first voltage is greater than the second voltage. In addition, the logical level of the signal may be different from or opposite to the described logical level. For example, a signal described as having a logical "high" level may alternatively have a logical "low" level, and a signal described as having a logical "low" level may alternatively have a logical "high" level.

It is understandable that in the operation process of DRAM, it is necessary to use a sense amplifier to realize signal amplification in various operation processes. See FIG1, which shows a schematic diagram of an application scenario of a sense amplifier. As shown in FIG1, the application scenario may include a first signal line 11, a second signal line 12, and a sense amplifier 13. Among them,

The first signal line 11 has a first switch Sx and a first capacitor C1 for inputting a signal to be processed Vin+; the second signal line 12 has a second switch Sy and a second capacitor C2 for inputting a reference signal to be processed Vin-; the sense amplifier 13 is used to amplify the signal to be processed Vin+ and the reference signal to be processed Vin-, and there is a voltage difference of ΔVin between the signal to be processed Vin+ and the reference signal to be processed Vin-. The first switch Sx and the second switch Sy are used to control the connection between the first signal line 11 and the second signal line 12 and the sense amplifier 13, and the first capacitor C1 and the second capacitor C2 are used to filter the signal to be processed Vin+ and the reference signal to be processed Vin- to weaken their high-frequency characteristics.

Specifically, the sense amplifier 13 may include a first switching tube M1, a second switching tube M2, a third switching tube M3, and a fourth switching tube M4. The control end of the first switching tube M1, the control end of the second switching tube M2, the first end of the third switching tube M3, and the first end of the fourth switching tube M4 are all connected to the reference signal to be processed Vin-, and the first end of the first switching tube M1, the first end of the second switching tube M2, the control end of the third switching tube M3, and the control end of the fourth switching tube M4 are all connected to the signal to be processed Vin+. In this application scenario, there are also a fifth switching tube M5 and a sixth switching tube M6. The control end of the fifth switching tube 135 is connected to the first control signal SAP, the first end of the fifth switching tube M5 is connected to the power signal VBLH, and the second end of the fifth switching tube M5 is connected to the second end of the first switching tube M1 and the second end of the third switching tube M3 to form a first reference signal end, which is represented by PCS; the control end of the sixth switching tube M6 is connected to the second control signal SAN, the first end of the sixth switching tube M6 is connected to the ground signal GND, the second end of the sixth switching tube M6 is connected to the second end of the second switching tube M2 and the second end of the fourth switching tube M4 to form a second reference signal end, which is represented by NCS.

In addition, a pre-charge circuit may exist between the first signal line 11 and the second signal line 12, and a pre-charge circuit may exist between the second end of the third switch tube M3 and the second end of the fourth switch tube M4, for pre-charging the first reference signal end and the second reference signal end.

It should be noted that in FIG. 1 , the first switch tube M1, the third switch tube M2, and the fifth switch tube M5 are P-type metal oxide semiconductor field effect transistors (PMOSFET, referred to as PMOS tubes for short); the second switch tube M2, the fourth switch tube M4, and the sixth switch tube M6 are N-type metal oxide semiconductor field effect transistors (NMOSFET, referred to as NMOS tubes for short).

It should also be noted that in FIG1 , the first switch tube M1 and the second switch tube M2 form an inverter INV1, and the third switch tube M3 and the fourth switch tube M4 form another inverter INV2, and their inputs and outputs are respectively connected to form a latch. Among them, the power signal VBLH provides power to the sense amplifier 13, and the fifth switch tube M5 is connected to the sense amplifier 13; the ground signal GND is the ground line of the sense amplifier, and the sixth switch tube M6 is connected to the sense amplifier 13.

In the embodiment of the present invention, the working process can be divided into three stages: precharge (EQ) stage, small signal input stage and signal amplification stage. In the EQ stage, the precharge circuit performs precharge for the sense amplifier 13; in the small signal input stage, the small signal can be input from Sx or Sy in FIG1; in the signal amplification stage, the signal can be amplified through the sense amplifier 13.

In related technologies, the storage data needs to be read out or written after being amplified by a sense amplifier to improve the signal quality of the storage cell content. However, the precharge circuit and the pull-down reference circuit in the traditional sense amplifier share a power supply, which is easy to introduce noise at different working stages of the SA, which is not good for the sense margin, thereby affecting the amplification process of the data signal, resulting in the need to improve the performance of the sense amplifier. Based on this, an embodiment of the present invention provides a control circuit, which is connected to the sensing amplifier circuit, and the control circuit includes a pre-charge control module and a power control module, wherein: the pre-charge control module includes a pre-charge drive module and a pre-charge module, and the pre-charge drive module is connected to a first power source, and is used to provide a pre-charge drive signal to the pre-charge module through the pre-charge drive module, and the pre-charge drive signal is used to control the pre-charge module to perform pre-charge processing for the sensing amplifier circuit; the power control module includes a power drive module and a reference power module, and the power drive module is connected to a second power source, and is used to provide a power drive signal to the reference power module through the power drive module, and control the reference power module according to the power drive signal to provide a reference voltage for the sensing amplifier circuit; wherein the first power source is different from the second power source. In this way, since the pre-charge drive module and the power drive module use different power supplies, the power supply noise at different stages can be isolated, so that the SA noise suppression and the read and write speed are effectively improved, and the signal amplification process of the sensing amplifier circuit can be optimized; at the same time, according to the difference between the first power supply and the second power supply, the sense margin can also be optimized, thereby improving the performance of the sensing amplifier.

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

In one embodiment of the present invention, refer to FIG. 2, which shows a schematic diagram of the composition structure of a control circuit provided by the embodiment of the present invention. As shown in FIG. 2, the control circuit 20 may include a pre-charge control module 21 and a power supply control module 22, wherein:

The pre-charge control module 21 includes a pre-charge drive module 211 and a pre-charge module 212, and the pre-charge drive module 211 is connected to the first power source, and is used to provide a pre-charge drive signal to the pre-charge module 212 through the pre-charge drive module 211, and the pre-charge drive signal is used to control the pre-charge module 212 to perform pre-charge processing for the sensing amplifier circuit;

The power control module 22 includes a power drive module 221 and a reference power module 222, and the power drive module 221 is connected to the second power source, and is used to provide a power drive signal to the reference power module 222 through the power drive module 221, and control the reference power module 222 to provide a reference voltage for the sensing amplifier circuit according to the power drive signal; wherein the first power source is different from the second power source.

It should be noted that, in the embodiment of the present invention, the control circuit 20 can be applied to a variety of signal amplification scenarios, such as a sense amplifier in a DRAM.

It should also be noted that, in FIG. 2 , the first power supply can be represented by VDD1, and the second power supply can be represented by VDD2. In addition, the control circuit 20 can be connected to the sensing amplifier circuit 30. Specifically, in the pre-charging stage, the pre-charging drive module 211 provides a pre-charging drive signal to the pre-charging module 212, so that the pre-charging module 212 performs pre-charging processing for the sensing amplifier circuit 30; in the signal amplification stage, the power drive module 221 provides a power drive signal to the reference power module 222, so that the reference power module 222 provides a reference voltage for the sensing amplifier circuit, thereby enabling signal amplification processing.

It is understandable that the second power source may be a directly provided external power source or may be obtained from an external power source after relevant processing. In some embodiments, based on the control circuit 20 shown in FIG. 2 , referring to FIG. 3 , the control circuit 20 may further include a power switch module 23, and the power switch module 23 is connected to the third power source, wherein:

The power switch module 23 is used to receive a power enable signal and control the state of the switch tube inside the power switch module according to the power enable signal to provide a second power to the power drive module 221 through a third power source. The first power source is different from the third power source.

It should be noted that in the embodiment of the present invention, the third power source can be represented by VDD3. As for the second power source, it can be obtained by the third power source through the relevant processing of the power switch module 23, so as to provide different second power sources for the power drive module 221 at different stages, thereby achieving the purpose of reducing power noise. In other words, the power switch module 23 has a voltage regulation function, and the power switch module 23 can output different second power sources under the condition that the third power source VDD3 remains unchanged.

In parallel, in order to better realize that the power switch module 23 outputs different second power supplies at different stages, in some embodiments, the third power supply may include a first working power supply and a second working power supply, and the first working power supply and the second working power supply are in different voltage domains and/or have different temperature characteristics. The first working power supply is different from the second working power supply, and the first working power supply is used to provide the power drive module 221 with the working power required in the first stage, and the second working power supply is used to provide the power drive module 221 with the working power required in the second stage.

It should also be noted that when the third power source includes the first working power source and the second working power source, the power enable signal may include the first power enable sub-signal and the second power enable sub-signal. Accordingly, in some embodiments, based on the control circuit 20 shown in FIG3 , referring to FIG4 , the power switch module 23 may include a first switch tube Q1 and a second switch tube Q2; wherein the first end of the first switch tube Q1 is connected to the first working power source, the control end of the first switch tube Q1 is connected to the first power enable sub-signal, the first end of the second switch tube Q2 is connected to the second working power source, the control end of the second switch tube Q2 is connected to the second power enable sub-signal, the second end of the first switch tube Q1 is connected to the second end of the second switch tube Q2, and the first switch tube Q1 and the second switch tube Q2 are selectively turned on to provide the second power source for the power drive module 221.

It should be noted that in the embodiment of the present invention, the first switch tube Q1 and the second switch tube Q2 are not turned on at the same time. In different stages, the first switch tube Q1 and the second switch tube Q2 are turned on, so as to provide different second power sources for the power drive module 221. In some embodiments, the first power enable sub-signal is also used to control the conduction degree of the first switch tube Q1, and the second power enable sub-signal is also used to control the conduction degree of the second switch tube Q2 to adjust the size of the second power source VDD2.

Specifically, in the embodiment of the present invention, if the sensing amplifier circuit 30 works in the first stage, then for the power switch module 23, the first switch tube Q1 is controlled to be in the on state according to the first power enable sub-signal, and the second switch tube Q2 is controlled to be in the off state according to the second power enable sub-signal, so as to provide the second power to the power drive module 221 through the first working power; if the sensing amplifier circuit 30 works in the second stage, then for the power switch module 23, the first switch tube Q1 is controlled to be in the off state according to the first power enable sub-signal, and the second switch tube Q2 is controlled to be in the on state according to the second power enable sub-signal, so as to provide the second power to the power drive module 221 through the second working power.

It should also be noted that, in the embodiment of the present invention, the first stage may be an offset cancel (OC or NC) stage, and the second stage may be a signal amplification (Develop) stage. Therefore, in some embodiments, when the sensing amplifier circuit 30 works in the offset cancel stage, the first switch tube Q1 is turned on to provide the second power to the power drive module 221 through the first working power; when the sensing amplifier circuit 30 works in the signal amplification stage, the second switch tube Q2 is turned on to provide the second power to the power drive module 221 through the second working power.

In the embodiment of the present invention, the second power supply is adjusted according to the OC stage and the Develop stage, which can improve SA noise suppression, read/write speed control, and sense margin optimization. In addition, during the adjustment process, the first working power supply in the OC stage and the second working power supply in the Develop stage are in different voltage domains and/or have different temperature characteristics; that is, the second power supply required by the power drive module 221 can be separated according to the OC stage and the Develop stage, and the working power supplies in the OC stage and the Develop stage can adjust the corresponding voltage range (voltage trim range) and temperature characteristics respectively, which is more beneficial to the sense margin optimization of the sensing amplifier circuit 30.

It can also be understood that in the embodiment of the present invention, the power control module 22 can be a pull-up power control module or a pull-down power control module. In some embodiments, for the power control module 22, based on the control circuit 20 shown in FIG. 2, see FIG. 5, the control circuit 20 can also include a pull-up power control module 24 and a pull-down power control module 25, wherein:

The pull-up power control module 24 includes a pull-up power driving module 241 and a pull-up reference power module 242, and the pull-up power driving module 241 is connected to the fourth power source, and is used to provide a pull-up power driving signal to the pull-up reference power module 242 through the pull-up power driving module 241, and control the pull-up reference power module 242 to provide a first reference voltage for the sensing amplifier circuit 30 according to the pull-up power driving signal;

The pull-down power control module 25 includes a pull-down power driving module 251 and a pull-down reference power module 252, and the pull-down power driving module 251 is connected to the fifth power source, and is used to provide a pull-down power driving signal to the pull-down reference power module 252 through the pull-down power driving module 251, and control the pull-down reference power module 252 according to the pull-down power driving signal to provide a second reference voltage for the sensing amplifier circuit 30.

In the embodiment of the present invention, the first power source is different from the fourth power source, and the first power source is also different from the fifth power source. Among them, the fourth power source can be represented by VDD4, and the fifth power source can be represented by VDD5. In addition, the pull-up power control module 24 can be the power control module 22 in FIG. 2, or the pull-down power control module 25 can be the power control module 22 in FIG. 2, that is, the internal structures of the pull-up power control module 24 and the pull-down power control module 25 are the same as the internal structure of the power control module 22.

That is, when the control circuit 20 includes two power control modules 22, the two power control modules can be referred to as a pull-up power control module 24 and a pull-down power control module 25. Since the second power can be generated by the power switch module and the first working power and the second working power connected thereto, correspondingly, for the pull-up power control module 24, the fourth power can also be generated by the power switch module and the first working power and the second working power connected thereto; and for the pull-down power control module 25, the fifth power can also be generated by the power switch module and the first working power and the second working power connected thereto.

Thus, when the power control module 22 can be a pull-up power control module and/or a pull-down power control module, in some embodiments, the power switch module 23 includes at least one of the following: a pull-up power switch module and a pull-down power switch module;

Among them, the first switch tube and the second switch tube included in the pull-up power switch module can be PMOS tubes, the first switch tube and the second switch tube included in the pull-down power switch module can be NMOS tubes, and the first working power supply connected to the pull-up power switch module is different from the first working power supply connected to the pull-down power switch module, and the second working power supply connected to the pull-up power switch module is different from the second working power supply connected to the pull-down power switch module.

In the embodiment of the present invention, referring specifically to FIG. 5 , the control circuit 20 may further include a pull-up power switch module 26 and a pull-down power switch module 27. Among them, the pull-up power switch module 26 is connected to the pull-up power driving module 241, and is used to provide the fourth power VDD4 for the pull-up power driving module 241, so that the pull-up power driving module 241 can drive the pull-up reference power module 242, and then provide the first reference voltage for the sensing amplifier circuit 30; the pull-down power switch module 27 is connected to the pull-down power driving module 251, and is used to provide the fifth power VDD5 for the pull-down power driving module 251, so that the pull-down power driving module 251 can drive the pull-down reference power module 252, and then provide the second reference voltage for the sensing amplifier circuit 30.

It should also be noted that, in Figure 5, the pull-up power switch module 26 may include a first switch tube P1 and a second switch tube P2, the first end of the first switch tube P1 is connected to the third working power vnocp, the control end of the first switch tube P1 is connected to the first power enable sub-signal, the first end of the second switch tube P2 is connected to the fourth working power vpcsg, the control end of the second switch tube P2 is connected to the second power enable sub-signal, the second end of the first switch tube P1 is connected to the second end of the second switch tube P2, and the first switch tube P1 and the second switch tube P2 are selectively turned on to provide the fourth power VDD4 for the pull-up power drive module 241.

The pull-down power switch module 27 may include a first switch tube N1 and a second switch tube N2, wherein the first end of the first switch tube N1 is connected to the fifth working power vnoc, the control end of the first switch tube N1 is connected to the first power enable sub-signal, the first end of the second switch tube N2 is connected to the sixth working power vncsgh, the control end of the second switch tube N2 is connected to the second power enable sub-signal, the second end of the first switch tube N1 is connected to the second end of the second switch tube N2, and one of the first switch tube N1 and the second switch tube N2 is turned on to provide the fifth power VDD5 for the pull-down power drive module 251.

It should be noted that, in the embodiment of the present invention, for the pull-up power switch module 26, in the OC stage, the first switch tube P1 is turned on to provide the second power to the pull-up power driver module 241 through the third working power vnocp; in the signal amplification stage, the second switch tube P2 is turned on to provide the second power (specifically the fourth power) to the pull-up power driver module 241 through the fourth working power vpcsg. Since the third working power vnocp and the fourth working power vpcsg are in different voltage domains and/or have different temperature characteristics, different second power supplies can be provided to the pull-up power driver module 241 at different stages; for the pull-down power switch module 27, in the OC stage, the first switch tube N1 is turned on to provide the second power supply to the pull-down power driver module 251 through the fifth working power vnoc; in the signal amplification stage, the second switch tube N2 is turned on to provide the second power supply (specifically the fifth power supply) to the pull-down power driver module 251 through the sixth working power vncsgh. Since the fifth working power vnoc and the sixth working power vncsgh are in different voltage domains and/or have different temperature characteristics, different second power supplies can be provided to the pull-down power driver module 251 at different stages.

In this way, the second power required by both the pull-up power driver module 241 and the pull-down power driver module 251 can be separated according to the OC stage and the Develop stage, and the working power of the OC stage and the Develop stage can adjust the corresponding voltage trim range and temperature characteristics respectively, thereby improving SA noise suppression, read and write speed control, and sense margin optimization, etc., and ultimately improving the performance of the sensing amplifier.

It can also be understood that when the number of the power switch module 23 is at least one, the power enable signal required at this time corresponds to at least one group. Therefore, based on the control circuit 20 shown in FIG5 , in some embodiments, see FIG6 , the control circuit 20 may further include a power switch control module 28, wherein:

The power switch control module 28 is used to receive the bias elimination enable signal and the target power enable signal, and generate at least one set of power enable signals according to the bias elimination enable signal and the target power enable signal; wherein each set of power enable signals includes a first power enable sub-signal and a second power enable sub-signal, and at least one set of power enable signals has a corresponding relationship with at least one power switch module.

It should be noted that in Figure 6, taking the pull-up power switch module 26 and the pull-down power switch module 27 as an example, the power switch control module 28 can output two sets of power enable signals after receiving the bias elimination enable signal and the target power enable signal, one set of power enable signals is sent to the pull-up power switch module 26, and the other set of power enable signals is sent to the pull-down power switch module 27.

It should also be noted that, in the embodiment of the present invention, the target power enable signal may include a first target power enable signal and a second target power enable signal. Accordingly, in some embodiments, referring to FIG. 7 , the power switch control module 28 may include a first logic control module 281 and a second logic control module 282, wherein:

The first logic control module 281 is used to receive the bias elimination enable signal and the second target power enable signal, and output at least one first power enable sub-signal;

The second logic control module 282 is used to receive the bias elimination enable signal and the first target power enable signal, and output at least one second power enable sub-signal.

Here, the first target power enable signal and the first power enable sub-signal have the same effective state, and the second target power enable signal and the second power enable sub-signal have the same effective state. In other words, the effective levels of the first target power enable signal and the first power enable sub-signal correspond to the same operating state, and the effective levels of the second target power enable signal and the second power enable sub-signal correspond to the same operating state.

It should also be noted that the power switch control module 28 can output at least one set of power enable signals, and the number of power enable signals is related to the number of power switch modules 23. Specifically, if the control circuit 20 includes two power switch modules, namely a pull-up power switch module and a pull-down power switch module, then the power switch control module 28 needs to output two sets of power enable signals, each set of power enable signals corresponding to one power switch module, such as the pull-up power switch module 26 in FIG. 6 is connected to one set of power enable signals, and the pull-down power switch module 27 is connected to another set of power enable signals.

In some embodiments, as shown in FIG. 7 , the first logic control module 281 may include a first gate U1, a first gate U2, a first level conversion module U3, and a second gate U4, wherein:

The input end of the first gate U1 is used to receive the second target power enable signal, the output end of the first gate U1 is connected to the first input end of the first gate U2, the second input end of the first gate U2 is used to receive the bias elimination enable signal, the output end of the first gate U2 is connected to the input end of the first level conversion module U3, the output end of the first level conversion module U3 is connected to the input end of the second gate U4, and the output end of the second gate U4 is used to output at least one first power enable sub-signal;

The second logic control module 282 may include a first anti-OR gate U5, a third anti-gate U6, a second level switching module U7 and a fourth anti-gate U8, wherein:

The first input end of the first NOR gate U5 is used to receive the bias elimination enable signal, the second input end of the first NOR gate U5 is used to receive the first target power enable signal, the output end of the first NOR gate U5 is connected to the input end of the third NOR gate U6, the output end of the third NOR gate U6 is connected to the input end of the second level conversion module U7, the output end of the second level conversion module U7 is connected to the input end of the fourth NOR gate U8, and the output end of the fourth NOR gate U8 is used to output at least one second power enable sub-signal.

It should be noted that in the embodiment of the present invention, the first level switching module U3 or the second level switching module U7 can realize voltage domain switching (Level shift), and different voltage domains can correspond to different sets of power enable signals; after the power switch control module 28 outputs at least one set of power enable signals, these power enable signals can be sent to different power switch modules.

It should also be noted that, for the power switch control module 28, based on the power switch control module 28 shown in FIG. 7, in some embodiments, see FIG. 8, the power switch control module 28 may further include a fifth gate U9, wherein:

The input end of the fifth gate U9 is used to receive the bias elimination inverted signal. The output end of the fifth gate U9 is connected to the second input end of the first AND gate U2 and the first input end of the first NOR gate U5 respectively, and is used to provide a bias elimination enable signal for the second input end of the first AND gate U2 and the first input end of the first NOR gate U5.

It should be noted that, in the embodiment of the present invention, the offset cancellation inverted signal and the offset cancellation enable signal are mutually inverted signals. The offset cancellation enable signal can be represented by NcEn, and the offset cancellation inverted signal can be represented by NcEnN.

It should also be noted that, in the embodiment of the present invention, the power switch control module 28, as a master control circuit, can provide a set of power enable signals (including a first power enable sub-signal and a second power enable sub-signal) for different power switch modules. In addition, the first power enable sub-signal and the second power enable sub-signal in each set are generated according to the bias elimination inverted signal, and the first power enable sub-signal and the second power enable sub-signal will not be in a valid level state at the same time; that is, there is a timing relationship between the bias elimination inverted signal and the first power enable sub-signal and the second power enable sub-signal.

It can also be understood that in the pull-up power control module 24, for the pull-up reference power module 242, the pull-up reference power module 242 can include a plurality of pull-up switch tubes, wherein:

The control end (gate) of the pull-up switch tube is used to receive the pull-up power drive signal, the first end of the pull-up switch tube is connected to the pull-up reference power supply, and the second end of the pull-up switch tube is used to output the first reference voltage PCS.

Correspondingly, for the pull-up power driving module 241, the pull-up power driving module 241 may include a plurality of pull-up inverters, wherein:

The control end of the pull-up inverter is connected to the pull-up driving power supply, the input end of the pull-up inverter is used to receive the pull-up control input signal, and the output end of the pull-up inverter is used to output the pull-up power driving signal.

It should be noted that in the embodiment of the present invention, the number of pull-up switch tubes is consistent with the number of pull-up inverters. The output end of each pull-up inverter is connected to the control end of the corresponding pull-up switch tube to provide a pull-up power drive signal for the pull-up switch tube.

Exemplarily, taking the pull-up power driving module 241 including three pull-up inverters and the pull-up reference power module 242 including three pull-up switch tubes as an example, specifically referring to FIG. 9, in the pull-up power control module 24, the pull-up power driving module 241 may include a first pull-up inverter I1, a second pull-up inverter I2 and a third pull-up inverter I3, and the pull-up reference power module 242 may include a first pull-up switch tube M1, a second pull-up switch tube M2 and a third pull-up switch tube M3, wherein:

In the pull-up power driving module 241, the input end of the first pull-up inverter I1 is used to receive the first control input signal Vpu1, and the output end of the first pull-up inverter I1 is used to output the first pull-up power driving signal Pup1; the input end of the second pull-up inverter I2 is used to receive the second control input signal Vpu2, and the output end of the second pull-up inverter I2 is used to output the second pull-up power driving signal Pup2; the input end of the third pull-up inverter I3 is used to receive the third control input signal Vpu3, and the output end of the third pull-up inverter I3 is used to output the third pull-up power driving signal Pup3; the control end of the first pull-up inverter I1, the control end of the second pull-up inverter I2, and the control end of the third pull-up inverter I3 are all connected to the pull-up driving power vpcsgloc. In the pull-up reference power module 242, the first end of the first pull-up switch tube M1 is connected to the first pull-up reference power vblh1, the first end of the second pull-up switch tube M2 is connected to the second pull-up reference power vblh2, and the first end of the third pull-up switch tube M3 is connected to the third pull-up reference power vblh3; the control end of the first pull-up switch tube M1 is used to receive the first pull-up power drive signal Pup1, the control end of the second pull-up switch tube M2 is used to receive the second pull-up power drive signal Pup2, and the control end of the third pull-up switch tube M3 is used to receive the third pull-up power drive signal Pup3, and the second end of the first pull-up switch tube M1, the second end of the second pull-up switch tube M2 and the second end of the third pull-up switch tube M3 are connected to output the first reference voltage PCS. Here, the first pull-up reference power supply vblh1, the second pull-up reference power supply vblh2 and the third pull-up reference power supply vblh3 may be the same or different, and there is no limitation here.

It should be noted that in FIG9 , the pull-up driving power vpcsgloc (i.e., the fourth power described in the aforementioned embodiment) is provided by the pull-up power switch module 26. As shown in FIG9 , in the pull-up power switch module 26, the first end of the first switch tube P1 is connected to the third working power vnocp, the control end of the first switch tube P1 is connected to the first power enable sub-signal SCmosOcEn, the first end of the second switch tube P2 is connected to the fourth working power vpcsg, the control end of the second switch tube P2 is connected to the second power enable sub-signal SCmosSDTEn, the second end of the first switch tube P1 is connected to the second end of the second switch tube P2, and the first switch tube P1 and the second switch tube P2 are selectively turned on to provide the pull-up driving power vpcsgloc for the pull-up power driver module 241.

It can also be understood that in the pull-down power control module 25, for the pull-down reference power module 252, the pull-down reference power module 252 may include a plurality of pull-down switch tubes, wherein:

The control end of the pull-down switch tube is used to receive a pull-down power drive signal, the first end of the pull-down switch tube is connected to the pull-down reference power supply, and the second end of the pull-down switch tube is used to output a second reference voltage NCS.

Correspondingly, for the pull-down power driving module 251, the pull-down power driving module 251 may include a plurality of pull-down inverters, wherein:

The control end of the pull-down inverter is connected to the pull-down driving power supply, the input end of the pull-down inverter is used to receive the pull-down control input signal, and the output end of the pull-down inverter is used to output the pull-down power driving signal.

It should be noted that in the embodiment of the present invention, the number of pull-down switch tubes is consistent with the number of pull-down inverters. The output end of each pull-down inverter is connected to the control end of the corresponding pull-down switch tube to provide a pull-down power drive signal for the pull-down switch tube.

Exemplarily, taking the pull-down power driving module 251 including three pull-down inverters and the pull-down reference power module 252 including three pull-down switch tubes as an example, specifically referring to FIG. 10, in the pull-down power control module 25, the pull-down power driving module 251 may include a first pull-down inverter I4, a second pull-down inverter I5 and a third pull-down inverter I6, and the pull-down reference power module 252 may include a first pull-down switch tube M4, a second pull-down switch tube M5 and a third pull-down switch tube M6, wherein:

In the pull-down power driving module 251, the input end of the first pull-down inverter I4 is used to receive the fourth control input signal Vpd1, and the output end of the first pull-down inverter I4 is used to output the first pull-down power driving signal Pdn1; the input end of the second pull-down inverter I5 is used to receive the fifth control input signal Vpd2, and the output end of the second pull-down inverter I5 is used to output the second pull-down power driving signal Pdn2; the input end of the third pull-down inverter I6 is used to receive the sixth control input signal Vpd3, and the output end of the third pull-down inverter I6 is used to output the third pull-down power driving signal Pdn3; the control end of the first pull-down inverter I4, the control end of the second pull-down inverter I5, and the control end of the third pull-down inverter I6 are all connected to the pull-down driving power vncsgloc. In the pull-down reference power module 252, the control end of the first pull-down switch tube M4 is used to receive the first pull-down power driving signal Pdn1, the control end of the second pull-down switch tube M5 is used to receive the second pull-down power driving signal Pdn2, and the control end of the third pull-down switch tube M6 is used to receive the third pull-down power driving signal Pdn3; the first end of the first pull-down switch tube M4, the first end of the second pull-down switch tube M5 and the first end of the third pull-down switch tube M6 are connected to output the second reference voltage NCS; the second end of the first pull-down switch tube M4, the second end of the second pull-down switch tube M5 and the second end of the third pull-down switch tube M6 are all connected to the pull-down reference power VSS.

It should be noted that in FIG10 , the pull-down driving power vncsgloc (i.e., the fifth power described in the aforementioned embodiment) is provided by the pull-down power switch module 27. As shown in FIG10 , in the pull-down power switch module 27, the first end of the first switch tube N1 is connected to the fifth working power vnoc, the control end of the first switch tube N1 is connected to the first power enable sub-signal SCmosOcEn, the first end of the second switch tube N2 is connected to the sixth working power vncsgh, the control end of the second switch tube N2 is connected to the second power enable sub-signal SCmosSDTEn, the second end of the first switch tube N1 is connected to the second end of the second switch tube N2, and one of the first switch tube N1 and the second switch tube N2 is turned on to provide the pull-down driving power vncsgloc for the pull-down power driver module 251.

In addition, in the embodiment of the present invention, the third working power vnocp and the fourth working power vpcsg are in different voltage ranges and/or have different temperature characteristics, so that different pull-up driving power supplies vpcsgloc can be provided for the pull-up power driving module 241 at different stages; the fifth working power vnoc and the sixth working power vncsgh are in different voltage domains and/or have different temperature characteristics, so that different pull-down driving power supplies vncsgloc can be provided for the pull-down power driving module 251 at different stages; in this way, the pull-up/pull-down driving power supply can be adjusted according to the OC stage and the Develop stage, and the power supply noise of the OC stage and the Develop stage can be isolated, so that the SA noise suppression and the read and write speeds are effectively improved, and at the same time it is more beneficial to the optimization of the sense margin.

It can also be understood that in the embodiment of the present invention, for the sensing amplifier circuit 30, in some embodiments, referring to FIG. 11 , the sensing amplifier circuit 30 may include a seventh switching tube M7, an eighth switching tube M8, a ninth switching tube M9, a tenth switching tube M10, an eleventh switching tube M11, a twelfth switching tube M12, a thirteenth switching tube M13 and a fourteenth switching tube M14. Among them, the seventh switching tube M7, the eighth switching tube M8, the ninth switching tube M9 and the tenth switching tube M10 form an amplification module, the eleventh switching tube M11 and the twelfth switching tube M12 form an isolation control module, and the thirteenth switching tube M13 and the fourteenth switching tube M14 form a bias elimination module.

Here, the first end of the seventh switch tube M7 is connected to the first end of the eighth switch tube M8, and both are used to receive the first reference voltage PCS; the second end of the ninth switch tube M9 is connected to the second end of the tenth switch tube M10, and both are used to receive the second reference voltage NCS; the second end of the seventh switch tube M7, the control end of the eighth switch tube M8, the first end of the ninth switch tube M9, the second end of the twelfth switch tube M12, and the first end of the thirteenth switch tube M13 are all connected to the complementary read-out bit line saBlb; the second end of the eighth switch tube M8, the control end of the seventh switch tube M7, the first end of the tenth switch tube M10, the first end of the eleventh switch tube M11 are all connected to the complementary read-out bit line saBlb. The first end of the 11th switch tube M11 and the second end of the 13th switch tube M13 are all connected to the read bit line saBla; the second end of the 11th switch tube M11, the second end of the 13th switch tube M13 and the control end of the 9th switch tube M9 are all connected to the bit line Bla; the first end of the 12th switch tube M12, the first end of the 14th switch tube M14 and the control end of the 10th switch tube M10 are all connected to the complementary bit line Blb; the control end of the 11th switch tube M11 and the control end of the 12th switch tube M12 are both used to receive the isolation control signal Iso; the control end of the 13th switch tube M13 and the control end of the 14th switch tube M14 are both used to receive the bias elimination enable signal NcEn. In addition, in FIG. 11 , the ninth switching tube M9 , the tenth switching tube M10 , the eleventh switching tube M11 , the twelfth switching tube M12 , the thirteenth switching tube M13 and the fourteenth switching tube M14 may be NMOS tubes, and the seventh switching tube M7 and the eighth switching tube M8 may be PMOS tubes.

Taking DRAM as an example, the sensing amplifier circuit 30 is connected to the target storage cell through the bit line and to the complementary storage cell through the complementary bit line. In the initial state, the potential on the bit line and the complementary bit line is the same. After the target storage cell on the bit line is turned on, the target storage cell shares charge with the bit line, so that the potential on the bit line increases or decreases; the complementary storage cell on the complementary bit line is always closed, so the potential on the complementary bit line remains unchanged. Due to the increase and decrease of the potential on the bit line, the voltage difference between the bit line and the complementary bit line will change, so that some devices in the sensing amplifier circuit 30 are turned on and the signal amplification process is performed. At this time, the signal received by the sensing amplifier circuit 30 from the bit line can be regarded as a signal to be processed, and the signal received by the sensing amplifier circuit 30 from the complementary bit line can be regarded as a reference signal to be processed. In this way, in the signal amplification stage, when the eleventh switch tube M11 and the twelfth switch tube M12 are controlled to be in the on state according to the isolation control signal Iso, the transmission rate of the signal to be processed between the target storage unit and the amplifier module can be accelerated, so that the potential of the bit line or the complementary bit line can be quickly pulled up or down, thereby improving the signal amplification speed.

In some embodiments, for the pre-filling module 212, based on the sensing amplifier circuit 30 shown in FIG. 11, see FIG. 12, the pre-filling module 212 may include a pre-filling switch tube M15, wherein:

A first end of the pre-charge switch tube M15 is connected to the pre-charge power source VAD2, a control end of the pre-charge switch tube M15 is used to receive a pre-charge drive signal PreEQ, and a second end of the pre-charge switch tube M15 is connected to the read bit line saBla.

Further, as shown in FIG. 12 , the pre-charge drive module 211 may include a pre-charge inverter 17, wherein:

The input end of the pre-charge inverter I7 is used to receive the pre-charge enable signal eqN, the control end of the pre-charge inverter I7 is connected to the first power source Vdleq, and the output end of the pre-charge inverter I7 is used to output the pre-charge drive signal PreEQ.

It should be noted that, in the embodiment of the present invention, according to the pre-charge drive signal PreEQ output by the pre-charge drive module 211, the pre-charge module 212 can be controlled to perform pre-charge processing for the sensing amplifier circuit 30, so that the voltage on the read bit line saBla can be pre-charged to a preset value.

In some other embodiments, for the pre-filling module 212, based on the sensing amplifier circuit 30 shown in FIG. 11, see FIG. 13, the pre-filling module 212 may include a pre-filling switch tube M16, wherein:

A first end of the pre-charge switch tube M16 is connected to the read bit line saBla, a control end of the pre-charge switch tube M16 is used to receive a pre-charge drive signal EQ, and a second end of the pre-charge switch tube M16 is connected to the complementary read bit line saBlb.

Further, as shown in FIG. 13 , the pre-charge drive module 211 may include a pre-charge inverter 18, wherein:

The input end of the pre-charge inverter I8 is used to receive the pre-charge enable signal eqN, the control end of the pre-charge inverter I8 is connected to the first power source Vdleq, and the output end of the pre-charge inverter I8 is used to output the pre-charge drive signal EQ.

It should be noted that in the embodiment of the present invention, according to the pre-charge drive signal EQ output by the pre-charge drive module 211, the pre-charge module 212 can be controlled to perform pre-charge processing for the sensing amplifier circuit 30, thereby achieving voltage balance between the read bit line saBla and the complementary read bit line saBlb.

In addition, whether it is the pre-charge drive module 211 and the pre-charge module 212 in FIG. 12 or the pre-charge drive module 211 and the pre-charge module 212 in FIG. 13, the first power supply Vdleq is different from the third working power supply vnocp, the fourth working power supply vpcsg, the fifth working power supply vnoc, and the sixth working power supply vncsgh, so that the power supply noise at different stages can be isolated to achieve the purpose of suppressing the power supply noise. It should be noted that different power supplies refer to that the power supply signals have different external sources, and it does not mean that the specified voltage values must be different.

In some other embodiments, for the sensing amplifier circuit 30, the pre-charge drive module 211 and the pre-charge module 212 in FIG12 and the pre-charge drive module 211 and the pre-charge module 212 in FIG13 may exist at the same time. Among them, the pre-charge drive module 211 and the pre-charge module 212 in FIG12 are used to pre-charge the voltage on the read bit line saBla to a preset value, and the pre-charge drive module 211 and the pre-charge module 212 in FIG13 are used to achieve voltage balance between the read bit line saBla and the complementary read bit line saBlb.

In summary, an embodiment of the present invention provides a control circuit 20, which is connected to a sensing amplifier circuit, and the control circuit includes a pre-charge control module and a power control module. The pre-charge control module includes a pre-charge drive module and a pre-charge module, and the pre-charge drive module is connected to a first power source; the power control module includes a power drive module and a reference power module, and the power drive module is connected to a second power source, and the first power source is different from the second power source. In this way, since the pre-charge drive module and the power drive module use different power sources, power supply noise at different stages can be isolated, so that SA noise suppression and read-write speeds are effectively improved, and the signal amplification process of the sensing amplifier circuit can be optimized, thereby improving the performance of the sensing amplifier.

In another embodiment of the present invention, the control circuit 20 described in the above embodiment is applied to a sense amplifier. Referring to FIG. 14 , a schematic diagram of an application scenario of a sense amplifier provided by an embodiment of the present invention is shown. As shown in FIG. 14 , in this application scenario, there are a bit line Bla, a complementary bit line Blb, a read bit line saBla, a complementary read bit line saBlb, and a sense amplifier 51. A first storage unit 52 is provided on the bit line Bla, and a second storage unit 53 is provided on the complementary bit line Blb. Here, the first storage unit 52 and the second storage unit 53 can each be used as an object of a preset instruction.

In addition, the sense amplifier 51 may include a pull-up power control circuit 511, a pull-down power control circuit 512, a sense amplifier circuit 513 and a pre-charge control circuit 514. Among them, the pull-up power control circuit 511 includes a first pull-up inverter I1, a second pull-up inverter I2, a third pull-up inverter I3, a first pull-up switch tube M1, a second pull-up switch tube M2 and a third pull-up switch tube M3, the pull-down power control circuit 512 includes a first pull-down inverter I4, a second pull-down inverter I5, a third pull-down inverter I6, a first pull-down switch tube M4, a second pull-down switch tube M5 and a third pull-down switch tube M6, the sensing amplifier circuit 513 includes a seventh switch tube M7, an eighth switch tube M8, a ninth switch tube M9, a tenth switch tube M10, an eleventh switch tube M11, a twelfth switch tube M12, a thirteenth switch tube M13 and a fourteenth switch tube M14, and the pre-charge control circuit 514 includes a pre-charge switch tube M15 and a pre-charge inverter I7. Here, the specific working principle of the circuit of FIG. 14 can be found in the above content, and will not be elaborated here.

In Figure 14, the control end of the first pull-up inverter I1, the control end of the second pull-up inverter I2 and the control end of the third pull-up inverter I3 are all connected to the pull-up drive power Vpcsg, the control end of the first pull-down inverter I4, the control end of the second pull-down inverter I5 and the control end of the third pull-down inverter I6 are all connected to the pull-down drive power Vncsgh, and the control end of the pre-charge inverter I7 is connected to the pre-charge drive power Vdleq.

It should be noted that in the related art, the pre-charge drive power Vdleq and the pull-down drive power Vncsgh share the same power supply, and there is noise when the SA works at different stages, which is not good for the sense margin; and because the temperature characteristics of the power supply at different stages are exactly the same, the sense amplifier lacks flexibility. In the embodiment of the present invention, for the sense amplifier shown in FIG14, the pre-charge drive power Vdleq and the pull-down drive power Vncsgh use different power supplies, and the pre-charge drive power Vdleq and the pull-up drive power Vpcsg also use different power supplies, so that the noise of the power bus at different stages (such as the OC stage and the Develop stage) can be isolated.

Based on FIG. 14 , see FIG. 15 , which shows a signal timing diagram of a sense amplifier provided by an embodiment of the present invention. As shown in FIG. 15 , Iso refers to the aforementioned isolation control signal, which can be a first voltage value and a second voltage value; PreEQ refers to the aforementioned pre-charge drive signal, NcEn refers to the aforementioned bias elimination enable signal (which can also be represented by Nc, or called a noise elimination signal); SanEn refers to the aforementioned pull-down power drive signal (Pdn1, Pdn2, Pdn3, etc.), SapEn refers to the aforementioned pull-up power drive signal (Pup1, Pup2, Pup3, etc.); WL refers to the word line turn-on signal. When WL is in the second level state, the word line where the target storage unit is located is turned on. When WL is in the first level state, the word line where the target storage cell is located is closed, so that the target storage cell and the bit line are not connected; PCS/NCS refers to the first reference voltage signal/the second reference voltage signal, the first reference voltage signal has a fourth voltage value and a fifth voltage value, the first reference voltage signal has a fourth voltage value and a sixth voltage value, and the fourth voltage value is between the fifth voltage value and the sixth voltage value; Bla refers to the bit line, Blb refers to the complementary bit line, saBla refers to the read-out bit line, and saBlb refers to the complementary read-out bit line. Among them, the first level state represents a low level state, and the second level state represents a high level state.

As shown in FIG15 , when the amplifier circuit is in the idle stage, the isolation control signal Iso maintains the second voltage value, the pre-charge drive signal PreEQ and the bias elimination enable signal NcEn are in the second level state, the pull-down power drive signal SanEn/the pull-up power drive signal SapEn are both in the first level state, the word line start signal WL is in the first level state, the first reference voltage signal PCS/the second reference voltage signal NCS maintain the fourth voltage value, and the bit line Bla/the complementary bit line Blb are both in the fourth voltage value; at this time, preliminary preparations are made for executing the user's operation instructions. It should be noted that due to process deviations of the ninth switch tube M9 and the tenth switch tube M10, there is a difference in the performance of the two switch tubes, resulting in a voltage difference dVt between the read bit line saBla/complementary read bit line saBlb. In order to balance the voltages on both sides, after the pre-charge stage, it is necessary to enter the bias elimination stage. Under ideal conditions, dVt should be as close to zero as possible.

Specifically, assuming that the target storage unit is the first storage unit 52, after the user sends a read command for the target storage unit, the sensing amplifier circuit 513 enters the bias elimination stage from the standby stage, at which time the isolation control signal Iso is adjusted from the second voltage value to the first voltage value, the pre-charge drive signal PreEQ is adjusted from the second level state to the first level state, and the pull-down power drive signal San En/pull-up power drive signal SapEn are both adjusted from the first level state to the second level state, so the first reference voltage signal PCS changes from the fourth voltage value to the fifth voltage value, the second reference voltage signal NCS changes from the fourth voltage value to the sixth voltage value, and the bias elimination enable signal NcEn still maintains the second level state, thereby performing bias elimination processing on the sensing amplifier circuit 513. Afterwards, the pull-down power drive signal SanEn/pull-up power drive signal SapEn switches to the first level state, and the first reference voltage signal PCS and the second reference voltage signal NCS continue to be powered by the pre-charge control circuit 514 to recover to the fourth voltage value.

After the bias elimination phase is completed, when the word line opening signal WL changes to the second level state, the word line where the target storage cell is located is adjusted to the open state, so that the sensing amplifier circuit 513 enters the word line opening phase, specifically the first charge sharing (CS) phase, at which the target storage cell (e.g., the first storage cell 52) is read. As shown in FIG15 , taking the data stored in the first storage cell 52 as "0" as an example, after the first charge sharing phase is completed, the voltage of the bit line Bla is reduced, that is, a signal to be processed is generated, and the complementary bit line Blb forms a reference signal to be processed. In addition, in the first charge sharing stage, the isolation control signal Iso maintains the first voltage value, so that the bit line Bla and the read bit line saBla are not connected, and the complementary bit line Blb and the complementary read bit line saBlb are not connected. The pre-charge drive signal PreEQ, the bias elimination enable signal NcEn, the pull-down power drive signal SanEn/the pull-up power drive signal SapEn are all in the first level state.

After the first charge sharing stage is finished, the sense amplifier circuit 513 enters the second charge sharing stage. In the second charge sharing stage, the isolation control signal Iso maintains the second voltage value, so that the bit line Bla is connected to the read bit line saBla, and the bit line Blb is connected to saBlb, so that the sense amplifier circuit 513 receives the signal to be processed and the reference signal to be processed to the internal node, and reduces the voltage of the read bit line saBla, which can be regarded as the bit line Bla/complementary bit line Blb and the read bit line saBla/complementary read bit line saBlb perform read charge sharing. In addition, except for the isolation control signal Iso, other signals maintain the voltage value of the previous stage.

After the second charge sharing phase ends, the sensing amplifier circuit 513 enters the amplification phase, and the pull-down power driving signal SanEn/the pull-up power driving signal SapEn is adjusted from the first level state to the second level state, so that the first reference voltage signal PCS changes from the fourth voltage value to the fifth voltage value, and the second reference voltage signal NCS changes from the fourth voltage value to the sixth voltage value, and the voltage of the read bit line saBla decreases, so that the seventh switch tube M7 is turned on, and the first reference voltage signal PCS pulls up the voltage of the complementary read bit line saBlb. The tenth switch tube M10 is turned on, and the second reference voltage signal NCS pulls down the voltage of the read bit line saBla, so that the sensing amplifier circuit 513 can amplify the signal to be processed (the signal of the bit line Bla)/the reference signal to be processed (the signal of the complementary bit line Blb) according to the first reference voltage signal PCS/the second reference voltage signal NCS, and the isolation control signal Iso still maintains the second voltage value to complete the signal amplification on the signal to be processed (the signal of the bit line Bla)/the reference signal to be processed (the signal of the complementary bit line Blb).

In addition, if the data stored in the first storage unit 52 is "1", the voltage of the bit line Bla will be pulled up in the first amplification stage. Since the isolation control signal Iso is at the second voltage value, the rising rate of the bit line Bla/complementary bit line Blb can be suppressed and the noise on the bit line Bla/complementary bit line Blb can be reduced. However, the signal on the read bit line saBla/complementary read bit line saBlb inside the sensing amplifier circuit 513 can quickly reach the high reference potential/low reference potential.

After the amplification stage is finished, when the word line turn-on signal WL changes to the first level state, the word line where the target storage unit is located is adjusted to the closed state. At this time, the sensing amplifier circuit 513 enters the word line closing stage, and at the same time, the isolation control signal Iso maintains the second voltage value, and the pre-charge drive signal PreEQ and the bias elimination enable signal NcEn maintain the first level state; in addition, during this stage, the pull-down power drive signal SanEn/pull-up power drive signal SapEn will be adjusted from the second level state to the first level state.

Furthermore, the sensing amplifier circuit 513 enters the pre-charge stage, and the pre-charge drive signal PreEQ and the bias elimination enable signal NcEn are adjusted to the second level state. At this time, the first reference voltage signal PCS/the second reference voltage signal NCS will be restored to the fourth voltage value, and the bit line Bla/the complementary bit line Blb and the read bit line saBla/the complementary read bit line saBlb will be restored to the same voltage value.

After the pre-charge phase ends, the sensing amplifier circuit 513 enters the idle phase again to prepare for the next operation.

In the embodiment of the present invention, for the pre-charge drive signal PreEQ and the bias elimination enable signal NcEn, when they are in the second level state, the corresponding voltage value can be provided by the pre-charge drive power Vdleq; for the pull-up power drive signal SapEn, when it is in the second level state, the corresponding voltage value can be provided by the pull-up drive power Vpcsg (specifically the third working power vnocp and the fourth working power vpcsg) Provided; for the pull-down power drive signal SanEn, when it is in the second level state, its corresponding voltage value can be provided by the pull-down drive power Vncsgh (specifically the fifth working power vnoc and the sixth working power vncsgh); for the first reference voltage signal PCS/the second reference voltage signal NCS, the bit line Bla/the complementary bit line Blb, its lowest value is the ground signal, which can be provided by the pull-down reference power VSS.

In summary, the specific implementation of the aforementioned embodiment is explained in detail based on the aforementioned embodiment. It can be seen that according to the technical solution of the aforementioned embodiment, since the pre-charge control circuit 514 and the pull-up power control circuit 511/pull-down power control circuit 512 use different power supplies, the power supply noise in different stages can be isolated, so that the SA noise suppression and the read-write speed are effectively improved, and the signal amplification process of the sensing amplifier circuit can be optimized, thereby improving the performance of the sensing amplifier.

In some embodiments, refer to FIG. 16, which shows a schematic diagram of the composition structure of a semiconductor memory provided by an embodiment of the present invention. As shown in FIG. 16, the semiconductor memory includes a control circuit, a plurality of storage blocks, and a sensing amplifier circuit module disposed between two adjacent storage blocks, and a switch module is disposed between two adjacent sensitive amplifier modules. Among them, the control circuit includes a pre-charge control module and a power control module, the sensitive amplifier module storage block includes a sensing amplifier circuit and a pre-charge control module, and the switch module includes a power control module, wherein:

The pre-charge control module may include a pre-charge drive module and a pre-charge module, and the pre-charge drive module is connected to the first power source, and is used to provide a pre-charge drive signal to the pre-charge module through the pre-charge drive module, and control the pre-charge module to perform pre-charge processing for the sensing amplifier circuit according to the pre-charge drive signal;

The power control module may include a power drive module and a reference power module, and the power drive module is connected to a second power source, and is used to provide a power drive signal to the reference power module through the power drive module, and control the reference power module to provide a reference voltage for the sensing amplifier circuit according to the power drive signal; wherein the first power source is different from the second power source.

Taking four storage blocks as an example, it can be seen from FIG16 that in the first direction, a sensitive amplifier module including a sensing amplifier circuit, a pre-charge module, and a pre-charge drive module is disposed between adjacent storage blocks; in the second direction, a row decoder is disposed between adjacent storage blocks, and a switch module is also disposed between adjacent sensitive amplifier modules, and the switch module is also located between adjacent row decoders. Here, the storage block can be a plurality of storage sections (sections) divided by a storage body (bank) in the first direction, that is, each storage block is a storage section.

In some embodiments, the semiconductor memory may further include the power switch module described in the aforementioned embodiments and the power switch control module described in the aforementioned embodiments, wherein: the power switch module and the power switch control module are both located in the switch module; or, the power switch module is located in the switch module, and the power switch control module is located in a peripheral area of the semiconductor memory; or, the power switch module and the power switch control module are both located in a peripheral area of the semiconductor memory. In this way, placing the power switch module and the power switch control module in the peripheral area can realize the merging of the power switch modules and the power switch control modules corresponding to multiple storage blocks in the same storage body or even multiple storage bodies in the same memory to perform overall control, thereby saving chip area and increasing the number of chips on the same wafer (Die Per Wafer, DPW).

It is understood that the above-mentioned overall control means that the same power switch control module is used to control the power switch modules corresponding to multiple storage blocks or multiple storage bodies, reducing the number of power switch control modules, and the same power switch module controls the power conduction corresponding to multiple storage blocks or multiple storage bodies. Furthermore, when the power switch module is set in the peripheral area, the corresponding connected power is generated in the peripheral area.

The above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention.

It should be noted that, in the present invention, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, an element defined by the phrase "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

The serial numbers of the above embodiments of the present invention are for description only and do not represent the advantages or disadvantages of the embodiments.

The methods disclosed in the several method embodiments provided by the present invention can be arbitrarily combined without conflict to obtain new method embodiments.

The features disclosed in several product embodiments provided by the present invention can be arbitrarily combined without conflict to obtain new product embodiments.

The features disclosed in several method or device embodiments provided by the present invention can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

The above are only specific implementations of the present invention, but the protection scope of the present invention is not limited thereto. Any technical personnel familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the patent application.

11: First signal line 12: Second signal line 13: Sense amplifier 20: Control circuit 21: Precharge control module 211: Precharge drive module 212: Precharge module 22: Power control module 221: Power drive module 222: Reference power module 23: Power switch module 24: Pull-up power control module 241: Pull-up power drive module 242: Pull-up reference power module 25: Pull-down power control module 251: Pull-down power drive module 252: Pull-down reference power module 26: Pull-up power switch module 27: Pull-down power switch module 28: Power switch control module 281: First logic control module 282: Second logic control module 30: Sense amplifier circuit 51: Sense amplifier 511: Pull-up power control circuit 512: Pull-down power control circuit 513: Sense amplifier circuit 514: Pre-charge control circuit 52: First storage unit 53: Second storage unit

Figure 1 is a schematic diagram of an application scenario of a sensing amplifier; Figure 2 is a schematic diagram of a control circuit provided in an embodiment of the present invention; Figure 3 is a schematic diagram of a control circuit provided in an embodiment of the present invention; Figure 4 is a schematic diagram of a control circuit provided in an embodiment of the present invention; Figure 5 is a schematic diagram of a control circuit provided in an embodiment of the present invention; Figure 6 is a schematic diagram of a control circuit provided in an embodiment of the present invention; Figure 7 is a schematic diagram of a power switch control module provided in an embodiment of the present invention; Figure 8 is a schematic diagram of a power switch control module provided in an embodiment of the present invention; Figure 9 is a schematic diagram of a pull-up power control module provided in an embodiment of the present invention; Figure 10 is a schematic diagram of the composition structure of a pull-down power supply control module provided in an embodiment of the present invention; Figure 11 is a schematic diagram of the composition structure of a sensing amplifier circuit provided in an embodiment of the present invention; Figure 12 is a schematic diagram of the composition structure of a sensing amplifier circuit provided in an embodiment of the present invention; Figure 13 is a schematic diagram of the composition structure of a sensing amplifier circuit provided in an embodiment of the present invention; Figure 14 is a schematic diagram of the application scenario of a sensing amplifier provided in an embodiment of the present invention; Figure 15 is a schematic diagram of the signal timing of a sensing amplifier provided in an embodiment of the present invention; Figure 16 is a schematic diagram of the composition structure of a semiconductor memory provided in an embodiment of the present invention.

20: Control circuit

21: Pre-charge control module

211: Pre-charge drive module

212: Pre-charge module

22: Power control module

221: Power drive module

222: Reference power module

30: Perception amplifier circuit

Claims (10)

A control circuit, characterized in that the control circuit is connected to a sensing amplifier circuit, and the control circuit includes a pre-charge control module and a power supply control module, wherein: the pre-charge control module includes a pre-charge drive module and a pre-charge module, and the pre-charge drive module is connected to a first power supply, and is used to provide a pre-charge drive signal to the pre-charge module through the pre-charge drive module, and the pre-charge drive signal is used to control the pre-charge module to The sensing amplifier circuit performs pre-charging processing; the power control module includes a power drive module and a reference power module, and the power drive module is connected to a second power source, and is used to provide a power drive signal to the reference power module through the power drive module, and control the reference power module according to the power drive signal to provide a reference voltage for the sensing amplifier circuit; wherein the first power source is different from the second power source. The control circuit as described in claim 1 is characterized in that the control circuit also includes a power switch module, and the power switch module is connected to a third power source, wherein: the power switch module is used to receive a power enable signal, and control the state of the switch tube inside the power switch module according to the power enable signal to provide the second power to the power drive module through the third power source, and the first power source is different from the third power source. The control circuit as described in claim 2 is characterized in that the third power supply includes a first working power supply and a second working power supply, the first working power supply and the second working power supply are in different voltage domains and/or have different temperature characteristics, and the power enable signal includes a first power enable sub-signal and a second power enable sub-signal; the power switch module includes a first switch tube and a second switch tube; wherein the first end of the first switch tube is connected to the first working power supply, the control end of the first switch tube is connected to the first power enable sub-signal, the first end of the second switch tube is connected to the second working power supply, the control end of the second switch tube is connected to the second power enable sub-signal, the second end of the first switch tube is connected to the second end of the second switch tube, and the first switch tube and the second switch tube are selectively turned on to provide the second power supply to the power drive module. The control circuit as described in claim 3 is characterized in that, when the sensing amplifier circuit operates in a bias elimination stage, the first switch tube is turned on to provide the second power supply to the power drive module through the first working power supply; when the sensing amplifier circuit operates in a signal amplification stage, the second switch tube is turned on to provide the second power supply to the power drive module through the second working power supply. The control circuit as described in claim 3 is characterized in that the power switch module includes at least one of the following: a pull-up power switch module and a pull-down power switch module; wherein the first switch tube and the second switch tube included in the pull-up power switch module are PMOS tubes, and the first switch tube and the second switch tube included in the pull-down power switch module are NMOS tubes, and the first working power supply connected to the pull-up power switch module is different from the first working power supply connected to the pull-down power switch module, and the second working power supply connected to the pull-up power switch module is different from the second working power supply connected to the pull-down power switch module. The control circuit as described in claim 5 is characterized in that, when the number of the power switch modules is at least one, the control circuit further includes a power switch control module, wherein: the power switch control module is used to receive a bias elimination enable signal and a target power enable signal, and generate at least one group of power enable signals according to the bias elimination enable signal and the target power enable signal; wherein each group of power enable signals includes the first power enable sub-signal and the second power enable sub-signal, and at least one group of power enable signals has a corresponding relationship with at least one power switch module. The control circuit as described in claim 6 is characterized in that the target power enable signal includes a first target power enable signal and a second target power enable signal, and the power switch control module includes a first logic control module and a second logic control module, wherein: the first logic control module is used to receive the bias elimination enable signal and the second target power enable signal, and output at least one of the first power enable sub-signals; the second logic control module is used to receive the bias elimination enable signal and the first target power enable signal, and output at least one of the second power enable sub-signals; wherein the first target power enable signal and the first power enable sub-signal have the same valid state, and the second target power enable signal and the second power enable sub-signal have the same valid state. The control circuit as described in claim 7 is characterized in that the first logic control module includes a first inverter, a first NAND gate, a first level conversion module and a second inverter, wherein: the input end of the first inverter is used to receive the second target power enable signal, the output end of the first inverter is connected to the first input end of the first NAND gate, the second input end of the first NAND gate is used to receive the bias elimination enable signal, the output end of the first NAND gate is connected to the input end of the first level conversion module, the output end of the first level conversion module is connected to the input end of the second inverter, and the output end of the second inverter is used to output at least one of the first power enable sub-signals; the second logic control module includes a first NOR gate, a third inverter, a second level conversion module and a second NAND gate. The power switch control module further comprises a fifth gate, wherein: the first input terminal of the first gate is used to receive the bias elimination enable signal, the second input terminal of the first gate is used to receive the first target power enable signal, the output terminal of the first gate is connected to the input terminal of the third gate, the output terminal of the third gate is connected to the input terminal of the second level conversion module, the output terminal of the second level conversion module is connected to the input terminal of the fourth gate, and the output terminal of the fourth gate is used to output at least one of the second power enable sub-signals; or, the power switch control module further comprises a fifth gate, wherein: the input terminal of the fifth gate is used to receive the bias elimination inverted signal, and the output terminal of the fifth gate is used to output the bias elimination enable signal. The control circuit as described in claim 1 is characterized in that the pre-charge module includes a pre-charge switch tube, wherein: the first end of the pre-charge switch tube is connected to the pre-charge power supply, the control end of the pre-charge switch tube is used to receive the pre-charge drive signal, and the second end of the pre-charge switch tube is connected to the read bit line; or, the first end of the pre-charge switch tube is connected to the read bit line, the control end of the pre-charge switch tube is used to receive the pre-charge drive signal, and the second end of the pre-charge switch tube is connected to the complementary read bit line; wherein the pre-charge drive module includes a pre-charge inverter, wherein: the input end of the pre-charge inverter is used to receive the pre-charge enable signal, the control end of the pre-charge inverter is connected to the first power supply, and the output end of the pre-charge inverter is used to output the pre-charge drive signal. A semiconductor memory, characterized in that the semiconductor memory includes a control circuit as described in any one of claim items 1 to 9, a plurality of storage blocks, and a sensitive amplifier module arranged between two adjacent storage blocks, a switch module is arranged between the two adjacent sensitive amplifier modules, the control circuit includes a pre-charge control module and a power control module, the sensitive amplifier module includes a sensing amplifier circuit and the pre-charge control module, and the switch module includes the power control module.

Images