TW202411988A - Apparatus for page-copy data accessing - Google Patents

Abstract

An apparatus for page-copy data accessing is provided, which includes a memory cell array, bit-line sense-amplifier/buffers (BLSABFs), page buffers and a logic operation processing circuit. Data voltage signals on bit-lines in a memory section of the apparatus are transferred to the bit-lines in an adjacent memory section adjacent to the memory section by BLSABFs and the voltage data signals are sequentially propagated across subsequent memory sections through BLSABFs between the subsequent memory sections. The scheme can be applied as a method of page-data write access in a memory chip, of which page data can be propagated sequentially from section to subsequent adjacent section until a target location is reached, and then, activating a word line in a section of the memory comprising target location to write voltages to the memory cells at the target location.

Description

Device for copying, moving and accessing web data

The present invention relates to memory management, and more particularly to a device for copying, moving and accessing page data using its low power and wide data access characteristics.

Traditional semiconductor memory blocks can be used to store data, and one of the important considerations in memory block design is to maximize bandwidth data access. However, some problems may occur in the data access method of the prior art. For example, it may be necessary to balance the number of pre-fetches for data access, overall power consumption, normalized access energy efficiency, and memory block area size. In addition, without significantly increasing the memory block area, the traditional cell array architecture of the memory block may have reached the limit of the number of pre-fetches. Therefore, a new data access architecture and method are needed to solve this problem.

Therefore, the purpose of the present invention is to provide a device for copying, moving and accessing data in units of "pages" (or in units of memory block data coupled on the entire bit line), and to utilize its low-power data access characteristics to solve the above-mentioned problems.

The present invention provides a device for copying, moving and accessing page data, the device comprising: a memory cell array, divided into a plurality of memory blocks, each memory block comprising a plurality of memory cells divided into a plurality of pages, and each memory cell of a page is coupled to a corresponding word line (word-line), and the data in the memory cell coupled to a word line is called page data (page data). age-data); a plurality of bit-line sense amplifiers/buffers coupled to the memory cell array via a plurality of bit-lines or bit-line pairs, each bit-line sense amplifier/buffer coupled to two bit-lines or bit-line pairs in two different memory blocks located on two opposite sides thereof, a bit-line or bit-line pair in a memory block The data voltage signal on the bit line pair is transmitted to the bit line or bit line pair in an adjacent memory block adjacent to the memory block through the signal sensing and buffering performed by the plurality of bit line sense amplifiers/buffers, and the page data in the form of the data voltage signal is sequentially transmitted between the plurality of subsequent memory blocks through the bit line sense amplifiers/buffers coupled to the two adjacent memory blocks in the subsequent memory blocks; a plurality of page buffers are coupled to the plurality of bit line sense amplifiers The invention relates to a device for storing the page data voltage signal from the coupled bit line sense amplifier/buffer to the coupled bit line sense amplifier/buffer; and a logic operation processing circuit coupled to the plurality of page buffers, configured to receive the data voltage signal from the coupled bit line sense amplifier/buffer to a data interface of the device, or configured to store the data voltage signal from the data interface of the device to the coupled bit line sense amplifier/buffer; and a logic operation processing circuit coupled to the plurality of page buffers, configured to receive the data voltage signal from the plurality of page buffers and perform a one-bit multiplication operation on the data voltage signal.

FIG. 1 is a schematic diagram of a device for enhancing data access (e.g., read/write/move) in a memory module 100 according to an embodiment of the present invention. For example, the memory module 100 may include a static-random-access memory (SRAM), a dynamic random access memory (DRAM), a flash memory, a magneto-resistive random-access memory (MRAM), a ferroelectric random-access memory (FeRAM), or a resistive random access memory (RRAM), but the present invention is not limited thereto. The device may include at least a portion (e.g., a portion or all) of the memory module 100. For example, the device may include a portion of the memory architecture of the memory module 100. In another embodiment, the device may include a combination of a portion of the memory architecture and the associated control mechanism. In another embodiment, the device may include the entire memory module.

As shown in FIG. 1 , the memory module 100 may include a memory bank 101 and a secondary semiconductor chip 102. The memory bank 101 may include a word line decoder 110 and a memory cell array. The memory cell array 120 includes a plurality of memory cells, for example, (M*N) memory cells, where M and N can be represented by positive integers, respectively. The plurality of memory cells are respectively coupled to a plurality of bit lines (or bit line pairs) and a plurality of word lines of the memory cell array 120, for example, N bit lines {BL(1), BL(2), ..., BL(N)} or N groups of bit line pairs coupled to the (M*N) memory cells, and M word lines {WL(1), WL(2), ..., WL(M)} coupled to the (M*N) memory cells, but the present invention is not limited thereto. In some embodiments, in addition to the word line driver, the word line decoder 110 can be at least partially implemented in the secondary semiconductor chip 102. For example, a word line decoder front-stage circuit of the word line decoder 110 may be implemented on the secondary semiconductor chip 102 , and a word line decoder final-stage circuit (which may include a word line driver) of the word line decoder 110 may be implemented on the memory bank 101 .

The memory bank 101 may further include a plurality of bit-line sense amplifiers/buffers (BLSABFs), which are coupled to the memory cell array 120 via a plurality of bit lines, for example, the page buffer module 130 may include N bit-line sense amplifiers/buffers BLSABFs. The memory bank 101 may further include a plurality of page buffers, coupled to all or part of the plurality of bit-line sense amplifiers/buffers BLSABFs, for example, the page buffers in the page buffer module 130. The memory bank 101 may further include a plurality of main data lines coupled to the N bit line sense amplifiers/buffers BLSABF of the page buffer module 130, wherein the plurality of main data lines may be used as an off-chip data interface of the memory bank 101. For example, the secondary semiconductor chip 102 may be electrically connected to the memory bank 101 by direct face-to-face attachment, but the present invention is not limited thereto. In addition, the secondary semiconductor chip 102 may include access-related peripheral circuits 150, and the access-related peripheral circuits 150 may include access circuits 152. For example, the secondary semiconductor chip 102 may include a plurality of secondary amplifiers located in the access circuits 152. A plurality of page buffers are configured to receive data voltage signals from the coupled bit line sense amplifier/buffer BLSABF and propagate the data voltage signals to the device's off-chip data interface (e.g., logic operation processing circuit), or are configured to store data voltage signals from the device's off-chip data interface to the coupled bit line sense amplifier/buffer BLSABF.

The memory cell array 120 can store data, and the memory module 100 can be installed in a host system. Examples of the host system can include a multi-function mobile phone, a tablet computer, and a personal computer such as a desktop computer and a laptop computer. The memory cell array 120 can include SRAM cells, DRAM cells, flash memory cells, MRAM cells, FeRAM cells, RRAM cells, or any other types of memory cells. A plurality of bit lines, such as N bit lines or {BL(1), BL(2), ..., BL(N)} or bit line pairs {BL(1)/BLF(1), BL(2)/BLF(2), ..., BL(N)/BLF(N)}, and a plurality of word lines, such as M word lines {WL(1), WL(2), ..., WL(M)}, can access and control the memory cell array 120. According to the present embodiment, a plurality of BLSAs can respectively sense a plurality of bit line signals read from (M*N) memory cells and convert the bit line signals into a plurality of amplified signals. The data in the plurality of memory cells coupled to a word line is page data. According to this embodiment, a plurality of BLSABFs can respectively sense a plurality of bit line signals read from (M*N) memory cells and convert the bit line signals into a plurality of amplified signals.

With respect to the architecture shown in FIG. 1 , the device may include a memory bank 101 in a memory module 100, but the present invention is not limited thereto. For example, the device may further include a secondary semiconductor chip 102. According to some embodiments, in addition to the memory bank 101, the memory module 100 may include at least a portion (e.g., a portion or all) of the secondary semiconductor chip 102. For example, one or more other circuits having any external functions of the memory module 100 may be integrated into the secondary semiconductor chip 102.

In some embodiments, the structure shown in FIG. 1 is changeable. For example, the memory cell array 120 may be divided into a plurality of memory cell array (CA) blocks according to a predetermined bit line length to increase access speed, and a plurality of BLSABFs (e.g., N BLSABFs in the page buffer 130) may be divided into a plurality of BLSABF portions corresponding to the cell array portions coupled to perform related sensing operations.

FIG. 2 is a schematic diagram of an alternate arrangement of a plurality of memory cell array blocks and a plurality of bit line sense amplifiers/buffers BLSABF in an embodiment of the present invention. FIG. 2 shows the memory cell array (CA) blocks and the bit line sense amplifiers/buffers (BLSABF) blocks of the architecture in an embodiment of the present invention (labeled as "CA blocks" and "BLSABF blocks" in FIG. 2 for simplicity). In addition, any two memory cell array blocks may be identical or similar to each other (having different bit line lengths or different numbers of cells per bit line), and any two bit line sense amplifiers/buffers BLSABF may be identical or similar to each other.

FIG. 3A is a schematic diagram of an embodiment of a 1T1C (one transistor and one capacitor) DRAM memory cell of the memory module in FIG. 1. The memory cell may be an embodiment of any memory cell (e.g., each memory cell) among a plurality of memory cells in the memory cell array 120. As shown in FIG. 3A, the memory cell may include a switching transistor coupled to a word line among a plurality of word lines (e.g., word line WL(m)) and a bit line among a plurality of bit lines (e.g., bit line BL(n)), and a capacitor Cap. The capacitor Cap may store memory charge, and different states of the charge may represent one bit of information (e.g., 0 or 1), but the present invention is not limited thereto. In some embodiments, a 2T2C (two transistors and two capacitors) memory cell may also be utilized. Those skilled in the art are aware of the general structure and function of a 2T2C memory cell. FIG. 3B is a schematic diagram of an embodiment of a 6T (six transistors) SRAM memory cell of the memory module of FIG. 1. The memory cell may be an embodiment of any memory cell (e.g., each memory cell) of a plurality of memory cells of a memory cell array 120. As shown in FIG. 3B, the memory cell may include transistors Q1-Q6. Transistors Q1 and Q2 are coupled to a word line (WL) among a plurality of word lines (e.g., word line WL(m) and a bit line pair (e.g., bit line BL(n) and bit line BLB(n))) to access or store data in a memory cell.

FIG. 4 is a schematic diagram of the bit line sense amplifier/buffer BLSABF of the memory module 100 in FIG. The data in the plurality of memory cells coupled to a corresponding word line is page data, and the bit line sense amplifier/buffer BLSABF is coupled to two bit lines or bit line pairs in two different memory cell array blocks located on both sides thereof (for example, two memory cell array blocks are respectively adjacent to a bit line sense amplifier/buffer block including the bit line sense amplifier/buffer BLSABF). Through signal sensing and buffering performed by the bit line sense amplifier/buffer BLSABF, page data in the form of a data voltage signal on a bit line or bit line pair of a memory cell array block can be transmitted to a bit line or bit line pair of an adjacent memory cell array block. In this way, the data voltage signal can be sequentially propagated through multiple bit line sense amplifiers/buffers BLSABF between multiple subsequent memory cell array blocks.

The bit line sense amplifier/buffer BLSABF can operate according to a propagation control signal BLISO and a sense or latch control signal SEN to obtain respective bit information (voltage), wherein the memory module 100 (e.g., the memory bank 101) can select any one of a plurality of memory cells according to the access control signal of the word line decoder 110. For example, in the first stage of the read phase, the bit line sense amplifier/buffer BLSABF can obtain the bit information of a first memory cell of the two memory cells through a first bit line or a bit line pair, and amplify the signal carrying the bit information of the first memory cell. For example, in the second stage of the read phase, the bit line sense amplifier/buffer BLSABF may obtain bit information of a second memory cell of the two memory cells through a second bit line or a bit line pair and amplify the signal carrying the bit information of the second memory cell.

The bit line sense amplifier/buffer BLSABF can be controlled by the propagation control signal BLISO and the sense or latch control signal SEN. Since the application is for moving a page of data at a time, where a page is defined as the data in all memory cells of the memory activated by the same word line, no row select lines or data lines are required. By sequentially activating adjacent bit line sense amplifier/buffer BLSABF blocks, the data present in the first bit line sense amplifier/buffer BLSABF is copied to the next sequential bit line sense amplifier/buffer BLSABF. In this embodiment, page data can be propagated from a source location to a target location in either direction perpendicular to the word line.

For example, by enabling BLSABF between a first memory cell array block and a second memory cell array block adjacent to the first memory cell array block, a plurality of voltages loaded onto a plurality of bit lines or bit line pairs of the first memory cell array block are latched, so that the plurality of latched voltages are propagated to a plurality of bit lines or bit line pairs in the second memory cell array block. A BLSABF between the second memory cell array block and a third memory cell array block adjacent to the second memory cell array block is used to latch a plurality of voltages on a plurality of bit lines or bit line pairs loaded to the second memory cell array block, so that the plurality of latched voltages are propagated to a plurality of bit lines or bit line pairs in the third memory cell array block (the third memory cell array block is different from the first memory cell array block and is adjacent to the second memory cell array block). Using the sequential activation BLSABF method in the embodiment, the voltage can be propagated from one memory cell array block to the subsequent adjacent memory cell array block in sequence until the target location is reached. The voltage can be loaded onto the bit line or bit line pair by activating the appropriate word line to read the source voltage, or the source voltage can be provided by the data access circuit 152.

Thus, a read operation may activate the word line of the source location, loading the plurality of voltages from the memory cells at the source location onto the corresponding bit lines or bit line pairs, which may be latched by activating the adjacent BLSABF. Then, whether the target location is the data access circuit 152 or another memory cell array block (when moving data), the voltages may be sequentially propagated from one memory cell array block to another adjacent memory cell array block until the target location is reached. Once the data has been moved to the bit line or bit line pair at the target location to store the data in the associated memory cell, a write operation requires activating the word line at the target location. Writing access to memory cells associated with word lines in a memory cell array block includes timing at which a data voltage signal is driven to a bit line or bit line pair prior to activating the associated word line.

Please continue to refer to FIG. 4, the bit line sense amplifier/buffer BLSABF includes a propagation control circuit 402 and a latch circuit 404. The propagation control circuit 402 is coupled to a bit line pair in a memory cell array block (such as a first memory cell array block) and a bit line pair in an adjacent memory cell array block (such as a second memory cell array block) adjacent to the memory cell array block. For example, when applied to a memory cell array with a differential bit line mechanism, the propagation control circuit 402 may be coupled to a bit line pair in a memory cell array block and a bit line pair in an adjacent memory cell array block adjacent to the memory cell array block. When applied to a memory cell array with a single bit line mechanism, the propagation control circuit 402 may be coupled to a bit line in a memory cell array block and a bit line in an adjacent memory cell array block adjacent to the memory cell array block. The propagation control circuit 402 is configured to transmit the data voltage signal in the memory cell array block to the bit line or bit line pair in the adjacent memory cell array block or transmit the data voltage signal in the adjacent memory block to the bit line or bit line pair in the memory block in response to a propagation control signal BLISO. The latch circuit 404 is coupled to the bit line or bit line pair in the memory block and/or the adjacent memory block, and is configured to respond to a sense or latch control signal SEN to sense the data voltage signal and latch the sensed and amplified data voltage signal, so that the sensed/amplified data voltage signal latched by the latch circuit 404 can be transmitted to the bit line or bit line pair in the adjacent memory block. In this way, the data voltage signal of the bit line that has been propagated to the second memory cell array block can be further transmitted to the third memory cell array block by utilizing the latch circuit of the bit line sense amplifier/buffer BLSABF between the second memory cell array block and the third memory cell array block. In addition, the bit line or bit line pairs in the first memory cell array block are precharged to a first supply voltage before the word line in the first memory cell array block is activated or before the data voltage signal is transmitted from the adjacent memory cell array block or the second memory cell array block through the propagation control circuit 402 associated with the bit line or bit line in the adjacent or second memory cell array block.

For example, when the propagation control signal BLISO of the bit line sense amplifier/buffer BLSABF is enabled, the propagation control circuit 402 is configured to sense the data voltage signal driven on the bit line or bit line pair of the memory cell array block during a propagation period, and transmit the sensed data voltage signal to the bit line or bit line pair of the adjacent memory cell array block. When the sense or latch control signal SEN of the bit line sense amplifier/buffer BLSABF is enabled, the latch circuit 404 of the bit line sense amplifier/buffer BLSABF is configured to latch the sensed and amplified data voltage signal during a sensing or latching period. In other words, through the signal sensing and buffering performed by the propagation control circuit 402 and the latch circuit 404 of the bit line sense amplifier/buffer BLSABF, the data voltage signal on the bit line or bit line pair of the memory cell array block can be transmitted to the bit line or bit line pair of the adjacent memory cell array block. In this way, the data voltage signal can be sequentially transmitted between a plurality of subsequent memory cell array blocks through a plurality of bit line sense amplifiers/buffers BLSABF between a plurality of subsequent memory cell array blocks.

In one embodiment, as shown in FIG. 4 , the propagation control circuit 402 includes transistors M1 and M2. Transistors M1 and M2 may be metal oxide semiconductor field effect transistors (MOS) or other devices having similar functions. For example, transistors M1 and M2 may be n-type MOS transistors (NMOS). The drains of transistors M1 and M2 are coupled to a bit line or a bit line pair of a memory cell of a first memory cell array block to transmit a data voltage signal. The gates of transistors M1 and M2 are controlled by the propagation control signal BLISO. The sources of transistors M1 and M2 are coupled to the bit lines of memory cells of a second memory cell array block adjacent to the first memory cell array block or the bit lines. In addition, when applied to a memory cell array with a differential bit line mechanism, transistors M1 and M2 of the propagation control circuit 402 can be coupled to the bit line pairs of the first memory cell array block and the second memory cell array block. When applied to a memory cell array with a single bit line mechanism, one of the transistors M1 and M2 of the transmission control circuit 402 may be coupled to the bit line of the first memory cell array block, and the other transistor of the transmission control circuit 402 may be coupled to the bit line of the second memory cell array block. When the propagation control signal BLISO of the bit line sense amplifier/buffer BLSABF is enabled, the bit line sense amplifier/buffer BLSABF is enabled, the sensing control of the bit line sense amplifier/buffer BLSABF is enabled and the propagation control circuit 402 is configured to sense the data voltage signal from the bit line of the first memory cell array block and transmit the sensed/amplified data voltage signal to the bit line of the second memory cell array block.

The latch circuit 404 includes transistors M3-M7. Transistors M3-M7 may be MOS transistors or other devices with similar functions. For example, transistors M3 and M5 may be p-type MOS transistors (PMOS). Transistors M4, M6 and M7 may be NMOS transistors. The sources of transistors M3 and M5 are coupled to a first supply voltage. The gate of transistor M3 is coupled to the gate of transistor M4. The drain of transistor M3 is coupled to the drain of transistor M4, the bit line of the first memory cell array block, and the drain/source of the MOS transistor coupled to the second memory cell array block in the propagation control circuit 402. The gate of transistor M5 is coupled to the gate of transistor M6 and the drain of transistor M3. The drain of transistor M5 is coupled to the drain of transistor M6, the gate of transistor M3, the bit line of the first memory cell array block, and the drain/source of the MOS transistor coupled to the second memory cell array block in the propagation control circuit 402. The source of transistor M6 is coupled to the source of transistor M4 and the drain of transistor M7. The gate of transistor M7 is controlled by the sense or latch control signal SEN. During a propagation period, the data voltage signal can be transmitted to the bit line of the second memory cell array block by the propagation control circuit 402. When the sense or latch control signal SEN of the bit line sense amplifier/buffer BLSABF is enabled, the latch circuit 404 of the bit line sense amplifier/buffer BLSABF can operate as a data buffer to send the data voltage signal to the bit line of the second memory cell array block. Thus, through the signal sensing and buffering performed by the bit line sense amplifier/buffer BLSABF, the data voltage signal on the bit line or bit line pair of the first memory cell array block can be transmitted to the bit line or bit line pair of the second memory cell array block adjacent to the first memory cell array block.

FIG. 5A is a schematic diagram of a page buffer 132 of the memory module 100 in FIG. 1. The page buffer 132 is coupled to a bit line or a bit line pair and an off-chip data interface. The page buffer 132 is configured to receive a data voltage signal from the coupled bit line or bit lines and output the data voltage signal to the off-chip data interface. The page buffer 132 is configured to store the data voltage signal from the off-chip data interface and transmit the data voltage signal to the coupled bit line or bit lines. As shown in FIG. 5A, the page buffer 132 includes a signal transmission control circuit 1322 and a buffer circuit 1324. The signal transfer control circuit 1322 is coupled to a bit line or a bit line pair connected to a bit line sense amplifier/buffer BLSABF. For example, the signal transfer control circuit 1322 is coupled to a bit line or a bit line connected to the last stage bit line sense amplifier/buffer BLSABF of the plurality of bit line sense amplifiers/buffers BLSABF. The signal transfer control circuit 1322 is configured to sense the data voltage signal from the coupled bit line sense amplifier/buffer BLSABF or transmit the data voltage signal to the coupled bit line sense amplifier/buffer BLSABF through the bit line or bit line of the coupled bit line sense amplifier/buffer BLSABF in response to a signal transfer control signal BLISO_U. The buffer circuit 1324 is coupled to the signal transfer control circuit 1322 and is configured to latch the sensed and amplified data voltage signal in response to a sense/latch control signal SEN_U.

For example, when the signal transfer control signal BLISO_U of the page buffer 132 is enabled, the signal transfer control circuit 1322 is configured to transfer the data voltage signal from the bit line or bit line pair of the last stage bit line sense amplifier/buffer BLSABF coupled to the buffer during a signal transfer period. The buffer circuit 1324 transmits the data voltage signal to the last stage bit line sense amplifier/buffer BLSABF among the plurality of bit line sense amplifiers/buffers BLSABF through a bit line or a bit line pair coupled to the last stage bit line sense amplifier/buffer BLSABF among the plurality of bit line sense amplifiers/buffers BLSABF. When the sense/latch control signal SEN_U of the page buffer 132 is activated, the buffer circuit 1324 is enabled and configured to latch the sensed and amplified data voltage signal in response to the sense/latch control signal SEN_U during a sense/latch period. In other words, through the signal sensing and buffering performed by the signal transmission control circuit 1322 and the buffer circuit 1324, the page buffer 132 can receive and sense the data voltage signal from the coupled bit line sense amplifier/buffer BLSABF through the bit line or bit line pair of the last stage bit line sense amplifier/buffer BLSABF among the plurality of bit line sense amplifiers/buffers BLSABF and store the data voltage signal. The page buffer 132 may also transmit the data voltage signal to the coupled bit line sense amplifier/buffer BLSABF via the bit line or bit line pair coupled to the last stage bit line sense amplifier/buffer BLSABF among the plurality of bit line sense amplifiers/buffers BLSABF.

In one embodiment, as shown in FIG. 5A , the signal transmission control circuit 1322 includes transistors M8 and M9. Transistors M8 and M9 may be MOS transistors or other devices having similar functions. For example, transistors M8 and M9 may be NMOS transistors. The drains of transistors M8 and M9 are coupled to the bit line or bit line pair of the last stage bit line sense amplifier/buffer BLSABF coupled to a plurality of bit line sense amplifiers/buffers BLSABF to transmit a data voltage signal. The gates of transistors M8 and M9 are controlled by the signal transmission control signal BLISO_U. The sources of transistors M8 and M9 are coupled to the buffer circuit 1324. For example, when the signal transfer control signal BLISO_U is enabled, the signal transfer control circuit 1322 is configured to sense the data voltage signal via the bit line of the last stage bit line sense amplifier/buffer BLSABF coupled to the plurality of bit line sense amplifiers/buffers BLSABF.

The buffer circuit 1324 includes transistors M10-M16 and an inverter 1326. Transistors M10-M16 may be MOS transistors. For example, transistors M10 and M12 may be PMOS transistors. Transistors M11 and M13-M16 may be NMOS transistors. The sources of transistors M10 and M12 are coupled to a first supply voltage. The gate of transistor M10 is coupled to the gate of transistor M11. The drain of transistor M10 is coupled to the drain of transistor M11. The gate of transistor M12 is coupled to the gate of transistor M13 and the drain of transistor M10. The drain of transistor M12 is coupled to the drain of transistor M13 and the gate of transistor M10. The source of transistor M13 is coupled to the source of transistor M11 and the drain of transistor M14. The gate of transistor M14 is controlled by the sense/latch control signal SEN_U. When the sense/latch control signal SEN_U is enabled, the buffer circuit 1324 can operate as a latch to transmit the data voltage signal sensed by the control circuit 1322 with the latch signal.

FIG. 6 is a schematic diagram of an embodiment of the data flow of the memory module 100 of the present invention. In FIG. 6, the memory cell array block is labeled as "CA block" and the bit line sense amplifier/buffer BLSABF block is labeled as "BLSABF block" for simplicity. As shown in FIG. 6, the bit line sense amplifier/buffer BLSABF block can be regarded as a data signal buffer or repeater between two adjacent memory cell array blocks. The data voltage signal may be sequentially propagated from a memory cell array block to a subsequent adjacent memory cell array block through a corresponding bit line sense amplifier/buffer BLSABF until reaching a target location. That is, the data voltage signal may be sequentially propagated between a plurality of subsequent memory cell array blocks through a plurality of bit line sense amplifiers/buffers BLSABF located between the subsequent memory cell array blocks. The page buffer may access data in the coupled bit line sense amplifier/buffer BLSABF or an off-chip data interface. The page buffer can receive the data voltage signal from the coupled bit line sense amplifier/buffer BLSABF block, and transmit and store the data voltage signal to the coupled bit line sense amplifier/buffer BLSABF block.

FIG. 7 is a schematic diagram of an embodiment of the inter-sectional page-data-copy method of the memory cell array block of the embodiment of the present invention. FIG. 8 is a schematic diagram of the operation signal waveforms of the memory cell array block, the bit line sense amplifier/buffer, and the page buffer of FIG. 7 of the embodiment of the present invention. The upper half of FIG. 7 shows a schematic diagram of a portion of the memory cell array block, and the memory cell array block is represented by a dotted line and is numbered 0-4. Each memory cell array block includes a word line, and FIG. 7 only shows the word line WL of one memory cell array block. A bit line sense amplifier/buffer BLSABF is disposed between every two memory cell array blocks, and each bit line sense amplifier/buffer BLSABF is connected to two adjacent memory cell array blocks through a bit line or a bit line pair. For example, the bit line sense amplifier/buffer BLSABF_0 is coupled to the bit line (bit line pair) BL_0 located in the memory cell array block 0 and is coupled to the bit line (bit line pair) BL_1 located in the memory cell array block 1, the bit line sense amplifier/buffer BLSABF_1 is coupled to the bit line (or bit line pair) BL_1 in the bit line (bit line pair) in the memory cell array block 1 and is coupled to the bit line (or bit line pair) BL_2 in the memory cell array block 2, and so on. The page buffer 132 is coupled to the bit line sense amplifier/buffer BLSABF_3 through the bit line (bit line pair) BL_4 in the memory cell array block 4. Each of the bit line sense amplifiers/buffers BLSABF_0-BLSABF_3 has a similar structure, operation, and function to the bit line sense amplifier/buffer BLSABF shown in FIG. 4. The page buffer 132 has a similar structure, operation, and function to the page buffer 132 shown in FIG. 5A.

Please continue to refer to FIG. 7 and FIG. 8. At time T0, the word line WL associated with the memory cell array block 0 is activated, and then a voltage signal is generated on the bit line (or bit line pair) in the memory cell array block 0. At time T1, the propagation control signal BLISO_0 of the bit line sense amplifier/buffer BLSABF_0 is enabled (for example, BLISO_0 is VDD), and then the sense control of the bit line sense amplifier/buffer BLSABF_0 is enabled, and the propagation control circuit of the bit line sense amplifier/buffer BLSABF_0 is configured to transmit the data voltage signal The data voltage signal is transmitted from the memory cell of the memory cell array block 0 coupled to the word line WL to the bit line BL_0 (or the bit line pair BL_0/BLf_0) of the memory cell array block 0, and during a first propagation period (e.g., time T1 to time T3), the data voltage signal is transmitted from the bit line BL_0 (or the bit line pair BL_0/BLf_0) of the memory cell array block 0 to the bit line BL_0 (or the bit line pair BL_0/BLf_0) of the memory cell array block 0. The data voltage signal is transmitted to the bit line BL_1 (or the bit line pair BL_1/BLf_1) of the memory cell array block 1, and then the data voltage signal is sensed/amplified, and the sensed/amplified data voltage signal is transmitted to the bit line BL_1 (or the bit line pair BL_1/BLf_1) of the memory cell array block 1. At time T2, the sense or latch control signal SEN_0 of the bit line sense amplifier/buffer BLSABF_0 is enabled (for example, SEN_0 is VDD), and the latch circuit of the bit line sense amplifier/buffer BLSABF_0 is configured to sense/amplify/latch the data voltage signal during a first sensing or latching period (for example, time T2 to time T5). During the first sensing or latching period, the bit line sense amplifier/buffer BLSABF_0 is enabled, the data voltage signal is transmitted from the bit line BL_0 (or the bit line pair BL_0/BLf_0) of the memory cell array block 0 to the bit line BL_1 (or the bit line pair BL_1/BLf_1) of the memory cell array block 1, and the sensed/amplified data voltage signal on the bit line BL_0 (or the bit line pair BL_0/BLf_0) is latched into the latch circuit of the bit line sense amplifier/buffer BLSABF_0. Thus, the page data is read from the memory cell of the open word line WL, and the page data is copied from the memory cell array block 0 to the bit line sense amplifier/buffer BLSABF_0 for use by the memory cell array block 0 and the memory cell array block 0 (indicated by the circled number 1 in FIG. 7 ).

At time T4, the propagation control signal BLISO_1 of the bit line sense amplifier/buffer BLSABF_1 is enabled (e.g., BLISO_1 is VDD), and the sensing control of the bit line sense amplifier/buffer BLSABF_1 is enabled. The sensing control of the bit line sense amplifier/buffer BLSABF_1 starts before the first sensing or latching period of the bit line sense amplifier/buffer BLSABF_0 ends. Since the sense or latch control signal SEN_0 is maintained in an active state at time T4, the latch circuit of the bit line sense amplifier/buffer BLSABF_0 still latches the sensed/amplified data voltage signal, so that the data voltage signal loaded on the bit line BL_1 (or the bit line pair BL_1/BLf_1) of the memory cell array block 1 is driven by the latch circuit of the bit line sense amplifier/buffer BLSABF_0. The propagation control circuit of the bit line sense amplifier/buffer BLSABF_1 is configured to transmit the data voltage signal loaded on the bit line BL_1 (or the bit line pair BL_1/BLf_1) of the memory cell array block 1 and driven by the latch circuit of the bit line sense amplifier/buffer BLSABF_0 to the bit line BL_2 (or the bit line pair BL_2/BLf_2) of the memory cell array block 2 during a second propagation period (e.g., time T4 to time T6). The start point (e.g., time T4) of the second propagation period is later than the first propagation period and earlier than the end point of the first sensing or latching period of the bit line sense amplifier/buffer BLSABF_0. In addition, the bit line (or bit line pair) of the memory cell array block 0 may be precharged to a first supply voltage before the word line WL in the memory cell array block 0 is activated and after the first propagation period. The bit line (or bit line pair) of the memory cell array block 1 may be precharged to the first supply voltage before the first sense or latch period and after the second propagation period.

At time T5, the sensing or latching control signal SEN_1 of the bit line sense amplifier/buffer BLSABF_1 is enabled (eg, SEN_1 is VDD), and the latching circuit of the bit line sense amplifier/buffer BLSABF_1 is configured to latch the sensed/amplified data voltage signal during a second sensing or latching period (eg, time T5 to time T8). During the second sensing or latching period, the bit line sense amplifier/buffer BLSABF_1 is enabled, the data voltage signal is transmitted from the bit line BL_1 (or the bit line pair BL_1/BLf_1) of the memory cell array block 1 to the bit line BL_2 (or the bit line pair BL_2/BLf_2) of the memory cell array block 2, and the sensed/amplified data voltage signal on the bit line BL_1 (or the bit line pair BL_1/BLf_1) is latched into the latching circuit of the bit line sense amplifier/buffer BLSABF_1. Therefore, the page data is copied from the memory cell array block 1 to the bit line sense amplifier/buffer BLSABF_1 for use by the memory cell array block 1 and the memory cell array block 2 (indicated by the circled number 2 in FIG. 7 ).

At time T7, the propagation control signal BLISO_2 of the bit line sense amplifier/buffer BLSABF_2 is enabled (for example, BLISO_2 is VDD). The propagation control circuit of the bit line sense amplifier/buffer BLSABF_2 is configured to sense the data voltage signal loaded on the bit line BL_2 (or the bit line pair BL_2/BLf_2) of the memory cell array block 2 and driven by the latch circuit of the bit line sense amplifier/buffer BLSABF_1 during a third propagation period (for example, time T7 to time T9), and transmit the sensed data voltage signal to be loaded on the bit line BL_3 (or the bit line pair BL_3/BLf_3) of the memory cell array block 3. At time T8, the sensing or latching control signal SEN_2 of the bit line sense amplifier/buffer BLSABF_2 is enabled (eg, SEN_2 is VDD), and the latching circuit of the bit line sense amplifier/buffer BLSABF_2 is configured to latch the sensed/amplified data voltage signal during a third sensing or latching period (eg, time T8 to time T11). The bit line sense amplifier/buffer BLSABF_2 is enabled, and the page data is copied from the memory cell array block 2 to the bit line sense amplifier/buffer BLSABF_2 for use by the memory cell array block 2 and the memory cell array block 3 (indicated by the circled number 3 in FIG. 7 ).

At time T10, the propagation control signal BLISO_3 of the bit line sense amplifier/buffer BLSABF_3 is enabled (for example, BLISO_3 is VDD). The propagation control circuit of the bit line sense amplifier/buffer BLSABF_3 is configured to sense the data voltage signal loaded on the bit line BL_3 (or the bit line pair BL_3/BLf_3) of the memory cell array block 3 and driven by the latch circuit of the bit line sense amplifier/buffer BLSABF_2 during a fourth propagation period (for example, time T10 to time T12), and transmit the sensed data voltage signal to be loaded on the bit line BL_4 (or the bit line pair BL_4/BLf_4) of the memory cell array block 4. At time T11, the sensing or latching control signal SEN_3 of the bit line sense amplifier/buffer BLSABF_3 is enabled (eg, SEN_3 is VDD), and the latching circuit of the bit line sense amplifier/buffer BLSABF_3 is configured to latch the sensed/amplified data voltage signal during a fourth sensing or latching period (eg, time T11 to time T14). The bit line sense amplifier/buffer BLSABF_3 is enabled, and the page data is copied from the memory cell array block 3 to the bit line sense amplifier/buffer BLSABF_3 for use by the memory cell array block 3 and the memory cell array block 4 (indicated by the circled number 4 in FIG. 7 ).

In addition, the bit line (or bit line pair) of the memory cell array block 2 may be precharged to the first supply voltage before the second sensing or locking period and after the third propagation period. The bit line (or bit line pair) of the memory cell array block 3 may be precharged to the first supply voltage before the third sensing or locking period and after the fourth propagation period. The bit line (or bit line pair) of the memory cell array block 4 may be precharged to the first supply voltage before the fourth sensing or locking period.

At time T13, the signal transfer control signal BLISO_U of the page buffer 132 is enabled (e.g., BLISO_U is VDD). The signal transfer control circuit of the page buffer 132 is configured to sense the data voltage signal loaded on the bit line BL_4 (or the bit line pair BL_4/BLf_4) of the memory cell array block 4 and driven by the latch circuit of the bit line sense amplifier/buffer BLSABF_3 during a signal transfer period (e.g., time T13 to time T15). At time T14, the sense/latch control signal SEN_U of the page buffer 132 is enabled (e.g., SEN_U is VDD), and the buffer circuit of the page buffer 132 is configured to latch the sensed/amplified data voltage signal during a sense/latch period (e.g., time T14 to time T16). The page buffer 132 is enabled, and the page data is copied from the memory cell array block 4 to the page buffer 132. Therefore, through the signal sensing and buffering performed by the bit line sense amplifier/buffer BLSABF_0-BLSABF_3, the data voltage signal on the bit line or bit line pair of the memory cell array block 0 can be sequentially transmitted through the bit line sense amplifier/buffer BLSABF_0, the memory cell array The data is transmitted to the page buffer 132 through the column block 1, the bit line sense amplifier/buffer BLSABF_1, the memory cell array block 2, the bit line sense amplifier/buffer BLSABF_2, the memory cell array block 3, the bit line sense amplifier/buffer BLSABF_3 and the memory cell array block 4.

Please continue to refer to FIG. 5A , the page buffer module 130 further includes a logic operation processing circuit 134 coupled to the page buffer 132. The logic operation processing circuit 134 is configured to receive a data voltage signal (hereinafter referred to as page copy access data) latched in the page buffer 132, receive the data voltage signal, and perform a one-bit multiplication operation on the page copy access data. The logic operation processing circuit 134 includes a source transistor M17 and transistors M18_a-M18_d. The source transistor M17 and the transistors M18_a-M18_d can be MOS transistors or other devices with similar functions. For example, the source transistor M17 and the transistors M18_a-M18_d may be PMOS or NMOS transistors. The control end of the source transistor M17 is coupled to the page buffer 132. The transistors M18_a to M18_d are connected in parallel. The number of parallel transistors may be varied and designed according to the needs of the actual system. The control end of the source transistor M17 is coupled to the page buffer 132. The transistors M18_a-M18_d are connected in parallel to each other. The first ends of the transistors M18_a-M18_d are coupled to the first end of the source transistor M17. The control ends of the transistors M18_a-M18_d are respectively coupled to the selection signals X0-X3. The second ends of transistors M18_a-M18_d are respectively coupled to data bit lines DL_a-DL_d. When a data voltage signal (hereinafter referred to as page copy access data) is latched in the buffer circuit 1324 of the page buffer 132, the latched data (page copy access data) can be transferred to the control of the source transistor M17. When the source transistor M17 and the transistors M18_a-M18_d coupled to the source transistor M17 are all turned on (in the "ON" state), each of the transistors M18_a-M18_d coupled to the source transistor M17 can absorb current. According to such an operation method, it can be used as a component for bit operation. Furthermore, by controlling the selection signals X0-X3, the logic operation processing circuit 134 can output the bit multiplication result.

Memory cell array blocks near the page buffer can be designated as cache memory for fast access to arithmetic operations. Each memory cell array includes a column decoder (and a row decoder) coupled to the memory cell array. Through a predetermined decoding sequence of the decoder, the bit multiplication operation result can be completed in the logic operation processing circuit 134, for example, it can be part of the arithmetic/logic operation combined with the logical operation to complete in the convolution neural network.

The present embodiment can access the data page from the top of the memory cell array using a page copy method and store it in a page buffer adjacent to the logic operation processing circuit 134. The logic operation processing circuit 134 can process the conditional access data stored in the page buffer and store the result in another page buffer. Afterwards, the stored result data is stored in the memory cell array using a page copy method, and the present embodiment can repeat the data stream as many times as needed to complete the processing of the localized data stream without any long-distance data transmission.

The above-described conditional access data flow aims to further reduce data transmission, energy consumed by data movement, and complexity by using addition instead of multiplication in each layer of processing, as shown in FIG. 5A , which can be accomplished by using a page buffer.

FIG. 5B is a schematic diagram of the embodiment of the present invention in which the results of the operations of multiple single-bit multiplication by single-bit method are permuted and added to obtain an equal result when multiplying vectors. The sum of Xi*Wj is required, and Xi*Wj represents the product of Xi and Wj. The embodiment of the present invention can copy the data accumulated by the logic operation processing circuit 134 as the multiplication result to the page buffer of the original processing block or the page buffer in the adjacent processing block. Since data transmission accounts for 90% to 99% of the power consumed by the convolutional neural network, this method of combining parallel page copying with conditional access can significantly save power.

In short, conditionally accessing data includes accessing Xi by activating a selection bit represented as Wi (page data stored in a row of the memory cell array), so that the accessed data is Xi*Wj (i.e., Xi AND Wj) instead of the original Xi, and the sum of the conditionally accessed data Xi*Wj is equal to the product of two vectors X and W in a specific arrangement. In addition, conditionally accessing data includes accessing Xi (page data stored in a row of the storage cell array) by activating multiple selection bits (Wj, Wj+1, Wj+2,...). The result can be expressed as (Xi*Wj, Xi*Wj+1, Xi*Wj+2,...), and the sum of these conditionally accessed data in a specific arrangement is equal to the product of two vectors X and W.

FIG9A and FIG9B are schematic diagrams showing an embodiment of data copying between memory blocks and between improved memory cell array blocks in a conventional open bit line array architecture. In the conventional open bit line array shown in FIG9A, since the open bit line structure cannot copy data all the time, the disclosed data copying method cannot be continuously transferred beyond two memory cell array blocks (e.g., from memory cell array block 2 to memory cell array block 3 in FIG9A). To solve this problem, FIG. 9B shows a structural modification of an open bit line array to form an electrical link connecting the first bit line and the second bit line in each memory cell array block. The modification of FIG. 9B ensures that the subsequent bit line sense amplifier/buffer BLSABF and memory cell array block in the memory can continue to use the data of the previous bit line sense amplifier/buffer BLSABF. FIG. 9C shows a schematic diagram of an embodiment of data replication in a 1T1C cell array (modified from a conventional 1T1C open bit line array).

FIG. 10 is a schematic diagram showing an embodiment of another possible page copy structure modification of the open bit line array. In FIG. 10, each bit line sense amplifier/buffer BLSABF is connected to a plurality of transistors (four transistors in the embodiment of FIG. 10), each transistor having a first end, a second end, and a control end. FIG. 10 shows that the first bit line in the memory block is sequentially connected in series with the first end of the first transistor, the second end of the first transistor, the first node, the first end of the second transistor, the second end of the second transistor, and the first bit line in the adjacent memory portion. The second bit line in the memory block is sequentially connected in series with the first end of the third transistor, the second end of the third transistor, the second node, the first end of the fourth transistor, the second end of the fourth transistor, and the second bit line in the adjacent memory portion. The bit line sense amplifier/buffer BLSABF is coupled to the first node and the second node. Each of the four transistors can be controlled to electrically connect the bit line sense amplifier/buffer BLSABF to a bit line (or bit line pair) in an adjacent memory cell array block to ensure propagation of the required data voltage.

FIG. 11 shows an embodiment of the operation of data copying in an embodiment of an open bit line array, so that page data moves inter-sectionally between memory blocks. In FIG. 11, time increases from the top to the bottom of the figure, and data is copied from left to right as time passes. In FIG. 11, after the bit line (or bit line pair) of cell array block 2 is precharged, the word line of cell array block 2 is activated, data is read and amplified from the memory cell, and data A (labeled "A" in the figure) is latched into the appropriate bit line sense amplifier/buffer BLSABF, and the word line is then closed. When the subsequent bit line sense amplifier/buffer BLSABF is activated, data A is copied from the current bit line sense amplifier/buffer BLSABF to the subsequent bit line sense amplifier/buffer BLSABF. The activation process of the bit line sense amplifier/buffer BLSABF continues, transferring data A from one bit line sense amplifier/buffer BLSABF to the next bit line sense amplifier/buffer BLSABF until it reaches the target position.

Some benefits of this page duplication method include:

1. Access to memory data can reach the maximum data prefetch amount that the memory array can provide;

2. The second-stage sense amplifier (called the data line readout amplifier) can be omitted to save power consumption of unnecessary row select decoders;

3. Power savings due to the inherent low voltage transition mode of the bit line (or bit line pair); and

4. Comply with the BL-before-WL page data writing method to achieve very fast and low-power data writing.

FIG. 12 illustrates the application of array data access on chip peripherals to achieve long-distance, wide-bus and high-performance data movement.

FIG. 12 is similar in notation to FIG. 11 except that FIG. 12 shows the voltage signal propagating across the data buffer of the peripheral device.

In summary, the scheme of the embodiment of the present invention can be applied to a page data write access method in a memory chip, wherein page data can be sequentially propagated from a memory cell array block to subsequent adjacent memory blocks until reaching a target location, and then the word lines in the memory cell array block including the target location are activated to write the data voltage into the memory cell at the target location. In other words, through the sensing and buffering of the bit line sense amplifier/buffer and the page buffer, the page data can be sequentially propagated from the memory block/page buffer to the page buffer/memory block based on the page data replication method, thereby effectively improving the energy efficiency of data movement in the memory module and the accompanying operation logic capabilities. The above is only a preferred embodiment of the present invention, and all equal changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

100: memory module 101: memory bank 102: secondary semiconductor chip 110: word line decoder 120: memory cell array 130: page buffer module 132: page buffer 1322: signal transmission control circuit 1324: buffer circuit 1326: inverter 134: logic operation processing circuit 150: peripheral circuit 152: access circuit 402: transmission control circuit 404: lock circuit A, P, Z: data BL,BL_0,BL_1,BL_2,BL_3,BL_4,BLB,BL(1),BL(2),BL(N),DL_a,DL18_b,DL18_c,DL_d: bit lines BLISO,BLISO_0,BLISO_1,BLISO_2,BLISO_3: propagation control signals BLISO_U: signal transmission control signals BLSABF,BLSABF_0,BLSABF_1,BLSABF_2,BLSABF_3: bit line sense amplifier/buffer Cap: capacitor M1-M16,M18_a,M18_b,M18_c,M18_d,Q1-Q6: transistors M17: source transistors SEN,SEN_0,SEN_1,SEN_2,SEN_3: sense or latch control signals SEN_U: Sense/Lock control signal T0-T16: Time WL, WL(1), WL(2), WL(M): Word line X0-X3: Select signal

FIG. 1 is a schematic diagram of a device for enhancing data access in a memory module in an embodiment of the present invention. FIG. 2 is a schematic diagram of a plurality of memory cell array blocks and a plurality of bit line sense amplifiers/buffers alternately arranged in an embodiment of the present invention. FIG. 3A is a schematic diagram of an embodiment of a 1T1C DRAM memory cell of the memory module in FIG. 1. FIG. 3B is a schematic diagram of an embodiment of a 6T SRAM memory cell of the memory module in FIG. 1. FIG. 4 is a schematic diagram of a bit line sense amplifier/buffer of the memory module in FIG. 1. FIG. 5A is a schematic diagram of a page buffer of the memory module in FIG. 1. FIG. 5B is a schematic diagram showing that when vectors are multiplied in an embodiment of the present invention, the positions of the results of multiple one-bit multiplication operations can be swapped and added to obtain an equal result. FIG. 6 is a schematic diagram showing an embodiment of the data flow of the memory module in an embodiment of the present invention. FIG. 7 is a schematic diagram showing an embodiment of the page data copying method between memory blocks (inter-section) in an embodiment of the present invention. FIG. 8 is a schematic diagram showing the operation signal waveforms of the memory cell array block, bit line sense amplifier/buffer, and page buffer in FIG. 7 of the embodiment of the present invention. FIG. 9A shows an embodiment of the memory block in a traditional open bit line array architecture. FIG. 9B is a schematic diagram showing an embodiment of data replication in a 2T2C cell array (modified from a conventional 1T1C open bit line array). FIG. 9C is a schematic diagram showing an embodiment of data replication in a 1T1C cell array (modified from a conventional 1T1C open bit line array). FIG. 10 is a schematic diagram showing another embodiment of data replication in a 1T1C cell array (modified from a conventional 1T1C open bit line array). FIG. 11 is a schematic diagram showing an operation of data replication in an open bit line array. FIG. 12 is a schematic diagram showing an application of an array data access method to a chip peripheral device.

100:Memory module

101: Memory Bank

102: Secondary semiconductor chip

110: Character line decoder

120: Memory cell array

130: Page buffer module

132: Page buffer

150: Peripheral circuits

152: Access circuit

BL(1),BL(2),BL(N):bit line

WL(1),WL(2),WL(M): character line

Claims (21)

A device for copying, moving and accessing page data, the device comprising: A memory cell array, divided into a plurality of memory blocks, each memory block comprising a plurality of memory cells divided into a plurality of pages, wherein the memory cells of each page are collectively referred to as memory cells coupled to the same corresponding word line; A plurality of bit-line sense amplifiers/buffers (bit-line A sense-amplifier/buffer (BLSABF) is coupled to a memory cell array via a plurality of bit lines or bit line pairs. Each bit line sense amplifier/buffer is coupled to two bit lines or bit line pairs in two different memory blocks located on two opposite sides thereof. The data voltage on the bit line or bit line pair in a memory block The signal is transmitted to the bit line or bit line pair in an adjacent memory block adjacent to the memory block through the signal sensing and buffering performed by the plurality of bit line sense amplifiers/buffers, and the data voltage signal is sequentially transmitted between the plurality of subsequent memory blocks through the bit line sense amplifiers/buffers coupled to two adjacent memory blocks in the subsequent memory blocks; A plurality of page buffers, coupled to all or part of the plurality of bit line sense amplifiers/buffers, configured to receive the data voltage signal from the coupled bit line sense amplifiers/buffers to a data interface of the device, or configured to store the data voltage signal from the data interface of the device to the coupled bit line sense amplifiers/buffers; and A logic operation processing circuit, coupled to the plurality of page buffers, configured to receive the data voltage signal from the plurality of page buffers and perform a one-bit multiplication operation on the data voltage signal. The device as claimed in claim 1, wherein the memory cell array comprises static random access memory, dynamic random access memory, flash memory, magnetoresistive random access memory, ferroelectric random access memory or variable resistance memory. The device as described in claim 1, wherein each bit line sense amplifier/buffer of the plurality of bit line sense amplifiers/buffers comprises: A propagation control circuit coupled to a bit line or bit line pair in the memory block and a bit line or bit line pair in the adjacent memory block adjacent to the memory block, and configured to respond to a propagation control signal to transmit a data voltage signal in the memory block to the bit line or bit line pair in the adjacent memory block and to transmit a data voltage signal in the adjacent memory block to the bit line or bit line pair in the memory block; and A latch circuit is coupled to the bit line or bit line pair in the memory block and the adjacent memory block and is configured to respond to a sense or latch control signal to sense the data voltage signal and latch the sensed and amplified data voltage signal. The device of claim 3, wherein a word line is activated, a sensing control of a first bit line sense amplifier/buffer of the plurality of bit line sense amplifiers/buffers is enabled, and the first bit line sense amplifier/buffer is configured to sense the data voltage signal from a memory cell coupled to the word line to a bit line or bit line pair in a first memory block associated with the first bit line sense amplifier/buffer during a first propagation period, and then The sensed and amplified data voltage signal is transmitted to a bit line or a bit line pair in a second memory block adjacent to the first bit line sense amplifier/buffer via the propagation control circuit of the first bit line sense amplifier/buffer, and a latch circuit of the first bit line sense amplifier/buffer is configured to latch the sensed and amplified data voltage signal in response to a first sensing or latching control signal during a first sensing or latching period. A device as described in claim 4, wherein the starting point of the first sensing or latching period is during the first propagation period, and the data voltage signal has been transmitted to the bit line or bit line pair in the second memory block during the first propagation period. A device as described in claim 4, wherein the bit line or bit line pair in the first memory block is precharged to a first supply voltage before a word line in the first memory block is activated or before the data voltage signal is transmitted from an adjacent memory block or the second memory block through the propagation control circuit associated with the bit line or bit line in the adjacent memory block or the second memory block. A device as described in claim 4, wherein during a second propagation period, a propagation control circuit of a second bit line sense amplifier/buffer is enabled to transmit the data voltage signal driven by the sensing or latching circuit of the first bit line sense amplifier/buffer to a bit line or bit line pair of a memory cell in a third memory block adjacent to the first and second memory cells, and a latching circuit of the second bit line sense amplifier/buffer is enabled and configured to respond to a second sensing or latching control signal during a second sensing or latching period to sense and latch the sensed and amplified data voltage signal on the bit line or bit line pair in the second memory block. A device as described in claim 5, wherein the starting point of the second propagation period is before the end of the first sensing or locking period, at which time the data voltage signal has been transmitted to the bit line or the bit line pair of the second memory block and a second data sensing starts before the end of the first sensing or locking period, and the starting point of the second sensing or locking period is between the second propagation cycle and after the first propagation period. A device as described in claim 7, wherein the bit line or bit line pair in the second memory block is precharged to a first supply voltage before a word line in the second memory block is activated or before a data voltage signal is transmitted from an adjacent memory block through the bit line in the adjacent memory block or the propagation control circuit associated with the bit line. The device as claimed in claim 2, wherein each transmission control circuit comprises: A first transistor or transistor pair, comprising a first terminal or terminal pair coupled to the bit line or the bit line of the memory cell of the memory block and configured to transmit the data voltage signal, a control terminal or terminal pair controlled by the transmission control signal, and a second terminal or terminal pair coupled to the bit line or the bit line of the memory cell of the adjacent memory block. The device as described in claim 2, wherein each latch circuit comprises: a second transistor comprising a first terminal coupled to a first supply voltage, a control terminal, and a second terminal; a third transistor comprising a first terminal coupled to the second terminal of the second transistor, a control terminal coupled to the control terminal of the second transistor, and a second terminal; a fourth transistor comprising a first terminal coupled to the first supply voltage, a control terminal coupled to the second terminal of the second transistor and the first terminal of the third transistor, and a second terminal coupled to the control terminals of the second transistor and the third transistor, wherein at least one of the second terminal of the second transistor and the second terminal of the fourth transistor is coupled to the bit line or the bit line pair of the memory cell of the adjacent memory block; A fifth transistor, including a first end coupled to the second end of the fourth transistor and the control end of the second transistor, a control end coupled to the control end of the fourth transistor, and a second end; and A sixth transistor, including a first end coupled to the second end of the third transistor and the fifth transistor, a control end controlled by the sensing or latching control signal, and a second end. The device as claimed in claim 1, wherein each of the plurality of page buffers comprises: a signal transfer control circuit coupled to a bit line or a bit line pair of a bit line sense amplifier/buffer and configured to respond to a signal transfer control signal to sense a data voltage signal from the coupled bit line sense amplifier/buffer or transmit the data voltage signal to the coupled bit line sense amplifier/buffer; and a buffer circuit coupled to the signal transfer control circuit and configured to respond to a sense/latch control signal to latch the sensed and amplified data voltage signal. A device as described in claim 12, wherein the signal transfer control circuit is enabled and configured to transmit the data voltage signal from the last stage of the plurality of bit line sense amplifiers/buffers in response to the signal transfer control signal during a signal transfer period or to transmit the data voltage signal to the last stage of the plurality of bit line sense amplifiers/buffers via the bit line or the bit line pair coupled to the last stage of the plurality of bit line sense amplifiers/buffers, and the buffer circuit is enabled and configured to latch the sensed and amplified data voltage signal in response to the sensing/latch control signal during a sensing/latch period. The device of claim 12, wherein the signal transfer control circuit is enabled and configured to transfer the data voltage signal from the buffer circuit to the last stage of the plurality of bit line sense amplifiers/buffers during a signal transfer period. A device as described in claim 13, wherein the sensing/locking period overlaps with the signal transmission period. A device as described in claim 13, wherein the bit line or the bit line pair coupled to the last stage of the plurality of bit line sense amplifiers/buffers is precharged to a first supply voltage before the sensing/locking period begins or before the data voltage signal is transmitted from an adjacent memory block via the signal transfer circuit associated with the bit line or the bit line coupled to the last stage of the plurality of bit line sense amplifiers/buffers. The device as claimed in claim 12, wherein the signal transmission control circuit comprises: A seventh transistor or transistor pair, comprising a first terminal or terminal pair, coupled to the bit line or the bit line of the last stage of the plurality of bit line sense amplifiers/buffers and configured to transmit the data voltage signal, a control terminal or terminal pair, controlled by the signal transmission control signal, and a second terminal or terminal pair. The device as described in claim 17, wherein the buffer circuit comprises: an eighth transistor, comprising a first end coupled to a first supply voltage, a control end, and a second end; a ninth transistor, comprising a first end coupled to the second end of the eighth transistor, a control end coupled to the control end of the eighth transistor, and a second end; a tenth transistor, comprising a first end coupled to the first supply voltage, a control end coupled to the second end of the eighth transistor and the first end of the ninth transistor, and a second end coupled to the control ends of the eighth transistor and the ninth transistor, wherein at least one of the second end of the eighth transistor and the second end of the tenth transistor is coupled to the second end or terminal pair of the seventh transistor or transistor pair; An eleventh transistor, comprising a first end coupled to the second end of the tenth transistor, a control end coupled to the control end of the tenth transistor and a second end; A twelfth transistor, comprising a first end coupled to the ninth transistor and the second end of the eleventh transistor, a control end controlled by the sensing/latch control signal, and a second end; A thirteenth transistor, comprising a first end coupled to the second end of the eighth transistor, a control end, and a second end; A fourteenth transistor, comprising a first end coupled to the second end of the tenth transistor, a control end, and a second end; and An inverter, comprising an input end coupled to the second end of the fourteenth transistor, and an output end coupled to the second end of the thirteenth transistor. A device as described in claim 1, wherein write access to data to a memory cell associated with a word line in a memory block includes a timing at which a data voltage signal is driven to a bit line or a bit line pair before activating the associated word line. The device as described in claim 1, wherein the logic operation processing circuit includes: a source transistor, including: a first end, a control end, coupled to a page buffer, and a second end; and a plurality of fifteenth transistors connected in parallel with each other, wherein each fifteenth transistor includes a first end, a second end and a control end, wherein the first end of the plurality of fifteenth transistors is coupled to the first end of the source transistor. A device as described in claim 20, wherein the data voltage signal latched in the page buffer is transmitted to the control end of the source transistor, and when the source transistor and the plurality of fifteenth transistors are both turned on, the plurality of fifteenth transistors connected to the source transistor absorb current.

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