TW202407782A - Method of forming protective layer utilized in silicon remove process - Google Patents

Abstract

A method of forming a protective layer utilized in a silicon remove process includes bonding a first wafer to a second wafer, wherein the first wafer comprises a first silicon substrate with a first device structure disposed thereon and the second wafer comprises a second silicon substrate with a second device structure disposed thereon. After that, a first trim process is performed to thin laterally an edge of the first wafer and an edge of the second device structure. After the first trim process, a protective layer is formed to cover a back side of the second silicon substrate. After forming the protective layer, a silicon remove process is performed to remove only the first silicon substrate.

Description

A method of forming a protective layer for silicon removal process

The present invention relates to a manufacturing method for forming a protective layer, and in particular to a manufacturing method for forming a protective layer for a silicon removal process.

Wafer bonding is a process that connects a component wafer to another component wafer or handles a wafer so that it can be processed.

Wafer bonding provides wafer-level packaging of semiconductor devices and is used in a variety of technologies, including 3D integrated circuits (ICs), wafer-scale packaging (CSP) components, and microelectromechanical systems (MEMS). Advantages of using wafer bonding include enhanced electrical properties, providing higher density, reducing device size, lowering costs, and allowing additional testing at the wafer level.

Semiconductor wafer manufacturing uses very complex wafer processing procedures and complex manufacturing systems. To reduce the size of semiconductor packages, manufacturers have reduced component dimensions including wafer thickness. However, in traditional manufacturing processes, when the thickness of part of a component wafer is removed, the surface of another component wafer will be damaged.

In view of this, the present invention provides a protective layer used in a silicon removal process to prevent the surface of the device wafer from being damaged.

According to a preferred embodiment of the present invention, a method for forming a protective layer for a silicon removal process includes first bonding a first wafer to a second wafer, wherein the first wafer includes a first silicon The substrate and a first device structure, the first device structure is disposed on the first silicon substrate, the second wafer includes a second silicon substrate and a second device structure, the second device structure is disposed on the second silicon substrate, and then A first trimming process is performed. The first trimming process includes thinning an edge of the first wafer and an edge of the second device structure along the lateral direction. Then, after the first trimming process, a protective layer is formed, and the protective layer covers the second component structure. On a back side of the second silicon substrate, after the protective layer is formed, a silicon removal process is performed. The silicon removal process includes removing only the first silicon substrate.

In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the following describes the preferred embodiments in detail with reference to the accompanying drawings. However, the following preferred embodiments and drawings are only for reference and illustration, and are not intended to limit the present invention.

Figures 1 to 7 illustrate a method of forming a protective layer for a silicon removal process according to a preferred embodiment of the present invention.

As shown in Figure 1, a first wafer 10 and a second wafer 20 are provided. The first wafer 10 includes a first silicon substrate 14 and a first device structure 12. The first silicon substrate 14 includes a first A front side 14a and a first back side 14b, the first front side 14a and the first back side 14b are opposite, the first element structure 12 is disposed on and contacts the first front side 14a of the first silicon substrate 14, the first element structure 12 includes an interlayer dielectric Component 12a, dielectric layer 12b and transistor (not shown).

Similarly, the second wafer 20 includes a second silicon substrate 24 and a second device structure 22. The second silicon substrate 24 includes a second front side 24a and a second back side 24b. The second front side 24a and the second back side 24b. In contrast, the second device structure 22 is disposed on and in contact with the second front surface 24a of the second silicon substrate 24. The second device structure 22 includes an interlayer dielectric device 22a, a dielectric layer 22b and a transistor (not shown). According to another preferred embodiment of the present invention, the first wafer 10 may be a handling wafer made of silicon. Continuing the steps of Figure 1, at this time, the first back surface 14b of the first silicon substrate 14 and the second back surface 24b of the second silicon substrate 24 are exposed. Specifically, the first back surface 14b and the second back surface of the first silicon substrate 14 are exposed. The second backside 24b of the silicon substrate 24 does not contact silicon nitride or silicon oxide.

Next, the first wafer 10 is bonded to the second wafer 20 . The first wafer 10 and the second wafer 20 may be bonded by bonding the upper surface of the first element structure 12 to the upper surface of the second element structure 22 . surface. For example, the bonding method may include bonding the interlayer dielectric component 12a of the first component structure 12 to the interlayer dielectric component 22a of the second component structure 22. There may be metal between the interlayer dielectric component 12a and the interlayer dielectric component 22a. Metal-to-metal bonding (e.g. copper-to-copper bonding). Alternatively, the bonding method may include bonding the dielectric layer 12b of the first device structure 12 to the dielectric layer 22b of the second device structure 22. The dielectric layer 12b and the dielectric layer 22b may be oxide-to-oxide bonded.

As shown in FIG. 2 , a first grinding process 30 is performed. The first grinding process 30 includes thinning the first back surface 14 b of the first silicon substrate 14 along the longitudinal direction. The first grinding process 30 may use a grinding wheel. As shown in FIG. 3 , a first trimming process 32 is performed. The first trimming process 32 includes thinning the edge of the first wafer 10 and the edge of the second device structure 22 along the lateral direction. For example, the first trimming process 32 is performed. The trimming process 32 may use a grinder or other equipment that can be mechanically smoothed to grind the edge of the first wafer 10 and the edge of the second device structure 22 along the circumference.

As shown in FIG. 4 , a silicon oxide layer 34 is formed to cover the first wafer 10 , the second backside 24 b of the second silicon substrate 24 and the edge of the second element structure 22 . The silicon oxide layer 34 covers the first silicon substrate accordingly. 14. The first device structure 12, the second device structure 22 and the second front surface 24a of the second silicon substrate 24. The silicon oxide layer 34 may be tetraethoxysilane (TEOS) formed by deposition.

As shown in Figure 5, the first wafer 10 and the second wafer 20 are turned upside down, and then a protective layer 36 is formed to cover the second backside 24b of the second silicon substrate 24. The protective layer 36 is preferably oxidized. Silicon or silicon nitride. When the protective layer 36 is silicon oxide, the thickness of the protective layer 36 is between 300 and 400 angstroms; when the protective layer 36 is silicon nitride, the thickness of the protective layer 36 is between 400 and 700 angstroms. The protective layer 36 can be formed using a deposition process, an oxidation process or a nitridation process.

As shown in FIG. 6 , the first wafer 10 and the second wafer 20 are turned upside down, and then a second grinding process 38 is performed. The second grinding process 38 includes removing the first backside 14 b of the first silicon substrate 14 The silicon oxide layer 34 on the silicon oxide layer 34 and the first back surface 14 b of the first silicon substrate 14 are thinned along the longitudinal direction. After the second grinding process 38 , the thickness of the first silicon substrate 14 is preferably about 15 microns.

As shown in FIG. 7 , a silicon removal process 40 is performed. The silicon removal process 40 includes only removing the first silicon substrate 14 . Specifically, the silicon removal process 40 uses tetramethylammonium hydroxide (TMAH) as an etchant to remove the first silicon substrate 14 . Because the edges of the first element structure 12 and the second element structure 22 are covered with the silicon oxide layer 34 and the second backside 24b and sidewalls of the second silicon substrate 24 are covered with the protective layer 36, only the second side of the first silicon substrate 14 is A backside 14b is exposed to tetramethylammonium hydroxide so that only the first silicon substrate 14 is removed. At this time, a method of forming a protective layer for a silicon removal process of the present invention has been completed, and the bonded wafer structure 100 has also been completed.

Figures 8 to 9 illustrate a method for forming through-hole plugs on a bonded wafer structure according to a preferred embodiment of the present invention, in which components with the same function and the same position will be used as shown in Figure 8. The same component numbers are used in Figures 1 to 7, and the relevant description of the components will not be repeated again.

Continuing from FIG. 7 , as shown in FIG. 8 , a planarization process, such as a chemical mechanical polishing process 42 , is performed to remove the silicon oxide layer 34 protruding on the edge of the first device structure 12 . After the chemical mechanical polishing process 42 , a second trimming process (not shown) is selectively performed to remove the silicon oxide layer 34 on the edge of the first device structure 12 and the oxidation on the edge of the second device structure 22 . The silicon layer 34 thins the first element structure 12 and the second element structure 22 along the lateral direction. In this embodiment, the second trimming process is omitted as an example.

As shown in FIG. 9 , a dielectric layer 44 is formed to cover the first device structure 12 , and then a through-hole plug 46 is formed to penetrate the dielectric layer 44 and be disposed in the dielectric layer 12 b of the first device structure 12 . The via plug 46 contacts one of the interlayer dielectric elements 12 a in the first device structure 12 , and then a conductive pad 48 is formed on the surface of the dielectric layer 44 to contact the via plug 46 .

The step of forming the protective layer 36 can be performed at different stages, as long as the protective layer 36 is formed after the first trimming process 32 and before the silicon removal process 40 . In the above embodiment, the protective layer 36 is formed after the silicon oxide layer 34 is formed and before the second grinding process 38 . As shown in FIG. 10 , according to different process designs, the protective layer 36 may be formed after the first trimming process 32 and before the silicon oxide layer 34 is formed. Alternatively, the protective layer 36 may be formed after the second grinding process 38 and before the silicon removal process 40 is performed.

Traditionally, the protective layer is formed on the second wafer during the formation of shallow trench isolation. After the protective layer is formed, when the front end of line (FEOL) process is performed, the second wafer will be adsorbed on the second wafer. On the electrostatic chuck (e-chuck), however, the protective layer will be damaged because the protective layer is adsorbed on the electrostatic chuck. Then, after joining the first wafer and the second wafer, the third wafer is etched with tetramethylammonium hydroxide. When a silicon substrate is used, tetramethylammonium hydroxide contacts the second silicon substrate through the damaged area of the protective layer, thereby damaging the surface of the second silicon substrate.

In contrast, in the present invention, the protective layer is formed after the first wafer and the second wafer are bonded. Therefore, the protective layer will not be damaged during the front-end process, so that the integrity of the second silicon substrate can be maintained in subsequent processes. The above are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the patentable scope of the present invention shall fall within the scope of the present invention.

10: First wafer 12: First component structure 12a: Interlayer dielectric components 12b: Dielectric layer 14:The first silicon substrate 14a: First front 14b: first back 20: Second wafer 22: Second component structure 22a: Interlayer dielectric components 22b: Dielectric layer 24:Second silicon substrate 24a:Second front 24b: Second back 30: The first grinding process 32: The first trimming process 34: Silicon oxide layer 36:Protective layer 38: Second grinding process 40:Silicon removal process 42: Chemical mechanical polishing process 44:Dielectric layer 46: Piercing plug 48:Conductive pad 100: Bonded wafer structure

Figures 1 to 7 illustrate a method of forming a protective layer for a silicon removal process according to a preferred embodiment of the present invention. Figures 8 to 9 illustrate a method of forming through-hole plugs on bonded wafer structures according to a preferred embodiment of the present invention. FIG. 10 illustrates a process flow chart of forming a protective layer for silicon removal process according to the present invention.

10: First wafer

12: First component structure

12a: Interlayer dielectric components

12b: Dielectric layer

14:The first silicon substrate

14a: First front

14b: first back

20: Second wafer

22: Second component structure

22a: Interlayer dielectric component

22b: Dielectric layer

24:Second silicon substrate

24a:Second front

24b: Second back

34: Silicon oxide layer

36:Protective layer

Claims (11)

A method of forming a protective layer for a silicon removal process, including: A first wafer is bonded to a second wafer, wherein the first wafer includes a first silicon substrate and a first device structure, the first device structure is disposed on the first silicon substrate, and the second The wafer includes a second silicon substrate and a second device structure, the second device structure is disposed on the second silicon substrate; Performing a first trim process, the first trim process includes thinning an edge of the first wafer and an edge of the second device structure along the lateral direction; After the first trimming process, a protective layer is formed covering a back side of the second silicon substrate; and After forming the protective layer, a silicon removal process is performed. The silicon removal process includes removing only the first silicon substrate. The method of forming a protective layer for a silicon removal process as described in claim 1 further includes: Before performing the first trimming process, a first grinding process is performed. The first grinding process includes thinning a backside of the first silicon substrate along the longitudinal direction. The method of forming a protective layer for a silicon removal process as described in claim 1 further includes: After the first trimming process, forming a silicon oxide layer covering the first wafer, a front side of the second silicon substrate and the edge of the second device structure; and After forming the silicon oxide layer, a second polishing process is performed. The second polishing process includes removing the silicon oxide layer on a back side of the first silicon substrate and thinning the first silicon substrate along the longitudinal direction. The back. The method of forming a protective layer for a silicon removal process as described in claim 3, wherein the protective layer is formed after performing the first trimming process and before forming the silicon oxide layer. The method of forming a protective layer for a silicon removal process as described in claim 3, wherein the protective layer is formed after forming the silicon oxide layer and before the second grinding process. The method of forming a protective layer for a silicon removal process as described in claim 3, wherein the protective layer is formed after the second grinding process and before the silicon removal process. The method of forming a protective layer for a silicon removal process as described in claim 1, wherein the protective layer includes silicon oxide or silicon nitride. The method of forming a protective layer for a silicon removal process as described in claim 1, wherein when the protective layer is silicon oxide, the thickness of the protective layer is between 300 and 400 angstroms. The method of forming a protective layer for a silicon removal process as described in claim 1, wherein when the protective layer is silicon nitride, the thickness of the protective layer is between 400 and 700 angstroms. The method of forming a protective layer for a silicon removal process as described in claim 1, wherein the silicon removal process uses tetramethylammonium hydroxide (TMAH) as an etchant to remove the first Silicon base. The method of forming a protective layer for a silicon removal process as described in claim 1 further includes: After the silicon removal process, a dielectric layer is formed to cover the first device structure; Forming a through-hole plug disposed in the dielectric layer; and A conductive pad is formed on the dielectric layer, and the conductive pad contacts the through-hole plug.

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