TW202406074A - Integrated circuit layout including standard cells and method to form the same - Google Patents

Abstract

A method for forming an integrated circuit layout including at least two standard cells having different cell heights is disclosed. The standard cells respectively have a well boundary to divide a PMOS region and an NMOS region. The standard cells are abutted side by side along their side edges in a way that the well boundaries of the cells are aligned along the row direction. The power rail and the ground rail of one of the standard cells are shifted to align and connect to the power rail and the ground rail of the other one of the standard cells.

Description

Integrated circuit layout composed of standard cells and formation method thereof

The present invention relates to the technical field of integrated circuits, and in particular to a method of forming an integrated circuit layout using standard cells and the integrated circuit layout obtained thereby.

With the improvement of performance and various application requirements, the design of integrated circuits (ICs) has become increasingly complex, often containing hundreds of thousands or even millions of logic gates. For the convenience of design, the industry will first design specific functions that are often used in integrated circuits (ICs) using logic gates, and make them into standard cells (Standard cells), such as NAND gates, NAND gates, and NAND gates. OR gate (NOR), D-type flip-flop (D-Flip-Flop), latch (latch), input/output unit (I/O), amplifier (OP Amp), analog-to-digital converter (ADC), digital Analog converter (DAC), etc. After verifying the manufacturability of the standard cell, the standard cell library is then licensed to chip designers through logic simulators, logic synthesizers and automatic placement. /routing) and other electronic design automation (EDA) arrange and combine these standard units to produce the required circuit functions. Generally speaking, the circuit design process usually includes using a hardware programming language to specify the function of the circuit, synthesizing/mapping the generated circuit description to the basic logic gates of the standard cell library, and then arranging and

Bureau and connections, and finally verify the overall connectivity and functionality of the layout. In this way, the layout of complex large-scale integrated circuit systems can be constructed automatically, accurately and quickly.

In advanced technology, in order to improve the area efficiency, speed and power consumption of integrated circuits, standard cell libraries can provide standard cells with functional components of different sizes (and therefore different cell heights) for designers to choose and use according to design needs. However, when standard cells of different cell heights are mixed in the same circuit block (routing block), the efficiency of synthesis tools is often reduced due to irregularities caused by patterns of different sizes, and patterns that violate design specifications are easily produced. Affects process yield. In order to solve the above problems, a commonly used method in the industry is to form standard units of different unit heights into different circuit blocks, and then use metal windings to complete the electrical connections between the circuit blocks. However, this not only limits design flexibility, but also increases power loss due to the increased metal winding length.

Therefore, there is still a need in the art for an improved integrated circuit layout including standard cells of mixed heights and a method for forming the same, so as to improve the deficiencies of the aforementioned conventional technologies.

The object of the present invention is to provide an integrated circuit layout including mixed-height standard cells and a forming method thereof, wherein the mixed-height standard cells can be selected from different standard cell libraries, or selected from the same mixed-height (mixed-height). Standard cell library. The invention can improve design flexibility and layout synthesis efficiency, and the obtained integrated circuit layout has better manufacturability.

An embodiment of the present invention provides a method for forming an integrated circuit layout, including the following steps. First, select a first standard unit and a second standard unit. The first standard unit and the second standard unit have different unit heights, and respectively include a power line and a ground line extending in parallel along a first direction. , and the boundary of a well area. Two active areas, having opposite conductivity types, are arranged between the power line and the ground line and are located on both sides of the boundary of the well area. A gate line extends across the two active regions along a second direction, wherein the first direction is perpendicular to the second direction. Next, a temporary cell layout is obtained by adjoining the first standard cell and the second standard cell in such a manner that the well area boundaries of the first standard cell and the second standard cell are aligned along the first direction. Then, the power line and the ground line of the second standard unit are moved along the second direction to be aligned with the power line and the ground line of the first standard unit along the first direction and connected to each other, thereby The temporary cell layout forms the integrated circuit layout.

Another embodiment of the present invention provides an integrated circuit layout, including a power line and a ground line extending in parallel along a first direction. A first standard unit and a second standard unit are located between the power line and the ground line and adjacent to each other. The first standard unit and the second standard unit respectively include an upper edge, a lower edge, and a well area boundary located between the upper edge and the lower edge, extending in parallel along the first direction. Two active zones, with opposite conductivity types, are located on either side of the boundary of the well zone. A gate line extends between the upper edge and the lower edge and spans the two active regions along a second direction, wherein the first direction is perpendicular to the second direction. Wherein, a first unit height between the upper edge and the lower edge of the first standard unit is different from a second unit height between the upper edge and the lower edge of the second standard unit, and the first The well boundary of the standard unit and the well boundary of the second standard unit are aligned along the first direction.

In order to enable those skilled in the technical field of the present invention to further understand the present invention, several preferred embodiments of the present invention are enumerated below, and together with the accompanying drawings, the composition and intended achievements of the present invention are described in detail. effect. Structural, logical and electrical modifications may be made and applied to other embodiments without departing from the scope of the present invention. Each drawing of the present invention is only a schematic diagram, and its detailed proportions can be adjusted according to design requirements without departing from the present invention.

In order to facilitate the explanation of the spatial relationship of the features, the first direction X and the second direction Y which are perpendicular to each other are shown in the figure. In addition to the orientation shown in the drawings, other orientations of the invention (eg, rotated 90 degrees or other orientations) may also be explained by the spatially relative description in the specification. Herein, the "cell width" of a standard unit is defined as the width between the two edges of the adjacent frame (or adjacent area) of the standard unit taken along the first direction X. The "cell height" of a standard unit is defined as the height between the upper edge and the lower edge of the abutment box or adjacent area of the standard unit taken along the second direction Y. The width of the power rail or ground rail is defined as the width cut along the second direction Y. In some embodiments, the width of the power and ground lines may be approximately one track width. Unit height and unit width can also be described by the number of tracks, such as 7T, 8T or 9T.

The number of gate lines of the standard unit in the embodiment is only an example. The number can be modified and applied to other embodiments without departing from the scope of the present invention, and the number can be singular or plural.

FIG. 1 is a partial plan view of an integrated circuit layout 10 according to an embodiment of the present invention, illustrating how standard cells with different cell heights are arranged in rows. FIG. 1 schematically illustrates four element columns of the integrated circuit layout 10 , wherein each element column extends along the first direction X, and the column edges BN of the element columns are adjacent to each other. The first direction X is also called a row direction. As shown in Figure 1, each element column has the same column height RH, which means that the column edges BN are equidistant. The standard cells are arranged in each element column and are respectively electrically connected to voltage lines (such as power lines and ground lines) extending continuously along the column edge BN through the integrated circuit layout 10 . It is worth noting that the standard cells constituting the integrated circuit layout 10 may have different cell heights, and the column height RH of each element column is substantially equal to the maximum cell height constituting the standard cells.

For example, as shown in FIG. 1 , the integrated circuit layout 10 may include standard cells 12 and 14 disposed within the same element column and having different cell heights, which can each be selected from different standard cell libraries for specific logic functions. (cell library) or the same mixed-height standard cell library. The adjacent frame of the standard unit 12 includes an upper edge 12a, a lower edge 12b and two side edges 12c, where the unit height H12 of the standard unit 12 is defined as the distance between the upper edge 12a and the lower edge 12b, and the unit width of the standard unit 12 W12 is defined as the distance between the two side edges 12c. Similarly, the adjacent frame of the standard unit 14 includes an upper edge 14a, a lower edge 14b and two side edges 14c, where the unit height H14 of the standard unit 14 is defined as the distance between the upper edge 14a and the lower edge 14b. The standard unit 14 The cell width W14 is defined as the distance between the two side edges 14c. The standard unit 12 and the standard unit 14 are adjacent in such a manner that the side edges 12c and 14c overlap, thereby reducing the idle area between the two. The standard cell 12 and the standard cell 14 may have the same logic function (such as AND, NAND, OR, NOR, inverter, or flip-flop, but are not limited thereto) but different cell heights to provide different sized functions. components to provide different component performance. According to an embodiment of the present invention, the unit height H12 of the standard unit 12 is greater than the unit height H14 of the standard unit 14 and is substantially equal to the column height RH of the element column. Therefore, the upper edge 12 a and the lower edge 12 b of the standard unit 12 overlap the column edge BN, while the upper edge 14 a and the lower edge 14 b of the standard unit 14 are spaced apart from the column edge BN by the same or different distances. The respective functional components of the standard unit 12 and the standard unit 14 are electrically connected to the same power line and/or ground line extending along the top column edge BN and/or the bottom column edge BN of the element column.

The integrated circuit layout 10 may include another standard cell 16 disposed in another element column adjacent the lower edge 12 b of the standard cell 12 . Standard unit 16 may be selected from another standard unit library, a standard unit library of standard unit 12 , a standard unit library of standard unit 14 , or the same mixed-height standard unit library as standard unit 12 and standard unit 14 . In some embodiments, the cell height of the standard unit 16 may be equal to the column height RH, when the upper and lower edges of the adjoining frame of the standard unit 16 overlap the column edge BN, and may also be along the lower edge of the adjoining frame of the standard unit 12 . The edge 12b adjoins the standard unit 12 side. In other embodiments, the unit height of the standard unit 16 may be smaller than the column height RH (similar to the standard unit 14 ), in which case the upper and lower edges of the adjoining frame of the standard unit 16 are spaced at the same or different distances from the column edge BN, respectively. , and are separated from the adjacent frame of the standard unit 12 and do not touch. In some embodiments, the functional components of standard unit 12 and standard unit 16 may be electrically connected to the same power line (or the same ground line, depending on the orientation of the standard unit) extending along the column edge BN between them. ), thereby improving the space efficiency of the integrated circuit layout 10 and obtaining a more densely arranged array.

Please refer to Figures 2 to 5 and Figure 9. FIG. 2 illustrates a flowchart of a method for forming an integrated circuit layout using standard cells with different cell heights according to an embodiment of the present invention. 3 to 5 illustrate the steps of using the method of FIG. 2 to adjoin the first standard cell Cell-A and the second standard cell Cell-B with different cell heights to form an integrated circuit layout. FIG. 9 is a circuit diagram of the integrated circuit layout shown in FIG. 5 . The method shown in Figure 2 can be performed in an electronic design automation (EDA) environment.

First, step 22 is performed to select a first standard unit and a second standard unit according to a designed integrated circuit gate netlist. The first standard cell and the second standard cell have the same logic function but different cell heights and different device performance. For example, as shown in Figure 3, the first standard cell Cell-A and the second standard cell Cell-B may be inverters, where the adjacent frame (indicated by a thick dotted line frame) of the first standard cell Cell-A includes An upper edge A1 and a lower edge A2 extending in parallel along the first direction X and two side edges A3 extending in parallel along the second direction Y. The first standard cell Cell-A has a cell height H1 defined by the upper edge A1 and a lower edge A2, and a cell width W1 defined by the two side edges A3. The center line 114 of the first standard cell Cell-A extends through the center of the adjacent frame along the first direction X, thereby dividing the adjacent frame into two equal parts (the upper half and the lower half). In other words, the distance from the center line 114 to the upper edge A1 and the lower edge A2 is the same. Two active regions 120p and 120n having opposite conductivity types are respectively provided in the upper and lower halves of the adjacent frame. The gate line 130 extends along the second direction Y and spans the active region 120p and the active region 120n. Two dummy gate lines 132 parallel to the gate line 130 are respectively provided on both sides of the active area 120p and the active area 120n along the two side edges A3. According to an embodiment of the present invention, the gate line 130 and the dummy gate line 132 have the same length in the second direction Y, and the ends of the gate line 130 and the dummy gate line 132 are aligned along the first direction X. The first standard cell Cell-A may also include a well area 116 overlapping the upper half of the adjacent frame and the active area 120p. As shown in FIG. 3, the well boundary 116a of the well 116 may overlap the centerline 114 of the adjacent frame. According to an embodiment of the present invention, the conductivity type of the active region 120p is p-type, and the conductivity type of the active region 120n is n-type. The overlapping area of the gate line 130 and the active region 120p forms a p-type metal oxide semiconductor transistor (PMOS). The overlapping area of the gate line 130 and the active region 120n forms an n-type metal oxide semiconductor transistor (NMOS). The part of the active area 120p and the active area 120n located on the left side of the gate line 130 (close to the side of the conductive connector 142 and the conductive connector 152) is the source area S of PMOS and NMOS. The active area 120p and the active area 120n are located on the gate line. The part on the right side of 130 is the drain region D of PMOS and NMOS. When manufacturing an integrated circuit, the well region 116 is used to define an n-type well region in a p-conductivity type substrate to set the p-type active region 120p.

The first standard cell Cell-A also includes a power line 140 and a ground line 150 extending along the first direction X and respectively provided on the upper edge A1 and the lower edge A2. width) can be the same or different. According to an embodiment of the present invention, the center line 140a of the power line 140 that divides the power line 140 into two equal parts may completely overlap the upper edge A1. The center line 150a of the ground line 150 which bisects the ground line 150 may completely overlap the lower edge A2.

The first standard cell Cell-A also includes a conductive connector and a contact plug for electrically connecting the transistor to the power line and the ground line to implement the logic function of the first standard cell Cell-A. Specifically, as shown on the right side of Figure 3, the conductive connector 142 and the conductive connector 152 are disposed on the same side of the gate line 130, are respectively connected to the edges of the power line 140 and the ground line 150, and are respectively connected to the active area 120p. It partially overlaps with the source region S of the active region 120n. The conductive connection 162a is disposed on the other side of the gate line 130 and partially overlaps the drain region D of the active region 120p and the active region 120n. The conductive connector 162 b is disposed on the same side as the conductive connector 142 and the conductive connector 152 and includes a bump that overlaps the middle portion of the gate line 130 . A plurality of contact plugs 118 electrically connect the source region S of the active region 120p to the conductive connector 142 and the power line 140, and electrically connect the source region S of the active region 120n to the conductive connector 152 and the ground wire 150. The gate line 130 is electrically connected to the conductive connection 162b, and the drain region D of the active region 120p and the active region 120n is electrically connected to the conductive connection 162a. According to an embodiment of the present invention, the power line 140, the ground line 150 and the conductive connectors 142, 152, 162a, 162b are laid out on the same layout layer, such as the first metal layer. According to an embodiment of the present invention, compared with the second standard cell Cell-B, the first standard cell Cell-A is a high-performance unit with larger dynamic current and faster speed.

Please refer to the left side of Figure 3. The second standard cell Cell-B is the same as the first standard cell Cell-A. The adjacent frame (indicated by a thick dotted frame) includes an upper edge B1, a lower edge B2, two side edges A3, as well as a cell height H2 and a cell width W2. . The center line 214 of the second standard cell Cell-B extends along the first direction X through the center of the adjoining frame of the second standard cell Cell-B. The active region 220p with p conductivity type and the active region 220n with n conductivity type are respectively disposed on both sides of the center line 214. The gate line 230 extends along the second direction Y across the active region 220p and the active region 220n to form NMOS respectively. and PMOS. Two dummy gate lines 232 are located on both sides of the active area 120p and the active area 120n. The gate line 230 and the dummy gate line 232 may have the same length along the second direction Y, and the ends may be flush with each other along the first direction X. The well area 216 overlaps the upper half of the adjacent frame of the second standard cell Cell-B, and the well area boundary 216a may overlap the centerline 214. The power line 240 and the ground line 250 are provided on the upper edge B1 and the lower edge B2 respectively. The center line 240a of the power line 240 that divides the power line 240 into two equal parts may completely overlap the upper edge B1. The center line 250a of the ground wire 250 that divides the ground wire 250 into two equal parts may completely overlap the lower edge B2. The power line 240 of the second standard cell Cell-B may have the same width as the power line 140 of the first standard cell Cell-A. The ground line 250 of the second standard cell Cell-B may have the same width as the ground line 150 of the first standard cell Cell-A. The second standard cell Cell-B also includes a plurality of conductive connectors 242, 252, 262a, 262b and contact plugs 218 for electrically connecting the transistor to the power line 240 and the ground line 250 to implement the second standard cell Cell-B. -B logic function. For other detailed descriptions of the second standard unit Cell-B, please refer to the foregoing description of the first standard unit Cell-A. To simplify the description, they will not be described again. According to an embodiment of the present invention, compared with the first standard cell Cell-A, the second standard cell Cell-B is a low-power unit with better space efficiency and lower power leakage. In some embodiments, as shown in FIG. 3 , along the second direction Y, the width of the active area 220p, the width of the active area 220n and the length of the gate line 230 of the second standard cell Cell-B are respectively smaller than the first standard cell. The width of the active area 220p, the width of the active area 220n, and the length of the gate line 130 of the cell Cell-A. The cell height H2 of the second standard cell Cell-B is smaller than the cell height H1 of the first standard cell Cell-A.

Next, step 24 is performed to adjoin the first standard cell and the second standard cell to obtain a temporary cell layout. As shown in Figure 4, the first standard cell Cell-A and the second standard cell Cell-B overlap each other with the side edge A3 of the first standard cell Cell-A and the side edge B3 of the second standard cell Cell-B. The well area boundary 116a of a standard cell Cell-A and the well area boundary 216a of the second standard cell Cell-B are adjacent in a manner aligned with each other along the first direction X, thereby obtaining a temporary cell layout 10A. According to an embodiment of the present invention, the dummy gate lines 132 and the dummy gate lines 232 located on the overlapping side edges A3 and B3 overlap and combine with each other to form a common dummy gate line 332. According to an embodiment of the present invention, the dummy gate line 332 is spaced at the same distance from the gate line 130 and the gate line 230 . According to an embodiment of the present invention, the dummy gate line 332 and the gate line 130 may have the same length along the second direction Y, and their ends may be aligned along the first direction X.

Next, step 26 is performed to form the integrated circuit layout from the temporary cell layout. As shown in Figures 4 and 5, after being adjacent to the first standard cell Cell-A and the second standard cell Cell-B, the power line 240 and the ground line 250 of the second standard cell Cell-B are identified, and then along the second Direction Y moves the two distances P1 and P2 respectively (as shown in Figure 4) until the center line 240a' of the power line 240' of the shifted second standard unit Cell-B is in contact with the first standard unit Cell-A. The center line 140a of the power line 140 is aligned along the first direction Centerline 150a is aligned along the first direction X. Therefore, the power line 240' and the ground line 250' of the second standard cell Cell-B can be smoothly connected to the power line 140 and the ground line 150 of the first standard cell Cell-A, respectively, to obtain a continuously extending power line 340 and ground. Line 350. According to an embodiment of the present invention, the distance P1 and the distance P2 are the same. When the power line 240 and the ground line 250 of the second standard unit Cell-B move, the conductive connector 242 and the conductive connector 252 must extend along the second direction Y to maintain connection with the shifted power line 240' and ground. The wire 250' is connected, while the contact plug 118 of the second standard cell Cell-B remains in place without moving. According to an embodiment of the present invention, the length L1 of the extended conductive connecting member 242 and the length L2 of the extended conductive connecting member 252 may be the same. The length L3 of the conductive connector 142 may be equal to or different from the lengths L1 , L2 of the conductive connectors 242 and 252 . After completing step 26, the integrated circuit layout 10B according to an embodiment of the present invention is obtained.

Next, step 28 is performed to verify the connectivity and circuit function of the integrated circuit layout 10B. After passing the verification, the integrated circuit layout 10B is output as a set of photomasks used in the process of manufacturing integrated circuit wafers.

Please refer to FIG. 9 , which is a circuit diagram of the integrated circuit layout 10B shown in FIG. 5 . The first standard cell Cell-A and the second standard cell Cell-B are connected in series, and respectively include a p-type metal oxide semiconductor transistor (PMOS) T1 and an n-type metal oxide semiconductor transistor (NMOS) T2. In each unit, the gates of PMOS T1 and NMOS T2 are connected to each other and are the input terminals of the units, electrically connected to an input voltage Vin. The drain regions D of the PMOS T1 and the NMOS T2 are coupled to each other and are the output terminals of the cells, electrically connected to an output voltage Vout. The source region S of the PMOS T1 is electrically connected to the power line Vdd, and the source region S of the NMOS T2 is electrically connected to the ground line Vss. The output terminal of the second standard cell Cell-B is the input terminal of the first standard cell Cell-A. The power line Vdd is electrically connected to a high potential or an operating voltage. The ground wire Vss is electrically connected to a low potential, a reference voltage, or a ground voltage.

It is worth noting that in the embodiments of FIGS. 3 and 5 , since the center line 114 of the first standard cell Cell-A is aligned with the center line 214 of the second standard cell Cell-B, the distance P1 moved by the power line 240 will It is equal to the distance P2 moved by the ground wire 250. At this time, the distance D1 between the power line 240' and the upper edge B1 of the second standard cell Cell-B is equal to the distance D2 between the ground line 250' and the lower edge B2 of the second standard cell Cell-B, and is greater than the distance D1 between the power line 240' and the upper edge B1 of the second standard cell Cell-B. The distance D3 between the line 140 and the upper edge A1 of the first standard cell Cell-A. In some embodiments, the edge a1 of the active region 120p and the edge b1 of the active region 220p that are adjacent to and parallel to the well region boundaries 116a and 216a and are of the same conductivity type (eg, p-type) may be aligned along the first direction X, such as Align along tangent line I. In some embodiments, edge a2 of active region 120n and edge b2 of active region 220n that are adjacent and parallel to well region boundaries 116a and 216a and are of the same conductivity type (eg, n-type) may be aligned along the first direction X, such as Align along tangent line II.

Different embodiments of the invention will be described below. To simplify the description, the following description mainly describes the differences between the embodiments, and does not repeat the similarities. The same components in each embodiment are labeled with the same reference numerals to facilitate comparison between the embodiments.

In some embodiments, the n-type active region and the p-type active region of a standard cell may have different well enclosure/space specifications, resulting in a situation where the well boundary does not overlap with the centerline of the standard cell. For example, please refer to the schematic plan view of the integrated circuit layout 10C according to an embodiment of the present invention shown in Figure 6. The main difference between it and the integrated circuit layout 10B of Figure 5 is that the well of the first standard cell Cell-A Neither the zone boundary 116a nor the well zone boundary 216a of the second standard cell Cell-B overlaps the center lines 114 and 214, and other features are substantially the same. More specifically, the well area boundary 116a is located on a side of the center line 114 close to the active area 120p of the first standard cell Cell-A, and extends along the first direction X. The well area boundary 216a is located on a side of the center line 214 close to the active area 220p of the second standard cell Cell-B, and extends along the first direction X. As shown in FIG. 6 , in some embodiments, the spacing between the well boundary 116 a and the center line 114 and the spacing between the well boundary 216 a and the center line 214 may be the same, so that the well boundary 116 a and the well boundary 216 a are adjacent in a aligned manner. After the first standard cell Cell-A and the second standard cell Cell-B, the center line 114 and the center line 214 can also be aligned along the first direction X, and the length L1 of the extended conductive connector 242 is equal to the extended conductive connection. The length L2 of member 252 and the length L3 of conductive connection member 142 may or may not be equal to L1 and L2.

Please refer to FIG. 7 , which is a schematic plan view of an integrated circuit layout 10D according to an embodiment of the present invention. The main difference between it and the integrated circuit layout 10B of FIG. 5 is that the well boundary 216a of the second standard cell Cell-B does not overlap. At center line 214, other features are generally the same. More specifically, the well area boundary 116a overlaps the centerline 114 of the first standard cell Cell-A, and the well area boundary 216a is located on the side of the centerline 214 close to the active area 220p of the second standard cell Cell-B. and extends along the first direction X. After the first standard cell Cell-A and the second standard cell Cell-B are adjacent to each other in a manner that aligns the well boundary 116a and the well boundary 216a, the centerline 114 and the centerline 214 include an offset in the first direction X, and The distance P1 moved by the power line 240 is greater than the distance P2 moved by the ground line 250 (P1 and P2 are shown in FIG. 4 ), and the length L1 of the extended conductive connector 242 is greater than the length L2 of the extended conductive connector 252 . In some embodiments, L1 is also greater than the length L3 of conductive connector 142 .

Please refer to FIG. 8 , which is a schematic plan view of an integrated circuit layout 10E according to an embodiment of the present invention. The main difference between it and the integrated circuit layout 10B of FIG. 5 is that the well boundary 116 a of the first standard cell Cell-A does not overlap. At center line 114, other features are generally the same. More specifically, the well area boundary 116a is located on one side of the center line 114 close to the active area 120p of the first standard cell Cell-A, and extends along the first direction -B's center lines 214 overlap. After the first standard cell Cell-A and the second standard cell Cell-B are adjacent to each other in a manner that aligns the well boundary 116a and the well boundary 216a, the centerline 114 and the centerline 214 include an offset in the first direction X, and The distance P1 moved by the power line 240 is less than the distance P2 moved by the ground line 250 (P1 and P2 are shown in FIG. 4 ), and the length L1 of the extended conductive connector 242 is shorter than the length L2 of the extended conductive connector 252 . In some embodiments, L1 is also less than the length L3 of conductive connector 142 .

Please refer to FIG. 10 , which illustrates an electronic design automation (EDA) environment for executing the method shown in FIG. 2 . Environment 100 includes specification tool 102 , synthesis tool 104 , configuration/routing tool 106 , verification tool 108 , and standard cell library assembly 110 . The design process of the integrated circuit includes using a standard hardware description language (such as Verilog) in the specification description tool 102 to formulate the function and design specifications of the chip, and then using the synthesis tool 104 (such as the Synopsys product Design Compiler) to synthesize the circuit description / is mapped to a gate-level netlist (gate netlist) based on basic logic gates based on standard cells, where the standard cells can be selected from at least one standard cell library of the standard cell library combination 110 . Next, a configuration/wiring tool 106 (such as Blast Fusion, a product of Magma Company) is used to lay out and wire the physical structure according to the gate-level netlist. Subsequently, the verification tool 108 is used to check the connectivity and circuit functionality of the circuit layout.

In summary, the present invention provides a method for forming an integrated circuit layout including standard cells of mixed heights, in which standard cells of the same element column are adjacent and moved in such a manner that the side edges overlap and the well boundaries are aligned along the column direction. The voltage lines (such as power lines and ground lines) of the standard cells with a smaller unit height are aligned and connected with the voltage lines of the standard cells with a larger unit height, thereby obtaining continuous voltage lines extending along the column edges to connect each standard unit. . The method provided by the present invention can effectively improve layout synthesis efficiency, and the obtained layout can reduce the probability of violating design specifications (such as well area enclosure/spacing specifications). The integrated circuit of the present invention can improve space efficiency as well as chip speed and power efficiency by mixing standard cells with different cell heights (ie, different performance). The above are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the patentable scope of the present invention shall fall within the scope of the present invention.

10:Integrated circuit layout 10A: Temporary unit layout 10B:Integrated circuit layout 10C: Integrated circuit layout 10D: Integrated circuit layout 10E:Integrated circuit layout 12:Standard unit 14:Standard unit 16:Standard unit 22: Steps 24: Steps 26: Steps 28: Steps 100:Environment 102: Specification description tool 104:Synthesis Tools 106:Configuration/wiring tools 108:Verification tool 110: Standard unit library combination 114: Center line 116:Well area 118:Contact plug 130: Gate line 132: Dummy gate line 140:Power cord 142: Conductive connectors 150: Ground wire 152: Conductive connectors 214: Center line 216:Well area 218:Contact plug 230: Gate line 232: Dummy gate line 240:Power cord 240a: Centerline 242: Conductive connectors 250: Ground wire 250a: Centerline 252: Conductive connectors 116a: Well area boundary 120n: Active area 120p:active area 12a:Top edge 12b: Lower edge 12c: side edge 140a: Centerline 14a:Top edge 14b: Lower edge 14c: side edge 150a: Centerline 162b: Conductive connector 216a: Well area boundary 220n: Active area 220p:active area 240':Power cord 240a: Centerline 250': Ground wire 250a': Center line 262b: Conductive connectors A1: Upper edge A2: Lower edge A3: side edge B1: Upper edge B2: lower edge B3: Side edge BN: column edge Cell-A: the first standard unit Cell-B: The second standard unit D: Drainage area D1: distance D2: distance D3: distance H1: unit height H12: unit height H14: unit height H2: unit height I: tangent II: tangent L1:Length L2: length L3: length P1: distance P2: distance RH: column height S: source area W1: unit width W12: unit width W14: unit width W2: unit width X: first direction Y: second direction T1:PMOS T2:NMOS Vdd: power line Vin: input voltage Vout: output voltage Vss: ground wire a1: edge b1: edge a2: edge b2: edge

The accompanying drawings are schematic diagrams and are included to provide a further understanding of embodiments, and are incorporated in and constitute a part of this specification. The drawings illustrate some embodiments and together with the description serve to explain their principles. The relative sizes and proportions of portions of the drawings have been exaggerated or reduced for clarity and convenience of the drawings and are not necessarily drawn to scale. The same reference numbers are generally used to refer to corresponding or similar features in modified and different embodiments. FIG. 1 is a partial plan view of an integrated circuit layout according to an embodiment of the present invention. FIG. 2 is a flowchart of a method of forming an integrated circuit layout according to an embodiment of the present invention. Figures 3, 4 and 5 are schematic diagrams of the steps of the method shown in Figure 2. FIG. 6 is a schematic plan view of an integrated circuit layout according to an embodiment of the present invention. FIG. 7 is a schematic plan view of an integrated circuit layout according to an embodiment of the present invention. FIG. 8 is a schematic plan view of an integrated circuit layout according to an embodiment of the present invention. FIG. 9 is a circuit diagram of an integrated circuit layout according to an embodiment of the present invention. Figure 10 is a schematic diagram of an electronic design automation (EDA) environment.

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Claims (20)

A method of forming an integrated circuit layout, comprising: Select a first standard unit and a second standard unit. The first standard unit and the second standard unit have different unit heights and respectively include: A power line, a ground line, and a well area boundary extend in parallel along a first direction; Two active areas, with opposite conductivity types, are arranged between the power line and the ground line and are located on both sides of the boundary of the well area; a gate line extending across the two active regions along a second direction, wherein the first direction is perpendicular to the second direction; A temporary cell layout is obtained by adjoining the first standard cell and the second standard cell in such a manner that the well boundaries of the first standard cell and the second standard cell are aligned along the first direction; and The power line and the ground line of the second standard unit are moved along the second direction to be aligned with the power line and the ground line of the first standard unit along the first direction and connected to each other, so that the temporary The cell layout forms the integrated circuit layout. In the method of forming an integrated circuit layout as described in item 1 of the patent application, the power line and the ground line of the second standard unit are moved by the same distance to form the integrated circuit layout. The method for forming an integrated circuit layout as described in item 1 of the patent application, wherein the well area boundary of the first standard unit and the second standard unit is respectively connected with a boundary of the first standard unit and the second standard unit. Center lines overlap. The method for forming an integrated circuit layout as described in item 1 of the patent application, wherein in the temporary unit layout, a center line of the first standard unit and a center line of the second standard unit are along the first direction. Aligned and parallel to the well area boundary of the first standard unit and the second standard unit. The method for forming an integrated circuit layout as described in item 1 of the patent application, wherein in the temporary unit layout, a center line of the first standard unit and a center line of the second standard unit are in the first direction. Including a dislocation, the power line and the ground line of the second standard unit are moved to different distances to form the integrated circuit layout. The method for forming an integrated circuit layout as described in item 1 of the patent application, wherein the first standard unit and the second standard unit further include: a conductive connector connected to an edge of the power line and overlapping one of the two active areas adjacent to the power line; and Another conductive connector is connected to an edge of the ground line and overlaps the other of the two active areas adjacent to the ground line, wherein The conductive connector and the other conductive connector of the second standard unit are extended as the power line and the ground line move to form the integrated circuit layout. The method of forming an integrated circuit layout as described in item 1 of the patent application, wherein the power line and the ground line adjacent to the first standard unit and the second standard unit and moving the second standard unit are in an electronic Executed in a design automation (EDA) environment. The method for forming an integrated circuit layout as described in item 1 of the patent application, wherein the first standard unit and the second standard unit further include: Two dummy gate lines are provided on both sides of the two active areas and parallel to the gate lines. The method of forming an integrated circuit layout as described in claim 8, wherein the step of adjoining the first standard cell and the second standard cell includes combining one of the dummy gate lines of the first standard cell and the One of the dummy gate lines of the second standard cell. The method of forming an integrated circuit layout as described in item 1 of the patent application further includes outputting the integrated circuit layout to a set of photomasks used in a process of manufacturing an integrated circuit chip. An integrated circuit layout including: A power cord and a ground wire extend in parallel along a first direction; and A first standard unit and a second standard unit are located between the power line and the ground line and adjacent to each other, and respectively include: An upper edge, a lower edge, and a well zone boundary located between the upper edge and the lower edge extend in parallel along the first direction; and Two active zones, with opposite conductivity types, are provided on both sides of the boundary of the well zone; A gate line extends between the upper edge and the lower edge along a second direction and spans the two active regions, wherein the first direction is perpendicular to the second direction, wherein A first unit height between the upper edge and the lower edge of the first standard unit is different from a second unit height between the upper edge and the lower edge of the second standard unit. The first standard unit The well area boundary of and the well area boundary of the second standard unit are aligned along the first direction. For example, the integrated circuit layout of claim 11, wherein a center line between the upper edge and the lower edge of the first standard unit and a center line between the upper edge and the lower edge of the second standard unit A centerline is aligned along the first direction. For example, in the integrated circuit layout of claim 12, the center line of the first standard unit and the second standard unit overlap with the well area boundary. For example, in the integrated circuit layout of claim 12, the center line of the first standard unit and the second standard unit and the well area boundary do not overlap. For example, in the integrated circuit layout of claim 11, the distance between the power line of the second standard unit and the upper edge is greater than the distance between the power line of the first standard unit and the upper edge. For example, the integrated circuit layout in Item 11 of the patent scope includes: A center line between the upper edge and the lower edge of the first standard unit and a center line between the upper edge and the lower edge of the second standard unit include an offset in the first direction; and The distance between the power line and the upper edge of the second standard unit is different from the distance between the ground line and the lower edge. For example, the integrated circuit layout of claim 11, wherein the edge of the active area of the same conductivity type adjacent to the first standard unit and the second standard unit and parallel to the boundary of the well area is along the first Orientation alignment. For example, the integrated circuit layout of item 11 of the patent application, wherein the edge of the active area of the same conductivity type adjacent to the first standard unit and the second standard unit and parallel to the boundary of the well area is on the first side. Upward includes a dislocation. For example, the integrated circuit layout in item 18 of the patent scope also includes: a first conductive connector extending a first length along the second direction from an edge of the power line and partially overlapping one of the active areas of the first standard unit; and A second conductive connector extends a second length from the edge of the power line along the second direction and partially overlaps one of the active areas of the second standard unit, wherein the first length and the second length different. For example, the integrated circuit layout in item 11 of the patent scope also includes: a first dummy gate line, disposed on one side of the first standard unit and relative to the second standard unit; a second dummy gate line, disposed on one side of the second standard cell and opposite to the first standard cell; and A third dummy gate line is provided between the first standard cell and the second standard cell, wherein the ends of the first dummy gate line and the third dummy gate line are respectively connected with the first standard cell. The end of the gate line is aligned, and the end of the second dummy gate line is aligned with the end of the gate line of the second standard cell.

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