TW202401902A - Radio-frequency circuit for phased array antenna - Google Patents

Abstract

A wireless communication system includes a plurality of antennas, and a plurality of RF chips, arranged in a row and coupled to the antennas, for providing a plurality radio-frequency (RF) output signals to the antennas according to an RF signal. The wireless communication system also includes a transmission line arranged to be a straight line in parallel to the row, and to connect to the RF chips, and a resistive load, coupled to a first end of the transmission line. A second end of the transmission line is arranged to receive the RF signal.

Description

RF circuits for phased array antennas

The present application relates to a radio frequency circuit, and in particular to a radio frequency circuit for a phased array antenna.

In modern wireless communication technology, phased array antenna technology has attracted much attention due to its advantages such as higher gain, higher reliability and beam control capabilities compared with traditional antenna technology. Phased array antenna technology uses an antenna array arrangement with appropriately controlled antenna spacing, so the substrate area for deploying array antennas will be much larger than traditional non-array antennas. Substrate flatness is one of the important issues in developing cost-effective large-scale antenna arrays. On the other hand, radio frequency (RF) circuits with higher circuit density and lower power consumption are needed to achieve better signal processing performance in antenna arrays. Therefore, it is necessary to develop a new phased array antenna architecture to solve the problem of the substrate, so that low-cost, high-performance radio frequency circuits and antennas can be formed on the substrate.

An embodiment of the present invention proposes a wireless communication system, which includes multiple antennas; multiple radio frequency chips arranged in a row and coupled to the antennas for providing multiple radio frequency output signals to the antennas according to radio frequency signals; and transmission lines. is a straight line parallel to the column and connects the radio frequency chips; and a resistive load is coupled to the first end of the transmission line. The second end of the transmission line is configured to receive the radio frequency signal.

An embodiment of the present invention proposes a wireless communication system that includes multiple antennas; multiple radio frequency chips arranged in a row and coupled to the antennas for receiving multiple radio frequency signals from the antennas to output multiple radio frequency output signals; A transmission line is arranged as a straight line parallel to the column and connects the radio frequency chips and receives the radio frequency output signals; and a resistive load is coupled to the first end of the transmission line. The second end of the transmission line is configured to output an accumulated radio frequency output signal of the radio frequency output signals.

With the proposed arrangement of phased array antennas and radio frequency wafers, transmitters and receivers can be manufactured at less cost and operate at lower power, and the reliability of the components can also be improved.

The above description has quite broadly summarized the technical features and advantages of the embodiments of the present invention, so that the detailed implementations of the present invention described below can be more easily understood. Other technical features and advantages possessed by the subject matter of the patent application scope of the present invention will be described below. It should be understood by those skilled in the art that other structures or methods can be easily modified or designed using the concepts and specific embodiments disclosed below to achieve the same purposes as the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs should also understand that such a concept to achieve similar effects does not depart from the spirit and scope of the present invention as defined in the patent application scope described herein.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present case. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include additional features that may be formed between the two features. embodiment such that the first and second features may not be in direct contact. Additionally, the case may repeatedly refer to numbers and/or letters in various examples. This repetition is for simplicity and clarity and is not intended per se to describe the relationship between the various embodiments and/or configurations discussed.

In addition, for ease of description, spatially relative terms such as "below," "beneath," "beneath," "above," "above," and other spatially relative terms may be used herein to describe one element or feature in relation to another as illustrated in the figures. element or characteristic. Spatially relative terms are intended to encompass different orientations of elements in use or operation in addition to the orientation depicted in the figures. The element may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Notwithstanding that the broad numerical ranges and parameters setting forth the present invention are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the biases typically found in corresponding testing measurements. Furthermore, as used herein, the terms "about," "substantially," or "substantially" generally mean within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, the terms "about," "substantially," or "substantially" mean within an acceptable standard error of the mean when considered by one of ordinary skill in the art. Except in examples of operation/operation, or unless otherwise expressly stated, all numerical ranges, quantities, values and percentages, such as those disclosed herein, such as amounts of material, durations, temperatures, operating conditions, ratios, etc. are to be understood as such. is modified in each case by the term "approximately", "substantially" or "substantially". Accordingly, unless indicated to the contrary, the numerical parameters set forth in this application and in the accompanying patent claims are approximations that may be varied as necessary. At a minimum, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. A range may be expressed in this article as from one endpoint to another endpoint or between two endpoints. Unless otherwise stated, all ranges disclosed herein include the endpoints.

As used herein, the term "connected" may be interpreted as "electrically connected" and the term "coupled" may also be interpreted as "electrically coupled." "Connected" and "coupled" can also be used to indicate that two or more elements collaborate or interact with each other.

Figure 1 shows a schematic diagram of a wireless communication system 10 in a next-generation communication scenario according to some embodiments of the present case. Wireless communication system 10 includes one or more user equipments 12, 14, 16 and 18, terrestrial base stations 22 and non-terrestrial base stations 24. In some embodiments, user devices 12, 14 are carried and moved by humans and are referred to as handheld devices. In some embodiments, user equipment 16 is a mobile device mounted in a land-mobile vehicle, such as a car, a train, etc. In some embodiments, the user equipment 18 is a user equipment mounted in a vessel moving in the sea, river, etc.

In some embodiments, terrestrial base station 22 is an example of a base station deployed in a communications network, such as a cellular communications network. The ground base station 22 is used to provide a communication network to the user equipments 12, 14 and 16, where the user equipments 12, 14 and 16 can send or receive information between each other through the network established by the plurality of ground base stations 22. The ground base station 22 may also be called a low-altitude platform. In some embodiments, non-terrestrial base stations 24 are examples of communications satellites deployed in a communications satellite network. Non-terrestrial base station 24 is configured to provide a communications network to user equipment 12, 14, 16, and 18, where user equipment 12, 14, 16, and 18 can send and receive information to and from each other over the satellite network. Multiple terrestrial base stations 22 and multiple non-terrestrial base stations 24 can be connected to each other to form a unified communication network, realizing a global communication network and covering user equipment all over the world. The users can be located at low altitude locations, high altitude locations or ground base stations. 22 anywhere not covered.

To achieve the goals of a global communications network, exemplified by wireless communications system 10, user equipment 12, 14, 16, or 18 may need to be redesigned to include a transmitter or receiver with greater communications capabilities to communicate with non-terrestrial devices located at high altitudes. Base station 24 communicates. In various transmitter or receiver designs, phased array antenna technology is a promising solution to implement beamforming technology, which can significantly increase the gain of the transmitter or receiver, has higher reliability, and is suitable for Satellite communications.

Figure 2A is a perspective schematic diagram showing the transmitter 100 of the user equipment 12, 14, 16 or 18 shown in Figure 1 according to some embodiments. In some embodiments, transmitter 100 is a radio frequency transmitter. In some embodiments, the transmitter 100 includes a control circuit board 110 , a radio frequency circuit board 120 , and a connection circuit board 130 that electrically connects the radio frequency circuit board 120 to the control circuit board 110 . Furthermore, the radio frequency circuit board 120 includes an antenna array formed by an array of antenna elements 140 (eg, antenna patches) formed on a substrate of the radio frequency circuit board 120 . In some embodiments, transmitter 100 is suitable for use with terrestrial base stations 22 or non-terrestrial base stations 24.

In some embodiments, the control circuit board 110 is a printed circuit board (PCB) and includes a substrate with a plurality of circuit dies and wiring formed thereon. In some embodiments, control circuit board 110 includes one or more semiconductor dies, such as semiconductor die 150 mounted on a surface of control circuit board 110 . The substrate of the control circuit board 110 may be formed of epoxy resin with metal (for example, copper) foil. The control circuit board 110 is used to generate control signals and data signals, and provide them to the radio frequency circuit board 120 through the connection circuit board 130 . The data signal may be a baseband signal or an intermediate frequency (IF) signal. A modulated carrier wave of a predetermined frequency, such as 455 kHz. if. In some embodiments, the control circuit board 110 is configured to convert the first voltage level to a second voltage level and transmit the appropriate supply voltage to the radio frequency circuit board 120 . In some embodiments, the connection circuit board 130 includes a flexible or non-flexible substrate and includes a plurality of transmission lines for transmitting power voltage, control signals and intermediate frequency data signals to the radio frequency circuit board 120 .

In some embodiments, user equipment 12, 14, 16, and 18 also have receivers (not shown separately) to operate with transmitter 100 to accomplish two-way communications. The configuration of the transmitter 100 shown in Figure 2A can also be applied to the receiver 101 (see Figure 4A), which also has a control circuit board 111, a radio frequency circuit board 121 and connections interconnected in a similar manner to the transmitter 100 Circuit board 130. User equipments 12, 14, 16 and 18 may include both a transmitter 100 and a receiver 101 to form a wireless communication system. The differences between transmitter 100 and receiver 101 will be explained later.

Figure 2B is an enlarged view of portion A1 of the radio frequency circuit board 120 shown in Figure 2A, according to some embodiments. . Please note that the vertical direction (positive Z-axis direction) of the radio frequency circuit board 120 shown in FIG. 2B is opposite to that of FIG. 2A. In some embodiments, the radio frequency circuit board 120 includes a substrate 202 and an interconnect structure 204 located above the substrate 202 . The interconnect structure 204 has an upper surface and the substrate 202 has a lower surface. In some embodiments, an array of antenna elements 206 is formed on the lower surface of the substrate 202 and a plurality of radio frequency dies 208 are located on the upper surface of the interconnect structure 204 . RF dies 208 may be interconnected by a plurality of wires 210 . In some embodiments, conductors 210 may be encapsulated by an electrically insulating material or exposed through the surface of interconnect structure 204 . In some embodiments, the antenna array of transmitter 100 includes patch antenna structures, and antenna elements 206 are antenna patches of individual antenna structures.

FIG. 2C is a schematic cross-sectional view of the radio frequency circuit board 120 shown in FIG. 2B according to some embodiments. The schematic cross-sectional view shown in FIG. 2C is taken along line AA of FIG. 2B. As shown in FIG. 2C , the substrate 202 is formed of a transparent material, such as glass, silica, silica, quartz, etc. In some embodiments, substrate 202 separates antenna element 206 from interconnect structure 204 or electronic circuitry of radio frequency die 208 . In some embodiments, RF signals are transmitted from RF die 208 formed on the upper side of substrate 202 , through RF circuitry formed in interconnect structure 204 , radiated through transparent substrate 202 , and coupled to an antenna formed on the underside of substrate 202 Element 206. In some embodiments, the thickness of substrate 202 is determined based on the operating frequency of antenna element 206 . Because the material of substrate 202 is transparent to radio frequency signals, substrate 202 may not contain any conductive members to connect interconnect structure 204 to antenna element 206 .

In some embodiments, interconnect structure 204 is formed from stacked multiple metallization layers. The metallization layer includes patterned wires or conductive vias that are patterned or electrically interconnected to form interconnect paths and other portions of the antenna. For example, a first metallization layer formed on substrate 202 includes first wire or pad 222A. The first wire or pad 222A may serve as a ground plate, and the remaining space may be formed as a hole for coupling radio frequency signals to the antenna element 206 . A second metallization layer is formed over the first metallization layer and includes first conductive vias, including example first conductive via 224A. Likewise, a third metallization layer is formed over the second metallization layer and includes a second conductive line or pad 222B, and a fourth metallization layer is formed over the third metallization layer and includes a plurality of second conductive vias, including examples Second conductive vias 224B. The second conductive lines may be patterned to form power lines or signal transmission lines. A fifth metallization layer is formed over the fourth metallization layer and includes third conductive line 222C. Third conductors 222C may be patterned to form transmission lines for transmitting radio frequency signals or control signals between radio frequency wafers 208 . In some embodiments, conductors 222A, 222B, 222C are interconnected by conductive vias 224A and 224B. In some embodiments, a plurality of conductors 210 are located over the sixth metallization layer and electrically connect conductors 222C to the radio frequency die 208 .

In some embodiments, conductors 222A, 222B, 222C, and 210 and conductive pathways 224A and 224B are formed from a conductive material, such as copper, tungsten, aluminum, titanium, tantalum, alloys thereof, or the like. Wires 222A, 222B, 222C and conductive vias 224A and 224B are further electrically insulated by an insulating material 226A, 226B, or 226C, such as a polymer-based material such as polyimide or epoxy.

Figure 3A is a block schematic diagram of the transmitter 100 shown in Figure 2A according to some embodiments. Referring to FIGS. 2A and 3A , in some embodiments, the control circuit board 110 includes a power conversion module 312 , a memory module 314 , a controller 316 , a local oscillator module 318 and a data processing module 322 . The control circuit board 110 is configured to provide the power supply voltage VD, the IF data signal IF_in, the reference frequency signal LO and the control signal (including the calibration data Din) via the input/output ports on both sides of the connection circuit board 130 and the signal lines in the connection circuit board 130 , data clock signal CLK and synchronization clock signal SYNC) to the radio frequency circuit board 120 .

In some embodiments, the power conversion module 312 is configured to receive input power from a supply voltage source 302 external to the control circuit board 110 . The power conversion module 312 may include a voltage converter configured to convert the initial power voltage of the supply voltage source 302 , such as 110 volts, to a power supply voltage VD for the components of the radio frequency circuit board 120 , such as 5 volts or 1.2 volts. . The power conversion module 312 can further provide power to other components of the control circuit board 110 , such as the memory module 314 , the controller 316 , the local oscillator module 318 and the data processing module 322 . In some embodiments, the power conversion module 312 includes a voltage transformer to provide the power voltage VD. In some embodiments, the power conversion module 312 also includes an electromagnetic interference filter for filtering interference.

In some embodiments, memory module 314 is configured to store data and instructions accessible to controller 316 and data processing module 322, such as transfer data. The memory module 314 may include different types of memory, such as random access memory (RAM), read only memory (ROM), flash memory, cache memory, etc.

In some embodiments, the controller 316 is configured to generate the intermediate frequency data signal IF_in by modulating the transmission data by an intermediate frequency modulated carrier. The transmission data may be provided by the data processing module 322. The intermediate frequency data signal IF_in will be up-converted by the radio frequency circuit board 120 into a radio frequency signal RF_in.

In some embodiments, the controller 316 is further configured to generate control signals for calibrating the radio frequency signals, such as calibration data Din, data clock signal CLK, and synchronization clock signal SYNC. In some embodiments, the calibration data Din is used to calibrate the amplitude or phase of the radio frequency signal RF_in according to the transmission data or instructions. Calibration data may include amplitude calibration data or phase calibration data, or both. In some embodiments, the data clock signal CLK is used to provide a common clock for registers in components of the radio frequency circuit board 120 . The frequency of the data clock signal CLK may represent the operating frequency of digital data processing in the radio frequency circuit board 120 . In some embodiments, the synchronization clock signal SYNC is used to provide clocks for some registers in different stages to output calibration data at the same clock time. The synchronization clock signal SYNC can represent the update rate of calibration data. In some embodiments, because the control signals include digital forms, they are also referred to as digital control signals.

The local oscillator module 318 is configured to generate a reference frequency signal FR for up-conversion or down-conversion between the intermediate frequency data signal IF_in and the radio frequency signal RF_in. In some embodiments, the local oscillator module 318 includes a crystal oscillator configured to generate a reference frequency signal FR of a predetermined frequency.

In some embodiments, the data processing module 322 is configured to receive input data or instructions from the control unit 304 external to the control circuit board 110 . The data processing module 322 may also be configured to send output data 316 provided by the controller. In some embodiments, data processing module 322 includes network interface circuitry configured to receive or transmit data or instructions under a transport protocol. The data processing module 322 may be used to extract transmission data or control signals from input data.

In some embodiments, RF circuit board 120 includes a pair of RF signal generation paths, a pair of power divider networks 342, and two rows of transmitter arrays 300. Each radio frequency signal generation path includes an IF signal receiver 332, a phase locked loop module 334, amplifiers 335 and 338, and a mixer 336.

In some embodiments, each power divider network 342 is connected to the output of a corresponding mixer 336 and is configured to deliver the radio frequency signal RF_in to each radio frequency die 208 (see Figure 3C). In some embodiments, the power divider network 342 is a multi-stage power divider network formed by connecting multiple power dividers 344 in a tree structure or a binary structure. In some embodiments, the power divider network 342 includes two stages, K1 and K2, and each power divider 344 in the K1 stage or the K2 stage is configured to distribute the power of the radio frequency signal RF_in substantially equally to the power split The two output terminals of the converter 344. The output in the power divider 344 of each K2 stage is connected to the corresponding transmitter array 300 . In some embodiments, the left power splitter network 342 and the right power splitter network 342 are symmetrically disposed along a centerline between the left power splitter network 342 and the right power splitter network 342 . In some embodiments, the left row of transmitter array 300 and the right row of transmitter array 300 are symmetrically disposed along a centerline between the left and right rows. In some embodiments, power divider 344 may also be used as a power combiner in a receiver architecture, where the input and output terminals of the power combiner are opposite to the output and input terminals of power divider 344.

In some embodiments, control signals, including calibration data Din, data clock signal CLK, and synchronization clock signal SYNC, are provided to each transmitter array 300 through a bus or multiple signal lines. In some embodiments, the depicted embodiment shows only a two-stage power divider network 342. However, in other embodiments, a power divider network 342 with more than or less than two stages may also be applied to the transmitter 100. In some embodiments, the depicted embodiment shows only four transmitter arrays 300 in a row of transmitter arrays 300 . However, a number of transmitter arrays 300 greater or less than four in an array may also be applicable to transmitters 100 in other embodiments, where the number of transmitter arrays 300 scales with the number of stages of power divider network 342 .

In some embodiments, the intermediate frequency signal receiver 332 is configured to receive the intermediate frequency data signal IF_in from the connection circuit board 130 . The phase locked loop module 334 may be configured to generate the local oscillator signal LO via a phase locked loop based on the reference frequency FR. In some embodiments, local oscillator signal LO is amplified by amplifier 335 . In some embodiments, amplifier 335 is an operational amplifier. Mixer 336 is configured to up-convert IF signal IF_in to a radio frequency signal RF_in at a predetermined operating frequency (eg, 18 GHz, 28 GHz, or other suitable frequency). In some embodiments, radio frequency signal RF_in is amplified via amplifier 338 . In some embodiments, amplifier 338 is an operational amplifier. In some embodiments, the control circuit board 110 provides more control signals to the phase locked loop module 334, such as phase locked loop control signals.

FIG. 3B is a block diagram of the transmitter array 300 of the transmitter 100 shown in FIG. 1 . Referring to Figure 3A, in accordance with some embodiments. In some embodiments, transmitter array 300 includes another power divider network 346 and a plurality of transmitter blocks 310. In some embodiments, the power divider network 346 and the power divider network 342 form a combined power divider network, wherein the power divider 344 is connected to the corresponding transmitter at the last stage K _N of the power divider network 346 Machine block 310. In some embodiments, the power divider network 346 includes N-2 stages, and each power divider 344 of each stage is configured to divide the power of the radio frequency signal RF_in at the input to the power divider with substantially equal power. Two output terminals of 344. In some embodiments, the supply voltage VD and the control signals Din, CLK, and SYNC are also provided to each transmitter block 310 through a bus or multiple signal lines.

Figure 3C is a block schematic diagram of transmitter block 310 of transmitter array 300 shown at 3B, in accordance with some embodiments. In some embodiments, transmitter block 310 is formed from an array of radio frequency dies 208 and an array of antenna feeds 212 corresponding to the array of radio frequency dies 208 . As shown in FIG. 2B , each radio frequency die 208 includes an individual radio frequency circuit and is also referred to as radio frequency circuit 208 . In some embodiments, radio frequency die 208 is configured as a transmitter (TX) die. In some embodiments, a supply voltage VD may be provided and delivered to each radio frequency die 208 . In addition, control signals, including calibration data Din, data clock signal CLK and synchronization clock signal SYNC, are fed to each radio frequency chip 208 through one or more signal lines. In some embodiments, radio frequency signal RF_in is also fed into each radio frequency die 208 through transmission line 220. Referring to FIG. 2B and FIG. 3C, in some embodiments, the radio frequency signal RF_in is transmitted through the transmission line 220, the radio frequency chip 208 (output is the radio frequency signal RF_out), the feeder 212 and the substrate 202, and is radiated outward to the antenna patch 206.

The radio frequency chip 208 is configured to generate the calibrated radio frequency signal as the radio frequency output signal RF_out after calibrating the radio frequency signal RF_in according to the calibration data Din. In some embodiments, the calibrated update rate is controlled by the data clock signal CLK and the synchronization clock signal SYNC. In some embodiments, the radio frequency chip 208 includes input ports corresponding to the radio frequency signal RF_in, the power supply voltage VD, the calibration data Din, the data clock signal CLK, and the synchronization clock signal SYNC. In some embodiments, the radio frequency chip 208 includes output ports for two branch signals RF_out_I and RF_out_Q corresponding to the calibration data Dout and the radio frequency output signal RF_out.

In some embodiments, the radio frequency output signal RF_out consists of components corresponding to horizontal (H)-polarization and vertical (V)-polarization, namely, the in-phase component RF_out_I and the quadrature component RF_out_Q, respectively. The separate components RF_out_I and RF_out_Q represent the in-phase component RF_out_I and the quadrature component RF_out_Q, which are orthogonal to each other. Separating the radio frequency output signal RF_out into separate mutually orthogonal components may assist in the calibration of the radio frequency signal RF_in or the radio frequency output signal RF_out.

In some embodiments, the data clock signal CLK and the synchronization clock signal SYNC are fed to the input ports of the data clock signal CLK and the synchronization clock signal SYNC, respectively, of each radio frequency chip 208 . In some embodiments, the calibration data Din is transmitted over a signal line from the input port of the calibration data Din to the first (leftmost) radio frequency chip 208, and the first radio frequency chip 208 relays the calibration data Din to the adjacent second radio frequency Wafer 208. The first radio frequency chip 208 passes through another signal line from the output port Dout of the first radio frequency chip 208 . Subsequently, the calibration data Din is transmitted to the input port Din of the calibration data Din of the third radio frequency chip 208 . As a result, the calibration data Din is transmitted through the serially connected RF chips 208 through each other's input and output ports until reaching the last (rightmost) RF chip 208 . The timing of data reading can be controlled by the data clock signal CLK and the synchronization signal SYNC.

In some embodiments, the transmitter block 310 includes a transmission line 220 located between a first end (ie, the input port of the transmitter block 310 ) and a second end of the transmission line 220 . In some embodiments, the second end of transmission line 220 is connected to ground through resistive load 372 . In some embodiments, the transmission line 220 is a straight line or a line including multiple line segments extending in different directions. In some embodiments, transmission lines 220 are parallel to a row of RF dies 208 . Resistive load 372 may include a resistor. In some embodiments, the resistance of resistive load 372 is determined to match the impedance of transmission line 220 in order to eliminate signal reflections. In some embodiments, resistive load 372 includes a resistance value of approximately 50 ohms.

In some embodiments, radio frequency signal RF_in propagates from a first end to a second end of transmission line 220 . In some embodiments, in a phased array antenna configuration, adjacent antenna feeds 212 are spaced apart by a predetermined antenna spacing. The spacing of the antennas may be related to the wavelength of the radio frequency signal RF_in. In addition, the radio frequency output signals RF_out_I and RF_out_Q transmitted by each antenna feeder 212 should be modulated with an appropriate phase delay according to the phase adjustment data in the calibration data Din to jointly construct a directional radio frequency signal beam. Therefore, each of the radio frequency output signal components RF_out_I and RF_out_Q are phase modulated according to one or more design criteria, such as their location in the antenna array.

In some embodiments, the RF die 208 is not randomly placed on the interconnect structure 204 . In some embodiments, a column of radio frequency dies 208 in the same transmitter block 310 is connected to the connection end at a different position Di on the transmission line 220, where the argument i represents the ith radio frequency die 208 in the transmitter block 310, and 1<i<=L, where L can be any integer greater than 1. In some embodiments, the number L ranges between 2 and 8. The positions Di are separated by a predetermined distance. In some embodiments, the RF chips 208 are evenly distributed between the first end and the second end of the transmission line 220 . This type of signal feeding of the radio frequency die 208 in the transmitter block 310 using a single transmission line 220 is referred to as a "series feed" signal feeding method. The radio frequency signal RF_in may have phase differences between different positions D1, D2,...D7,...DL of the transmission line 220. Unwanted phase delays caused by different positions D1 to DL can be simultaneously addressed and compensated for by the calibration data Din phase adjustment data. In this way, phase inaccuracies in phased array antennas can be resolved at no additional cost.

The in-phase radio frequency signal RF_out_I and the quadrature radio frequency signal RF_out_Q are coupled to the antenna patch 206, combined and radiated outwardly through the antenna patch 206. The combined radio frequency signal RF_out generates a circularly polarized radio frequency signal RF_out based on the in-phase radio frequency signal RF_out_I and the quadrature radio frequency signal RF_out_Q. In some embodiments, the combined RF signal RF_out is a right-hand circularly polarized RF signal or a left-hand circularly polarized signal, depending on the phase order of the in-phase RF signal RF_out_I relative to the quadrature RF signal RF_out_Q. In some embodiments, since the ideal circular polarization of the RF signal output RF_out is achieved by equal amplitude and precise 90-degree phase difference between the in-phase RF signal RF_out_I and the quadrature RF signal RF_out_Q, the validity of the calibration data Din plays an important role. role. In some embodiments, the in-phase RF signal RF_out_I and the quadrature RF signal RF_out_Q are separated and independently amplitude calibrated and phase calibrated before being transmitted to the antenna patch 206 . Additionally, in some embodiments, the in-phase RF signal RF_out_I and the quadrature RF signal RF_out_Q are received from the antenna patch 206 and independently subjected to amplitude calibration and phase calibration in the radio frequency die 208 before they are combined and transmitted off the radio frequency die 208 . Therefore, the calibration task can be easily completed without complex calibration circuits.

In some embodiments, the radio frequency chip 208 is designed to include input terminals or input ports with high impedance. For example, the input impedance Rin of the radio frequency chip 208 viewed from the transmission line 220 through the input end 208A or input port of the radio frequency chip 208 toward the radio frequency chip 208 is relatively high, such as greater than about 100K ohms, greater than 500K ohms, or greater than 1000K ohms.

The left panel of Figure 3D is a block diagram of the radio frequency chip 208 shown in Figure 3C according to some embodiments. In some embodiments, the input port 208A of the radio frequency chip 208 is connected to a field effect transistor (FET) M1, such as a metal oxide semiconductor FET (MOSFET), in which the gate terminal M1G or gate electrode is connected to the transmission line 220 through the branch transmission line 221. In some embodiments, MOSFET M1 is connected to the input terminal 208A of the radio frequency chip 208 through the capacitor Cp1. In some embodiments, capacitor Cp1 connects diodes D11 and D12 of radio frequency die 208 at gate terminal M1G. Referring to the right subfigure of FIG. 3D , the circuit of the radio frequency chip 208 connected to the input port 208A shown in the left subfigure can be expressed as an equivalent circuit formed by a capacitor Cp and an input resistor Rp connected in parallel. In some embodiments, the input resistance Rp (or Rin) of the radio frequency die 208 or the input impedance seen from the gate terminal M1G of the radio frequency die 208 is substantially equal to or greater than that seen from the input port 208A connected to the transmission line 220 towards the transmission line 220 Ten times the impedance, such as equal to or greater than about 500 ohms, in some embodiments, the input resistance Rp is equal to the input resistance Rin shown in FIG. 3C, at least equal to or greater than 500 ohms, 1000 ohms, or 5000 ohms. In some embodiments, in order to maintain the high impedance characteristics of the input port 208A of the radio frequency chip 208 , the MOSFET disposed at the input port 208A of the radio frequency chip 208 is not connected in parallel with other circuits of the radio frequency chip 208 . In some embodiments, there are no intermediate circuits, matching networks, or buffer circuits between the branch transmission line 221 and the gate terminal M1G of the radio frequency chip 208 . In some embodiments, the above-mentioned series-fed signal feeding type of the radio frequency signal RF_in is implemented through a voltage-driven signal feeding type. The radio frequency output signal RF_out is generated based on the voltage signal transmitted at the gate terminal M1G of the input MOSFET M1, rather than based on the current drive signal.

Based on the above description, the series signal feeding method proposed in this case provides advantages. If the leakage current can be well controlled, the current flowing into the input port 208A of the RF chip 208 will be very low due to the high impedance nature of the MOSFET. Therefore, the power consumption of the radio frequency chip 208 will be relatively low without affecting the performance of the component. In addition, since the calibration data in the control signal already includes the phase calibration data in the phased array antenna architecture to assist in calibrating the radio frequency signal RF_in, there is no need for an additional phase calibration module in the transmitter block 310, where the adjustment of the delayed phase Also includes phase adjustment or calibration.

Existing RF chips use a current drive signal feed method to transmit RF signals, coupled with a tree-shaped power divider network. Each of the power dividers in the last stage of the tree power divider network is connected to a corresponding radio frequency chip. The input ports are designed to comply with impedance matching rules, including, for example, an impedance of approximately 50 ohms. Drive current flows from the RF signal source into each RF chip through a tree-like network of power dividers. This RF signal feed architecture consumes power when the RF signal is distributed to the RF chips at the terminals of the power divider network. Although the phase error between RF wafers of the current drive signal feed type may be smaller than that of the voltage drive signal feed type because all RF wafers have essentially the same transmission length relative to the RF signal source, the differences caused by the process still often result in The phase difference cannot be ignored. Therefore, a phase calibration module is usually required to ensure the performance of the phased array antenna. In comparison, the proposed voltage-driven signal type consumes less power and requires a smaller number of power dividers without compromising component performance. Therefore, via the proposed array antenna architecture, the power, cost and reliability of the transmitter can be improved.

In some embodiments, the present series-fed signal feed type further contributes to wiring efficiency. 3A, 3B and 3C, the transmitter array 300 (including the radio frequency chip 208) is arranged in a row direction in the central portion of the radio frequency circuit board 120, and peripheral circuits, such as power divider networks 342 and 346, amplifiers 335, 338 and Mixers 336 are located on both sides of the radio frequency circuit board 120 . The one-dimensional arrangement of transmitter blocks 310 extends along the column direction, where the antenna spacing and the number of radio frequency dies determine the length/width ratio. Taking the number of stages N=5 and the number of RF dies L=8 in the transmitter block 310 as an example, the resulting transmitter array of the transmitter 100 formed by the transmitter array 300 will be the size of 32x32 RF dies 208 in a square shape. Furthermore, when routing power and signal transmission lines, such as the power supply voltage VD, the control signals Din, CLK, SYNC, and the radio frequency signal RF_in of the transmitter block 310, the percentage of wiring crossovers is relatively low due to its appearance in columns. . As a result, a square phase antenna array with high wiring efficiency can be realized. Furthermore, the phased array antenna of the present invention can be enlarged or reduced in a direct manner by simply adjusting the numbers of N and L without redesigning the layout and wiring.

Figure 4A is a block schematic diagram of receiver 101 in accordance with some embodiments. In some embodiments, receiver 101 is a radio frequency receiver. In some embodiments, the receiver 101 is considered a device opposite to the transmitter 100 , wherein the receiver 101 also includes a control circuit board 111 , a radio frequency circuit board 121 , and connections connecting the control circuit board 111 to the radio frequency circuit board 130 Circuit board 130. Receiver 101 may operate at a different frequency than transmitter 100 to facilitate duplex transmission, for example, one of transmitter 100 and receiver 101 is configured to operate at a frequency of 18 GHz while the other is configured to operate at a frequency of 28 GHz. . Due to different operating frequencies, the device design parameters of the transmitter 100 and the receiver 101 may be different. In some embodiments, the receiver 101 is suitable for use with user devices 12, 14, 16, 18, terrestrial base stations 22, or non-terrestrial base stations 24.

In some embodiments, the control circuit board 111 includes a power conversion module 312, a memory module 314, a controller 317, a local oscillator module 318, and a data processing module 323. In some embodiments, additional modules may be added to the control circuit board 111, or some of the above modules may be omitted or replaced with other modules. The functions and configurations of the connection circuit board 130, the power conversion module 312, the memory module 314 and the local oscillator module 318 are similar to those described in FIG. 3A and will not be described again here for the sake of brevity.

In some embodiments, controller 317 is configured to control demodulation of the receiver signal. In some embodiments, the received signal generated by the control circuit board 111 takes the form of an intermediate frequency (IF) input signal and becomes IF_out, which is down-converted into a base frequency signal by the controller 317 or the data processing module 323. In some embodiments, the controller 317 is powered by an external power supply or the power conversion module 312 and receives the IF signal IF_out according to the receiver data IF_out provided by the radio frequency circuit board 121 . In some embodiments, the controller 317 is configured to generate phase control signals for the array antenna, such as calibration data Din, data clock signal CLK, and synchronization clock signal SYNC.

In some embodiments, the data processing module 323 shown in FIG. 4A is configured to receive instructions from the control unit 304 located external to the control circuit board 110 . The data processing module 323 or the controller 317 may be configured to receive the extracted transmission data from the IF signal IF_out provided by the radio frequency circuit board 121 and transmit the transmission data to the control unit 304 .

The RF circuit board 121 includes a pair of RF signal receiving paths, a pair of power combiner networks 352 and two rows of receiver arrays 301 . The radio frequency signal generation path of Figure 4A proceeds in the opposite manner to that shown in Figure 3A. In some embodiments, the left row of receiver array 301 and the right row of receiver array 301 are arranged symmetrically along a centerline between the left and right rows of receiver array 301 . In an embodiment, the left power combiner network 352 and the right power combiner network 352 are arranged symmetrically along a centerline between the left and right power combiner networks 352 . In some embodiments, each radio frequency signal receive path includes an IF signal receiver 362, a phase locked loop module 334, amplifiers 335 and 338, and a mixer 336. In some embodiments, IF signal receiver 332 is configured to receive IF signal IF_out from the output of mixer 336 . The phase locked loop module 334 may be configured to generate the local oscillator signal LO based on the reference frequency FR through a phase locking process. In some embodiments, local oscillator signal LO is amplified by amplifier 335 . In some embodiments, amplifier 335 is an operational amplifier. The mixer 336 is configured to down-convert the radio frequency signal RF_out to an IF signal IF_out of a predetermined frequency band (eg, 445 kHz). In some embodiments, the radio frequency signal RF_out is amplified by an amplifier, such as an operational amplifier.

In some embodiments, power combiner network 352 is connected to the input of mixer 336 and is configured to collect the radio frequency signals RF_out from each radio frequency die 208 (see Figure 4C) into a combined radio frequency data signal RF_out. The power combiner network 352 shown in Figure 4A is similar to the multi-stage power combiner network of the power divider 342 shown in Figure 3A, except that the input and output ends are reversed from each other. In some embodiments, control signals including calibration data Din, data clock signal CLK, and synchronization clock signal SYNC are provided to each receiver array 301 through a bus or multiple signal lines.

Figure 4B is a block schematic diagram of receiver array 301 of receiver 101 shown in Figure 4A, according to some embodiments. In some embodiments, receiver array 301 includes another power combiner network 356 and a plurality of receiver blocks 311. In some embodiments, the power combiner network 356 shown in Figure 4B is similar to the power divider network 346 shown in Figure 3B except that the input and output ends are reversed from each other. In some embodiments, the supply voltage VD and control signals, including calibration data Din, data clock signal CLK and synchronization clock signal SYNC, are also provided to each receiver block 311 through a bus or multiple signal lines. .

Figure 4C is a block schematic diagram of receiver block 311 of receiver array 301 shown in Figure 4B, according to some embodiments. In some embodiments, the receiver block 311 is formed from an array of radio frequency dies 209 and an array of antenna feeds 213 corresponding to the array of radio frequency dies 209 . In some embodiments, as discussed previously with reference to FIG. 2B , each radio frequency die 209 includes a separate radio frequency circuit, also referred to as radio frequency circuit 209 . In some embodiments, radio frequency die 209 is configured as a receiver (RX) radio frequency die. In some embodiments, supply voltage VD is provided and delivered to each radio frequency die 209 . In addition, control signals including calibration data Din, data clock signal CLK and synchronization clock signal SYNC are fed to each radio frequency chip 209 . 2B and 4C, in some embodiments, the radio frequency signal RF_in is received by the antenna patch 206 and transmitted to the signal port RF_in through the substrate 202, the feeder 213, the radio frequency chip 209 (output as the radio frequency signal RF_out) and the transmission line 220.

The radio frequency chip 209 is configured to provide a calibrated radio frequency signal RF_out from the radio frequency input signal RF_in on the antenna feeder 213 according to the calibration data Din. In some embodiments, the calibrated update rate is controlled by the data clock signal CLK and the synchronization clock signal SYNC. In some embodiments, the radio frequency chip 209 includes input ports for the in-phase radio frequency signal component RF_in_I and the quadrature radio frequency signal component RF_in_Q, the supply voltage VD, the calibration data Din, the data clock signal CLK and the synchronization clock signal respectively. In some embodiments, the radio frequency chip 209 includes an output port Dout for corresponding calibration data and radio frequency signal RF_out. The functions and configurations of the calibration data Din, the data clock signal CLK and the synchronization clock signal SYNC are similar to those described in FIGS. 3A to 3C and will not be described again here.

In some embodiments, receiver block 311 includes transmission line 220 between a first end (ie, the output port of receiver block 311 ) and a second end of transmission line 220 . In some embodiments, the second end of the receiver transmission line 220 is connected to ground through a resistive load 372 . In some embodiments, the transmission line 220 is a straight line or a line including multiple line segments extending in different directions. In one embodiment, the transmission lines 220 are parallel to a row of RF chips 209 . Resistive load 372 may include a resistor. In some embodiments, the resistance value of resistive load 372 is determined to match the impedance of transmission line 220 in order to eliminate signal reflections. In some embodiments, resistive load 372 includes a resistance value of approximately 50 ohms.

In some embodiments, the provided radio frequency signal RF_out propagates between the first end and the second end of the transmission line 220 . The radio frequency signals provided by the respective antenna feeders 213 should be demodulated with appropriate phase delays according to the phase adjustment data phase in the calibration data Din to jointly form the accumulated constructive radio frequency signal RF_out. Therefore, before combining the radio frequency signal components RF_in_I and RF_in_Q or before feeding the individual radio frequency signals RF_in to the transmission line 220, they are phase demodulated according to one or more design criteria, such as their position in the antenna array. In some embodiments, each radio frequency signal RF_out is a current signal Iout fed from a corresponding radio frequency chip 209 to a corresponding connection end on the transmission line 220 at a different position Di.

In some embodiments, the radio frequency chip 209 is designed to include an output terminal with an impedance matched to the transmission line 220 for maximizing the current Iout of the radio frequency signal RF_out. For example, the output impedance of the radio frequency chip 209 is approximately 50 ohms.

Referring to Figures 4A and 4B, the collected and combined radio frequency signal RF_out is transmitted to mixer 336 through power combiner networks 356 and 352 to perform down conversion to IF signal IF_out. The phase locked loop module 334 may be configured to generate the local oscillator signal LO via a phase lock procedure according to the reference frequency FR. In some embodiments, IF signal receiver 362 is configured to receive an intermediate frequency (IF) data signal IF_in from the output of mixer 336 . In some embodiments, local oscillator signal LO is amplified by amplifier 335 . In some embodiments, amplifier 335 is an operational amplifier. The intermediate frequency signal IF_out is transmitted to the control circuit board 110 through the intermediate frequency signal receiver 362 and the connection circuit board 130 . In some embodiments, the intermediate frequency signal IF_out is down-converted to a base frequency signal by the controller 317 or the data processing module 323, and the modulated transmission data in the radio frequency signal RF_out can be demodulated and detected from the base frequency signal.

FIG. 4D shows a schematic block diagram of the radio frequency chip 209 shown in FIG. 4C and an equivalent circuit of the output of the radio frequency chip 209 according to some embodiments. The left sub-figure of Figure 4D shows a schematic block diagram of the radio frequency chip 209 shown in Figure 4C according to some embodiments. In some embodiments, the output terminal 209A or output port of the radio frequency chip 209 is formed by FET M2, with the drain terminal M2D connected to the transmission line 220 through the branch transmission line 221. In some embodiments, the output terminal 209A of the radio frequency chip 209 is designed to include a relatively high input impedance to ensure that most of the output current Iout received from the radio frequency chip 209 to provide the RF signal RF_out to the transmission line 220 does not flow back to the same Other radio frequency chips 209 in the receiver block 311.

In some embodiments, MOSFET M2 is connected to output port 209A of radio frequency chip 209 through capacitor Cp1. In some embodiments, capacitor Cp1 is connected to diodes D21 and D22 of radio frequency die 209 at drain terminal M2D. Referring to the right subfigure of FIG. 4D , the circuit connected to the input terminal 209A of the radio frequency chip 209 shown in the left subfigure can be expressed as an equivalent circuit composed of a capacitor Cp and an input resistor Rp connected in parallel. In some embodiments, the input impedance or resistance Rp looking toward the radio frequency chip 209 from the drain terminal M2D of the radio frequency chip 209 is substantially equal to or greater than ten times the input impedance looking toward the transmission line 220 from the output terminal 209A connected to the transmission line 220 . In some embodiments, the input resistance Rp of the radio frequency chip 209 is at least equal to or greater than 500 ohms, 1000 ohms, or 5000 ohms.

Based on the above, the proposed series-type signal accumulation method provides advantages. If the leakage current can be managed well, the current flowing from one RF die 209 to the other RF die 209 in the same receiver block 311 will be very low due to the high impedance nature of the MOSFETs. Therefore, the power collection efficiency of the radio frequency chip 209 will be relatively high without affecting device performance. Furthermore, an additional phase calibration module of the receiver block 311 is not necessary because the calibration data in the control signal already includes the phase calibration data in the phased array antenna architecture to assist in calibrating the RF signal RF_in (including the in-phase RF signal components RF_in_I and Quadrature radio frequency signal component RF_in_Q), in which the adjustment of the delay phase also includes phase adjustment or calibration.

The features of several embodiments are summarized above so that those skilled in the art can better understand various aspects of the present case. Those skilled in the art should appreciate that they may readily use the present application as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent structures do not depart from the spirit and scope of the present invention, and various modifications, substitutions and alterations can be made herein without departing from the spirit and scope of the present invention.

10: Wireless communication system 12, 14, 16, 18: User equipment 22: Ground base station 24: Non-ground base station 100: Transmitter 101: Receiver 110, 111: Control circuit board 120, 121: Radio frequency circuit board 130: Connection circuit board 140: Antenna Component 150: Semiconductor die 202: Substrate 204: Interconnect structure 206: Antenna component 208, 209: Radio frequency (RF) chip 208A: Input terminal 209A: Output terminal 210: Wire 212, 213: Antenna feeder 220: Transmission line 221: Branch transmission line 222A, 222B , 222C: first wire/pad 224A, 224B: conductive via 226A, 226B, 226C: insulating material 300, 301: transmitter array 302: supply voltage source 304: control unit 310: transmitter block 311: receiver block 312: Power conversion module 314: Memory module 316, 317: Controller 318: Local oscillator module 322, 323: Data processing module 332, 362: Intermediate frequency (IF) signal receiver 334: Phase locked loop module 335, 338: Amplifier 336 :Mixer 342, 346: Power divider network 344: Power divider 352: Power combiner network 356: Power combiner network 360: Field effect transistor 360G: Gate terminal 372: Resistive load A1: Partial CLK: Data Clock signal Cp, Cp1: Capacitor D11, D12, D21, D22: Diode D1~D7: Position Din, Dout: Calibration data FR: Reference frequency signal IF_in: Intermediate frequency (IF) data signal IF_out: Radio frequency signal LO: Reference frequency signal M1, M2: transistor M1G, M2G: gate electrode M1D, M2D: drain terminal M1S, M2S: source terminal R _in , RP: input resistance RF_in, RF_out: radio frequency signal RF_in_I: in-phase component of radio frequency signal RF_in_Q: radio frequency Signal quadrature component RF_out_I: Radio frequency signal in-phase component RF_out_Q: Radio frequency signal quadrature component SYNC: Synchronous clock signal TX: Transmitter RX: Receiver VD: Power supply voltage

Aspects of the present case are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

Figure 1 is a schematic diagram of a wireless communication system in a next-generation communication scenario according to some embodiments of the present case.

Figure 2A is a three-dimensional schematic diagram of a transmitter or receiver of user equipment according to some embodiments.

Figure 2B is an enlarged view of a portion of the transmitter or receiver shown in Figure 2A, according to some embodiments.

Figure 2C is a schematic cross-sectional view of the transmitter or receiver of Figure 2B according to some embodiments.

Figure 3A is a block schematic diagram of a transmitter in accordance with some embodiments.

Figure 3B is a block schematic diagram of a transmitter array of the transmitter shown in Figure 3A, according to some embodiments.

Figure 3C is a block schematic diagram of a transmitter block of the transmitter array shown in Figure 3B, according to some embodiments.

Figure 3D is a block schematic diagram of the radio frequency chip shown in Figure 3C and an equivalent circuit of the input of the radio frequency chip according to some embodiments.

Figure 4A is a block schematic diagram of a receiver in accordance with some embodiments.

Figure 4B is a block schematic diagram of a receiver array of the receiver shown in Figure 4A, according to some embodiments.

Figure 4C is a block schematic diagram of a receiver block of the receiver array shown in Figure 4B, according to some embodiments.

Figure 4D is a block schematic diagram of the radio frequency chip shown in Figure 4C and an equivalent circuit of the input of the radio frequency chip according to some embodiments.

208: Radio frequency (RF) chip

212:Antenna feeder

220:Transmission line

221: Branch transmission line

310:Transmitter block

372: Resistive load

CLK: data clock signal

D1~D7: position

Din, Dout: calibration data

R _in : input resistance

RF_in: radio frequency signal

RF_out_I: In-phase component of radio frequency signal

RF_out_Q: Quadrature component of radio frequency signal

SYNC: synchronization clock signal

TX: transmitter

VD: power supply voltage

Claims (20)

A wireless communication system including: multiple antennas; A plurality of radio frequency chips arranged in a row and coupled to the antenna for providing a plurality of radio frequency output signals to the antennas according to the radio frequency signal; Transmission lines arranged as straight lines parallel to the columns and connecting the radio frequency chips; and resistive load, coupled to the first end of the transmission line, The second end of the transmission line is configured to receive the radio frequency signal. The wireless communication system of claim 1, wherein the radio frequency chips are evenly distributed between the first end and the second end of the transmission line to be connected to the transmission line. The wireless communication system of claim 1, wherein each of the radio frequency chips is configured to receive the radio frequency signal by coupling a voltage signal through a corresponding connection end on the transmission line. The wireless communication system of claim 1, wherein each of the radio frequency chips includes a transistor having a gate terminal connected to an input terminal of the transmission line. The wireless communication system of claim 4 further includes a plurality of branch transmission lines, each of the branch transmission lines being coupled between the gate end of the corresponding radio frequency chips and the transmission line. The wireless communication system of claim 4, wherein the first impedance viewed from the gate end of the corresponding radio frequency chips is ten times greater than the second impedance viewed from the corresponding input end connected to the transmission line toward the transmission line. The wireless communication system of claim 1 also includes: A substrate having a first surface and a second surface opposite to the first surface, Wherein, the antennas are disposed on the first surface, and the radio frequency chips and the transmission lines are disposed on the second surface. The wireless communication system of claim 7, wherein the substrate is transparent. The wireless communication system of claim 7, wherein the substrate is formed of glass, silica fused quartz or quartz. The wireless communication system of claim 7, wherein the radio frequency chips are configured to couple the radio frequency signals to the antennas through the substrate, wherein the substrate does not have any conductive elements between the chips and the antennas. The wireless communication system of claim 1 further includes a plurality of signal lines connected to the radio frequency chips and configured to provide calibration data of the radio frequency signals. The wireless communication system of claim 11, wherein the calibration data includes at least one of amplitude calibration data and phase calibration data. The wireless communication system of claim 12, wherein the phase calibration data provides a phase delay of each of the wafers for a phased array antenna scheme of the antennas. A wireless communication system including: multiple antennas; A plurality of radio frequency chips arranged in a row and coupled to an antenna for receiving a plurality of radio frequency signals from the antennas to output a plurality of radio frequency output signals; Transmission lines, arranged as straight lines parallel to the columns, connect the radio frequency chips and receive the radio frequency output signals; and resistive load, coupled to the first end of the transmission line, Wherein, the second end of the transmission line is configured to output an accumulated radio frequency output signal of the radio frequency output signals. The wireless communication system of claim 14, wherein the radio frequency chips are arranged to be evenly distributed between the first end and the second end for connection to the transmission line. The wireless communication system of claim 14, wherein each of the radio frequency output signals is a current signal fed from the corresponding radio frequency chips to the corresponding connection terminal on the transmission line. The wireless communication system of claim 14, wherein each of the radio frequency chips includes a transistor having a drain terminal connected to the transmission line through an output end of each of the chips. The wireless communication system of claim 17 also includes: A plurality of branch transmission lines, each of the branch transmission lines is coupled between the drain and the transmission line of the corresponding radio frequency chips. The wireless communication system of claim 17, wherein the first impedance viewed from the corresponding output end connected to the transmission line toward the drain terminal of the corresponding radio frequency chips is ten times greater than the second impedance viewed toward the transmission line. The wireless communication system of claim 14 also includes: The substrate has a first surface and a second surface opposite to the first surface, The antenna is disposed on the first surface, and the radio frequency chips and the transmission lines are disposed on the second surface.

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