TW202401822A - Semiconductor device having gate electrodes with dopant of different conductive types - Google Patents

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate, a first gate electrode, and a second gate electrode. The first gate electrode is disposed on the substrate. The first gate electrode has a first dopant of a first conductive type. The second gate electrode is disposed on the substrate. The second gate electrode has a second dopant of a second conductive type different from the first conductive type.

Description

Semiconductor device having gate electrodes with dopants of different conductivity types

This application claims priority to U.S. Patent Application Nos. 17/844,971 and 17/845,776 (that is, the priority date is "June 21, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor device. In particular, it relates to a semiconductor device having gate electrodes of dopants of different conductivity types.

With the rapid development of the electronics industry, the development of integrated circuits (ICs) has reached high performance and miniaturization. Technological advances in IC materials and design have produced several generations of ICs, each with smaller and more complex circuits than the previous generation.

Dynamic random access memory (DRAM) stores each bit of data in a separate capacitor within an integrated circuit. Typically, a DRAM is arranged in a square array with one capacitor and one transistor per cell. A vertical transistor has been developed for 4F ² DRAM cells, where F represents the lithographic minimum feature width or critical dimension (CD). RAM can be widely used in a variety of components, such as one-time programmable (OTP) components.

The above description of "prior art" only provides background technology, and does not admit that the above description of "prior art" reveals the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and any description of the above "prior art" does not constitute the prior art of the present disclosure. should not be used as any part of this case.

An embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a first gate electrode and a second gate electrode. The first gate electrode is disposed on the substrate. The first gate electrode is doped with a first dopant of a first conductivity type. The second gate electrode is disposed on the substrate. The second gate electrode is doped with a second dopant of a second conductivity type that is different from the first conductivity type.

Another embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a plurality of first gate electrodes and a plurality of second gate electrodes. The plurality of first gate electrodes and the plurality of second gate electrodes are arranged in an array and at least one of them is disposed on the substrate. The first gate electrodes are doped with a plurality of first dopants of a first conductivity type. The second gate electrodes are doped with a plurality of second dopants of a second conductivity type that is different from the first conductivity type.

Another embodiment of the present disclosure provides a method of manufacturing a semiconductor device. The preparation method includes providing a substrate; forming a plurality of gate electrodes on the substrate; doping a first portion of the plurality of gate electrodes with a first dopant that is a first conductivity type; and doping A second portion of the plurality of gate electrodes having a second dopant of a second conductivity type, and the second conductivity type is different from the first conductivity type.

Embodiments of the present disclosure provide a semiconductor device having a gate electrode with dopants of different conductivity types, thereby improving the threshold voltage of a transistor. Therefore, when a transistor including a gate electrode with dopants of different conductivity types is turned on, different currents can be measured to determine a lower logic value "0" and a higher logic value "1". As a result, the semiconductor device of the present disclosure can be configured to generate a code for identification.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

Specific language will now be used to describe the embodiments or examples of the present disclosure illustrated in the drawings. It should be understood that the scope of the present disclosure is not intended to be limited thereby. Any modifications or improvements to the described embodiments, as well as any further applications of the principles described in this document, are within the realm of ordinary skill in the art. Element numbering may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment apply to another embodiment even if they share the same element numbering.

It will be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be either directly connected or coupled to the other element, or other intermediate components.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not governed by these terms. limits. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present progressive concept.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and/or "comprising" are used in this specification, these terms specify the stated features, integers, steps, operations, elements, and/or components. exists, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups of the above.

It will be understood that in the description of the present disclosure, the term "about" is used to alter the amount of an ingredient, composition, or reactant of the present disclosure, meaning, for example, by typical measurements and liquid handling used to prepare concentrates or solutions. Quantity changes may occur due to the procedure. Furthermore, variations may result from inadvertent errors in measurement procedures, differences in the manufacture, source or purity of the ingredients used to make the compositions or practice the methods, and the like. In one aspect, the term "about" means within 10% of a reported value. In another aspect, the term "about" means within 5% of the reported value. Furthermore, in another aspect, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2 or 1% of the reported value.

FIG. 1A is a schematic top view illustrating a layout of a semiconductor device structure 100 according to some embodiments of the present disclosure.

In some embodiments, the semiconductor device 100 may be adapted to multiple semiconductor devices, which may include active devices and/or passive devices. Active components may include a memory component (such as a dynamic random access memory (DRAM) component, a one-time programmable (OTP) memory component, a static random access memory (SRAM) component, etc.), a power management A component (such as a power management integrated circuit (PMIC) component), a logic component (such as a system on chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), a microcontroller etc.), a radio frequency (RF) component, a sensor component, a microelectromechanical system (MEMS) component, a signal processing component (such as a digital signal processing (DSP) component), a front-end component (such as an analog front-end (AFE) component) ) or other active components. Passive components may include a capacitor, a resistor, an inductor, a fuse or other passive components.

In some embodiments, the semiconductor device 100 may be applied to a memory, memory device, memory die, memory chip, or other device. Semiconductor device 100 may be a memory, a memory device, a memory die, or part of a memory chip. For example, the memory may be a DRAM or an OTP memory. In some embodiments, the DRAM may be double data rate fourth generation (DDR4) DRAM. In some embodiments, memory may include one or more memory cells (or memory bits, memory blocks).

As shown in FIG. 1A , the semiconductor device 100 may include a substrate 102, active regions 111, 112, 113 and 114, gate structures 121 and 122, and doped regions 1311, 1312, 1313, 1321, 1322, 1323, 1331, 1332, 1333, 1341, 1342 and 1343.

At least one of the active regions 111-114 may extend along an X-axis. At least one of the active regions 111-114 may be arranged and spaced apart along a Y-axis. Active regions 111-114 may be located within substrate 102. Two adjacent active regions 111-114 may be separated by an insulating structure (not shown). For example, the insulating structure may be a shallow trench isolation (STI), a local oxidation of silicon (LOCOS) structure, or any other suitable insulating structure.

At least one of the gate structures 121 and 122 may be disposed on the substrate 102 . At least one of the gate structures 121 and 122 may extend along the Y-axis. At least one of the gate structures 121 and 122 may be arranged and spaced apart along the X-axis.

At least one of the doped regions 1311 - 1343 may be disposed in the substrate 102 . In some embodiments, the area A2 of at least one of the doping regions 1312, 1322, 1332, and 1342 may exceed the area A1 of the doping regions 1311, 1321, 1331, 1341, 1313, 1323, 1333, and 1343. In some embodiments, doped regions 1311, 1312, and 1313 and gate structures 121 and 122 may define two transistors. For example, the doped regions 1311, 1312 and the gate structure 121 may be included in a first transistor, and the doped regions 1312, 1313 and the gate structure 122 may be included in a second transistor. The doped region 1312 may be a common source or a common drain of the two transistors.

FIG. 1B is a schematic cross-sectional view illustrating a cross-section along the cross-section line A-A' of the semiconductor device 100 shown in FIG. 1A according to some embodiments of the present disclosure.

As shown in FIG. 1B , gate structures 121 and 122 may be disposed on the substrate 102 . Doped regions 1311, 1312, and 1313 may be disposed or formed within the substrate 102. In some embodiments, the doped regions 1311, 1312 and the gate structure 121 may define a transistor 110-1. In some embodiments, the doped regions 1312, 1313 and the gate structure 122 may define a transistor 110-2. Transistor 110-1 may include a channel region 141 between doped regions 1311 and 1312. Transistor 110-2 may include a channel region 142 between doped regions 1312 and 1313. In some embodiments, the doped region 1312 may be a common source or a common drain of the transistors 110-1 and 110-2.

The semiconductor device 100 may include a plurality of spacers (not shown). Spacers may be disposed on side surfaces of the gate structures 121 and 122 . The spacer may include a single layer structure or a multi-layer structure. Spacers may include dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, other dielectric materials, or combinations thereof.

In some embodiments, at least one of the transistors 110-1 and 110-2 may be an N-type metal oxide semiconductor (NMOS) or a P-type metal oxide semiconductor (PMOS). In some embodiments, at least one of the doped regions 1311, 1312, and 1313 may include a p-type dopant, such as boron (B), other Group III elements, or any combination thereof. In some embodiments, at least one of the doped regions 1311, 1312, and 1313 may include n-type dopants, such as arsenic (As), phosphorus (P), other group V elements, or any combination thereof.

The semiconductor device 100 may also include a dielectric layer 150 . The dielectric layer 150 may include silicon oxide (SiO _x ), silicon nitride ( _Six N _y ), silicon oxynitride (SiON), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), a Low-k (dielectric constant) dielectric materials (k<4) or other suitable materials.

The semiconductor device 100 may also include conductive contacts 161, 162, 163, 171, and 172. The conductive contact 161 may be electrically connected to the doped region 1311 . Conductive contact 162 may be electrically connected to doped region 1312 . The conductive contact 163 may be electrically connected to the doped region 1313 . The conductive contact 171 is electrically connected to the gate structure 121 . Conductive contact 172 may be electrically connected to gate structure 122 . The conductive contacts may include conductive materials such as tungsten (W), copper (Cu), aluminum (Al), tantalum (Ta), molybdenum (Mo), tantalum nitride (TaN), titanium, titanium nitride (TiN), or analogs, and/or combinations thereof.

In some embodiments, gate structures 121 and 122 may be doped with dopants of different conductivity types. For example, the gate electrode of the gate structure 121 may be doped with p-type dopants, and the gate electrode of the gate structure 122 may be doped with n-type dopants.

2A and 2B are schematic cross-sectional views illustrating the gate structures 121 and 122 of the semiconductor device 100 according to some embodiments of the present disclosure.

As shown in FIGS. 2A and 2B , the gate structure 121 may include a gate dielectric 1211 and a gate electrode 1212 above the gate dielectric 1211 . The gate structure 122 may include a gate dielectric 1221 and a gate electrode 1222 above the gate dielectric 1221.

At least one of the gate dielectrics 1211 and 1221 may have a single layer or a multi-layer structure. In some embodiments, at least one of gate dielectrics 1211 and 1221 may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, other dielectric materials, or combinations thereof. In some embodiments, at least one of gate dielectrics 1211 and 1221 is a multilayer structure including an interface layer and a high-k (dielectric constant greater than 4) dielectric layer. The interface layer may include dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, other dielectric materials, or combinations thereof. The high-k dielectric layer may include a high-k dielectric material, such as _HfO2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, other suitable high-k dielectric materials, or combinations thereof. In some embodiments, the high-k dielectric material may be further selected from metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal Aluminates and combinations thereof.

In some embodiments, at least one of gate electrodes 1212 and 1222 may include a charge trapping material. As used herein, charge may refer to electron and hole charges. As used herein, a charge trapping material may refer to a material that can restrict the movement of electrons (or holes). In some embodiments, at least one of gate electrodes 1212 and 1222 may include a semiconductor material or other suitable material. In some embodiments, at least one of gate electrodes 1212 and 1222 may include polysilicon or other suitable semiconductor materials.

As shown in FIG. 2A , dopants 181 may be doped in the gate structure 121 . In some embodiments, dopant 181 may be doped in gate electrode 1212 of gate structure 121 . In some embodiments, channel region 141 is not doped with dopant 181 or is not doped with dopants. In some embodiments, channel region 141 is free of dopants 182 . In some embodiments, at least one of gate dielectrics 1211 and 1221 is free of dopant 181 . As shown in FIG. 2B , dopants 182 may be doped into the gate structure 122 . In some embodiments, dopant 182 may be doped in gate electrode 1222 of gate structure 122 . In some embodiments, channel region 142 is free of dopants 182 . In some embodiments, channel region 142 is free of dopants 181 . In some embodiments, at least one of gate dielectrics 1211 and 1221 is free of dopant 182 . In some embodiments, dopant 181 may be a first conductivity type, such as a p-type. In some embodiments, dopant 182 may be a second conductivity type different from the first conductivity type, such as an n-type.

In some embodiments, dopants 181 and 182 may be used to modify the threshold voltage of transistors 110-1 and 110-2. The transistor 110-1 has a first threshold voltage. The transistor 110-2 has a second threshold voltage. In some embodiments, the first threshold voltage of transistor 110-1 may be different from the second threshold voltage of transistor 110-2. In some embodiments, the first threshold voltage of transistor 110-1 may be lower than the second threshold voltage of transistor 110-2.

Please refer back to FIG. 1B. In some embodiments, the doped region 1311 can receive a higher voltage, such as 1.2V, the doped region 1312 can be electrically connected to ground, and the doped region 1313 can be electrically floating. . In this case, a first current can be generated when the transistor 110-1 is turned on.

In some embodiments, the doped region 1311 can be electrically floating, the doped region 1312 can be electrically connected to ground, and the doped region 1313 can receive a higher voltage, such as 1.2V. In this case, a second current can be generated when the transistor 110-2 is turned on.

Since the threshold voltages of the transistors 110-1 and 110-2 are different, the first current and the second current are different. In some embodiments, logic values such as "1" and "0" may be determined based on the current when the transistor is turned on. That is, when the transistor 110-1 or 110-2 is turned on, it can be determined to be a high logic value “1” or a low logic value “0”. For example, when the transistor 110-1 is turned on, a high logic value "1" is determined, and when the transistor 110-2 is turned on, a low logic value "0" is determined.

In addition, the semiconductor device 100 may include a capacitor (not shown) for storing a logic value “1” or “0”. For example, during a read operation, a word line electrically coupled or connected to gate structure 121 or 122 may be established to turn on transistor 110-1 or 110-2. Enable transistor 110-1 or 110-2 allows the voltage across the capacitor to be read by a sense amplifier via a bit line. During a write operation, when the word line is asserted, the data to be written is provided on the bit line.

In a comparative semiconductor device, the threshold voltage of a transistor is changed by burning in the gate dielectric. In embodiments of the present invention, the threshold voltage can be changed by doping dopants of different conductivity types into the gate electrode. The arrangement (or distribution) of gate structures with n-type dopants or p-type dopants can be predetermined by a custom mask that determines the arrangement of logic values "1" or "0" (or distribution). As a result, semiconductor device 100 may be configured to generate a code for identification.

FIG. 3 is a top view schematic diagram illustrating a semiconductor device 200 according to some embodiments of the present disclosure. It should be understood that some elements are omitted from FIG. 3 for simplicity, and the semiconductor device 200 may also include other elements.

As shown in FIG. 3 , the semiconductor element 200 may include gate electrodes 2111, 2112, 2113, 2114, 2115, 2121, 2122, 2123, 2124, 2125, 2131, 2132, 2133, 2134, 2135, 2141, 2142, 2143, An array 220 of 2144 and 2145. At least one of gate electrodes 2111-2145 may be included in the transistor.

Array 220 may include columns 221, 222, 223, and 224. At least one of columns 221-224 may include five gate electrodes. The number of columns and the number of gate electrodes in a column are examples only, and the disclosure is not intended to be limited thereto. The pattern (or dots) of the gate electrodes 2111-2145 can be used to identify what type of dopant is incorporated into the gate electrodes 2111-2145. For example, gate electrodes 2111, 2112, 2113, 2114, 2115, 2121, 2124, 2125, 2131, 2132, 2135, 2143, and 2145 may have n-type dopants doped therein and may be grouped into "gate electrodes" Electrode 210-1". Gate electrodes 2122, 2123, 2133, 2134, 2141, 2142, and 2144 may have dopants of p-type dopants therein, and may be grouped into "gate electrodes 210-2."

In some embodiments, columns 221-224 may have different numbers of gate electrodes 210-1 and 210-2. For example, column 221 may have five gate electrodes 210-1 and column 222 may have three gate electrodes 210-1. In some embodiments, columns 221-224 may have different numbers of gate electrodes 210-2. For example, column 223 may have two gate electrodes 210-2 and column 224 may have three gate electrodes 210-2.

As mentioned earlier, when the gate electrode is doped with different types of dopants, the critical voltage of the transistor can be changed. That is, one transistor including gate electrode 210-1 and another transistor including gate electrode 210-2 may have different threshold voltages. For example, a transistor including gate electrode 210-1 may have a higher threshold voltage, and a transistor including gate electrode 210-2 may have a lower threshold voltage. Therefore, when the transistor including gate electrode 210-1 is turned on, a lower current can be measured to determine a lower logic value "0". When the transistor including gate electrode 210-2 is turned on, a higher current can be measured to determine a higher logic value "1".

In some embodiments, each column 221-224 may have a different configuration (or distribution) of gate electrodes 210-1 and 210-2. The arrangement of gate electrodes 210-1 and 210-2 may be configured to store information or data. The stored information or data can generate a code, a function or an identifier when read or executed by a processor. Referring to FIG. 4 , the logic information 300 corresponding to the semiconductor device 200 shown in FIG. 3 may include bit strings 321 , 322 , 323 and 324 . At least one of the bit strings 321-324 may include five logical values composed of logical values "0", "1" and combinations thereof. For example, the bit string 321 may be composed of "0", "0", "0", "0", and "0" in sequence, and the bit string 322 may be composed of "0", "1", "1", It is composed of "0" and "0" in sequence.

In some embodiments, a portion of the logical information 300 may be used as a code for identification. For example, a sequence of logical information 300 can be used as a code for identification. In other embodiments, a portion of the logical information 300 may be used as a code for identification. In some embodiments, a 2×2 array of logical information 300 may be used as an encoding for identification. In a 2×2 array, 4-bit data can be represented by 16 arrangements of logical values “0” and “1”, at least one of which corresponds to an arrangement of gates and electrodes 210-1 and 210-2. Referring back to FIG. 3 , gate electrodes 2121 , 2122 , 2131 and 2132 may define a 2×2 array and correspond to logic values “0”, “1”, “0” and “0” respectively. The arrangement of logical values in an array can be used as a code for identification. The above array may be an M×N array, where at least one of M and N is a real number or a positive integer.

In other embodiments, gate electrodes 210-1 and 210-2 may be used to perform logic operations, such as an XOR logic operation (or its complement XNOR), a NAND logic operation (or its complement AND), or a NOR logic operation ( or its complement OR). For example, when a circuit includes gate electrodes 210-1 and/or 210-2, it can realize the identification of OR function, NAND function and XNOR function. These three operations are respectively complementary operations of the above-mentioned logical operations.

FIG. 5 is a schematic flowchart illustrating a method 400 for manufacturing a semiconductor device according to some embodiments of the present disclosure.

The preparation method 400 begins with step 402, which provides a substrate.

The method 400 continues with step 404 where a plurality of gate structures are formed. At least one gate structure may include a gate dielectric and a gate electrode formed thereon. Step 404 may also include forming a plurality of doped regions in the substrate to define a plurality of transistors. Some doped regions may be a common source or a common drain of two adjacent transistors. Step 404 may also include forming a dielectric layer over the substrate to cover the gate electrode.

The method 400 continues with step 406 where a plurality of openings of the dielectric layer are formed. The openings may expose the doped regions and/or the gate electrodes.

The manufacturing method 400 continues with step 408, where a first photomask is provided. The first photomask exposes a first portion of the gate electrodes, and a second portion of the gate electrodes is covered by the first photomask. Step 408 may also include doping the first portion of the gate electrodes with a first conductivity type dopant. Step 408 may also include forming a photosensitive material to cover the dielectric layer. The photosensitive material is exposed by the first light to form a plurality of first openings defined by the photosensitive material. Dopants having the first conductivity type may be doped into the first portions of the gate electrodes through the first openings of the photosensitive material.

The method 400 continues with step 410, where the first photomask is removed. Additionally, the photosensitive material is removed. The first portions of the gate electrodes and the second portions of the gate electrodes are exposed.

The method 400 continues with step 412, where a second photomask is provided. The second photomask exposes the second portions of the gate electrodes, and the first portions of the gate electrodes are covered by the second photomask. Step 412 may also include doping the second portions of the gate electrodes with a dopant of a second conductivity type that is different from the first conductivity type. Step 412 may also include forming a photosensitive material to cover the dielectric layer. The photosensitive material is exposed through the second photomask, forming a plurality of second openings defined by the photosensitive material. A dopant having the second conductivity type may be doped into the second portion of the gate electrodes via the second openings.

The method 400 continues with step 414, where the second photomask is removed. Additionally, the photosensitive material is removed. The first portions of the gate electrodes and the second portions of the gate electrodes are exposed.

The method 400 continues with step 416 , wherein a plurality of conductive vias are formed to fill the openings of the dielectric layer, thereby producing the semiconductor device.

The preparation method 400 can be used to determine an arrangement (or distribution) of the gate electrodes with dopants of different conductivity types, thereby determining the arrangement (or distribution) of the logical values "1" or "0". As a result, preparation method 400 may be configured to generate a code for identification.

The preparation method 400 is only an example and is not intended to limit the present disclosure beyond the scope expressly stated in the claims. Additional steps may be provided before, during, or after each step of preparation method 400, and some of the steps described may be replaced, eliminated, or moved for additional embodiments of the method. In some embodiments, preparation method 400 may include another step not depicted in Figure 5. In some embodiments, preparation method 400 may include one or more steps depicted in FIG. 5 .

6A, 7A, 8A, 9A, 10A, 11A, 12A and 13A are schematic diagrams illustrating one or more stages of an example of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure; and FIG. 6B, FIG. 7B, FIG. 8B, FIG. 9B, FIG. 10B, FIG. 11B, FIG. 12B and FIG. 13B are schematic cross-sectional views, illustrated respectively along the lines of FIG. 6A, FIG. 7A, FIG. 8A, FIG. 9A, FIG. 10A, FIG. 11A, FIG. 12A and the cross-section along line BB' in Figure 13A. It should be understood that for the sake of simplicity, some elements are omitted from FIGS. 6B, 7B, 8B, 9B, 10B, 11B, 12B, and 13B.

Referring to FIGS. 6A and 6B , a substrate 202 is provided. The substrate 202 may have a well region (not shown). A plurality of insulating structures (not shown) may be formed in the substrate. As an example, forming the insulating structure may include a lithography process to expose a portion of the base substrate, etching a trench in the exposed portion of the base substrate (e.g., by using a dry etch and/or a wet etch ), filling the trench with one or more dielectric materials (e.g., by using a chemical vapor deposition process), and planarizing and removing the substrate by a grinding process, such as a chemical mechanical polishing (CMP) process The excess portion of the dielectric material. In some examples, the filled trench may have a multi-layer structure, such as a thermal oxide liner layer and multiple fill layers of silicon nitride or silicon oxide.

Please refer to FIG. 7A and FIG. 7B to form multiple gate structures. At least one gate structure may include one of gate electrodes 2111-2145. The manufacturing technology of the gate electrodes 2111-2145 may include chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low pressure chemical vapor deposition (LPCVD), or other suitable processes. Doped regions such as 2311, 2312 and 2313 may be formed in the substrate 202. The area of the doped region 2312 may exceed the area of the doped region 2311 or 2313. Doped region 2311, gate electrode 2123 and doped region 2312 may be used to define a transistor 220-1. Doped region 2312, gate electrode 2124, and doped region 2313 may be used to define a transistor 220-2. In some embodiments, the doped region 2312 may be a common source or a common drain of the transistors 220-1 and 220-2. A dielectric layer 250 may be formed over the substrate 202 to cover the gate electrodes 2123 and 2124. The manufacturing technology of the dielectric layer 250 may include CVD, ALD, PVD, LPCVD or other suitable processes.

Referring to Figure 8A and Figure 8B, openings 250o1, 250o2, 250o3, 250o4 and 250o5 are formed. The opening 250o1 penetrates the dielectric layer 250 and exposes the doped region 2311. Opening 250o2 penetrates a portion of dielectric layer 250 and exposes gate electrode 2123. Opening 250o3 penetrates dielectric layer 250 and exposes doped region 2312. Opening 250o4 penetrates a portion of dielectric layer 250 and exposes gate electrode 2124. The opening 250o5 penetrates the dielectric layer 250 and exposes the doped region 2313. The manufacturing technology of the openings 250o1-250o5 may include an etching process, such as a dry etching or a wet etching. In other embodiments, the openings 250-1-250-5 may be formed in different steps, and this disclosure is not intended to be limiting.

Please refer to FIG. 9A and FIG. 9B to provide a photomask E1. The photomask E1 exposes a portion of the gate electrodes, such as the gate electrodes 2111, 2112, 2113, 2114, 2115, 2121, 2124, 2125, 2131, 2132, 2135, 2143, and 2145. Other parts of the gate electrodes, such as the gate electrodes 2122, 2123, 2133, 2134, 2141, 2142 and 2144, are covered by the photomask E1.

In some embodiments, a photosensitive material M1 may be formed on the dielectric layer 250 . The photosensitive material M1 may include a negative photoresist or a positive photoresist. The photosensitive material M1 may be exposed through the photomask E1 to form a plurality of openings o1 to expose the gate electrodes 2111, 2112, 2113, 2114, 2115, 2121, 2124, 2125, 2131, 2132, 2135, 2143 and 2145. A doping process P1 may be performed to dope the gate electrodes 2111, 2112, 2113, 2114, 2115, 2121, 2124, 2125, 2131, 2132, 2135, 2143, and 2145 with the dopant D1. In some embodiments, dopant D1 may be a first conductivity type, such as n-type. The dopant D1 can be doped into the gate electrodes 2111, 2112, 2113, 2114, 2115, 2121, 2124, 2125, 2131, 2132, 2135, 2143 and 2145 through the openings o1. In some embodiments, openings 250o1, 250o2, 250o3, and 250o5 may be filled with photosensitive material M1 or other suitable materials. In other embodiments, the openings 250o1, 250o3, and 250o5 may be formed after the gate electrodes 2111-2145 are doped with dopants of different conductivity types.

Please refer to Figure 10A and Figure 10B, the removable mask E1 and the photosensitive material M1. Gate electrodes 2111-2145 may be exposed. The gate electrodes doped with dopant D1 may be grouped as "gate electrodes 210-1."

Please refer to FIG. 11A and FIG. 11B to provide a photomask E2. In some embodiments, the pattern of reticle E2 may be different from the pattern of reticle E1. The photomask E2 exposes part of the gate electrodes, such as the gate electrodes 2122, 2123, 2133, 2134, 2141, 2142 and 2144. Other parts of the gate electrode doped with the dopant D1, such as the gate electrodes 2111, 2112, 2113, 2114, 2115, 2121, 2124, 2125, 2131, 2132, 2135, 2143 and 2145 are covered by the photomask E2 Cover.

In some embodiments, a photosensitive material M2 may be formed on the dielectric layer 250 . The photosensitive material M2 may include a negative photoresist or a positive photoresist. The photosensitive material M2 may be exposed through the photomask E2 to form a plurality of openings o2 to expose the gate electrodes 2122, 2123, 2133, 2134, 2141, 2142 and 2144. A doping process P2 may be performed to dope the gate electrodes 2122, 2123, 2133, 2134, 2141, 2142, and 2144 with the dopant D2. In some embodiments, dopant D2 may be a second conductivity type, such as p-type. The dopant D2 can be doped into the gate electrodes 2122, 2123, 2133, 2134, 2141, 2142 and 2144 through the openings o2. In some embodiments, openings 250o1, 250o3, 250o4, and 250o5 may be filled with photosensitive material M2 or other suitable materials.

Please refer to Figure 12A and Figure 12B, the removable mask E2 and the photosensitive material M2. Gate electrodes 2111-2145 may be exposed. The gate electrodes doped with dopant D2 may be grouped as "gate electrodes 210-2."

Referring to FIGS. 13A and 13B , conductive contacts 261 , 262 , 263 , 271 and 272 can be formed to fill the openings 250o1 - 250o5 , thereby manufacturing the semiconductor device 200 . The manufacturing technology of the conductive contacts 261, 262, 263, 271 and 272 may include, for example, a PVD process.

The stages shown in Figures 6A-13A and 6B-13B can be used to determine the arrangement (or distribution) of the gate electrodes 210-1 and 210-2, thereby determining the logic value "1" or "0". As a result, semiconductor device 200 may be configured to generate a code for identification.

An embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a first gate electrode and a second gate electrode. The first gate electrode is disposed on the substrate. The first gate electrode is doped with a first dopant of a first conductivity type. The second gate electrode is disposed on the substrate. The second gate electrode is doped with a second dopant of a second conductivity type that is different from the first conductivity type.

Another embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a plurality of first gate electrodes and a plurality of second gate electrodes. The plurality of first gate electrodes and the plurality of second gate electrodes are arranged in an array and at least one of them is disposed on the substrate. The first gate electrodes are doped with a plurality of first dopants of a first conductivity type. The second gate electrodes are doped with a plurality of second dopants of a second conductivity type that is different from the first conductivity type.

Another embodiment of the present disclosure provides a method of manufacturing a semiconductor device. The preparation method includes providing a substrate; forming a plurality of gate electrodes on the substrate; doping a first portion of the plurality of gate electrodes with a first dopant that is a first conductivity type; and doping A second portion of the plurality of gate electrodes having a second dopant of a second conductivity type, and the second conductivity type is different from the first conductivity type.

Embodiments of the present disclosure provide a semiconductor device having a gate electrode with dopants of different conductivity types, thereby improving the threshold voltage of a transistor. Therefore, when a transistor including a gate electrode with dopants of different conductivity types is turned on, different currents can be measured to determine a lower logic value "0" and a higher logic value "1". As a result, the semiconductor device of the present disclosure can be configured to generate a code for identification.

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the claimed claims. For example, many of the processes described above may be implemented in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, etc. that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patent scope of this application.

100:Semiconductor components 102: Base 110-1: Transistor 110-2:Transistor 111:Active zone 112:Active zone 113:Active zone 114:Active zone 121: Gate structure 122: Gate structure 141: Passage area 142: Passage area 150:Dielectric layer 161:Conductive contact point 162:Conductive contact point 163:Conductive contact point 171:Conductive contact point 172:Conductive contact point 181:Adultants 200:Semiconductor components 202:Base 210-1: Gate electrode 210-2: Gate electrode 220:Array 221: column 222: column 223: column 224: column 250:Dielectric layer 250o1:Open your mouth 250o2:Open your mouth 250o3:Open your mouth 250o4:Open your mouth 250o5:Open your mouth 261:Conductive contact point 262:Conductive contact point 263:Conductive contact point 271:Conductive contact point 272:Conductive contact point 300:Logical information 321: bit string 322: bit string 323: bit string 324: bit string 400:Preparation method 402: Step 404: Step 406: Step 408: Step 410: Steps 412: Step 414: Step 416: Steps 1211: Gate dielectric 1212: Gate electrode 1221: Gate dielectric 1222: Gate electrode 1311: Doped area 1312: Doped area 1313: Doped area 1321: Doped area 1322: Doped area 1323: Doped area 1331: Doped area 1332: Doped area 1333: Doped area 1341: Doped area 1342: Doped area 1343: Doped area 2111: Gate electrode 2112: Gate electrode 2113: Gate electrode 2114: Gate electrode 2115: Gate electrode 2121: Gate electrode 2122: Gate electrode 2123: Gate electrode 2124: Gate electrode 2125: Gate electrode 2131: Gate electrode 2132: Gate electrode 2133: Gate electrode 2134: Gate electrode 2135: Gate electrode 2141: Gate electrode 2142: Gate electrode 2143: Gate electrode 2144: Gate electrode 2145: Gate electrode A1:Area A2:Area D1: Dopant D2: Dopant E1: Photomask E2: Photomask M1: Photosensitive material o1:Open your mouth o2:Open your mouth P1: Doping process P2: Doping process

A more complete understanding of the present disclosure can be obtained by referring to the detailed description and patent claims. The present disclosure should also be understood to be associated with the drawing element numbering, which represents similar elements throughout the description. FIG. 1A is a schematic top view illustrating the layout of semiconductor devices according to some embodiments of the present disclosure. FIG. 1B is a schematic cross-sectional view illustrating a cross-section along the cross-section line A-A' of the semiconductor device shown in FIG. 1A according to some embodiments of the present disclosure. FIG. 2A is a schematic cross-sectional view illustrating the gate structure of a semiconductor device according to some embodiments of the present disclosure. FIG. 2B is a schematic cross-sectional view illustrating the gate structure of a semiconductor device according to some embodiments of the present disclosure. FIG. 3 is a top view schematic diagram illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 4 is a schematic diagram illustrating logic information corresponding to the semiconductor device shown in FIG. 3 according to some embodiments of the present disclosure. FIG. 5 is a schematic flowchart illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. 6A, 7A, 8A, 9A, 10A, 11A, 12A and 13A are schematic diagrams illustrating one or more stages of an example of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Figure 6B, Figure 7B, Figure 8B, Figure 9B, Figure 10B, Figure 11B, Figure 12B and Figure 13B are schematic cross-sectional views, exemplified along the lines of Figure 6A, Figure 7A, Figure 8A, Figure 9A, Figure 10A, Figure 11A, respectively. The cross-sections taken along the line BB' in Fig. 12A and Fig. 13A.

100:Semiconductor components

102: Base

110-1: Transistor

110-2:Transistor

121: Gate structure

122: Gate structure

141: Passage area

142: Passage area

150:Dielectric layer

161:Conductive contact point

162:Conductive contact point

163:Conductive contact point

171:Conductive contact point

172:Conductive contact point

1311: Doped area

1312: Doped area

1313: Doped area

Claims (20)

A semiconductor component including: a base; a first gate electrode disposed on the substrate, wherein the first gate electrode is doped with a first dopant of a first conductivity type; and A second gate electrode is disposed on the substrate, wherein the second gate electrode is doped with a second dopant that is a second conductivity type, and the second conductivity type is different from the first conductivity type. The semiconductor device of claim 1, wherein the first gate electrode includes a charge trapping material. The semiconductor component as described in claim 1 also includes: a first doped region, a second doped region and a third doped region, at least one of which is disposed in the substrate; wherein the first doped region, the first gate electrode, the second doped region, the second gate electrode and the third doped region are sequentially arranged along a first direction; wherein the first doped region, the first gate electrode and the second doped region together define a first transistor; The second doped region, the second gate electrode and the third doped region together define a second transistor. The semiconductor device of claim 3, wherein in a top view, a first area of the first doped region is smaller than a second area of the second doped region, the second doped region is grounded, and The second doped region should use a common source or a common drain of the first transistor and the second transistor. The semiconductor device of claim 4, wherein the first transistor has a first threshold voltage, and the second transistor has a second threshold voltage, and the second threshold voltage is different from the first threshold voltage. The semiconductor device of claim 5, wherein the first transistor has a first channel region in the substrate, and the first channel region is not doped with the first dopant or the second dopant. The semiconductor device of claim 5, wherein the first transistor has a first channel region in the substrate, the second transistor has a second channel region in the substrate, and the first dopant and the At least one of the second dopants is not doped in both the first channel region and the second doped region. The semiconductor component as described in claim 1 also includes: a third gate electrode disposed on the substrate, wherein the third gate electrode has the second conductivity type, the first gate electrode and the second gate electrode are aligned along a first direction, and the The first gate electrode is aligned with the third gate electrode along a second direction, and the second direction is different from the first direction. The semiconductor component as described in claim 8 also includes: a fourth gate electrode disposed on the substrate, wherein the fourth gate electrode has the first conductivity type, the fourth gate electrode is aligned with the third gate electrode along the first direction, and The fourth gate electrode is aligned with the second gate electrode along the second direction. The semiconductor component as described in claim 8 also includes: a fourth gate electrode disposed on the substrate, wherein the fourth gate electrode has the second conductivity type, the fourth gate electrode is aligned with the third gate electrode along the first direction, and The fourth gate electrode is aligned with the second gate electrode along the second direction. The semiconductor component as described in claim 1 also includes: a third gate electrode disposed on the substrate, wherein the third gate electrode has the first conductivity type, the first gate electrode is aligned with the second gate electrode along a first direction, and The first gate electrode is aligned with the third gate electrode along a second direction, and the second direction is different from the first direction. The semiconductor component as described in claim 11 also includes: a fourth gate electrode disposed on the substrate, wherein the fourth gate electrode has the first conductivity type, the fourth gate electrode is aligned with the third gate electrode along the first direction, and The fourth gate electrode is aligned with the second gate electrode along the second direction. The semiconductor component as described in claim 11 also includes: a fourth gate electrode disposed on the substrate, wherein the fourth gate electrode has the second conductivity type, the fourth gate electrode is aligned with the third gate electrode along the first direction, and The fourth gate electrode is aligned with the second gate electrode along the second direction. A semiconductor component including: a base; A plurality of first gate electrodes and a plurality of second gate electrodes are arranged in an array on the substrate; a first dopant of a first conductivity type, wherein the first gate electrodes are doped with the first dopant; and A second dopant of a second conductivity type different from the first conductivity type, wherein the second gate electrodes are doped with the second dopant. The semiconductor device of claim 14, wherein the array includes a first column and a second column, and a number of the first gate electrodes in the first column is different from the number of the first gate electrodes in the second column. etc. a number of first gate electrodes. The semiconductor device of claim 14, wherein the array includes a first column and a second column, and an arrangement of the first gate electrodes and the second gate electrodes in the first column A configuration that is different from the first gate electrodes and the second gate electrodes in the second column. The semiconductor device of claim 16, wherein a number of the first gate electrodes in the first column is the same as a number of the first gate electrodes in the second column. The semiconductor device of claim 14, wherein at least one of the first gate electrodes includes a charge trapping material. The semiconductor device of claim 18, wherein at least one of the first gate electrodes includes polysilicon. The semiconductor device of claim 14, wherein a first transistor including the first gate electrode has a first critical voltage, and a second transistor including the second gate electrode has a second critical voltage. voltage, the second threshold voltage being different from the first threshold voltage; The first transistor has a first channel region in the substrate, the second transistor has a second channel region in the substrate, and at least one of the first dopant and the second dopant It is not doped in the first channel region and the second doped region.