TW202401822A - Semiconductor device having gate electrodes with dopant of different conductive types - Google Patents
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Abstract
Description
本申請案主張美國第17/844,971及17/845,776號專利申請案之優先權(即優先權日為「2022年6月21日」),其內容以全文引用之方式併入本文中。This application claims priority to U.S. Patent Application Nos. 17/844,971 and 17/845,776 (that is, the priority date is "June 21, 2022"), the contents of which are incorporated herein by reference in their entirety.
本揭露關於一種半導體元件。特別是有關於一種具有為不同導電類型摻雜物之閘極電極的半導體元件。The present disclosure relates to a semiconductor device. In particular, it relates to a semiconductor device having gate electrodes of dopants of different conductivity types.
隨著電子產業的快速發展,積體電路(ICs)的發展已經達到高效能以及小型化。在IC材料以及設計的技術進步產生了數個世代的ICs,而其每一世代均具有比上一世代更小、更複雜的電路。With the rapid development of the electronics industry, the development of integrated circuits (ICs) has reached high performance and miniaturization. Technological advances in IC materials and design have produced several generations of ICs, each with smaller and more complex circuits than the previous generation.
動態隨機存取記憶體(DRAM)將資料的每一位元儲存在一積體電路內的一單獨電容器中。通常,一DRAM以每一個單元之一個電容器以及一個電晶體而排列成一正方形陣列。一種垂直電晶體已經針對4F 2DRAM單元進行開發,其中F代表微影最小特徵寬度或臨界尺寸(CD)。RAM可廣泛地應用於多種元件,例如一次性可程式化(OTP)元件。 Dynamic random access memory (DRAM) stores each bit of data in a separate capacitor within an integrated circuit. Typically, a DRAM is arranged in a square array with one capacitor and one transistor per cell. A vertical transistor has been developed for 4F 2 DRAM cells, where F represents the lithographic minimum feature width or critical dimension (CD). RAM can be widely used in a variety of components, such as one-time programmable (OTP) components.
上文之「先前技術」說明僅提供背景技術,並未承認上文之「先前技術」說明揭示本揭露之標的,不構成本揭露之先前技術,且上文之「先前技術」之任何說明均不應作為本案之任一部分。The above description of "prior art" only provides background technology, and does not admit that the above description of "prior art" reveals the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and any description of the above "prior art" does not constitute the prior art of the present disclosure. should not be used as any part of this case.
本揭露之一實施例提供一種半導體元件。該半導體元件包括一基底、一第一閘極電極以及一第二閘極電極。該第一閘極電極設置在該基底上。該第一閘極電極摻雜有為一第一導電類型的一第一摻雜物。該第二閘極電極,設置在該基底上。該第二閘極電極摻雜有為一第二導電類型的一第二摻雜物,該第二導電類型不同於該第一導電類型。An embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a first gate electrode and a second gate electrode. The first gate electrode is disposed on the substrate. The first gate electrode is doped with a first dopant of a first conductivity type. The second gate electrode is disposed on the substrate. The second gate electrode is doped with a second dopant of a second conductivity type that is different from the first conductivity type.
本揭露之另一實施例提供一種半導體元件。該半導體元件包括一基底、多個第一閘極電極以及多個第二閘極電極。該多個第一閘極電極以及該多個第二閘極電極呈一陣列配置而且其中至少一個設置在該基底上。中該等第一閘極電極摻雜有為一第一導電類型的多個第一摻雜物。該等第二閘極電極摻雜有為一第二導電類型的多個第二摻雜物,該第二導電類型不同於該第一導電類型。Another embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a plurality of first gate electrodes and a plurality of second gate electrodes. The plurality of first gate electrodes and the plurality of second gate electrodes are arranged in an array and at least one of them is disposed on the substrate. The first gate electrodes are doped with a plurality of first dopants of a first conductivity type. The second gate electrodes are doped with a plurality of second dopants of a second conductivity type that is different from the first conductivity type.
本揭露之另一實施例提供一種半導體元件的製備方法。該製備方法包括提供一基底;形成多個閘極電極在該基底上;摻雜具有為一第一導電類型之一第一摻雜物的該多個閘極電極的一第一部分;以及摻雜具有為一第二導電類型之一第二摻雜物的該多個閘極電極的一第二部分,且該第二導電類型不同於該第一導電類型。Another embodiment of the present disclosure provides a method of manufacturing a semiconductor device. The preparation method includes providing a substrate; forming a plurality of gate electrodes on the substrate; doping a first portion of the plurality of gate electrodes with a first dopant that is a first conductivity type; and doping A second portion of the plurality of gate electrodes having a second dopant of a second conductivity type, and the second conductivity type is different from the first conductivity type.
本揭露的該等實施例提供一種半導體元件,該半導體元件具有為不同導電類型之摻雜物的閘極電極,藉此改良一電晶體的臨界電壓。因此,當包括具有不同導電類型之摻雜物的閘極電極的電晶體導通時,可測量不同的電流,以確定一較低的邏輯值「0」以及一較高的邏輯值「1」。結果,本揭露的半導體元件可經配置以產生用於識別的一編碼。Embodiments of the present disclosure provide a semiconductor device having a gate electrode with dopants of different conductivity types, thereby improving the threshold voltage of a transistor. Therefore, when a transistor including a gate electrode with dopants of different conductivity types is turned on, different currents can be measured to determine a lower logic value "0" and a higher logic value "1". As a result, the semiconductor device of the present disclosure can be configured to generate a code for identification.
上文已相當廣泛地概述本揭露之技術特徵及優點,俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解,可相當容易地利用下文揭示之概念與特定實施例可作為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解,這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.
現在使用特定語言描述附圖中所示之本揭露的實施例或例子。應當理解,本揭露的範圍無意由此受到限制。所描述之實施例的任何修改或改良,以及本文件中描述之原理的任何進一步應用,所屬技術領域中具有通常知識者都認為是通常會發生的。元件編號可在整個實施例中重複,但這並不一定意味著一個實施例的特徵適用於另一實施例,即使它們共享相同的元件編號。Specific language will now be used to describe the embodiments or examples of the present disclosure illustrated in the drawings. It should be understood that the scope of the present disclosure is not intended to be limited thereby. Any modifications or improvements to the described embodiments, as well as any further applications of the principles described in this document, are within the realm of ordinary skill in the art. Element numbering may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment apply to another embodiment even if they share the same element numbering.
應當理解,當一個元件被稱為「連接到(connected to)」或「耦接到(coupled to)」另一個元件時,則該初始元件可直接連接到或耦接到另一個元件,或是其他中間元件。It will be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be either directly connected or coupled to the other element, or other intermediate components.
應當理解,儘管這裡可以使用術語第一,第二,第三等來描述各種元件、部件、區域、層或區段(sections),但是這些元件、部件、區域、層或區段不受這些術語的限制。相反,這些術語僅用於將一個元件、組件、區域、層或區段與另一個區域、層或區段所區分開。因此,在不脫離本發明進步性構思的教導的情況下,下列所討論的第一元件、組件、區域、層或區段可以被稱為第二元件、組件、區域、層或區段。It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not governed by these terms. limits. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present progressive concept.
本文中使用之術語僅是為了實現描述特定實施例之目的,而非意欲限制本發明。如本文中所使用,單數形式「一(a)」、「一(an)」,及「該(the)」意欲亦包括複數形式,除非上下文中另作明確指示。將進一步理解,當術語「包括(comprises)」及/或「包括(comprising)」用於本說明書中時,該等術語規定所陳述之特徵、整數、步驟、操作、元件,及/或組件之存在,但不排除存在或增添一或更多個其他特徵、整數、步驟、操作、元件、組件,及/或上述各者之群組。The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and/or "comprising" are used in this specification, these terms specify the stated features, integers, steps, operations, elements, and/or components. exists, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups of the above.
應當理解,在本揭露的描述中,使用的術語「大約」(about)改變本揭露的成分、組成或反應物的數量,意指例如藉由用於製備濃縮物或溶液的典型測量以及液體處理程序而可能發生的數量變化。再者,在測量程序中的疏忽錯誤、用於製造組合物或實施方法之成分的製造、來源或純度的差異等可能會導致變化。在一方面,術語「大約」(about)是指在報告數值的10%以內。在另一個方面,術語「大約」(about)是指在報告數值的5%以內。進而,在另一方面,術語「大約」(about)是指在所報告數值的10、9、8、7、6、5、4、3、2或1%以內。It will be understood that in the description of the present disclosure, the term "about" is used to alter the amount of an ingredient, composition, or reactant of the present disclosure, meaning, for example, by typical measurements and liquid handling used to prepare concentrates or solutions. Quantity changes may occur due to the procedure. Furthermore, variations may result from inadvertent errors in measurement procedures, differences in the manufacture, source or purity of the ingredients used to make the compositions or practice the methods, and the like. In one aspect, the term "about" means within 10% of a reported value. In another aspect, the term "about" means within 5% of the reported value. Furthermore, in another aspect, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2 or 1% of the reported value.
圖1A是頂視示意圖,例示本揭露一些實施例之一半導體元件結構100的一佈局。FIG. 1A is a schematic top view illustrating a layout of a semiconductor device structure 100 according to some embodiments of the present disclosure.
在一些實施例中,半導體元件100可適用於多個半導體元件,其可包括主動元件及/或被動元件。主動元件可包括一記憶體元件(例如動態隨機存取記憶體(DRAM)元件、一次性可程式化(OTP)記憶體元件、一靜態隨機存取記憶體(SRAM)元件等)、一電源管理元件(例如電源管理積體電路(PMIC)元件)、一邏輯元件(例如系統上晶片(SoC)、中央處理單元(CPU)、圖形處理單元(GPU)、應用處理器(AP)、微控制器等)、一射頻(RF)元件、一感應器元件、一微機電系統(MEMS)元件、一訊號處理元件(例如數位訊號處理(DSP)元件)、一前端元件(例如類比前端(AFE)元件)或其他主動元件。被動元件可包括一電容器、一電阻器、一電感器、一熔絲或其他被動元件。In some embodiments, the semiconductor device 100 may be adapted to multiple semiconductor devices, which may include active devices and/or passive devices. Active components may include a memory component (such as a dynamic random access memory (DRAM) component, a one-time programmable (OTP) memory component, a static random access memory (SRAM) component, etc.), a power management A component (such as a power management integrated circuit (PMIC) component), a logic component (such as a system on chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), a microcontroller etc.), a radio frequency (RF) component, a sensor component, a microelectromechanical system (MEMS) component, a signal processing component (such as a digital signal processing (DSP) component), a front-end component (such as an analog front-end (AFE) component) ) or other active components. Passive components may include a capacitor, a resistor, an inductor, a fuse or other passive components.
在一些實施例中,半導體元件100可應用於一記憶體、記憶體元件、記憶體晶粒、記憶體晶片或其他元件。半導體元件100可為記憶體、記憶體元件、記憶體晶粒或記憶體晶片的一部分。舉例來說,記憶體可為一DRAM或一OTP記憶體。在一些實施例中,DRAM可為一雙倍資料速率第四代(DDR4)DRAM。在一些實施例中,記憶體可包括一或多個記憶體單元(或記憶體位元、記憶體塊)。In some embodiments, the semiconductor device 100 may be applied to a memory, memory device, memory die, memory chip, or other device. Semiconductor device 100 may be a memory, a memory device, a memory die, or part of a memory chip. For example, the memory may be a DRAM or an OTP memory. In some embodiments, the DRAM may be double data rate fourth generation (DDR4) DRAM. In some embodiments, memory may include one or more memory cells (or memory bits, memory blocks).
如圖1A所示,半導體元件100可包括一基底102、主動區111、112、113與114、閘極結構121與122,以及摻雜區1311、1312、1313、1321、1322、1323, 1331、1332、1333、1341、1342與1343。As shown in FIG. 1A , the semiconductor device 100 may include a substrate 102, active regions 111, 112, 113 and 114, gate structures 121 and 122, and doped regions 1311, 1312, 1313, 1321, 1322, 1323, 1331, 1332, 1333, 1341, 1342 and 1343.
主動區111-114的其中至少一個可沿一X軸延伸。主動區111-114的其中至少一個可沿著一Y軸配置並間隔開。主動區111-114可位在基底102內。兩個相鄰的主動區111-114可以藉由一絕緣結構(圖未示)而間隔開。舉例來說,該絕緣結構可為一淺溝槽隔離(STI)、矽一的局部氧化(LOCOS)結構或任何其他適合的絕緣結構。At least one of the active regions 111-114 may extend along an X-axis. At least one of the active regions 111-114 may be arranged and spaced apart along a Y-axis. Active regions 111-114 may be located within substrate 102. Two adjacent active regions 111-114 may be separated by an insulating structure (not shown). For example, the insulating structure may be a shallow trench isolation (STI), a local oxidation of silicon (LOCOS) structure, or any other suitable insulating structure.
閘極結構121與122的其中至少一個可設置在基底102上。閘極結構121與122的其中至少一個可沿Y軸延伸。閘極結構121與122的其中至少一個可沿著X軸配置並間隔開。At least one of the gate structures 121 and 122 may be disposed on the substrate 102 . At least one of the gate structures 121 and 122 may extend along the Y-axis. At least one of the gate structures 121 and 122 may be arranged and spaced apart along the X-axis.
摻雜區1311-1343的其中至少一個可設置在基底102中。在一些實施例中,摻雜區1312、1322、1332與1342之其中至少一個的面積A2可超過摻雜區1311、1321、1331、1341、1313、1323、1333與1343的面積A1。在一些實施例中,摻雜區1311、1312與1313以及閘極結構121與122可界定兩個電晶體。舉例來說,摻雜區1311、1312與閘極結構121可包括在一第一電晶體中,且摻雜區1312、1313與閘極結構122可包括在一第二電晶體中。摻雜區1312可為上述兩個電晶體的一共用源極或一共用汲極。At least one of the doped regions 1311 - 1343 may be disposed in the substrate 102 . In some embodiments, the area A2 of at least one of the doping regions 1312, 1322, 1332, and 1342 may exceed the area A1 of the doping regions 1311, 1321, 1331, 1341, 1313, 1323, 1333, and 1343. In some embodiments, doped regions 1311, 1312, and 1313 and gate structures 121 and 122 may define two transistors. For example, the doped regions 1311, 1312 and the gate structure 121 may be included in a first transistor, and the doped regions 1312, 1313 and the gate structure 122 may be included in a second transistor. The doped region 1312 may be a common source or a common drain of the two transistors.
圖1B是剖視示意圖,例示本揭露一些實施例如圖1A所示之半導體元件100沿剖線A-A’的剖面。FIG. 1B is a schematic cross-sectional view illustrating a cross-section along the cross-section line A-A' of the semiconductor device 100 shown in FIG. 1A according to some embodiments of the present disclosure.
如圖1B所示,閘極結構121與122可設置在基底102上。摻雜區1311、1312與1313可設置或形成在基底102內。在一些實施例中,摻雜區1311、1312與閘極結構121可界定一電晶體110-1。在一些實施例中,摻雜區1312、1313與閘極結構122可界定一電晶體110-2。電晶體110-1可包括在摻雜區1311與1312之間的一通道區141。電晶體110-2可包括在摻雜區1312與1313之間的一通道區142。在一些實施例中,摻雜區1312可為電晶體110-1與110-2的一共用源極或一共用汲極。As shown in FIG. 1B , gate structures 121 and 122 may be disposed on the substrate 102 . Doped regions 1311, 1312, and 1313 may be disposed or formed within the substrate 102. In some embodiments, the doped regions 1311, 1312 and the gate structure 121 may define a transistor 110-1. In some embodiments, the doped regions 1312, 1313 and the gate structure 122 may define a transistor 110-2. Transistor 110-1 may include a channel region 141 between doped regions 1311 and 1312. Transistor 110-2 may include a channel region 142 between doped regions 1312 and 1313. In some embodiments, the doped region 1312 may be a common source or a common drain of the transistors 110-1 and 110-2.
半導體元件100可包括多個間隙子(圖未示)。間隙子可設置在閘極結構121與122的側表面上。間隙子可包括一單層結構或一多層結構。間隙子可包括介電材料,例如氧化矽、氮化矽、氮氧化矽、其他介電材料或其組合。The semiconductor device 100 may include a plurality of spacers (not shown). Spacers may be disposed on side surfaces of the gate structures 121 and 122 . The spacer may include a single layer structure or a multi-layer structure. Spacers may include dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, other dielectric materials, or combinations thereof.
在一些實施例中,電晶體110-1與110-2的其中至少一個可為一N型金屬氧化物半導體(NMOS)或P型金屬氧化物半導體(PMOS)。在一些實施例中,摻雜區1311、1312與1313的其中至少一個可包括p型摻雜物,例如硼(B)、其他III族元素或其任何組合。在一些實施例中,摻雜區1311、1312與1313的其中至少一個可包括n型摻雜物,例如砷(As)、磷(P)、其他V族元素或其任意組合。In some embodiments, at least one of the transistors 110-1 and 110-2 may be an N-type metal oxide semiconductor (NMOS) or a P-type metal oxide semiconductor (PMOS). In some embodiments, at least one of the doped regions 1311, 1312, and 1313 may include a p-type dopant, such as boron (B), other Group III elements, or any combination thereof. In some embodiments, at least one of the doped regions 1311, 1312, and 1313 may include n-type dopants, such as arsenic (As), phosphorus (P), other group V elements, or any combination thereof.
半導體元件100還可包括一介電層150。介電層150可包括氧化矽(SiO x)、氮化矽(Si xN y)、氮氧化矽(SiON)、磷矽酸鹽玻璃(PSG)、硼磷矽酸鹽玻璃(BPSG)、一低k(介電常數)介電材料(k<4)或其他適合的材料。 The semiconductor device 100 may also include a dielectric layer 150 . The dielectric layer 150 may include silicon oxide (SiO x ), silicon nitride ( Six N y ), silicon oxynitride (SiON), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), a Low-k (dielectric constant) dielectric materials (k<4) or other suitable materials.
半導體元件100還可包括導電接觸點161、162、163、171與172。導電接觸點161可電性連接到摻雜區1311。導電接觸點162可電性連接到摻雜區1312。導電接觸點163可電性連接到摻雜區1313。導電接觸點171可電性連接到閘極結構121。導電接觸點172可電性連接到閘極結構122。導電接觸點可包括導電材料,例如鎢(W)、銅(Cu)、鋁(Al)、鉭(Ta)、鉬(Mo)、氮化鉭(TaN)、鈦、氮化鈦(TiN)或類似物,及/或其組合。The semiconductor device 100 may also include conductive contacts 161, 162, 163, 171, and 172. The conductive contact 161 may be electrically connected to the doped region 1311 . Conductive contact 162 may be electrically connected to doped region 1312 . The conductive contact 163 may be electrically connected to the doped region 1313 . The conductive contact 171 is electrically connected to the gate structure 121 . Conductive contact 172 may be electrically connected to gate structure 122 . The conductive contacts may include conductive materials such as tungsten (W), copper (Cu), aluminum (Al), tantalum (Ta), molybdenum (Mo), tantalum nitride (TaN), titanium, titanium nitride (TiN), or analogs, and/or combinations thereof.
在一些實施例中,閘極結構121與122可摻雜有不同導電類型的摻雜物。舉例來說,閘極結構121的閘極電極可摻雜有p型摻雜物,且閘極結構122的閘極電極可摻雜有n型摻雜物。In some embodiments, gate structures 121 and 122 may be doped with dopants of different conductivity types. For example, the gate electrode of the gate structure 121 may be doped with p-type dopants, and the gate electrode of the gate structure 122 may be doped with n-type dopants.
圖2A及圖2B是剖視示意圖,例示本揭露一些實施例之半導體元件100的閘極結構121與122。2A and 2B are schematic cross-sectional views illustrating the gate structures 121 and 122 of the semiconductor device 100 according to some embodiments of the present disclosure.
如圖2A及圖2B所示,閘極結構121可包括一閘極電介質1211以及在閘極電介質1211上方的一閘極電極1212。閘極結構122可包括一閘極電介質1221以及在閘極電介質1221上方的一閘極電極1222。As shown in FIGS. 2A and 2B , the gate structure 121 may include a gate dielectric 1211 and a gate electrode 1212 above the gate dielectric 1211 . The gate structure 122 may include a gate dielectric 1221 and a gate electrode 1222 above the gate dielectric 1221.
閘極電介質1211與1221的其中至少一個可具有一單層或一多層結構。在一些實施例中,閘極電介質1211與1221的其中至少一個可包括介電材料,例如氧化矽、氮化矽、氮氧化矽、其他介電材料或其組合。在一些實施例中,閘極電介質1211與1221的其中至少一個則為一多層結構,其包括一界面層與一高k(介電常數大於4)介電層。該界面層可包括介電材料,例如氧化矽、氮化矽、氮氧化矽、其他介電材料或其組合。該高k介電層可包括高k介電材料,例如HfO 2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、其他適合的高k介電材料或其組合。在一些實施例中,高k介電材料可進一步選自金屬氧化物、金屬氮化物、金屬矽酸鹽、過渡金屬氧化物、過渡金屬氮化物、過渡金屬矽酸鹽、金屬氮氧化物、金屬鋁酸鹽及其組合。 At least one of the gate dielectrics 1211 and 1221 may have a single layer or a multi-layer structure. In some embodiments, at least one of gate dielectrics 1211 and 1221 may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, other dielectric materials, or combinations thereof. In some embodiments, at least one of gate dielectrics 1211 and 1221 is a multilayer structure including an interface layer and a high-k (dielectric constant greater than 4) dielectric layer. The interface layer may include dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, other dielectric materials, or combinations thereof. The high-k dielectric layer may include a high-k dielectric material, such as HfO2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, other suitable high-k dielectric materials, or combinations thereof. In some embodiments, the high-k dielectric material may be further selected from metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal Aluminates and combinations thereof.
在一些實施例中,閘極電極1212與1222的其中至少一個可包括一電荷捕捉材料。如本文所用,電荷可指電子與電洞電荷。如本文所用,電荷捕捉材料可指可限制電子(或電洞)移動的一材料。在一些實施例中,閘極電極1212與1222的其中至少一個可包括一半導體材料或其他適合的材料。在一些實施例中,閘極電極1212與1222的其中至少一個可包括多晶矽或其他適合的半導體材料。In some embodiments, at least one of gate electrodes 1212 and 1222 may include a charge trapping material. As used herein, charge may refer to electron and hole charges. As used herein, a charge trapping material may refer to a material that can restrict the movement of electrons (or holes). In some embodiments, at least one of gate electrodes 1212 and 1222 may include a semiconductor material or other suitable material. In some embodiments, at least one of gate electrodes 1212 and 1222 may include polysilicon or other suitable semiconductor materials.
如圖2A所示,摻雜物181可摻雜在閘極結構121中。在一些實施例中,摻雜物181可摻雜在閘極結構121的閘極電極1212中。在一些實施例中,通道區141並未摻雜摻雜物181或沒有摻雜摻雜物。在一些實施例中,通道區141沒有摻雜物182。在一些實施例中,閘極介電質1211與1221的其中至少一個沒有摻雜物181。如圖2B所示,摻雜物182可摻雜在閘極結構122中。在一些實施例中,摻雜物182可摻雜在閘極結構122的閘極電極1222中。在一些實施例中,通道區142沒有摻雜物182。在一些實施例中,通道區142沒有摻雜物181。在一些實施例中,閘極介電質1211與1221的其中至少一個沒有摻雜物182。在一些實施例中,摻雜物181可為一第一導電類型,例如一p型。在一些實施例中,摻雜物182可為不同於該第一導電類型的一第二導電類型,例如一n型。As shown in FIG. 2A , dopants 181 may be doped in the gate structure 121 . In some embodiments, dopant 181 may be doped in gate electrode 1212 of gate structure 121 . In some embodiments, channel region 141 is not doped with dopant 181 or is not doped with dopants. In some embodiments, channel region 141 is free of dopants 182 . In some embodiments, at least one of gate dielectrics 1211 and 1221 is free of dopant 181 . As shown in FIG. 2B , dopants 182 may be doped into the gate structure 122 . In some embodiments, dopant 182 may be doped in gate electrode 1222 of gate structure 122 . In some embodiments, channel region 142 is free of dopants 182 . In some embodiments, channel region 142 is free of dopants 181 . In some embodiments, at least one of gate dielectrics 1211 and 1221 is free of dopant 182 . In some embodiments, dopant 181 may be a first conductivity type, such as a p-type. In some embodiments, dopant 182 may be a second conductivity type different from the first conductivity type, such as an n-type.
在一些實施例中,摻雜物181與182可用來修改電電晶110-1與110-2的臨界電壓。電晶體110-1具有一第一臨界電壓。電晶體110-2具有一第二臨界電壓。在一些實施例中,電晶體110-1的該第一臨界電壓可不同於電晶體110-2的該第二臨界電壓。在一些實施例中,電晶體110-1的該第一臨界電壓可低於電晶體110-2的該第二臨界電壓。In some embodiments, dopants 181 and 182 may be used to modify the threshold voltage of transistors 110-1 and 110-2. The transistor 110-1 has a first threshold voltage. The transistor 110-2 has a second threshold voltage. In some embodiments, the first threshold voltage of transistor 110-1 may be different from the second threshold voltage of transistor 110-2. In some embodiments, the first threshold voltage of transistor 110-1 may be lower than the second threshold voltage of transistor 110-2.
請往回參考圖1B,在一些實施例中,摻雜區1311可接收一更高的電壓,例如1.2V,摻雜區1312可電性連接到接地,且摻雜區1313可電性浮接。在此情況下,當電晶體110-1導通時可產生一第一電流。Please refer back to FIG. 1B. In some embodiments, the doped region 1311 can receive a higher voltage, such as 1.2V, the doped region 1312 can be electrically connected to ground, and the doped region 1313 can be electrically floating. . In this case, a first current can be generated when the transistor 110-1 is turned on.
在一些實施例中,摻雜區1311可為電性浮接,摻雜區1312可電性連接到接地,且摻雜區1313可接收一更高的電壓,例如1.2V。在此情況下,當電晶體110-2導通時可產生一第二電流。In some embodiments, the doped region 1311 can be electrically floating, the doped region 1312 can be electrically connected to ground, and the doped region 1313 can receive a higher voltage, such as 1.2V. In this case, a second current can be generated when the transistor 110-2 is turned on.
由於電晶體110-1與110-2的臨界電壓不同,因此該第一電流與該第二電流不同。在一些實施例中,可基於電晶體導通時的該電流以確定為例如「1」與「0」之類的邏輯值。意即,當電晶體110-1或110-2導通時,可確定為高邏輯值「1」或低邏輯值「0」。舉例來說,當電晶體110-1導通時,確定為一高邏輯值「1」,而當電晶體110-2導通時,確定為一低邏輯值「0」。Since the threshold voltages of the transistors 110-1 and 110-2 are different, the first current and the second current are different. In some embodiments, logic values such as "1" and "0" may be determined based on the current when the transistor is turned on. That is, when the transistor 110-1 or 110-2 is turned on, it can be determined to be a high logic value “1” or a low logic value “0”. For example, when the transistor 110-1 is turned on, a high logic value "1" is determined, and when the transistor 110-2 is turned on, a low logic value "0" is determined.
此外,半導體元件100可包含一電容(圖未示),用以儲存邏輯值「1」或「0」。舉例來說,在一讀取操作期間,可確立電性耦合到或連接到閘極結構121或122的一字元線,以導通電晶體110-1或110-2。致能電晶體110-1或110-2允許經由一位元線而藉由一感測放大器讀取跨經該電容器之兩端的該電壓。在一寫入操作期間,當確立該字元線時,可在該位元線上提供所要寫入的資料。In addition, the semiconductor device 100 may include a capacitor (not shown) for storing a logic value “1” or “0”. For example, during a read operation, a word line electrically coupled or connected to gate structure 121 or 122 may be established to turn on transistor 110-1 or 110-2. Enable transistor 110-1 or 110-2 allows the voltage across the capacitor to be read by a sense amplifier via a bit line. During a write operation, when the word line is asserted, the data to be written is provided on the bit line.
在一比較的半導體元件中,電晶體的臨界電壓藉由燒入閘極介電質進行改變。在本發明的實施例中,可藉由在閘極電極中摻雜不同導電類型的摻雜物以改變臨界電壓。具有n型摻雜物或p型摻雜物之閘極結構的排列(或分佈)可藉由一定制的光罩進行預先確定,該光罩可確定邏輯值「1」或「0」的排列(或分佈)。結果,半導體元件100可經配置以產生用於識別的一編碼。In a comparative semiconductor device, the threshold voltage of a transistor is changed by burning in the gate dielectric. In embodiments of the present invention, the threshold voltage can be changed by doping dopants of different conductivity types into the gate electrode. The arrangement (or distribution) of gate structures with n-type dopants or p-type dopants can be predetermined by a custom mask that determines the arrangement of logic values "1" or "0" (or distribution). As a result, semiconductor device 100 may be configured to generate a code for identification.
圖3是頂視示意圖,例示本揭露一些實施例的一半導體元件200。應當理解,為了簡潔,圖3中省略一些元件,且半導體元件200還可包括其他元件。FIG. 3 is a top view schematic diagram illustrating a semiconductor device 200 according to some embodiments of the present disclosure. It should be understood that some elements are omitted from FIG. 3 for simplicity, and the semiconductor device 200 may also include other elements.
如圖3所示,半導體元件200可包括閘極電極2111、2112、2113、2114、2115、2121、2122、2123、2124、2125、2131、2132、2133、2134、2135、2141、2142、2143、2144與2145的一陣列220。閘極電極2111-2145的其中至少一個可包括在電晶體中。As shown in FIG. 3 , the semiconductor element 200 may include gate electrodes 2111, 2112, 2113, 2114, 2115, 2121, 2122, 2123, 2124, 2125, 2131, 2132, 2133, 2134, 2135, 2141, 2142, 2143, An array 220 of 2144 and 2145. At least one of gate electrodes 2111-2145 may be included in the transistor.
陣列220可包括列221、222、223與224。列221-224的其中至少一個可包括五個閘極電極。列的數量以及在一列中之閘極電極的數量僅是舉例,且本揭露公開並不意旨以此為限。閘極電極2111-2145的圖案(或點)可用於識別將何種類型的摻雜物雜到閘極電極2111-2145中。舉例來說,閘極電極2111、2112、2113、2114、2115、2121、2124、2125、2131、2132、2135、2143與2145可在其中摻雜n型摻雜物,並可以分組為「閘極電極210-1」。閘極電極2122、2123、2133、2134、2141、2142與2144可在其中具有p型摻雜物的摻雜物,並且可以分組為「閘極電極210-2」。Array 220 may include columns 221, 222, 223, and 224. At least one of columns 221-224 may include five gate electrodes. The number of columns and the number of gate electrodes in a column are examples only, and the disclosure is not intended to be limited thereto. The pattern (or dots) of the gate electrodes 2111-2145 can be used to identify what type of dopant is incorporated into the gate electrodes 2111-2145. For example, gate electrodes 2111, 2112, 2113, 2114, 2115, 2121, 2124, 2125, 2131, 2132, 2135, 2143, and 2145 may have n-type dopants doped therein and may be grouped into "gate electrodes" Electrode 210-1". Gate electrodes 2122, 2123, 2133, 2134, 2141, 2142, and 2144 may have dopants of p-type dopants therein, and may be grouped into "gate electrodes 210-2."
在一些實施例中,列221-224可具有不同數量的閘極電極210-1與210-2。舉例來說,列221可具有五個閘極電極210-1,列222可具有三個閘極電極210-1。在一些實施例中,列221-224可具有不同數量的閘極電極210-2。舉例來說,列223可具有兩個閘極電極210-2,列224可具有三個閘極電極210-2。In some embodiments, columns 221-224 may have different numbers of gate electrodes 210-1 and 210-2. For example, column 221 may have five gate electrodes 210-1 and column 222 may have three gate electrodes 210-1. In some embodiments, columns 221-224 may have different numbers of gate electrodes 210-2. For example, column 223 may have two gate electrodes 210-2 and column 224 may have three gate electrodes 210-2.
如前所述,當閘極電極摻雜不同類型的摻雜物時,可改變電晶體的臨界電壓。意即,一個包括閘極電極210-1的電晶體以及另一個包括閘極電極210-2的電晶體可具有不同的臨界電壓。舉例來說,包括閘極電極210-1的電晶體可具有一較高的臨界電壓,並且包括閘極電極210-2的電晶體可具有一較低的臨界電壓。因此,當包括閘極電極210-1的電晶體導通時,可測量到一較低的電流,以確定一較低的邏輯值「0」。當包括閘極電極210-2的電晶體導通時,可測量到一更高的電流,以確定一更高的邏輯值「1」。As mentioned earlier, when the gate electrode is doped with different types of dopants, the critical voltage of the transistor can be changed. That is, one transistor including gate electrode 210-1 and another transistor including gate electrode 210-2 may have different threshold voltages. For example, a transistor including gate electrode 210-1 may have a higher threshold voltage, and a transistor including gate electrode 210-2 may have a lower threshold voltage. Therefore, when the transistor including gate electrode 210-1 is turned on, a lower current can be measured to determine a lower logic value "0". When the transistor including gate electrode 210-2 is turned on, a higher current can be measured to determine a higher logic value "1".
在一些實施例中,每一列221-224可具有閘極電極210-1與210-2的不同配置(或分佈)。閘極電極210-1與210-2的配置可經配置以儲存資訊或資料。儲存的資訊或資料可在一處理器讀取或執行時產生編碼、一功能或一標識。參考圖4,對應於如圖3所示之半導體元件200的邏輯資訊300可以包括位元串321、322、323與324。位元串321-324的其中至少一個可包括由邏輯值「0」、「1」及其組合所組成的五個邏輯值。舉例來說,位元串321可由「0」、「0」、「0」、「0」、「0」依序所組成,位元串322可由「0」、「1」、「1」、「0」以及「0」依序所組成。In some embodiments, each column 221-224 may have a different configuration (or distribution) of gate electrodes 210-1 and 210-2. The arrangement of gate electrodes 210-1 and 210-2 may be configured to store information or data. The stored information or data can generate a code, a function or an identifier when read or executed by a processor. Referring to FIG. 4 , the logic information 300 corresponding to the semiconductor device 200 shown in FIG. 3 may include bit strings 321 , 322 , 323 and 324 . At least one of the bit strings 321-324 may include five logical values composed of logical values "0", "1" and combinations thereof. For example, the bit string 321 may be composed of "0", "0", "0", "0", and "0" in sequence, and the bit string 322 may be composed of "0", "1", "1", It is composed of "0" and "0" in sequence.
在一些實施例中,邏輯資訊300的一部分可用作識別的一編碼。舉例來說,一列邏輯資訊300可作為識別的一編碼。在其他實施例中,邏輯資訊300的一部分可用作用於識別的一編碼。在一些實施例中,邏輯資訊300的2×2陣列可以用作用於識別的一編碼。在2×2陣列中,4位元資料可由邏輯值「0」與「1」的16個排列來表示,其中至少一個對應於閘及電極210-1與210-2的排列。請往回參考圖3,閘極電極2121、2122、2131與2132可藉界定2×2陣列,並分別對應於邏輯值「0」、「1」、「0」與「0」。一陣列之邏輯值的排列可作為識別的一編碼。上述陣列可為M×N陣列,其中M與N的其中至少一個為一實數或一正整數。In some embodiments, a portion of the logical information 300 may be used as a code for identification. For example, a sequence of logical information 300 can be used as a code for identification. In other embodiments, a portion of the logical information 300 may be used as a code for identification. In some embodiments, a 2×2 array of logical information 300 may be used as an encoding for identification. In a 2×2 array, 4-bit data can be represented by 16 arrangements of logical values “0” and “1”, at least one of which corresponds to an arrangement of gates and electrodes 210-1 and 210-2. Referring back to FIG. 3 , gate electrodes 2121 , 2122 , 2131 and 2132 may define a 2×2 array and correspond to logic values “0”, “1”, “0” and “0” respectively. The arrangement of logical values in an array can be used as a code for identification. The above array may be an M×N array, where at least one of M and N is a real number or a positive integer.
在其他實施例中,閘極電極210-1與210-2可用於執行邏輯運算,例如一XOR邏輯運算(或其互補XNOR)、一NAND邏輯運算(或其互補AND)或一NOR 邏輯運算(或其互補OR)。舉例來說,當一電路包括閘極電極210-1及/或210-2時,可實現識別OR功能、NAND功能以及XNOR功能,這三個操作分別是上述邏輯操作的互補操作。In other embodiments, gate electrodes 210-1 and 210-2 may be used to perform logic operations, such as an XOR logic operation (or its complement XNOR), a NAND logic operation (or its complement AND), or a NOR logic operation ( or its complement OR). For example, when a circuit includes gate electrodes 210-1 and/or 210-2, it can realize the identification of OR function, NAND function and XNOR function. These three operations are respectively complementary operations of the above-mentioned logical operations.
圖5是流程示意圖,例示本揭露一些實施例之一半導體元件的製備方法400。FIG. 5 is a schematic flowchart illustrating a method 400 for manufacturing a semiconductor device according to some embodiments of the present disclosure.
製備方法400開始步驟402,其提供一基底。The preparation method 400 begins with step 402, which provides a substrate.
製備方法400以步驟404繼續,其中形成多個閘極結構。至少一個閘極結構可包括一閘極介電質以及形成在其上的一閘極電極。步驟404還可包括形成多個摻雜區在該基底中以界定多個電晶體。一些摻雜區可為兩個相鄰電晶體的一共用源極或一共用汲極。步驟404還可包括在形成一介電層在該基底上方以覆蓋該閘極電極。The method 400 continues with step 404 where a plurality of gate structures are formed. At least one gate structure may include a gate dielectric and a gate electrode formed thereon. Step 404 may also include forming a plurality of doped regions in the substrate to define a plurality of transistors. Some doped regions may be a common source or a common drain of two adjacent transistors. Step 404 may also include forming a dielectric layer over the substrate to cover the gate electrode.
製備方法400以步驟406繼續,其中形成該介電層的多個開口。該等開口可暴露該等摻雜區及/或該等閘極電極。The method 400 continues with step 406 where a plurality of openings of the dielectric layer are formed. The openings may expose the doped regions and/or the gate electrodes.
製備方法400以步驟408繼續,其中提供一第一光罩。該第一光罩暴露該等閘極電極的一第一部分,而該等閘極電極的一第二部分被該第一光罩所覆蓋。步驟408還可包括以一第一導電類型的摻雜物摻雜該等閘極電極的該第一部分。步驟408還可包括形成一感光材料以覆蓋該介電層。該感光材料經過該第一光照而暴露,形成由該感光材料所界定的多個第一開口。具有該第一導電類型的摻雜物可經由該感光材料的該等第一開口而摻雜到該等閘極電極的該第一部分中。The manufacturing method 400 continues with step 408, where a first photomask is provided. The first photomask exposes a first portion of the gate electrodes, and a second portion of the gate electrodes is covered by the first photomask. Step 408 may also include doping the first portion of the gate electrodes with a first conductivity type dopant. Step 408 may also include forming a photosensitive material to cover the dielectric layer. The photosensitive material is exposed by the first light to form a plurality of first openings defined by the photosensitive material. Dopants having the first conductivity type may be doped into the first portions of the gate electrodes through the first openings of the photosensitive material.
製備方法400以步驟410繼續,其中移除該第一光罩。此外,移除該感光材料。暴露該等閘極電極的該第一部分與該等閘極電極的該第二部分。The method 400 continues with step 410, where the first photomask is removed. Additionally, the photosensitive material is removed. The first portions of the gate electrodes and the second portions of the gate electrodes are exposed.
製備方法400以步驟412繼續,其中提供一第二光罩。該第二光罩暴露出該等閘極電極的該第二部分,而該等閘極電極的該第一部分被該第二光罩所覆蓋。步驟412還可包括用不同於該第一導電類型之一第二導電類型的摻雜物對該等閘極電極的該第二部分進行摻雜。步驟412還可包括形成一感光材料以覆蓋該介電層。該感光材料經由該第二光罩而暴露,形成由該感光材料所界定的多個第二開口。具有該第二導電類型的摻雜物可以經由該等第二開口而摻雜到該等閘極電極的該第二部分中。The method 400 continues with step 412, where a second photomask is provided. The second photomask exposes the second portions of the gate electrodes, and the first portions of the gate electrodes are covered by the second photomask. Step 412 may also include doping the second portions of the gate electrodes with a dopant of a second conductivity type that is different from the first conductivity type. Step 412 may also include forming a photosensitive material to cover the dielectric layer. The photosensitive material is exposed through the second photomask, forming a plurality of second openings defined by the photosensitive material. A dopant having the second conductivity type may be doped into the second portion of the gate electrodes via the second openings.
製備方法400以步驟414繼續,其中移除該第二光罩。此外,移除該感光材料。暴露該等閘極電極的該第一部分與該等閘極電極的該第二部分。The method 400 continues with step 414, where the second photomask is removed. Additionally, the photosensitive material is removed. The first portions of the gate electrodes and the second portions of the gate electrodes are exposed.
製備方法400以步驟416繼續,其中形成多個導電通孔以填充該介電層的該等開口,藉此生產該半導體元件。The method 400 continues with step 416 , wherein a plurality of conductive vias are formed to fill the openings of the dielectric layer, thereby producing the semiconductor device.
製備方法400可用於確定具有不同導電類型之摻雜物的該等閘極電極的一排列(或分佈),藉此確定邏輯值「1」或「0」的排列(或分佈)。結果,製備方法400可經配置以產生用於識別的一編碼。The preparation method 400 can be used to determine an arrangement (or distribution) of the gate electrodes with dopants of different conductivity types, thereby determining the arrangement (or distribution) of the logical values "1" or "0". As a result, preparation method 400 may be configured to generate a code for identification.
製備方法400僅是例子,並不意旨在將本揭露限制在申請專利範圍請求項中明確記載的範圍之外。可在製備方法400的每一個步驟之前、期間或之後提供額外的步驟,並且對於方法的額外實施例,可替換、消除或移動所描述的一些步驟。在一些實施例中,製備方法400可包括圖5中未描繪的另一步驟。在一些實施例中,製備方法400可包括圖5中所描繪的一或多個步驟。The preparation method 400 is only an example and is not intended to limit the present disclosure beyond the scope expressly stated in the claims. Additional steps may be provided before, during, or after each step of preparation method 400, and some of the steps described may be replaced, eliminated, or moved for additional embodiments of the method. In some embodiments, preparation method 400 may include another step not depicted in Figure 5. In some embodiments, preparation method 400 may include one or more steps depicted in FIG. 5 .
圖6A、圖7A、圖8A、圖9A、圖10A、圖11A、圖12A及圖13A是示意圖,例示本揭露一些實施例之半導體元件的製備方法的一例子之一或多個階段;以及圖6B、圖7B、圖8B、圖9B、圖10B、圖11B、圖12B及圖13B是剖視示意圖,例示分別沿著圖6A、圖7A、圖8A、圖9A、圖10A、圖11A、圖12A及圖13A之剖線B-B’的剖面。應當理解,為了簡潔,圖6B、圖7B、圖8B、圖9B、圖10B、圖11B、圖12B以及圖13B中省略一些元件。6A, 7A, 8A, 9A, 10A, 11A, 12A and 13A are schematic diagrams illustrating one or more stages of an example of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure; and FIG. 6B, FIG. 7B, FIG. 8B, FIG. 9B, FIG. 10B, FIG. 11B, FIG. 12B and FIG. 13B are schematic cross-sectional views, illustrated respectively along the lines of FIG. 6A, FIG. 7A, FIG. 8A, FIG. 9A, FIG. 10A, FIG. 11A, FIG. 12A and the cross-section along line BB' in Figure 13A. It should be understood that for the sake of simplicity, some elements are omitted from FIGS. 6B, 7B, 8B, 9B, 10B, 11B, 12B, and 13B.
請參考圖6A及圖6B,提供一基底202。基底202可具有一井區(圖未示)。多個絕緣結構(圖未示)可形成在該基底中。作為一個例子,形成該絕緣結構可包括一微影製程,以暴露該基底的一部分、蝕刻一溝槽在該基襯底的暴露部分中(例如藉由使用一乾式蝕刻及/或一濕式蝕刻)、用一或多種介電材料填充該溝槽(例如藉由使用一化學氣相沉積製程),以及藉由一研磨製程,例如化學機械研磨(CMP)製程,而平坦化該基底並移除該介電材料的多餘部分。在一些例子中,所填充的溝槽可具有一多層結構,例如一熱氧化物襯墊層以及氮化矽或氧化矽的多個填充層。Referring to FIGS. 6A and 6B , a substrate 202 is provided. The substrate 202 may have a well region (not shown). A plurality of insulating structures (not shown) may be formed in the substrate. As an example, forming the insulating structure may include a lithography process to expose a portion of the base substrate, etching a trench in the exposed portion of the base substrate (e.g., by using a dry etch and/or a wet etch ), filling the trench with one or more dielectric materials (e.g., by using a chemical vapor deposition process), and planarizing and removing the substrate by a grinding process, such as a chemical mechanical polishing (CMP) process The excess portion of the dielectric material. In some examples, the filled trench may have a multi-layer structure, such as a thermal oxide liner layer and multiple fill layers of silicon nitride or silicon oxide.
請參考圖7A及圖7B,形成多個閘極結構。至少一個閘極結構可包括閘極電極2111-2145的其中之一。閘極電極2111-2145的製作技術可包含化學氣相沉積(CVD)、原子層沉積(ALD)、物理氣相沉積(PVD)、低壓化學氣相沉積(LPCVD)或其他適合的製程。例如2311、2312與2313的摻雜區可形成在基底202中。摻雜區2312的面積可超過摻雜區2311或2313的面積。摻雜區2311、閘極電極2123以及摻雜區2312可用於界定一電晶體220-1。摻雜區2312、閘極電極2124以及摻雜區2313可用於界定一電晶體220-2。在一些實施例中,摻雜區2312可為電晶體220-1與220-2的一共用源極或一共用汲極。可在基底202上方形成一介電層250以覆蓋閘極電極2123與2124。介電層250的製作技術可包含CVD、ALD、PVD、LPCVD或其他適合的製程。Please refer to FIG. 7A and FIG. 7B to form multiple gate structures. At least one gate structure may include one of gate electrodes 2111-2145. The manufacturing technology of the gate electrodes 2111-2145 may include chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low pressure chemical vapor deposition (LPCVD), or other suitable processes. Doped regions such as 2311, 2312 and 2313 may be formed in the substrate 202. The area of the doped region 2312 may exceed the area of the doped region 2311 or 2313. Doped region 2311, gate electrode 2123 and doped region 2312 may be used to define a transistor 220-1. Doped region 2312, gate electrode 2124, and doped region 2313 may be used to define a transistor 220-2. In some embodiments, the doped region 2312 may be a common source or a common drain of the transistors 220-1 and 220-2. A dielectric layer 250 may be formed over the substrate 202 to cover the gate electrodes 2123 and 2124. The manufacturing technology of the dielectric layer 250 may include CVD, ALD, PVD, LPCVD or other suitable processes.
請參圖8A及圖8B,形成開口250o1、250o2、250o3、250o4與250o5。開口250o1穿透介電層250並暴露摻雜區2311。開口 250o2 穿透介電層250的一部分並暴露閘極電極 2123。開口250o3穿透介電層250並暴露摻雜區2312。開口 250o4 穿透介電層 250 的一部分並暴露閘極電極 2124。開口250o5穿透介電層250並暴露摻雜區2313。開口250o1-250o5的製作技術可包含蝕刻製程,例如一乾式蝕刻或一濕式蝕刻。在其他實施例中,開口250-1-250-5可在不同的步驟中所形成,本揭露並非用於進行限制。Referring to Figure 8A and Figure 8B, openings 250o1, 250o2, 250o3, 250o4 and 250o5 are formed. The opening 250o1 penetrates the dielectric layer 250 and exposes the doped region 2311. Opening 250o2 penetrates a portion of dielectric layer 250 and exposes gate electrode 2123. Opening 250o3 penetrates dielectric layer 250 and exposes doped region 2312. Opening 250o4 penetrates a portion of dielectric layer 250 and exposes gate electrode 2124. The opening 250o5 penetrates the dielectric layer 250 and exposes the doped region 2313. The manufacturing technology of the openings 250o1-250o5 may include an etching process, such as a dry etching or a wet etching. In other embodiments, the openings 250-1-250-5 may be formed in different steps, and this disclosure is not intended to be limiting.
請參考圖9A及圖9B,提供一光罩E1。光罩E1暴露該等閘極電極的一部分,例如閘極電極2111、2112、2113、2114、2115、2121、2124、2125、2131、2132、2135、2143與2145。該等閘極電極的其他部分,例如閘極電極2122、2123、2133、2134、2141、2142與2144則被光罩E1所覆蓋。Please refer to FIG. 9A and FIG. 9B to provide a photomask E1. The photomask E1 exposes a portion of the gate electrodes, such as the gate electrodes 2111, 2112, 2113, 2114, 2115, 2121, 2124, 2125, 2131, 2132, 2135, 2143, and 2145. Other parts of the gate electrodes, such as the gate electrodes 2122, 2123, 2133, 2134, 2141, 2142 and 2144, are covered by the photomask E1.
在一些實施例中,一感光材料M1可形成在介電層250上。感光材料M1可包括一負性光阻或一正性光阻。感光材料M1可經由光罩E1而暴露,形成多個開口o1以暴露閘極電極2111、2112、2113、2114、2115、2121、2124、2125、2131、2132、2135、2143與2145。可執行一摻雜製程P1以用摻雜物D1摻雜閘極電極2111、2112、2113、2114、2115、2121、2124、2125、2131、2132、2135、2143與2145。在一些實施例中,摻雜物D1可為一第一導電類型,例如n型。摻雜物D1可經由該等開口o1而摻雜到閘極電極2111、2112、2113、2114、2115、2121、2124、2125、2131、2132、2135、2143與2145中。在一些實施例中,開口250o1、250o2、250o3與250o5可填充有感光材料M1或其他適合的材料。在其他實施例中,開口250o1、250o3與250o5可在閘極電極2111-2145摻雜有不同導電類型的摻雜物之後而形成。In some embodiments, a photosensitive material M1 may be formed on the dielectric layer 250 . The photosensitive material M1 may include a negative photoresist or a positive photoresist. The photosensitive material M1 may be exposed through the photomask E1 to form a plurality of openings o1 to expose the gate electrodes 2111, 2112, 2113, 2114, 2115, 2121, 2124, 2125, 2131, 2132, 2135, 2143 and 2145. A doping process P1 may be performed to dope the gate electrodes 2111, 2112, 2113, 2114, 2115, 2121, 2124, 2125, 2131, 2132, 2135, 2143, and 2145 with the dopant D1. In some embodiments, dopant D1 may be a first conductivity type, such as n-type. The dopant D1 can be doped into the gate electrodes 2111, 2112, 2113, 2114, 2115, 2121, 2124, 2125, 2131, 2132, 2135, 2143 and 2145 through the openings o1. In some embodiments, openings 250o1, 250o2, 250o3, and 250o5 may be filled with photosensitive material M1 or other suitable materials. In other embodiments, the openings 250o1, 250o3, and 250o5 may be formed after the gate electrodes 2111-2145 are doped with dopants of different conductivity types.
請參考圖10A及圖10B,可移除光罩E1與感光材料M1。可暴露閘極電極2111-2145。摻雜有摻雜物D1的閘極電極可分組為「閘極電極210-1」。Please refer to Figure 10A and Figure 10B, the removable mask E1 and the photosensitive material M1. Gate electrodes 2111-2145 may be exposed. The gate electrodes doped with dopant D1 may be grouped as "gate electrodes 210-1."
請參考圖11A及圖11B,提供一光罩E2。在一些實施例中,光罩E2的圖案可不同於光罩E1的圖案。光罩E2暴露部分閘極電極,例如閘極電極2122、2123、2133、2134、2141、2142與2144。用摻雜物D1摻雜的閘極電極的其他部分,例如閘極電極2111、2112、2113、2114、2115、2121、2124、2125、2131、2132、2135、2143與2145則被光罩E2所覆蓋。Please refer to FIG. 11A and FIG. 11B to provide a photomask E2. In some embodiments, the pattern of reticle E2 may be different from the pattern of reticle E1. The photomask E2 exposes part of the gate electrodes, such as the gate electrodes 2122, 2123, 2133, 2134, 2141, 2142 and 2144. Other parts of the gate electrode doped with the dopant D1, such as the gate electrodes 2111, 2112, 2113, 2114, 2115, 2121, 2124, 2125, 2131, 2132, 2135, 2143 and 2145 are covered by the photomask E2 Cover.
在一些實施例中,一感光材料M2可形成在介電層250上。感光材料M2可包括一負性光阻或一正性光阻。感光材料M2可經由光罩E2而暴露,形成多個開口o2以暴露閘極電極2122、2123、2133、2134、2141、2142與2144。可執行一摻雜製程P2以用摻雜物D2摻雜閘極電極2122、2123、2133、2134、2141、2142與2144。在一些實施例中,摻雜物D2可為一第二導電類型,例如p型。摻雜物D2可經由該等開口o2而摻雜到閘極電極2122、2123、2133、2134、2141、2142與2144中。在一些實施例中,開口250o1、250o3、250o4與250o5可填充有感光材料M2或其他適合的材料。In some embodiments, a photosensitive material M2 may be formed on the dielectric layer 250 . The photosensitive material M2 may include a negative photoresist or a positive photoresist. The photosensitive material M2 may be exposed through the photomask E2 to form a plurality of openings o2 to expose the gate electrodes 2122, 2123, 2133, 2134, 2141, 2142 and 2144. A doping process P2 may be performed to dope the gate electrodes 2122, 2123, 2133, 2134, 2141, 2142, and 2144 with the dopant D2. In some embodiments, dopant D2 may be a second conductivity type, such as p-type. The dopant D2 can be doped into the gate electrodes 2122, 2123, 2133, 2134, 2141, 2142 and 2144 through the openings o2. In some embodiments, openings 250o1, 250o3, 250o4, and 250o5 may be filled with photosensitive material M2 or other suitable materials.
請參考圖12A及圖12B,可移除光罩E2與感光材料M2。可暴露閘極電極2111-2145。摻雜有摻雜物D2的閘極電極可分組為「閘極電極210-2」。Please refer to Figure 12A and Figure 12B, the removable mask E2 and the photosensitive material M2. Gate electrodes 2111-2145 may be exposed. The gate electrodes doped with dopant D2 may be grouped as "gate electrodes 210-2."
請參考圖13A及圖13B,可形成導電接觸點261、262、263、271與272以填充開口250o1-250o5,藉此製造半導體元件200。導電接觸點261、262、263、271與272的製作技術可包含例如一PVD製程。Referring to FIGS. 13A and 13B , conductive contacts 261 , 262 , 263 , 271 and 272 can be formed to fill the openings 250o1 - 250o5 , thereby manufacturing the semiconductor device 200 . The manufacturing technology of the conductive contacts 261, 262, 263, 271 and 272 may include, for example, a PVD process.
圖6A-13A及圖6B-13B所示的各階段可用於確定閘極電極 210-1與210-2的排列(或分佈),藉此確定邏輯值「1」或「0」。結果,半導體元件200可經配置以產生用於識別的一編碼。The stages shown in Figures 6A-13A and 6B-13B can be used to determine the arrangement (or distribution) of the gate electrodes 210-1 and 210-2, thereby determining the logic value "1" or "0". As a result, semiconductor device 200 may be configured to generate a code for identification.
本揭露之一實施例提供一種半導體元件。該半導體元件包括一基底、一第一閘極電極以及一第二閘極電極。該第一閘極電極設置在該基底上。該第一閘極電極摻雜有為一第一導電類型的一第一摻雜物。該第二閘極電極,設置在該基底上。該第二閘極電極摻雜有為一第二導電類型的一第二摻雜物,該第二導電類型不同於該第一導電類型。An embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a first gate electrode and a second gate electrode. The first gate electrode is disposed on the substrate. The first gate electrode is doped with a first dopant of a first conductivity type. The second gate electrode is disposed on the substrate. The second gate electrode is doped with a second dopant of a second conductivity type that is different from the first conductivity type.
本揭露之另一實施例提供一種半導體元件。該半導體元件包括一基底、多個第一閘極電極以及多個第二閘極電極。該多個第一閘極電極以及該多個第二閘極電極呈一陣列配置而且其中至少一個設置在該基底上。中該等第一閘極電極摻雜有為一第一導電類型的多個第一摻雜物。該等第二閘極電極摻雜有為一第二導電類型的多個第二摻雜物,該第二導電類型不同於該第一導電類型。Another embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a plurality of first gate electrodes and a plurality of second gate electrodes. The plurality of first gate electrodes and the plurality of second gate electrodes are arranged in an array and at least one of them is disposed on the substrate. The first gate electrodes are doped with a plurality of first dopants of a first conductivity type. The second gate electrodes are doped with a plurality of second dopants of a second conductivity type that is different from the first conductivity type.
本揭露之另一實施例提供一種半導體元件的製備方法。該製備方法包括提供一基底;形成多個閘極電極在該基底上;摻雜具有為一第一導電類型之一第一摻雜物的該多個閘極電極的一第一部分;以及摻雜具有為一第二導電類型之一第二摻雜物的該多個閘極電極的一第二部分,且該第二導電類型不同於該第一導電類型。Another embodiment of the present disclosure provides a method of manufacturing a semiconductor device. The preparation method includes providing a substrate; forming a plurality of gate electrodes on the substrate; doping a first portion of the plurality of gate electrodes with a first dopant that is a first conductivity type; and doping A second portion of the plurality of gate electrodes having a second dopant of a second conductivity type, and the second conductivity type is different from the first conductivity type.
本揭露的該等實施例提供一種半導體元件,該半導體元件具有為不同導電類型之摻雜物的閘極電極,藉此改良一電晶體的臨界電壓。因此,當包括具有不同導電類型之摻雜物的閘極電極的電晶體導通時,可測量不同的電流,以確定一較低的邏輯值「0」以及一較高的邏輯值「1」。結果,本揭露的半導體元件可經配置以產生用於識別的一編碼。Embodiments of the present disclosure provide a semiconductor device having a gate electrode with dopants of different conductivity types, thereby improving the threshold voltage of a transistor. Therefore, when a transistor including a gate electrode with dopants of different conductivity types is turned on, different currents can be measured to determine a lower logic value "0" and a higher logic value "1". As a result, the semiconductor device of the present disclosure can be configured to generate a code for identification.
雖然已詳述本揭露及其優點,然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如,可用不同的方法實施上述的許多製程,並且以其他製程或其組合替代上述的許多製程。Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the claimed claims. For example, many of the processes described above may be implemented in different ways and replaced with other processes or combinations thereof.
再者,本申請案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質上相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此,此等製程、機械、製造、物質組成物、手段、方法、或步驟包含於本申請案之申請專利範圍內。Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, etc. that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patent scope of this application.
100:半導體元件 102:基底 110-1:電晶體 110-2:電晶體 111:主動區 112:主動區 113:主動區 114:主動區 121:閘極結構 122:閘極結構 141:通道區 142:通道區 150:介電層 161:導電接觸點 162:導電接觸點 163:導電接觸點 171:導電接觸點 172:導電接觸點 181:摻雜物 200:半導體元件 202:基底 210-1:閘極電極 210-2:閘極電極 220:陣列 221:列 222:列 223:列 224:列 250:介電層 250o1:開口 250o2:開口 250o3:開口 250o4:開口 250o5:開口 261:導電接觸點 262:導電接觸點 263:導電接觸點 271:導電接觸點 272:導電接觸點 300:邏輯資訊 321:位元串 322:位元串 323:位元串 324:位元串 400:製備方法 402:步驟 404:步驟 406:步驟 408:步驟 410:步驟 412:步驟 414:步驟 416:步驟 1211:閘極電介質 1212:閘極電極 1221:閘極電介質 1222:閘極電極 1311:摻雜區 1312:摻雜區 1313:摻雜區 1321:摻雜區 1322:摻雜區 1323:摻雜區 1331:摻雜區 1332:摻雜區 1333:摻雜區 1341:摻雜區 1342:摻雜區 1343:摻雜區 2111:閘極電極 2112:閘極電極 2113:閘極電極 2114:閘極電極 2115:閘極電極 2121:閘極電極 2122:閘極電極 2123:閘極電極 2124:閘極電極 2125:閘極電極 2131:閘極電極 2132:閘極電極 2133:閘極電極 2134:閘極電極 2135:閘極電極 2141:閘極電極 2142:閘極電極 2143:閘極電極 2144:閘極電極 2145:閘極電極 A1:面積 A2:面積 D1:摻雜物 D2:摻雜物 E1:光罩 E2:光罩 M1:感光材料 o1:開口 o2:開口 P1:摻雜製程 P2:摻雜製程 100:Semiconductor components 102: Base 110-1: Transistor 110-2:Transistor 111:Active zone 112:Active zone 113:Active zone 114:Active zone 121: Gate structure 122: Gate structure 141: Passage area 142: Passage area 150:Dielectric layer 161:Conductive contact point 162:Conductive contact point 163:Conductive contact point 171:Conductive contact point 172:Conductive contact point 181:Adultants 200:Semiconductor components 202:Base 210-1: Gate electrode 210-2: Gate electrode 220:Array 221: column 222: column 223: column 224: column 250:Dielectric layer 250o1:Open your mouth 250o2:Open your mouth 250o3:Open your mouth 250o4:Open your mouth 250o5:Open your mouth 261:Conductive contact point 262:Conductive contact point 263:Conductive contact point 271:Conductive contact point 272:Conductive contact point 300:Logical information 321: bit string 322: bit string 323: bit string 324: bit string 400:Preparation method 402: Step 404: Step 406: Step 408: Step 410: Steps 412: Step 414: Step 416: Steps 1211: Gate dielectric 1212: Gate electrode 1221: Gate dielectric 1222: Gate electrode 1311: Doped area 1312: Doped area 1313: Doped area 1321: Doped area 1322: Doped area 1323: Doped area 1331: Doped area 1332: Doped area 1333: Doped area 1341: Doped area 1342: Doped area 1343: Doped area 2111: Gate electrode 2112: Gate electrode 2113: Gate electrode 2114: Gate electrode 2115: Gate electrode 2121: Gate electrode 2122: Gate electrode 2123: Gate electrode 2124: Gate electrode 2125: Gate electrode 2131: Gate electrode 2132: Gate electrode 2133: Gate electrode 2134: Gate electrode 2135: Gate electrode 2141: Gate electrode 2142: Gate electrode 2143: Gate electrode 2144: Gate electrode 2145: Gate electrode A1:Area A2:Area D1: Dopant D2: Dopant E1: Photomask E2: Photomask M1: Photosensitive material o1:Open your mouth o2:Open your mouth P1: Doping process P2: Doping process
藉由參考詳細描述以及申請專利範圍而可以獲得對本揭露一更完整的理解。本揭露還應理解為與圖式的元件編號相關聯,而圖式的元件編號在整個描述中代表類似的元件。 圖1A是頂視示意圖,例示本揭露一些實施例之半導體元件的佈局。 圖1B是剖視示意圖,例示本揭露一些實施例如圖1A所示之半導體元件沿剖線A-A’的剖面。 圖2A是剖視示意圖,例示本揭露一些實施例之半導體元件的閘極結構。 圖2B是剖視示意圖,例示本揭露一些實施例之半導體元件的閘極結構。 圖3是頂視示意圖,例示本揭露一些實施例的半導體元件。 圖4是示意圖,例示本揭露一些實施例對應如圖3所示之半導體元件的邏輯資訊。 圖5是流程示意圖,例示本揭露一些實施例之半導體元件的製備方法。 圖6A、圖7A、圖8A、圖9A、圖10A、圖11A、圖12A及圖13A是示意圖,例示本揭露一些實施例之半導體元件的製備方法的一例子之一或多個階段。 圖6B、圖7B、圖8B、圖9B、圖10B、圖11B、圖12B及圖13B是剖視示意圖,例示分別沿著圖6A、圖7A、圖8A、圖9A、圖10A、圖11A、圖12A及圖13A之剖線B-B’的剖面。 A more complete understanding of the present disclosure can be obtained by referring to the detailed description and patent claims. The present disclosure should also be understood to be associated with the drawing element numbering, which represents similar elements throughout the description. FIG. 1A is a schematic top view illustrating the layout of semiconductor devices according to some embodiments of the present disclosure. FIG. 1B is a schematic cross-sectional view illustrating a cross-section along the cross-section line A-A' of the semiconductor device shown in FIG. 1A according to some embodiments of the present disclosure. FIG. 2A is a schematic cross-sectional view illustrating the gate structure of a semiconductor device according to some embodiments of the present disclosure. FIG. 2B is a schematic cross-sectional view illustrating the gate structure of a semiconductor device according to some embodiments of the present disclosure. FIG. 3 is a top view schematic diagram illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 4 is a schematic diagram illustrating logic information corresponding to the semiconductor device shown in FIG. 3 according to some embodiments of the present disclosure. FIG. 5 is a schematic flowchart illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. 6A, 7A, 8A, 9A, 10A, 11A, 12A and 13A are schematic diagrams illustrating one or more stages of an example of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Figure 6B, Figure 7B, Figure 8B, Figure 9B, Figure 10B, Figure 11B, Figure 12B and Figure 13B are schematic cross-sectional views, exemplified along the lines of Figure 6A, Figure 7A, Figure 8A, Figure 9A, Figure 10A, Figure 11A, respectively. The cross-sections taken along the line BB' in Fig. 12A and Fig. 13A.
100:半導體元件 100:Semiconductor components
102:基底 102: Base
110-1:電晶體 110-1: Transistor
110-2:電晶體 110-2:Transistor
121:閘極結構 121: Gate structure
122:閘極結構 122: Gate structure
141:通道區 141: Passage area
142:通道區 142: Passage area
150:介電層 150:Dielectric layer
161:導電接觸點 161:Conductive contact point
162:導電接觸點 162:Conductive contact point
163:導電接觸點 163:Conductive contact point
171:導電接觸點 171:Conductive contact point
172:導電接觸點 172:Conductive contact point
1311:摻雜區 1311: Doped area
1312:摻雜區 1312: Doped area
1313:摻雜區 1313: Doped area
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US17/844,971 US20230411488A1 (en) | 2022-06-21 | 2022-06-21 | Semiconductor device having gate electrodes with dopant of different conductive types |
US17/844,971 | 2022-06-21 | ||
US17/845,776 US20230411395A1 (en) | 2022-06-21 | 2022-06-21 | Method of manufacturing semiconductor device having gate electrodes with dopant of different conductive types |
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