TW202347185A - Pre-screening and tuning heterojunctions for topological quantum computer - Google Patents

Abstract

A method to evaluate a semiconductor-superconductor heterojunction for use in a qubit register of a topological quantum computer includes (a) measuring one or both of a radio-frequency (radio frequency; RF) junction admittance of the semiconductor-superconductor heterojunction and a sub-RF conductance including a non-local conductance of the semiconductor-superconductor heterojunction, to obtain mapping data and refinement data; (b) finding by analysis of the mapping data one or more regions of a parameter space consistent with an unbroken topological phase of the semiconductor-superconductor heterojunction; and (c) finding by analysis of the refinement data a boundary of the unbroken topological phase in the parameter space and a topological gap of the semiconductor-superconductor heterojunction for at least one of the one or more regions of the parameter space.

Description

Prescreening and tuning heterojunctions for topological quantum computers

This application claims priority from U.S. Provisional Patent Application No. 63/161,946, entitled PRE-SCREENING AND TUNING HETEROJUNCTIONS FOR TOPOLOGICAL QUANTUM COMPUTER, filed on March 16, 2021, which is incorporated by reference in its entirety for all purposes. into this article.

This disclosure is about prescreening and tuning heterojunctions for topological quantum computers.

A quantum computer is a physical machine configured to perform logical operations based on or affected by quantum mechanical phenomena. For example, such logical operations may include mathematical calculations. The current interest in quantum computer technology stems from analysis showing that the computational efficiency of a suitably configured quantum computer may exceed that of any practical non-quantum computer when applied to certain types of problems. These problems include computer modeling of natural and synthetic quantum systems, integer factorization, data search and function optimization with applications to linear equations and machine learning. In addition, we predict that the continued miniaturization of conventional computer logic structures will eventually lead to the development of nanoscale logic components that exhibit quantum effects and must be processed according to quantum computing principles.

Different types of quantum computers operate on different quantum mechanical phenomena. A "topological" quantum computer is a quantum computer that operates on non-Abelian topological phases of matter that may support "knitable" quasiparticles. We expect that such quantum computers will be less susceptible to quantum decoherence than other types of quantum computers and may therefore serve as a relatively fault-tolerant quantum computing platform.

One aspect of this disclosure relates to methods for evaluating semiconductor-superconductor heterojunctions in qubit registers for use in topological quantum computers. The method includes: (1) measuring one or both of the radio frequency (RF) junction admittance of the semiconductor-superconductor heterojunction and the sub-RF conductance including the non-local conductance of the semiconductor-superconductor heterojunction, and Obtain mapping data and refine the data; (2) analyze the mapping data to find one or more regions of parameter space consistent with the unbroken topology of the semiconductor-superconductor heterojunction; and (3) refine the data through analysis , searching for the boundary of the unbroken topological phase in the parameter space and the topological gap of the semiconductor-superconductor heterojunction in at least one of one or more regions of the parameter space.

This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or critical features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. The claimed subject matter is not limited to implementations that solve any or all disadvantages noted in any part of this disclosure.

Quantum computer architecture

Figure 1 shows what an exemplary quantum computer 10 configured to perform quantum logic operations looks like (see below). While conventional computer memory holds digital data in arrays of bits and performs bit-by-bit logical operations, quantum computers hold data in arrays of qubits and perform quantum mechanical operations on the qubits to perform desired operations. logic. Therefore, the quantum computer 10 of FIG. 1 includes at least one qubit register 12 including a qubit array 14 . The qubit register shown is eight qubits in length; qubit registers containing longer and shorter qubit arrays are also envisioned, as well as two or more qubit arrays of any length. A quantum computer with qubit registers.

The qubits 14 of the qubit register 12 can take various forms, depending on the desired architecture of the quantum computer 10 . Although the present disclosure relates to qubits exhibiting quasiparticles that exhibit non-Abelian topological phases, as non-limiting examples, qubits may alternatively include: superconducting Josephson junctions, trapped ions, coupling to Gurry Captured atoms in the resonance cavity, atoms or molecules constrained in the fullerene, ions or neutral doping atoms in the host lattice, quantum dots exhibiting discrete spatial or spin electronic states, via electrostatic hydrazine Entrained electron holes in semiconductor junctions, coupled quantum wire pairs, atomic nuclei that can be processed by magnetic resonance, free electrons in helium, molecular magnets, or metallic carbon nanospheres. More generally, each qubit 14 may include any particle or system of particles existing in two or more discrete quantum states that can be experimentally measured and manipulated. For example, qubits can be implemented in multiprocessing states corresponding to passage through linear optical elements such as mirrors, beam splitters, and phase shifters, and in states accumulated in Bose-Einstein condensates. of different light propagation modes.

Figure 2 illustrates a Bloch sphere 16, which graphically describes some quantum mechanical states of an individual qubit 14. In this description, the north and south poles of the Bloch sphere correspond to the standard basis vectors |0　 and |1　, respectively. The set of points on the surface of a Bloch sphere contains all possible pure states |𝜓　 of a qubit, while the points on the interior correspond to all possible mixed states. Mixed states of specific qubits may arise from decoherence, which may occur due to poor coupling to external degrees of freedom.

Returning to Figure 1, quantum computer 10 includes controller 18A. The controller includes at least one processor 20A and associated computer memory 22A. The processor 20A of the controller 18A can be operatively coupled to peripheral components (such as network components) to enable remote operation of the quantum computer. The processor 20A of the controller 18A may be in the form of a central processing unit (CPU), a graphics processing unit (GPU), or the like. Thus, the controller may contain classical electronic components. The terms "classical" and "non-quantum" are used in this article to apply to any component that can be accurately modeled as a population of particles without regard to the quantum state of any individual particle. For example, classical electronic components include integrated photolithographically etched transistors, resistors, and capacitors. Computer memory 22A may be configured to retain program instructions 24A that cause processor 20A to perform any function or process of the controller. Computer memory can also be configured to hold additional data 26A. In the case where qubit register 12 is a low temperature or cryogenic device, controller 18A may include control components that operate at low or cryogenic temperatures, such as a field-programmable gate array operating at 77K. programmable gate array; FPGA). In such examples, the low temperature control component may be operatively coupled to the interface component operating at normal temperature.

Controller 18A of quantum computer 10 is configured to receive a plurality of inputs 28 and provide a plurality of outputs 30 . Each of the inputs and outputs may include digital and/or analog lines. At least some of the inputs and outputs may be data lines through which data are provided to and/or extracted from the quantum computer. Other inputs may include control lines by which the operation of the quantum computer can be adjusted or otherwise controlled.

Controller 18A is operatively coupled to qubit register 12 via quantum interface 32 . The quantum interface is configured to exchange data bidirectionally with the controller. The quantum interface is further configured to bidirectionally exchange signals corresponding to the data with the qubit register. Depending on the architecture of quantum computer 10, this signal may include electrical, magnetic and/or optical signals. Through signals transmitted through the quantum interface, the controller can interrogate or otherwise affect the quantum state held in the qubit register, which quantum state is defined by the collective quantum state of the array of qubits 14 . To this end, the quantum interface includes at least one modulator 34 and at least one demodulator 36, each of which is operatively coupled to one or more qubits of the qubit register. Each modulator is configured to output a signal to the qubit register based on modulation data received from the controller. Each demodulator is configured to sense signals from the qubit register and output data to the controller based on the signals. In some examples, the data received from the demodulator may be an estimate of the measured observable quantity of the quantum state held in the qubit register.

In some examples, a suitably configured signal from modulator 24 can physically interact with one or more qubits 14 of qubit register 12 to trigger a change in the hold in one or more qubits. Measurement of quantum states. Demodulator 36 may then sense the resulting signal released by the one or more qubits based on the measurements, and may provide data corresponding to the resulting signal to controller 18A. In other words, the demodulator may be configured to output an estimate of one or more observables reflecting the quantum state of one or more qubits of the qubit register based on the received signal and provide the estimate to the controller . In one non-limiting example, the demodulator may provide appropriate voltage pulses or pulse trains to the electrodes of one or more qubits to cause a measurement based on data from the controller. For a short period of time, the demodulator can sense photon emission from one or more qubits and can announce the corresponding digital voltage level on the quantum interface line to the controller. Roughly speaking, any measurement of a quantum mechanical state is defined by an operator O corresponding to the observable to be measured; the result R of the measurement is guaranteed to be one of the allowed eigenvalues of O. In a quantum computer 10, R is statistically related to the qubit register state before the measurement, but is not uniquely determined by the qubit register state.

Based on appropriate input from controller 18A, quantum interface 32 may be configured to implement one or more quantum logic gates to operate on the quantum states held in qubit register 12 . While the function of each type of logic gate in a classical computer system is described in terms of the corresponding truth table, the function of each type of quantum gate is described in terms of the corresponding operator matrix. The operator matrix operates on (i.e., multiplies) a complex vector representing the qubit register state and causes a specified rotation of that vector in Hibbert space.

For example, HAD is defined by:

The HAD gate acts on a single qubit, which maps the ground state |0　 to , and map |1　 to . Therefore, the HAD gate forms an overlap of states that has an equal probability of displaying either |0　 or |1　 when measured.

Phase gate S is defined as follows:

The S gate leaves the ground state |0　 unchanged, but maps |1　 to . Therefore, this gate does not change the probability of measuring |0　 or |1　, but the phase of the quantum state of the qubit shifts. This is equivalent to rotating ψ by 90 degrees along the latitude circle on the Bloch sphere in Figure 2.

Some quantum gates operate on two or more qubits. For example, a SWAP gate acts on two different qubits and swaps their values. This gate is defined by:

The preceding list of quantum gates and related operator matrices is not exhaustive and is provided for ease of explanation. As non-limiting examples, other quantum gates include Baoli X, Y and Z gates, gate, other phase shift gates, Gates, controlled cX, cY and cZ gates, and Toffoli, Fredkin, Ising and Deutsch gates.

Continuing in FIG. 1 , suitably configured signals from modulator 34 of quantum interface 32 can physically interact with one or more qubits of qubit register 12 to declare any desired quantum gate. operate. As noted above, the desired quantum gate operation is specifically defined as the rotation of a complex vector representing the qubit register state. To induce the desired rotation O, one or more modulators of quantum interface 32 may apply a predetermined signal level _Si for a predetermined duration _Ti . In some examples, as shown in Figure 3, multiple signal levels may be applied over multiple sequences or otherwise related durations to declare a quantum gate on one or more qubits of the qubit register. operate. In general, each signal level _Si and each duration _Ti are control parameters that can be adjusted by appropriate programming of controller 18A.

The term "prophecy" is used herein to describe a predetermined sequence of basic quantum gate and/or measurement operations that can be performed by quantum computer 10 . For example, predictions can be used to convert the quantum state of the qubit register 12 to cause classical or non-elementary quantum gate operations, or to apply density operators. In some instances, oracles can be used to perform predefined "black box" operations f (x) that complex sequences of operations can include. To ensure the adjoint operation, n input qubits |igh　are mapped into m outputs, or auxiliary qubits The prediction of can be defined as a quantum gate operating on n+m qubits . In this case, O can be configured to keep the n input qubits unchanged, but combine the results of the operation f (x) with the auxiliary qubits via an XOR operation, such that . As described further below, a state preparation prediction is a prediction configured to produce a quantum state with a specified qubit length.

The description herein implies that each qubit 14 of the qubit register 12 can be interrogated via the quantum interface 32 to credibly reveal the standard basis vectors |0〉 or |1 characterizing the quantum state of that qubit. . However, in some embodiments, errors may occur in the measurement of the quantum state of the physical qubit. Thus, any qubit 14 may be implemented as a logical qubit, which includes a population of physical qubits measured according to an error correction prophecy that credibly indicates the quantum state of the logical qubit. Topological quantum computer

In a topological quantum computer, the quantum state held in each qubit is the state of two or more braidable quasiparticles, or "anyons," observed in non-Abelian topological phases of matter. Quantum mechanics prohibits the world lines of different anyons from crossing or merging. This feature causes their paths to form a stable braid that surrounds each other in space-time. Relative to the trapped particles used in other types of quantum computers, anyon braids are more resistant to quantum decoherence, a source of error in quantum calculations. However, realizing a topological quantum computer requires the ability to create suitable topological phases and manipulate the anyons within them.

Early experiments in topological quantum computing focused on a two-dimensional "electron gas" of ultracold thin layers of gallium arsenide (GaAs) sandwiched between layers of aluminum gallium arsenide (ALGaAs) and manipulated in a strong magnetic field. Implementing quantum computers using this architecture requires combining the weaving of individual quasiparticle excitations with interferometry-based measurements of anyons, which involves coherent quasiparticle transmission over long distances.

One-dimensional topological qubit architectures have recently been proposed, which appear to be more suitable for practical implementation. The proposed system uses a semiconductor-superconductor heterostructure in which superconductivity, strong spin-orbit coupling, and magnetic fields come together to form a topological superconducting state that supports the Majorana zero mode (MZM). This new architecture eliminates the need to move the quasiparticles using a "measurement-only" approach, in which the measurement sequence has the same effect as the weaving operation. Instead of moving quasiparticles through interference loops, this architecture exploits the difference between "fermion parity protected topological phases" (the actual nature of the proposed heterostructure) and true topological phases. Advantageously, the topological charges in the fermion parity-protected topological phase can be manipulated through the electron tunneling process in MZMs. Transmission through a pair of MZMs can provide a measure of their combined topological charge in the presence of large charging energy.

Because of these and other useful properties, MZMs can serve as the basis for qubits in topological quantum computers. MZM is generated at the end of the semiconductor-superconductor heterostructure, and the semiconductor-superconductor heterostructure is tuned to a topological state by appropriate magnetic fields and gate voltages. A series of practical implementations are described in Scalable Designs for Quasiparticle-Poisoning-Protected Topological Quantum Computation with Majorana Zero Modes, arXiv:1610.05289v4 [cond-mat.mes-hall], published by Karzig et al. on June 21, 2017. Majorana Fermions and a Topological PhaseTransition in Semiconductor-Superconductor Heterostructures, arXiv:1002.4033v2 [cond-mat.supr-con] published by Lutchyn et al. on August 13, 2010, describes suitable heterostructure materials and material properties. The above two references are incorporated by reference in their entirety for all purposes.

Exemplary embodiments include at least two topological superconducting segments in a qubit, such that each qubit has a total of at least four Majorana zero modes. In contrast to non-degenerate quantum computing architectures where the two states of a qubit have different energies, the state used in quantum computing will be the degenerate ground state of the qubit. The degradation of qubit states and the spatial separation of Majorana zero modes ensure long coherence times and the feasibility of accurately applying a set of Clifford gates.

Figure 4 illustrates an example of a topological qubit architecture including a linear tetrad particle array 38. The linear tetrad particle includes: segments 40 and 42, which include classical superconductors, such as aluminum (Al); segment 44, which includes semiconductors, such as indium arsenide (InAs) or indium antimonide (InSb); and a plurality of MZMs 46. The length ℓc of the non-topological segment is much larger than the corresponding coherence length ξc of the non-topological region, and the length ℓt of the topological segment is much larger than the coherence length ξ of the topological region. The dashed box in Figure 4 represents a single qubit in the form of a linear tetrad particle. Other topological superconducting chains and semiconductor structures allow appropriate measurements to be performed to manipulate and entangle linear tetrad particles.

It is difficult to fabricate the qubit structure shown in Figure 4 to the degree of reproducibility required for practical quantum computing. Some candidate structures may not operate in the desired topological state due to material or manufacturing defects. Even for candidate structures operating in the desired topological state, the appropriate terminal biases and magnetic field levels required for qubit operations cannot always be predicted a priori. Therefore, candidate semiconductor-superconductor heterojunctions must be "pre-screened" for appropriate topological behavior before being incorporated into qubit registers, and successful heterojunctions must be "tuned" to find the appropriate operating parameters. Method overview

This disclosure provides methods to prescreen and tune candidate semiconductor-superconductor heterojunctions for topological qubits. Methods include extracting "topological gaps" for candidate heterojunctions (see below) by using at least two stages of measurements followed by analysis. Measurements are made on a component with three current-carrying contacts, one of which is superconducting (a "three-terminal component" in this article). The "mapping" phase of this method involves rapid measurements that roughly identify promising areas. The subsequent "refinement" phase consists of slower measurements that are performed on each of the promising regions identified in the mapping phase. In some instances, methods use density-based clustering algorithms on both sides of the zero-bias peak (ZBP) data to extract predicted topological regions and classify bias traces using peak hunting or machine learning. The accuracy of previous methods was improved by checking the stability of ZBP to changes in the cutter gate voltage and by checking gap closure at the boundaries of suspected topological regions. Meta-analysis of ZBP data is used to extract the probability of finding a topological region among many components of the same preparation. This feature can be used to characterize the growth and/or fabrication methods of topological qubit structures.

As used in this article, "false positives" identify trivial systems as topological, while "false negatives" identify topological systems as trivial. Our technique is an improvement over the basic ZBP search in that it involves performing a ZBP search independently on both sides of a three-terminal component, thereby reducing the chance of false positives. It also includes non-local measurements to extract energy gaps in candidate systems, thereby providing additional information for detection of topological gaps. Finally, it consists in performing non-discriminative measurements in a region of parameter space with predefined boundaries, thus ruling out false positives caused by validation and selection biases (which can occur if the measurement region is artificially chosen).

Figure 5 shows an aspect of an exemplary semiconductor-superconductor heterojunction element 48 evaluated according to the methods herein. Generally speaking, a semiconductor-superconductor heterojunction suitable for testing includes at least three terminals and a plurality of electrostatic control terminals for supporting electronic admittance and conductance measurements. Component 48 of Figure 5 is a three-terminal component that includes: a topological midsection 50 coupled to ground probe 52 via a trivial superconductor; and two straight probes 54R and 54L coupled to both ends of the semiconductor line. This geometry allows simultaneous measurement of the tunneling signature of the topological phase at both ends of the midsection 50 in order to correlate with the zero-bias signature on both sides. Additionally, the non-local signal between two straight probes provides information about the lowest energy of the extended state of the topological segment, which can be used as a proxy for the topological gap (e.g. in a sufficiently long semiconductor wire, the non-local signal is fixed at The bias value corresponding to the lowest energy extended state in the line). Therefore, the method in this article does not directly measure the topological characteristics of the system, but measures a set of surrogate variables. Based on analytical calculations and numerical simulations, it is known that the surrogate variables have a good correlation with the topological invariants. The surrogate criterion for identifying topologically non-trivial regions is as follows:

1. The associated zero-bias differential conductance peak occurs over topological regions with well-separated Majorana on both sides of the element.

2. For low values of the magnetic field, there are gaps in the body of the system. As the magnetic field increases, the bulk gap should close and reopen in the topological region. The value of the energy gap in the body of the detection wire can be measured via non-local conductance in a three-terminal element.

The size of the agent gap varies within the region in the parameter space that satisfies the topological criteria. The operational meaning of the term "topological gap" in the context of this disclosure is the size of the largest body gap in this topological region.

To be able to distinguish topological from non-topological systems, methods must correctly identify topological regions in idealized numerical test data sets. Therefore, our method shows a high degree of overlap between the topologically identified regions and numerically determined topological indices (as shown in Figure 10). Additionally, the method must correctly label currently known candidates for false positive signatures as non-topological. These include:

1. Trivial local bound states caused by cutters, impurities, or smoothing potentials (such as quasi-Majorana mode pairs at the ends of the element), which are examples of non-topological zero-bias peaks;

2. Low-energy sub-gap states caused by disorder (non-topological zero-bias peaks and possible accidental gap closing/re-opening features);

3. Trivial gap closing without proper reopening in finite size systems (e.g. Coulomb blockade systems), where finite size gaps close at small fields and cause oscillations in low energy states (false gap closing/reopening characteristics); and

4. Trivial accidental closure-like features (false gap closing/reopening features) caused by a set of discrete states spanning zero energy.

Methods One way to reduce these false positives is by using data collected over a wide range of parameter values. Accidental or fine-tuned points should not persist when parameter values change, like topological phases. In addition, the method relates different indicators of the topological phase, since the above criteria need to be verified (i.e., the zero-bias conductance peak needs to be present at both ends), and the system needs to show gap closing and reopening in non-local inductance. Characteristics. Given these criteria, the above false positives can be correctly identified because:

1. False positives 1 and 2 listed above lack gap closing/reopening characteristics in non-local inductance; and

2. False positives 3 and 4 lack relevant and stable zero-bias peaks at both ends of the semiconductor line.

We expect that the simultaneous presence of different types of false positives is unstable to changes in parameter space.

A remaining concern with this approach is preventing false negatives, which is dealt with further below. Specifically, specifically constructed examples of binding features 1 and 4 with false positive regions are dealt with, and examples related to strongly disordered systems. Although disorder can lead to zero-bias peaks, in general it does not lead to extended regions of associated ZBPs. Similar stability requirements rule out possible false positives listed above3.

The approach is guided by the following principles:

1. The method must ensure that both criteria listed above are verified.

2. It is necessary to measure the parameter space of the component as widely as possible because:

(1) The initial uncertainty in the existence and location of topological phases can be high.

(2) Checking the stability of the zero-bias peak in parameter space helps rule out possible false positives.

(3) It reduces useless selection bias.

3. The method should be completed within a reasonable amount of time (up to a few days) and require a minimum of human decision-making during implementation of the method.

4. Non-local conductance measurement that relies on bias voltage in DC is currently slow. Therefore, bias-dependent non-local conductance measurements in DC can be replaced with non-local RF measurements or with non-local DC measurements at or near zero bias to determine the presence of gaps.

5. For a specific implementation of the method, the sequence of measurements should be predetermined and of finite length to prevent open-ended searches, which can take a long time and can introduce selection bias, especially for large parameter spaces. It is still possible to improve the measurement sequence over time by, for example, applying lessons learned from previous runs.

6. For the specific execution of the method, the data analysis program should be determined before collecting and testing the data, and the data analysis program should have predetermined output, so as to avoid over-fitting and confirmation bias, and ensure that the method has results. Furthermore, it is still possible to improve the data analysis code over time by, for example, using improved algorithms and applying lessons learned from previous runs.

In view of the above factors, Figure 6 shows aspects of an exemplary evaluation method 56 for semiconductor-superconductor heterojunctions in qubit registers for topological quantum computers. Method 56 includes a mapping stage 58 and a refinement stage 60 . In some instances, the mapping and refinement phases can be performed separately, for example, to evaluate new experimental settings or implement changes.

The mapping stage 58 and the refinement stage 60 each include measurements that are subsequently analyzed. The mapping stage includes fast RF measurements 62 of normal superconductor (NS) junction admittance, which provide mapping data. In other examples, the measurements may be DC measurements. The measured quantities include the local conductance at each end of the semiconductor line in a wide parameter space of bias, field, plunger and left/right chopper gate voltages. In some examples, the mapping data may also include non-local conductance data. In some examples, the "mapping data" derived from measurement 62 includes two 5D data sets of the RF signal relative to the field, left chopper, right chopper, plunger, and left or right bias. The associated data analysis 64 then looks for extended regions in the parameter space where the associated ZBP exists. In some instances, the output of analysis 64 includes a list of "promising" regions in the 4D parameter space (fields, left chopper, right chopper, plunger), in order of the future existence of finite topological regions in that region. The possibility of destroying the topological phase orders such regions.

Each promising region identified in this way is then further iteratively investigated in a refinement phase 60 . The refinement stage involves performing slower RF measurements 66 of the full conductance matrix using a lock-in amplifier and including local and non-local conductance within each region of interest. In other examples, more detailed measurements may be RF measurements. In some examples, the "refined data" obtained from measurement 66 includes the full conductance matrix of each promising region as a function of bias voltage. An analysis of the relevant data 68 of the global conductance matrix and especially of the non-local conductance provides information on the behavior of the bulk gaps in order to identify regions as topological according to the above criteria. Relevant data analysis 68 also allows for a quantitative assessment of the size of the gaps in each topological region. In some examples, analysis 68 includes determining the boundaries of the topological phase (or the absence of the topological phase) in each measurement region based on a joint analysis of local and non-local conductance. Additionally, for each region, determine the value of the topological gap (if any). In the refinement phase 60, for example, promising areas are repeatedly measured with the adjusted range and resolution, not indefinitely, but only under appropriate circumstances. Therefore, refinement stage 60 may include a heavily tuned feedback loop that adjusts the bias range and/or resolution in parameter space. For example, a feedback loop may contain a maximum of two iterations.

After the refinement stage 60 is completed, regions with optimal properties of the topological phase are identified. For example, regions can be defined combining large gaps and high confidence in topological properties. To further increase the confidence, optionally an additional validation phase 70 may be performed, in which the stability of the optimal region is included in additional tests. In some examples, the verification stage 70 includes verifying the ZBP in the region identified in the refinement stage 60 by examining the stability of the ZBP to changes in the disconnector-gate voltage. Such changes can be of any desired size, including large changes. Additionally, in the case where the semiconductor-superconductor heterojunction is one of a series of similarly prepared semiconductor-superconductor heterojunctions, the validation phase may include meta-analysis of ZBP data on that series. A meta-analysis can be performed to calculate the probability of finding topological regions in other similarly prepared semiconductor-superconductor heterojunctions.

As noted above, the measurements in Method 56 are performed on a three-terminal component as shown in Figure 5. Some limitations of the components to be measured will now be discussed with continued reference to that figure. Element 48 of Figure 5 includes semiconductor wires 72, which are typically nanowires, including in some examples a gate region of a two-dimensional semiconductor. In some embodiments, the semiconductor wires may include selective-area grown (SAG) nanowires. In element 48, semiconductor nanowire 72 is approximated by semiconductor 74. The semiconductor extends to the side away from the hybrid line. Figure 5 shows a representative position of the MZM 75 in the case where the element 48 is operating in the topological state. A "T" shaped semiconductor is not necessarily required, and the width of the vertical superconducting segments can extend to the entire length L of the element. Conventional contacts 54R and 54L contact semiconductor lines on each end of the element. Contact 52 is coupled to semiconductor 74, making the element with three terminals suitable for electrical transmission measurements. A dielectric layer covers the entire component (not shown). Static interrupter gates 76R and 76L are used to form tunneling energy barriers at each end of semiconductor line 72 . Electrostatic plunger gate 78 tunes the chemical potential within the element.

In the example shown, important dimensions include:

L: the maximum length of the topological region,

L _S : the length of the superconducting segment connecting the topological region to the lead-grounded superconductor 74,

W: the width W of the semiconductor line 72 (or more generally the cross section),

L _C : the distance between the cutter gate 76 and the superconductor 74,

W _C : the width of each cutter gate 76,

L _N : The spacing between each breaker gate 76 and the associated conventional lead 54.

The distance of the plunger gate 78 from the semiconductor line 72 can be important to the lever arm and the potential energy pattern in the semiconductor line, which also depends on the dielectric material used. Another variable is the geometry of the plunger gate 78 relative to the semiconductor wire (wrap gate versus side gate). If the plunger gate wraps around the semiconductor (wraps the gate), the lever arm will be larger, causing the chemical potential within the semiconductor wire to change by a larger amount. On the contrary, if the coupling of the plunger gate to the semiconductor line is too strong, the small voltage noise on the plunger gate will have a greater effect, which may artificially broaden the chemical potential within the semiconductor line 72 .

One of the most important parameters is the approximate length L of the semiconductor wire. For this, two effects compete with each other. On the one hand, the semiconductor wire needs to be of sufficient length to avoid finite-size effects and to make the signature of the topological phase transition and the associated ZBP clear. On the other hand, longer wires will make it more practical to grow or fabricate working components and may reduce non-local signals. Specifically, as the semiconductor wire length increases, it becomes more difficult to ensure that the semiconductor wire is sufficiently homogeneous and that strong defects are not present (such as poor contact with the superconductor suppressing proximity effects). Little data is currently available for components longer than 2 µm. According to theory, 5ξ (ξ is the topological coherence length) shows the smallest length scale where the effective size effect is fully suppressed. Even in clean lines, as the length of the semiconductor line increases, non-local signals will be suppressed. The above-mentioned problem will cause the component quality to depend on the upper limit of L for the successful extraction of non-local information.

The length L _S is chosen such that leakage of quasiparticles to the central lead is suppressed. A working estimate is L _S > 10ξ _S , where ξ _S is the coherence length of the superconductor 74 (ξ _S = 200 nm for disordered Al). In a typical experiment, L _S can reach the scale of millimeters, thus exceeding the minimum value by several orders of magnitude.

Experimental evidence shows that the distance L _C from the chopper gate 76 must be kept less than 100 nm so that false final states are avoided and high-resolution tunneling spectroscopy can be performed. The best choice of _LC and the design of the cutter gate can be determined by combining electrostatic simulation, actual transmission and manufacturing capabilities. As a placeholder, the requirement for L _C < 40 nm can be used. It should be noted that the cutter design can vary with regard to the width of the cutter W _C and the distance between the cutter and the conventional lead wire. For InSb lines, it may be necessary to reduce the spacing between the cutter and the regular leads, since these lines are normally closed, and the cutter needs to make this section of the line conductive as well.

It should be noted that the parameter of line width W is not necessarily important for the feasibility of the disclosed method, but it will affect the possibility of obtaining valid results from the method. For example, the width controls the number of channels, and numerical simulations show that fewer channels are beneficial in reaching topological phases.

Table 1 summarizes current estimates of various requirements for component geometries in terms of materials currently used, and presents material-specific requirements for estimates of component dimensions. For this value, the following estimates of the coherence length at the maximum gap point were used: ξ(InSb/Al) = 400 nm, ξ(InAs/Al) = 300 nm and ξ _S = 200 nm. quantity InSb/Al InAs/Al L ＞2.0 µm > 1.5 µm L _S > 2 µm > 2 µm L _C ＜40nm ＜40nm

To obtain a system with a sufficiently large topological gap requires an appropriate choice of materials. However, method 56 is independent of semiconductor wire materials. Although we are still investigating material stacking (both theoretically and experimentally), current results indicate that InAs with barrier materials and InSb without barrier are promising options for obtaining topological gaps in the appropriate energy range. In some instances, topological gaps in the range of 25 to 200 µeV may be suitable to support the operation of topological quantum computers. Narrower and wider scopes are also envisaged.

The current choice of superconductor is aluminum because it forms a hard-induced gap in the heterostructure and has no sub-gap state under zero field. Again, the method is largely independent of the choice of superconductor, as long as the measurement parameters are adjusted accordingly, such as extending the bias scan range for larger gap superconductors or adjusting the size of the component based on the values shown in Table 1.

The choice of dielectric depends largely on the material stack-up used. Hybrid systems impose limitations on the temperatures that a specific stack of materials can withstand. The maximum gate voltage that can be applied to the electrostatic gate before dielectric breakdown (breakdown voltage V _break ) is an important material quantity that is preferably known for a given dielectric layer and SAG material system because it sets the device operation basic restrictions. The breakdown voltage can be measured on the test component or determined by standard electrical characterization (SEG) measurements. If the experiment is feasible, one suggestion is to fabricate the same component as the component under test closely on the same wafer so that the actual V _break can be measured.

Returning to Figure 6, before detailed measurements are performed on the component, the component can be qualified to determine that it meets a set of criteria. Accordingly, method 56 includes an initial qualification phase 80 . As described below, the initial qualification phase may include preliminary assessments of conductance, tunneling spectroscopy, and temporal stability.

Regarding component conductance, a component is considered conductive if the resistance across the component measured between all three terminals at a high bias voltage V _bias,high > 2Δ (where Δ is the superconducting gap) is less than 25 kΩ of. For InSb-based devices, it may be necessary to initially open the channel by applying a positive voltage to the cutter gate. Regarding gate clamping, all gate resistances should be greater than 500 MΩ to ground. All gates used to form tunneling barriers (cutoffs) require individually clamped components. To test gate clamping, the conductance between a superconducting terminal and a corresponding conventional terminal was measured as a function of the cutter gate voltage under high bias. The component is considered clamped when a conductance of < 0.005 e ² /h is reached. The plunger gate used to tune the chemical potential in the topological segment should be able to tune the conductance through the element to some extent. The effect of the plunger gate can be most easily tested in the tunneling regime by using tunneling spectroscopy as described further below. Hysteresis on the cutter gate and plunger gate is acceptable because all measurements can be taken in the same sweep direction. However, it is required that the state in gate space does not shift measurably after a hysteresis cycle on either gate, as detailed below.

Regarding tunneling spectroscopy, once the cutter gate is tuned to a state where the high bias conductance is approximately 0.1 e ² /h, the bias and gate voltage dependencies (plunger or tunnel gate) are measured at zero magnetic field. pole) changes in conductance. At bias voltages near the expected superconducting gap, the peak value of the differential conductance with respect to the bias voltage should be clearly identifiable, and it should not change position with small changes in gate voltage (provided that high bias conductance There will be no major changes). At zero field and at energies below the superconducting gap, the number of finite conductance features should be small, thus reducing the chance of false positives. Ideally, the zero-field conductance trace should lack discrete subgap state features. This can be quantified by requiring the average subgap conductance to be less than 1/4 of the high bias conductance.

Regarding temporal stability, the high-bias conductance should be stable in the tunneling state. This means that the conductance should not move or drift more than Δg~0.2 e ² /h over a period of time t = 10 minutes. Regarding the RF response, for a specific component, resonances for fast RF measurements should be identified, for example, by comparing the resonances in the open and clamped states. For all terminals that need to be measured quickly, a clear response of the resonance is seen as a function of the corresponding tunnel gate. To obtain optimal sensitivity to conductance changes, effective impedance matching is required. Based on a typical component resistance of greater than or equal to 100 kΩ and a resonator inductance value of approximately 200 nH, the component's parasitic capacitance should be less than 1 pF to achieve high sensitivity.

Returning briefly to Figure 6, the measurements 62 of the mapping stage 58 include baseline corrections for electrical noise and energy broadening. This step is important because the energy broadening caused by the measurement setup will provide a lower limit for detectable topological gaps. To ensure negligible broadening due to electrical noise, the combined voltage noise RMS amplitude between 1 Hz and 500 Hz should be less than 3 µV.

Figure 7 shows an exemplary measurement setup for RF reflectometry. In RF reflection measurements, the sample is bonded to a transmission line via a resonator. The sample resistor changes the impedance match of the resonator to the transmission line, thereby changing the reflection coefficient of the RF signal sent into the line. RF reflection measurements were performed by bonding each of the component's two conventional conductive leads to a resonator with resonant frequencies fl _,res and _fr,res on the left and right sides, respectively. The frequency difference between the resonators on the left and right sides should be greater than the line width of each resonator. An intermediate-frequency (IF) source generates RF pulses within the bandwidth of the readout system. These pulses are upconverted into the frequency range of the resonator coupled to the component. For this purpose, a mixer with high (greater than 30 dB) carrier rejection mixes the IF signal with a local oscillator (LO) signal. The LO frequency must eliminate the frequency difference between the bandwidth f _ADC of the acquisition system and the two resonator frequencies fl _,res and f _r,res .

If the RF source does not have separate I and Q outputs, one of the upconverted sidebands must be filtered out. This can be achieved by selecting f _LO greater than max f _l,res , f _r,res and placing a low-pass filter with a cutoff frequency equal to f _LO between the upconversion mixer and the input port of the refrigerator. After the signal is reflected from the sample, it passes through a low-noise amplifier. This signal is then down-converted by a mixer using the original LO signal, low-pass filtered to the bandwidth of the acquisition system, and sent to the input of the acquisition system.

In order to measure local conductance by RF reflection measurement, the reflected RF signal value must be calibrated to the directly measured differential conductance, such as using a low-frequency lock-in amplifier. Since this is a sample-dependent procedure that can be executed in parallel with the actual measurement, it will be described below in conjunction with the measurement operation.

To benefit from the fast acquisition rate, the gate and bias scans on the components are triggered by hardware, thereby minimizing the time spent in software communication (typically around 10 ms). This can be accomplished in a hardware-triggered 2D scan synchronized with the acquisition system. Ramp one voltage with a sawtooth function and sample N times during each ramp, while the second voltage is at a lower rate during M cycles of the faster ramp, resulting in a scan of NxM points. To be compatible with the DC value of the voltage applied to the contacts and gates, these voltage sweeps are applied to the low-pass filtered DC line. The fastest ramp rate must be below the cutoff frequency of the low-pass filter in the refrigerator line (usually 1 kHz). For fast acquisition rates in sub-RF/DC measurements, measure a narrow bias range close to zero bias or measure the signal using, for example, a lock-in amplifier with a 2 Omega/3 Omega setting ’s second and third harmonics. In this manner, the bias scan is replaced with only target information regarding the presence of zero bias peaks and/or gaps in the component body. Details of mapping stage 58

Figure 8 shows other ways of measuring the radio frequency (RF) junction admittance of a semiconductor-superconductor heterojunction to obtain mapping data. Method 62A in Figure 8 illustrates the rapid measurement of local conductance by RF reflection measurements. Performing RF reflection measurements satisfies the first of the two topological gap criteria described above because it enables rapid Characterization and ZBP-based correlation identify candidates for topological regions. The identification of these regions lays the foundation for non-local measurements in the refinement stage 60 . The rapid local measurement of three-terminal components is closely related to the rapid measurement of conventional NS junctions.

In method 62A, step 82, the magnetic field is set to OT. In 84, for each side of a three-terminal component, the reflected RF signal is measured at a large bias voltage (e.g., 1 mV) that varies with frequencies near the estimated resonant frequency (100 MHz for each side) and Varies from the open channel set point (i.e. typically 0 V for InAs and 1 V for InSb) to the associated cutout voltage 100 mV above the full clamp-on voltage. The resonant frequency _fres is identified as the frequency at which the signal changes most dramatically with the cutter gate voltage, and the cutter voltage Vtunn _,res , where the inclination angle of the reflected signal as a function of frequency has the smallest absolute value.

In 86, the frequency is fixed at _fres and the cutter voltage range (V _c,min to V _c,max ) satisfying the following three conditions is determined:

(1) According to the reproducibility of the measurement after the hysteresis cycle, the range has no hysteresis.

(2) The local conductance measured well above the superconducting gap (eg 1 mV for Al) is 0.05 e ² /h to 0.2 e ² /h.

(3) The non-local conductance signal measured by standard low-frequency lock-in amplifier technology is higher than the noise level.

For large electrostatic crosstalk between plunger and cutter (geometry and material specific), this step can be repeated for different values of plunger gate voltage.

At 88, the RF readout power is optimized. In some instances, this action includes finding a region in cutter space that shows a clear gap with a well-defined coherence peak. To do this, scan the RF readout power on each side and measure it at the sample (bottom of the refrigerator) from -80 dBm to -130 dBm (in 1 dB steps). For each RF power, perform a rapid step of biasing the respective sides from _-1.5Δ0 to _1.5Δ0 (for Al, _Δ0 is the gap in the upper superconductor, which results in a bias range of -350 µV to 350 µV). Scan with a maximum step size of 5 µV and measure the reflected RF signal. For each side, find the maximum RF power that does not broaden the features (such as coherence peaks) in the measurement and set it as the operating RF power.

At 90, the magnetic field angle is calibrated to be parallel to the semiconductor wire. To this end, the magnetic field is set to a value such that the superconducting gap is not closed in the field parallel to the semiconductor wire, but is greatly reduced in the field perpendicular to the semiconductor wire, for example 500 mT for InAs and InSb SAG. The magnetic field angle is scanned around the expected value of the line geometry, and for each value of angle, the bias on each side of the element is scanned from -1.5Δ ₀ to +1.5Δ ₀ (-350 µV to +350 µV for Al). voltage with a maximum step size of 5 µV. The reflected RF signal is then measured. Set the field angle so that it gives the maximum gap size. The goal here is to achieve alignment accuracy better than 2° in both azimuth and polar angles.

In 92, the maximum magnetic field B _max with which the superconducting body gap is closed is determined. In 94, perform an RF-DC calibration by scanning the magnetic field from 0 T to B _max in steps of 100 mT. For each field value, perform the following additional calibration.

At 96, the optimal RF read power is measured. This can be accomplished by repeating step 84. However, once the readout frequency is identified, faster methods can be used. In one example, the cutter gate voltage is set to V _c,res , where the tilt angle of the reflected RF signal as a function of frequency has a minimum absolute value at zero field. The RF reflected signal is measured as a function of RF frequency on each side from 50 MHz to the resonant frequency found for the latest field value. The tilt angle closest to the magnitude of the RF signal to the previously found tilt angle is found and set to the RF readout frequency. The measurement results can be saved to the database.

At 98, the RF-DC calibration curve is measured. On each side, set the bias voltage to a high bias voltage (e.g. 1 mV for Al) so that it is above the superconducting gap. The respective cutout gate voltages are swept from the open channel set point (i.e., typically 0 V for InAs and 1 V for InSb) to 100 mV above the pinch-off voltage. For each disconnect voltage, the local conductance and reflected RF signals are measured using a lock-in amplifier on the respective side. The results of this measurement are saved to a database so that a calibration function between the reflected RF signal and the conductance can later be established.

In 100, set the magnetic field to 0T again. In 102, the magnetic field is ramped from 0 T to B _max in steps of ΔB. The field step ΔB depends on the g factor and allows the state to be tracked as the field moves. A reasonable range for InAs or InSb SAG is 10 mT≤ΔB≤50 mT. For each value of the field, perform the following additional steps.

At 104, the chopper gate potential is scanned independently for each side from V _c,min to V _c,max in N _C = 15 steps to obtain a total 2 N _C configuration. When the range of the cutter-plunger crosstalk lever arm and cutter gate scan is small enough that the effective plunger voltage does not change by more than the plunger voltage step, this independent scan is reasonable for local conductance measurements. . For each breaker gate configuration, perform the following measurements. The voltage limits V _c,min and V _c,max are determined at 86 .

At 106, a quick scan of the plunger voltage and bias is performed for each side. Scan the plunger voltage from V _p,max to V _p,min . The boundaries of the plunger are material specific and are limited by the upper and lower breakdown voltage (stopping at 80% of the breakdown voltage _Vbreak ) and the range of possible target areas. The latter ranges from completely gapless states to complete depletion and requires theoretical input. The resolution of the plunger scan needs to be sufficient to resolve the individual sub-gap states across the gap (depending on the lever arm). For each value of the plunger gate, scan the bias voltage at that terminal from -1.5Δ0 to 1.5Δ0 (-350 µV to +350 µV for Al) with a resolution of no more than 5 µV. Measure the reflected RF signal as a function of plunger and bias voltage. Save the resulting 2D scan to the database. In other instances, DC measurements may be used instead of RF in a narrow bias range close to zero bias.

The mapping data generated as the output of Method 62A includes the following:

1. The calibration data set consists of two 2D cutter-field scans on the left and right. For each point in this scan, three parameters are measured: the RF in-phase component, the RF out-of-phase component, and the conductance on each side.

2. Measurement data set containing two 5D field-left chopper-right chopper-plunger-bias scans, in which bias scans are performed on the left and right. For each point of this scan, two parameters are measured: the RF in-phase component and the RF out-of-phase component.

The goal of data analysis in this phase is to identify promising regions in parameter space that may contain unbroken topological phases. Figure 9 illustrates other aspects of analyzing mapping data to find one or more regions of parameter space consistent with the unbroken topology of a semiconductor-superconductor heterojunction.

At 108 of Method 64A, the RF signal input is converted to conductance using the calibration data set to define the transfer function. In 110, the local conductances of the respective left and right terminals (G _ll , G _rr ) from the bias traces measured at that point are used as inputs to (Field, Plunger, Cutoff) parameter space. Each point of is classified as (possibly) topological or trivial. In one example, during classification, both conductance traces can be checked for the presence of ZBP.

Analysis of the mapped data involves density-based clustering of ZBP data from both sides obtained from RF or sub-RF measurements. In 112, clusters of points that have been classified as topological are found and clusters deemed topologically incompatible with respect to quantities and shapes in parameter space are filtered out. In some instances, the amount of clustering must be greater than 0.03 V x T in plunger voltage-magnetic field space. The clusters that exist after filtering are possible regions where topological phases exist. In some examples, this step can be implemented with density-based clustering for each 2D plunger-field scan, and regions extending to zero magnetic field can be excluded. In 114, promising regions are ranked by their likelihood of containing topological phases. In some examples, the ranking score is determined by the average plunger gate voltage of each cluster, with priority associated with more negative gate voltages.

Figure 10 shows what mapping data looks like when analyzed according to Method 64A. Description and verification analysis of the simulation data set using InSb/Al nanowires with length L equal to 3 µm and a mean free path of 3 µm. The plunger gate (V) and magnetic field (T) shown in the figure from left to right are functions of: the topological index Q calculated from the scattering matrix; a binary array where 1 corresponds to the ZBP present on both sides of the element; and clustered ZBP Bollinger data, where the cluster color corresponds to the score of the corresponding cluster (smaller corresponds to better). Using this information, it is possible to find regions containing true topological regions for further analysis.

The results of the data analysis performed in the mapping stage 58 of the method 56 determine the measurements to be performed in the subsequent refinement stage 60 . For each promising region in the above ranking, a range of field, plunger, and cutter values for the enclosed region is specified as input to the refinement stage. In some instances, a refinement phase may be performed on each identified region in the ranking. The waiting time between the end of the measurement in the mapping phase and the start of the measurement in the refinement phase needs to be minimized to minimize the effects of gate drift, gate bounce and other problems that can occur when the component is idle . For this reason, it is critical that the data analysis outlined above be performed in a timely manner. It should be noted that the raw data generated during the RF measurement phase can be quite large: the total size of existing such RF data sets exceeds 100 GB, with reduction and analysis taking several hours. Details of Refinement Phase 60

A refinement phase is performed to find promising areas in more detail. Depending on the implementation, the refinement stage can be performed using RF or DC/sub-RF measurements. In one example, the differential conductance of the component under evaluation can be measured using standard low frequency lock-in amplifier techniques as shown in Figure 11. The full conductance matrix is measured by applying a DC _{bias voltage Vbias,l/r} and an AC voltage δVl _/r at the left and right terminals 54 using two different AC excitation frequencies f _l and _fr respectively. These frequencies must be below the low-pass filter cutoff in the system and low enough to minimize the effects of parasitic capacitance. To ensure this, the phase shift of the current relative to the voltage excitation must be less than 10°. The in-phase AC current δI _l/r flowing to the left or right side is measured using a grounded medium superconducting lead. The resistance of the connection to ground needs to be low ohmic compared to the other two lines (i.e. typically less than a few kΩ) to suppress false voltage divider effects. For this purpose, the low-pass filter can be designed accordingly, or the superconducting lead can be grounded at the PCB plane (cold ground).

This three-terminal setup enables measurement of all four elements of the conductance matrix G between the left (l) and right (r) terminals:

The conductivity matrix elements G _ll =dI _l /dV _l and G _rr =dI _r /dV _r are called "local conductance", while the elements G _lr =dI _l /dV _r and G _rl =dI _l /dV _r are called "non-conductance". local conductance".

The input to the refinement measurement 66 consists of a region in (slash gate, plunger gate, field) space that is a candidate for further study. In some embodiments, the size of the regions in the plunger gate/field space can be increased by 20% to ensure that the refined measurements adequately capture the topological phase transitions surrounding each region.

Figure 12 illustrates other aspects of measuring the sub-RF conductance of a semiconductor-superconductor heterojunction in each of one or more mapped regions of parameter space to obtain refined data. Specifically, Method 66A includes local and non-local conductance measurements suitable for extracting the energy gap of a semiconductor-superconductor heterojunction.

At 116 of method 66A, the magnetic field is set to the minimum field value in the candidate region. This field should be low enough that the induced gap is still open in order to observe whether it closes in the candidate region. At 118, the cutter gate is set to its median value in, for example, the candidate region. At 120, the small bias offsets of V _L and _VR (see Figure 11) are corrected to ensure direct extraction of the anti-symmetric components of the local and non-local signals. This can be achieved by finding the minimum value of the sum of the absolute currents (|I _L | + |I _R |) in the V _L -V _R parameter space. In 122, the magnetic field is ramped in the candidate region in steps of ΔB. For each value of the field, as will be described immediately below, a bias-plunger scan is performed.

At 124, the plunger voltage is set to the maximum plunger voltage (V _p,max ) in the area to be explored. Taking ΔV _p as a step, the plunger voltage is scanned from V _max to the minimum plunger voltage (V _p,min ) in the area to be explored. In other examples, the plunger voltage can be swept in opposite directions. For each plunger voltage value, sweep the bias voltage on the left terminal from –50 µV to +50 µV in 5 µV steps. If the data shows topological gaps outside this window, repeat the scan with a larger window size. Save the resulting 2D scan to the database.

The refined data produced by the slower full conductance matrix measurements is a data set for each candidate region. Each data set consists of two 3D field-plunger-bias scans, with separate bias scans on the left and right. For each point in the scan, two parameters are measured: conductance on the left and conductance on the right. In some embodiments, the dimensionality of the data set may be increased to also include, for example, a scan of the switch voltage. In some embodiments, each conductance may include a full conductance matrix for the corresponding side of the element.

Figure 13 illustrates finding boundaries of unbroken topological phases in parameter space and semiconductor-superconductor heterojunctions by analyzing refined data for at least one of one or more regions of parameter space interrogated in method 66A. Other aspects of topological gaps. In some embodiments, the illustrated method is performed iteratively for each promising region.

At 126 of method 68A, step 110 of method 64A is repeated to confirm that the measured region is still promising and to adjust the boundaries of the candidate topology region. At this point, analysis of the refined data includes checking for gap closure at the boundaries of each of the one or more regions of the parameter space. At 128, a check is performed to determine which portion of the boundary of the promising region is free of gaps based on the non-local conductance signal. At 130, the size of the gap Δ ^(j) at each point i in each region j is extracted by defining the non-local conductance. At 132, a score is assigned to the region based on the extent of the gap-free boundary and the value of gaps in the candidate topology region. The score reflects the probability that a promising region is actually topological and has gaps. In some instances, the fraction S is defined by S _i = X • median _i (Δ ^(j) ). At 134, estimates of the maximum gap and error within each topological region are obtained. In some instances, the uncertainty in the bounds of the non-local conductance at the point of maximum gap determines the error bar. This score is one of the possible scores, with the maximum replacing the median gap used as an exemplary surrogate score.

The output of this analysis contains a set of probabilities corresponding to the regions identified in the mapping stage 58 of the method 56 , ie, probabilities of having an unbroken topological phase. The maximum (topological) gap in each of the (non-trivial) regions is associated with each probability. Figure 14 shows the analysis of refined data according to Method 68A using the same simulation as in Figure 10. From left to right: gaps extracted from non-local data; fraction of ZBP clusters, which is defined by the average gap within a region multiplied by the percentage of gaps-free boundaries; and fraction of ZBP clusters, which is the same as the middle figure but with regions The median gap in replaces the mean gap. The maximum gap within the region is 175 µeV. The output of the overall method 56 is therefore an estimate of the value of the topological gap in each promising region and its position in the explored parameter space. Detailed examples of false positives and false negatives

One possible problem with quasi-Majorana is that it may arise as a precursor to a true topological state. This means that topological regions may be directly adjacent (in parameter space) to non-topological quasi-Majorana states. In that case, current algorithms for clustering regions of related ZBPs can identify regions that are too large during the mapping stage. In other words, although containing topological regions, the identified regions extend much further, including some quasi-Majorana states. In that case, the current analysis of the refinement phase fails because it identifies too much parameter space as topological or does not identify topological regions due to the absence of gap closing/reopening in the quasi-Majorana state.

The solution to this problem is to implement in the refinement phase another clustering algorithm that identifies lines of gap closing/reopening features in parameter space (specifically in field-plunger space); The intersection of this isoline with the region of the relevant ZBP is then determined to find the topological phase. It should be pointed out that this is mainly a problem of data analysis in the refinement stage. The mapping phase is still suitable for identifying promising areas of the material that are subject to closer inspection in the refinement phase.

Unstable behavior in data analysis can originate from data cutting with a fixed cutter voltage. Stability can be improved by using one or two switch-gate potentials as extra dimensions in refining the data analysis 68 . This should improve clustering and make better use of the available datasets.

The following example deals with smoothing potentials at the ends of semiconductor lines, which are associated with quasi-Majorana and false negatives. The presence of long-range inhomogeneities (changes in smooth potential) can make it more difficult to observe gap closing/reopening features, leading to false negatives. Interestingly, the change in smoothing potential is also what we would expect a quasi-Majorana pattern to appear. The interaction between the two effects is discussed here.

A typical situation in which quasi-Majorana modes occur is when the system is tuned close to but outside the topological phase. To make this concrete, consider an example where, in a fixed magnetic field, the chemical potential µ is smaller than the critical chemical potential µ _C required to enter the topological phase. The change in smooth potential can be interpreted as a spatially varying chemical potential µ(x) = µ ₀ V(x), where V(x) is the electric potential. In the above scenario, as shown in Figure 15, the potential inclination may be close to the end of the semiconductor wire (here on the right), thus locally tuning the system to the topological phase µ(x)>µ _C , which causes a local Majora That's the right pattern. The latter appears as a local conductance at the right end in much lower fields (which can be read out via the local conductance at the other (left) end where there is no smooth potential change) following the topological phase transition in the body of the semiconductor wire.

Figure 15 shows the effect of the smoothing potential at the right end of the semiconductor line in the 1D model. Left: Spatial dependence of the potential (bottom) and position of the semiconductor shell implemented via the self-energy of the semiconductor wire (orange, top). Right: Conductance matrix containing the antisymmetric part of the non-local conductance. It should be noted that the non-local conductance gapless reopening feature. The only characteristic of the phase transition is the occurrence of weak Majorana oscillations.

Specifically, in the example of Figure 15, the phase transition at fixed chemical potential is at _BC ≈ 2.7 T. In Method 56, the ZBP caused by the quasi-Majorana mode appearing near B≈1 T is accurately labeled as non-topological, because the non-local conductance has no gap closing and reopening characteristics. However, even in topological phase transitions, gap closing/reopening features are not visible. The reason is that part of the system under the smooth potential on the right has experienced phase transition, and therefore there is a gap in part of the system when B crosses B and _C. This suppresses the main mode signal during phase transition since it is only momentarily coupled to the right lead. It should be noted that in this particular model the topological gap is 100 µeV and is therefore larger than one would expect in a real system. For smaller gaps, the non-local signal becomes larger, thereby increasing the intensity of the gap closing/reopening feature. However, it is still difficult to observe gap closing/reopening since the signal of finite-sized oscillations will also be stronger.

In summary, although quasi-Majorana modes at the ends of semiconductor wires do not cause false positive features in non-local conductance, the presence of quasi-Majorana modes increases the likelihood of false negatives once the system is tuned to the topological phase .

The second example deals with the smoothing potential at the center of a semiconductor line associated with false positives. Here, we discuss the only example we have identified where a semiconductor wire has ZBP at both ends and there are non-trivial features in the non-local conductance that can be interpreted as gap closing (and possibly reopening), and the bulk of the system is non-trivial. Topological.

Figure 16 depicts the setup. The main body of the semiconductor wire is tuned to be non-topological, while the smooth potential bulge at the center of the semiconductor wire reaches the topological state of the potential. One can therefore think of a pair of Majorana zero modes nucleating at the center of a semiconductor wire. Although the central region is chosen to be too small for well-separated Majorana modes, the smoothness of the potential can lead to close but weakly coupled quasi-Majorana modes in the center of the semiconductor line.

As shown in Figure 16, due to the finite size effect, the corresponding zero mode can be detected as the associated ZBP of the conductance at each end. In addition, since the low-energy mode in the center overlaps with the sides, it also affects non-local conductance, which may be misinterpreted as gap closure.

Figure 16 shows the effect of the smoothing potential at the center of the semiconductor wire in the 1D model. Left: Spatial dependence of the potential (bottom) and position of the semiconductor shell implemented via the self-energy of the semiconductor wire (orange, top). Right: Conductance matrix containing the antisymmetric part of the non-local conductance. It should be noted that due to finite size effects, a quasi-Majorana mode nucleating at the central region is seen as the relevant ZBP and also affects the non-local conductance.

Figure 17 illustrates data analysis of the field/plunger parameter space of the gap method for a 1D model with a potential convexity at the center of a semiconductor wire. Left: Detected ZBP. Right: Gaps determined from data. In this case, the ZBP finder detects two overlapping regions: one centered on plunger equal to 0 (volume topology region), and one centered on plunger equal to 0.0025 (central convex topology). It is unclear whether this case represents a false positive (outside the volume topological region), since there is a small topological region in the center and the finite size effect is significant. In practical terms, the finite size effect results in the characteristic gap closure of each of the regions (center and body) in the estimated gap extracted from the data.

This problematic example illustrates the value of continued development of the data analysis used in the methods in this article. It should be noted that the ZBP clustering algorithm has identified two regions (center and body) as a single region. This example illustrates how nontopological regions adjacent to topological regions are relatively difficult to separate and require further refinement in data analysis.

The third example concerns non-topological ZBP caused by strong disorder. Represented here is an instance of a one-dimensional model with strong disorder. For example, Figure 18 shows data analysis of the field/plunger parameter space of an extremely disordered 1D model. Left: Points related to ZBP (red). Right: Extracted gap at each point in parameter space. Despite the presence of ZBPs, the data in Figure 18 show that the regions of associated ZBPs are sparse and largely disconnected. Extremely disordered regions can then be excluded by adding size and continuity requirements for the identified regions to the gap method. Instruments and other methods

Although the features and examples disclosed herein relate to methods for evaluating semiconductor-superconductor heterojunctions in qubit registers for use in topological quantum computers, these features and examples are also applicable to related instrumentation. Figure 19 shows aspects of an exemplary instrument 136 configured to evaluate semiconductor-superconductor heterojunctions in qubit registers for topological quantum computers. The instrument includes controller 18B. The controller includes at least one processor 20B and computer memory 22B operatively coupled to the processor. The computer memory is configured to hold instructions 24B that cause the processor to perform various measurement and analysis methods described herein. To this end, the processor may be operatively coupled to the RF admittance measurement element 138 and the sub-RF conductance measurement element 140 . The RF admittance measurement element may include the features shown in Figure 7; the sub-RF conductivity measurement element may include the features shown in Figure 11. In the example shown, instrument 136 includes interface 142 that couples the processor to the measurement element and also provides control signals to the electrostatic gate and magnet 144 of element 48 .

The features and examples revealed in this article are equally relevant for building topological quantum computers. Figure 20 shows aspects of an exemplary method 146 of building a topological quantum computer.

Fabricated in 148 of method 146 is a semiconductor-superconductor heterojunction having at least three terminals configured to support electron admittance testing. In 62, the RF junction admittance of the semiconductor-superconductor heterojunction is measured to obtain mapping data. At 64, the mapping data is analyzed to find one or more regions of parameter space consistent with the unbroken topology of the semiconductor-superconductor heterojunction. At 66, the sub-RF conductance of the semiconductor-superconductor heterojunction is measured in each of one or more regions of parameter space to obtain refined data. At 68, boundaries of unbroken topological phases and topological gaps of semiconductor-superconductor heterojunctions in the parameter space are found by analyzing the refined data for at least one of one or more regions of the parameter space. In 150, a semiconductor-superconductor heterojunction is added to the qubit register of a topological quantum computer, with the constraint that the found boundaries and topological gaps are within respective predetermined ranges. In the operation of a topological quantum computer built in this way, one or more values characterizing the boundaries in the parameter space can be used as tuning parameters to process the semiconductor-superconductor heterojunction in the qubit register.

Any aspect of the foregoing drawings or descriptions is not to be construed as limiting, as numerous additions, omissions and variations are also contemplated. As discussed above in the context of Figure 6 et seq., the Majorana zero mode can be found in two stages using a three-terminal element (e.g. element 48 of Figure 5), where for the first stage (i.e. For the mapping stage 58 of Figure 6), the measurements are done at RF, and for the second stage, the refinement stage 60, the measurements are done at low frequency or DC. Data analysis of the output data from the first stage effectively "converts" the output of the first stage into input suitable for the second stage. Final analysis of the output data from the second stage is then the basis for predictions of the existence and extent of topological regions useful for topological quantum computing. However, in other instances, the discrete and non-destructive stages of RF and DC measurements and the corresponding discrete and non-destructive stages of data analysis may not always be needed.

Figure 21 illustrates an example of a variant envisaged showing aspects of an exemplary method 56' for evaluating semiconductor-superconductor heterojunctions in qubit registers for topological quantum computers. Method 56' includes a mapping stage 58' and a refinement stage 60'. At 62', mapping data is obtained by measuring the RF admittance and/or sub-RF conductance of the semiconductor-superconductor heterojunction described herein. At 64', the mapping data is analyzed to find regions of parameter space that are consistent with the topology. At 66', refined data is obtained by measuring the RF admittance and/or sub-RF conductance of the semiconductor-superconductor heterojunction, focusing on any, some, or all of the regions found in 64'. At 68', the refined data are analyzed to find corresponding topological phase boundaries and topological gaps in each focus region.

For example, measurements with similar operations can be performed without being divided into discrete and non-destructive stages, since similar (e.g. equivalent) hardware and extraction methods can be used to measure the entire parameter space of a heterogeneous component or a predetermined region thereof Fast RF or DC measurements. In this case, the data analysis of the aforementioned second stage of measurement (68 in Figure 6) can be applied to a single measurement stage. The advantage of this variant may be one or more of speed (if RF technology is used) or thoroughness (if sub-RF or DC measurements are applied to the entire parameter space or a predetermined region thereof). Another advantage may be the combination of speed and other information, if sub-RF techniques are used to measure small bias windows close to zero bias, or to measure the second and third harmonics of the signal (see above).

In some examples, a two-phase protocol can also be performed in the first and second phases, but the two phases can be RF or DC. The second stage here may be a fine resolution scan of the sub-region shown in the first stage. The data analysis performed on the results of each stage may be similar to the data analysis obtained in the second stage (68 in Figure 6), with the output regions defined by the first stage analysis serving as input regions for the second stage measurements.

In some instances, immediate analysis of data from the first phase of measurement may trigger an abrupt transition to the second phase of measurement when promising regions are identified, as opposed to waiting for the entire parameter space to be covered before refinement. This variant can reduce the total evaluation time, especially when the parameter space to be covered is very large and/or the first stage of the measurement is a low-frequency or DC measurement.

In some examples, transitions in both directions between the first and second phases of measurement may be allowed, such that the mode of data acquisition alternates between the two phases. For this purpose, a fitness measurement of the parameter space is performed, and a shrinkage refinement of the found parameter values (i.e. a fine-resolution scan) is performed only when necessary. This strategy may lead to efficient scanning of large parameter spaces. In a more specific example, the initial first phase of measurements may be coarse-grained in magnetic fields and gate voltages, but can be adjusted after intermittent second phase data analysis to map with higher resolution. target area. Likewise, the bias range can be dynamically adjusted to perform volume gap extraction after initial gap closure is detected.

In some embodiments, any of the measurement and analysis sequences considered herein can be performed on a quad particle qubit element with an additional ground terminal. By grounding the tetrad, we can measure transmission through two regions that are simultaneously tuned to topological states. In these examples, tuning of the plunger and shutoff gate in the two regions can be done independently, but the magnetic field can be applied over the entire region. Here, a loop of parameters can be performed so that the outer loop is a magnetic field loop, thereby achieving simultaneous measurement of two regions. For example, data analysis can be performed as in Figure 13, but success is declared only when the topological states of the two regions overlap in the magnetic field values. For qubit operation after this tuning, the quadruple particle qubit can be operated in the ungrounded state.

In an example similar to the tetrad qubit example above, any of the measurement and analysis sequences considered herein can be performed on a tetrad qubit or a collection of many qubits (i.e., tetrads or higher). . One difference relative to the quadruple particle qubit example above is that success is only declared when three or more topological states overlap in magnetic field values.

In another variation on the two examples above, any of the existing (i.e. native) four-part and/or six-part terminals may be used as the ground terminal. Here, the current path through the element is used to ground individual qubits for Class 3 terminal measurements. In this variant, any sequence of measurements and analyzes considered here can be performed in series between different segments within the same qubit, but can also be performed in parallel on different qubits. Parallel interrogation of qubits can be used to further define target areas identified by individual interrogations. For both methods, the end of one segment is used to measure the other segments by bringing as many of the breaker gates to ground as possible. For tetrad or hexad qubits, this method involves performing agreement at least twice on a subset of the regions that will be tuned to the topological state.

In some scenarios, these additional instances could increase the speed of tuning a topological quantum computer and also increase the confidence in the obtained topological phases.

For additional context, the following references are incorporated herein by reference for all purposes.

T. Ô. Rosdahl, A. Vuik, M. Kjaergaard, and A. R. Akhmerov, Andreevrectifier: A nonlocal conductance signature of topological phase transitions, Phys. Rev. B 97, 045421 (2018).

Jeroen Danon, Anna Birk Hellenes, Esben Bork Hansen, Lucas Casparis,Andrew P. Higginbotham, and Karsten Flensberg, Nonlocal conductance spectroscopy of Andreev bound states: Symmetry relations and BCS charges, arXiv:1905.05438 [cond-mat] (2019), arXiv :1905.05438 [cond-mat].

G. C. Menard, G. L. R. Anselmetti, E. A. Martinez, D. Puglia, F. K.Malinowski, J. S. Lee, S. Choi, M. Pendharkar, C. J. Palmstrom, K. Flensberg, C. M. Marcus, L. Casparis, and A. P. Higginbotham, Conductance-matrix symmetries of a three-terminal hybrid device, arXiv:1905.05505 [cond-mat] (2019), arXiv:1905.05505 [cond-mat].

Davydas Razmadze, Deividas Sabonis, Filip K. Malinowski, Gerbold C.Menard, Sebastian Pauka, Hung Nguyen, David M.T. van Zanten, Eoin C.T. O'Farrell, Judith Suter, Peter Krogstrup, Ferdinand Kuemmeth, and Charles M. Marcus, Radio- Frequency Methods for Majorana-Based Quantum Devices: Fast Charge Sensing and Phase-Diagram Mapping, Phys. Rev. Applied 11,064011 (2019).

MITEQ AFS4-00100800-14-10P-4.

Appendix A: Agreement for finding topological phases in three-terminal approximate nanowire components Conclusion

In summary, one aspect of the present disclosure relates to methods for evaluating semiconductor-superconductor heterojunctions in qubit registers for use in topological quantum computers. Methods include measuring one or both of the radio frequency (RF) junction admittance of the semiconductor-superconductor heterojunction and the sub-RF conductance including the non-local conductance of the semiconductor-superconductor heterojunction to obtain mapping data and refinement data; by analyzing the mapping data to find one or more regions of parameter space consistent with an unbroken topology of the semiconductor-superconductor heterojunction; and by analyzing and refining the data for at least one or more regions of the parameter space One searches for the boundaries of unbroken topological phases in parameter space and the topological gaps of semiconductor-superconductor heterojunctions. This method provides a number of advantageous technical effects in the construction of topological quantum computers and topological quantum computers so constructed. These technical effects include the effects of accurately screening and tuning the qubits of quantum computers to improve performance.

In some embodiments, the measurement in this method is performed in a first and a second stage, wherein the mapping data is obtained in the first stage, and the refinement data is obtained in the second stage, and the second stage includes A scan of a subregion of one or more regions of parameter space found by analyzing mapping data. This variant provides additional technical benefits in increasing the efficiency of the screening/tuning process. In some embodiments, the method further includes an abrupt transition from the first stage to the second stage dependent on analysis of the mapping data. In some embodiments, measurements alternate between first and second stages to achieve adaptive measurements of the parameter space. These features provide the additional technical benefit of efficiently simultaneously exploring parameter space and accurately determining topological gaps in target regions, thereby improving filtering and tuning performance. In some embodiments, the measurements in the first stage have coarser granularity in magnetic field and/or gate voltage than in the second stage. In some embodiments, the method further includes dynamically adjusting the bias range between the first stage and the second stage to perform body gap extraction after detecting initial gap closure. In some embodiments, analysis of the mapping data includes performing density-based clustering of zero-bias peak data from opposite ends of the semiconductor-superconductor heterojunction. In some embodiments, the method further includes verifying a zero-bias peak (ZBP) in each of the one or more regions by examining the stability of the ZBP to changes in the cutter-gate voltage. ). In some embodiments, analysis of the refined data includes checking for gap closure at the boundaries of each of one or more regions of the parameter space. In some embodiments, the semiconductor-superconductor heterojunction is one of a series of similarly prepared semiconductor-superconductor heterojunctions, and the method further includes performing a meta-analysis on the zero-bias peak data in the series to calculate Probability of finding topological regions in another similarly prepared semiconductor-superconductor heterojunction. These variants provide the additional technical benefit of integrating other useful processes in the screening and tuning of topological qubits. In some embodiments, measuring sub-RF conductance includes performing local and non-local conductance measurements to identify and/or extract energy gaps of semiconductor superconductor heterojunctions. In some embodiments, a semiconductor-superconductor heterojunction includes a semiconductor wire and at least three terminals that support admittance and conductance measurements at opposite ends of the semiconductor wire. In some embodiments, a semiconductor-superconductor heterojunction includes a plurality of static control terminals. These variations provide the additional technical effect of performing qubit screening and tuning via accessible features of the qubit structure.

Another aspect of the disclosure relates to instruments configured to evaluate semiconductor-superconductor heterojunctions in qubit registers for topological quantum computers. The instrument includes a controller having a processor and a computer memory operatively coupled to the processor, the controller configured to: measure a radio frequency (RF) junction admittance of a semiconductor-superconductor heterojunction and include One or both of the non-local conductivity and the sub-RF conductance of the semiconductor-superconductor heterojunction to obtain mapping data and refined data; by analyzing the mapping data to find the unbroken topology consistent with the semiconductor-superconductor heterojunction one or more regions of the parameter space; and searching for the boundary of the unbroken topological phase in the parameter space and the topology of the semiconductor-superconductor heterojunction for at least one of the one or more regions of the parameter space by analyzing and refining the data gap. This provides the technical effect of increasing the efficiency of the screening/tuning instrument.

In some embodiments, the instrument is operatively coupled to an RF admittance measurement element and/or a sub-RF conductance measurement element.

Another aspect of the disclosure concerns methods for building topological quantum computers. The method includes: fabricating a semiconductor-superconductor heterojunction having at least three terminals configured to support electron admittance testing; measuring a radio frequency (RF) junction admittance of the semiconductor-superconductor heterojunction and including the semiconductor-superconductor heterojunction One or both of the non-local conductivity and sub-RF conductance of the junction are used to obtain mapping data and refined data; by analyzing the mapping data, a parameter space consistent with the unbroken topology of the semiconductor-superconductor heterojunction is found. or multiple regions; and searching for the boundary of the unbroken topological phase in the parameter space and the topological gap of the semiconductor-superconductor heterojunction for at least one of one or more regions of the parameter space by analyzing and refining the data; and in A semiconductor-superconductor heterojunction is added to the qubit register of a topological quantum computer. The restriction condition is that the found boundary and topology are within respective predetermined ranges. This approach provides technical results that improve the screening and tuning of constructed quantum computers.

In some embodiments, one or more values that characterize boundaries in parameter space are used as tuning parameters for processing semiconductor-superconductor heterojunctions in qubit registers. In some embodiments, a semiconductor-superconductor heterojunction is arranged in a quadruple particle qubit element with an additional ground terminal, and transmission through opposing regions tuned to a topological state is simultaneously measured. In some embodiments, a semiconductor-superconductor heterojunction is disposed in a hexagonal particle qubit element. In some embodiments, a semiconductor-superconductor heterojunction is disposed in a tetrad or hexad qubit element that has a native terminal used as a ground terminal in the present method, where the current path through the element is Connect individual qubits to ground to perform Class 3 terminal measurements. These variants provide the additional technical benefit of extending the method to topological quantum computer architectures that are currently of particular interest in the field.

Another aspect of the present disclosure concerns a two-stage method for topological phase extraction. Notably, this includes a separation by stage, where the mapping stage allows a broad search of the parameter space while still producing false positives, and the refinement stage allows false positives to be weeded out, thereby slowly scanning the target area of the mapping stage. Another aspect of this disclosure involves using density-based clustering algorithms on both sides of the ZBP data to extract predicted topological regions. It is worth noting that this includes the clustering algorithm used for this. We believe this is the first systematic approach to finding promising areas. Another aspect of the disclosure relates to mapping between RF and DC conductances to enable rapid conductance extraction in RF measurements. Notably, this involves using mapping to bypass the DC conductance measurement and still extract the same data, but much faster because RF technology is faster. Another aspect of the disclosure concerns using peak hunting or machine learning to perform classification of bias traces. Notably, this includes machine learning of topological traces and statistical characterization of how effective peak hunting is. Another aspect of the disclosure relates to gap extraction from non-local conductance traces, particularly using filtering and smoothing of bias traces and experimental noise or bias/field scans. Notably, this includes automatic gap extraction. Another aspect of the present disclosure relates to improving the accuracy of previous methods by checking for gap closure at the boundaries of suspected topological regions. Notably, this includes the application of self-extraction gaps to classify regions into topological/trivial regions. Another aspect of the disclosure is to perform a meta-analysis on ZBP data to extract the probability of finding a topological region among many components of the same preparation. This can be used to characterize growth/fabrication methods via topological phase diagrams. Another aspect of the present disclosure is to use any of the above to up-tune the qubits of a topological quantum computer.

It is to be understood that the configurations and/or methods described herein are illustrative in nature and such specific embodiments or examples should not be considered limiting as numerous variations are possible. The specific routines or methods described herein may represent one or more of any number of processing strategies. Thus, various actions illustrated and/or described may be performed in the sequence illustrated and/or described, performed in other sequences, performed in parallel, or omitted. Similarly, the order of the above-mentioned processes can be changed.

The subject matter of this disclosure includes all novel and non-obvious combinations and sub-combinations of the various processes, systems and configurations and other features, functions, behaviors and/or properties disclosed herein, and any and all equivalents thereof .

10: Quantum computer 12: Qubit register 14A: Qubit 14B: Qubit 14C: Qubit 14D: Qubit 14E: Qubit 14F: Qubit 14G: Qubit 14H: Quantum Bit 16: Bloch sphere 18A: Controller 18B: Controller 20A: Processor 20B: Processor 22A: Computer memory 22B: Computer memory 24A: Program instructions 24B: Instructions 26A: Data 28: Input 30: Output 32: Quantum interface 34: Modulator 36: Demodulator 40: Segment 42: Segment 44: Segment 46: MZM 48: Semiconductor-superconductor heterojunction element 50: Middle segment 52: Probe 54L: Contact 54R: Contact 56: Method 56': Method 58: Mapping stage 58': Mapping stage 60: Refining stage 60': Refining stage 62: Measurement 62': Step 62A: Method 64: Data analysis 64': Step 64A: Method 66 : Measurement 66A: Method 68: Data analysis 68A: Method 70: Verification stage 72: Semiconductor wire 74: Superconductor 75: MZM 76L: Electrostatic cutter gate 76R: Electrostatic cutter gate 78: Electrostatic plunger gate 80: Initial identification phase 82: Step 84: Step 86: Step 88: Step 90: Step 92: Step 94: Step 96: Step 98: Step 100: Step 102: Step 104: Step 106: Step 108: Step 110: Step 112: Step 114: Step 116: Step 118: Step 120: Step 122: Step 124: Step 126: Step 128: Step 130: Step 132: Step 134: Step 136: Instrument 138: RF admittance measurement element 140: times RF conductivity measurement element 142: Interface 144: Magnet 146: Method 148: Step 150: Step L: Maximum length of topological region L _N : Spacing between each cutter gate 76 and associated conventional lead 54 L _S : Length of the superconducting segment connecting the topological region to the lead-grounded superconductor 74 LO: local oscillator Q: topological index S: phase gate S ₀ : phase gate S ₁ : phase gate S ₂ : phase gate S ₃ : phase gate S ₄ : Phase gate V _P : Plunger voltage W: Semiconductor line width W _C : Width of each cutter gate 76 X: X quantum gate Y: Y quantum gate Z: Z quantum gate

Figure 1 shows what an exemplary quantum computer might look like.

Figure 2 illustrates a Bloch sphere, which graphically represents the quantum state of a qubit in a quantum computer.

Figure 3 shows the appearance of an exemplary signal waveform used to cause a quantum gate operation in a quantum computer.

Figure 4 shows an exemplary qubit architecture including a linear tetrad array.

Figure 5 shows aspects of an exemplary semiconductor-superconductor heterojunction device evaluated according to the methods of this article.

Figure 6 shows aspects of an exemplary method for evaluating semiconductor-superconductor heterojunctions in qubit registers for topological quantum computers.

Figure 7 shows an exemplary radio frequency (RF) reflection measurement test circuit.

Figure 8 shows aspects of an exemplary method for measuring the RF junction admittance of a semiconductor-superconductor heterojunction.

Figure 9 shows aspects of an exemplary method of finding a region of parameter space consistent with the unbroken topology of a semiconductor-superconductor heterojunction by analyzing data from the method of Figure 8.

Figure 10 shows how mapping data is analyzed according to the method in Figure 9.

Figure 11 shows what an exemplary sub-RF conductivity test circuit looks like.

Figure 12 shows aspects of an exemplary method for measuring sub-RF conductance of a semiconductor-superconductor heterojunction.

Figure 13 shows an aspect of an exemplary method for finding the boundaries of unbroken topological phases in parameter space and the topological gaps of semiconductor-superconductor heterojunctions by analyzing data from the method of Figure 12.

Figure 14 shows how the refined data is analyzed according to the method in Figure 13.

Figure 15 shows the effect of the smoothing potential at the right end of the semiconductor line in a 1D model of a semiconductor-superconductor heterojunction.

Figure 16 shows the effect of the smoothing potential at the center of the semiconductor line in a 1D model of a semiconductor-superconductor heterojunction.

Figure 17 shows the results of data analysis in the field/plunger parameter space of a 1D model of a semiconductor-superconductor heterojunction with a potential bulge at the center of the semiconductor wire.

Figure 18 shows the results of data analysis of the field/plunger parameter space for a highly disordered 1D model of a semiconductor-superconductor heterojunction.

Figure 19 shows aspects of an exemplary instrument configured to evaluate semiconductor-superconductor heterojunctions in qubit registers of a topological quantum computer.

Figure 20 shows an example method of building a topological quantum computer.

Figure 21 shows another exemplary evaluation method of a semiconductor-superconductor heterojunction in a qubit register for a topological quantum computer.

Domestic storage information (please note in order of storage institution, date and number) without Overseas storage information (please note in order of storage country, institution, date, and number) without

10:Quantum computer

12: Qubit register

14A: Qubits

14B: Qubit

14C: Qubit

14D: Qubits

14E: Qubits

14F: Qubit

14G: Qubits

14H: Qubit

18A:Controller

20A: Processor

22A:Computer memory

24A: Program instructions

26A:Information

28:Input

30:Output

32:Quantum interface

34:Modulator

36:Demodulator

Claims (20)

A method for evaluating a semiconductor-superconductor heterojunction in a qubit register for use in a topological quantum computer, the method comprising the following steps: One or both of a radio frequency (RF) junction admittance of the semiconductor-superconductor heterojunction and a primary RF conductance including a non-local conductance of the semiconductor-superconductor heterojunction are measured to obtain mapping data and refine data; Finding one or more regions of a parameter space consistent with an unbroken topology of the semiconductor-superconductor heterojunction by analyzing the mapping data; and Searching for a boundary of the unbroken topological phase in the parameter space and a topological gap of the semiconductor-superconductor heterojunction in at least one of the one or more regions of the parameter space by analyzing the refined data . The method of claim 1, wherein the measurement is performed in the first and second stages, wherein the mapping data is obtained in the first stage, and the refined data is obtained in the second stage, and wherein The second stage includes a scan of a sub-region of the one or more regions of the parameter space found by analyzing the mapping data. The method of claim 2, further comprising the step of suddenly transitioning from the first stage to the second stage depending on the analysis of the mapping data. The method of claim 2, wherein the measurement alternates between the first and the second stages to achieve an adaptive measurement of the parameter space. The method of claim 2, wherein the measurement in the first stage has coarser granularity in magnetic field and/or gate voltage than in the second stage. The method of claim 2, further comprising the step of dynamically adjusting a bias range between the first phase and the second phase to perform body gap extraction after detecting an initial gap closure. The method of claim 1, wherein the analyzing of the mapping data includes the step of performing density-based clustering on zero-bias peak data from opposite ends of the semiconductor-superconductor heterojunction. The method of claim 1, further comprising the step of verifying a zero bias in each of the one or more regions by checking the stability of the ZBP to changes in the disconnector-gate voltage. Pressure Peak (ZBP). The method of claim 1, wherein the step of analyzing the refined data includes the step of verifying gap closure at the boundary of each of the one or more regions of the parameter space. The method of claim 1, wherein the semiconductor-superconductor heterojunction is one of a series of semiconductor-superconductor heterojunctions with similar preparations, the method further includes the following steps: zero biasing the The peak data are subjected to meta-analysis to calculate a probability of finding a topological region in another similarly prepared semiconductor-superconductor heterojunction. The method of claim 1, wherein the step of measuring the secondary RF conductance includes the following steps: performing local and non-local conductance measurements suitable for identifying and/or extracting an energy gap of the semiconductor superconductor heterojunction . The method of claim 1, wherein the semiconductor-superconductor heterojunction includes a semiconductor wire and at least three terminals supporting admittance and conductance measurements at opposite ends of the semiconductor wire. The method of claim 1, wherein the semiconductor-superconductor heterojunction includes a plurality of electrostatic control terminals. An instrument configured to evaluate a semiconductor-superconductor heterojunction in a qubit register for a topological quantum computer, the instrument comprising: A controller having a processor and computer memory operatively coupled to the processor, the controller configured to: One or both of a radio frequency (RF) junction admittance of the semiconductor-superconductor heterojunction and a primary RF conductance including a non-local conductance of the semiconductor-superconductor heterojunction are measured to obtain mapping data and refine data; Finding one or more regions of a parameter space consistent with an unbroken topology of the semiconductor-superconductor heterojunction by analyzing the mapping data; and A boundary of the unbroken topological phase in the parameter space and a topological gap of the semiconductor superconductor heterojunction are found by analyzing the refined data for at least one of the one or more regions of the parameter space. The instrument of claim 14, wherein the instrument is coupled to an RF admittance measuring element and/or a primary RF conductance measuring element during operation. A method for building a topological quantum computer, the method includes the following steps: Fabricating a semiconductor-superconductor heterojunction having at least three terminals configured to support electronic admittance testing; One or both of a radio frequency (RF) junction admittance of the semiconductor-superconductor heterojunction and a primary RF conductance including a non-local conductance of the semiconductor-superconductor heterojunction are measured to obtain mapping data and refine data; Searching for one or more regions of a parameter space consistent with an unbroken topology of the semiconductor-superconductor heterojunction by analyzing the mapping data; searching for a boundary of the unbroken topological phase in the parameter space and a topological gap of the semiconductor-superconductor heterojunction by analyzing the refined data for at least one of the one or more regions of the parameter space; and The semiconductor-superconductor heterojunction is added to a qubit register of the topological quantum computer, and the restriction condition is that the found boundary and topological gap are within respective predetermined ranges. The method of claim 16, wherein one or more values characterizing the boundary in the parameter space are used as tuning parameters for processing the semiconductor-superconductor heterojunction in the qubit register. The method of claim 16, wherein the semiconductor-superconductor heterojunction is arranged in a quadrupole qubit element with an additional ground terminal, and wherein simultaneously crossing opposing regions tuned to a topological state The transmission is measured. The method of claim 16, wherein the semiconductor-superconductor heterojunction is arranged in a hexagonal particle qubit element. The method of claim 16, wherein the semiconductor-superconductor heterojunction is disposed in a quad- or hexa-particle qubit element with a native terminal serving as a ground terminal in the method, with the semiconductor-superconductor heterojunction passing through the A current path through the element is used to ground individual qubits to perform Class 3 terminal measurements.