TW202347169A - Sensing signal readout circuit, fingerprint identification device and information processing device controlled by a micro control unit to read out a sensing capacitance value from a capacitance sensing module - Google Patents

Abstract

The present invention mainly discloses a sensing signal readout circuit, which is controlled by a micro control unit to read out a sensing capacitance value from a capacitance sensing module, and includes: M*N charge amplifier units and M*N capacitance compensation units, wherein the capacitance compensation unit has a compensation capacitor. The sensing signal readout circuit further includes: M*N compensation signal generating units for generating M*N compensation signals to be respectively transmitted to the M*N compensation capacitors. According to the design of the present invention, each of the compensation signals has a compensation voltage, and the N compensation voltages in each row form a voltage value distribution. According to such design, after the sensing signal readout circuit of the present invention is used to read out the sensing capacitance value from the capacitance sensing module and convert it into a grayscale image, no black edges will appear on both sides of the grayscale image. Therefore, there is no need to use image processing software to perform any repair processing on the grayscale image.

Description

Sensing signal readout circuit, fingerprint identification device and information processing device

The present invention is in the technical field related to fingerprint identification, and in particular, refers to a sensing signal readout circuit controlled by a microcontrol unit to read out the sensing capacitance signal from a capacitance sensing module.

It is known that capacitive fingerprint recognition devices have been widely used in various electronic products. Traditionally, a capacitive fingerprint recognition device is usually installed on the front or back of a mobile smart terminal (such as a smartphone). However, as smartphones develop toward full-screen devices, capacitive fingerprint recognition devices share the same location as the power button, thus developing into side-side capacitive fingerprint recognition devices. Figure 1 shows a side view of a conventional full-screen smartphone. As shown in Figure 1, a capacitive fingerprint recognition device 2a is provided on the side of the full-screen smart phone 1a. Further, FIG. 2 is a schematic perspective view of the side-type capacitive fingerprint identification device 2a shown in FIG. 1 . Generally speaking, the capacitive fingerprint recognition device 2a includes a capacitive sensing module 20a and a fingerprint recognition circuit 21a, wherein the fingerprint recognition circuit 21a includes a circuit substrate 210a and a fingerprint recognition chip 211a, and the fingerprint recognition chip 211a Contains a sensing signal reading circuit and a micro control unit.

FIG. 3 is a side cross-sectional view of the capacitive sensing module 20a shown in FIG. 2 . As shown in FIGS. 2 and 3 , the capacitive sensing module 20a generally includes a substrate 201a, a capacitive sensor array 202a disposed on the substrate 201a, and a surface coating 203a. Further, FIG. 4 is a side cross-sectional view of the capacitive sensor array 202a shown in FIG. 3 . As shown in FIG. 4 , the capacitive sensor array 202a is covered by a surface coating 203a and includes M×N first metal plates M1a. When a finger presses on the surface coating 203a, an inductive capacitance (Cs1, Cs2,..., Csn) is formed between the first metal plate M1a and the finger. Therefore, the first metal plate M1a can be defined as a sensing pixel.

FIG. 5 is a top view of the capacitive sensing module 20a shown in FIG. 2 . Please refer to Figure 5, Figure 2 and Figure 1 at the same time. As smart phones become lighter and lighter, the width of the capacitive fingerprint recognition device 2a provided on the side of the phone is also forced to be reduced, resulting in the capacitive sensing module 20a The effective recognition area (Active area, AA) is getting smaller and smaller. Currently, the width of the AA area has been reduced from 3mm to 1.5mm or even lower.

To explain in more detail, FIG. 6 is a circuit topology diagram of a conventional charge amplifier unit. Generally speaking, the sensing signal readout circuit integrated in the fingerprint recognition chip 211a shown in FIG. 2 includes a plurality of charge amplifier units. As shown in FIG. 6 , the charge amplifier unit 212a includes: an operational amplifier 21OPa, a feedback capacitor CFa, a first switch S1a, a second switch S2a, and a reference capacitor. It is worth noting that when there is a finger touch, the capacitance value read by the charge amplifier unit 212a from the capacitance sensing module 20a is ΔC, which is represented by the capacitance Csa in the circuit of FIG. 6 . At the same time, FIG. 6 also depicts the so-called parasitic capacitance Cpa, where the parasitic capacitance Cpa represents the parasitic capacitance of a first metal plate M1a to ground.

The study found that due to the edge effect, the parasitic capacitance attached to the sensing pixel (first metal plate M1a) closer to the edge of the capacitive sensing module 20a is greater; conversely, the closer to the center of the capacitive sensing module 20a The smaller the parasitic capacitance attached to the sensing pixel is. If the capacitive sensing module 20a includes M×N sensing pixels, the capacitance value of the N parasitic capacitances in the j-th column can be expressed by the following formula (1): … … ………(1)

At the same time, due to the influence of the edge effect, the signal amount of the sensing capacitance Cs of the sensing pixel closer to the edge of the capacitive sensing module 20a will also be relatively large. As shown in Figure 7, after reading the signal amount of the sensing capacitance Cs from row 1 to row N, it can be found that the gray scale intensity of the sensing data is low in the middle and high on both sides. The sensing data is shown in Figure 8. The closer to the edge, the darker the image (semaphore), and eventually becomes a black border. Therefore, if the capacitive sensing module 20a is used to sense finger prints, the read image will be saturated due to excessive signal volume in the edge area, thereby causing image distortion.

The current solution is to use the outermost 1~2 rows of the capacitive sensing module 20a as dummy sensing pixels to ensure that no black edges will appear after the sensing data is read out and converted into a grayscale fingerprint image (i.e., Image distortion), and then use image processing software to repair the collected grayscale fingerprint image. However, such an approach will reduce the dynamic range and signal-to-noise ratio and is not an ideal solution.

From the above description, it can be seen that a new sensing signal readout circuit is urgently needed in this field.

The main purpose of the present invention is to provide a sensing signal readout circuit that is controlled by a microcontrol unit to read out the sensing capacitance value from the capacitance sensing module. After the sensing signal readout circuit of the present invention is used to read out the sensing capacitance value from the capacitance sensing module and convert it into a grayscale image, so-called black edges will not appear on both sides of the grayscale image. Therefore, There is no need to use image processing software to perform any repair processing on the grayscale image.

To achieve the above object, the present invention proposes a first embodiment of the sensing signal readout circuit, which is controlled by a microcontrol unit to read from a capacitive sensing module containing M×N sensing pixels. A plurality of sensing capacitance values are generated, and includes: M×N charge amplifier units and M×N capacitance compensation units respectively coupled to the M×N charge amplifier units, wherein the capacitance compensation units have a compensation Capacitor; It is characterized in that the sensing signal readout circuit further includes: M×N compensation signal generating units, used to generate M×N compensation signals to respectively transmit to the M×N compensation capacitors; Wherein, the N compensation signals in each column have a voltage value distribution.

In one embodiment, the compensation signal generating unit is a digital-to-analog converter or a non-inverting amplifier.

In one embodiment, the high-level voltages of the N compensation signals in each column satisfy the following mathematical inequality: … … Wherein, Vc1 is the high-level voltage of the compensation signal transmitted to the M compensation capacitors in the first row, and Vc2 is the high-level voltage of the compensation signal transmitted to the M compensation capacitors in the second row, Vcc is the high-level voltage of the compensation signal transmitted to the M compensation capacitors in the middle row, and Vcc+1 is the high-level voltage of the compensation signal transmitted to the M compensation capacitors in the adjacent row of the middle row. , and VcN is the high-level voltage of the compensation signal transmitted to the M compensation capacitors in the last row.

In one embodiment, the N compensation capacitors in each column have a compensation capacitance value distribution.

In order to achieve the above object, the present invention also proposes a second embodiment of the sensing signal readout circuit, which is controlled by a microcontrol unit to read from a capacitive sensing module containing M×N sensing pixels. A plurality of sensing capacitance values are generated, and includes: M×N charge amplifier units and M×N capacitance compensation units respectively coupled to the M×N charge amplifier units, wherein the capacitance compensation units have a compensation Capacitor; It is characterized in that the sensing signal readout circuit further includes: M×N compensation signal generating units, used to generate M×N compensation signals to respectively transmit to the M×N compensation capacitors; Wherein, the N compensation capacitors in each column have a compensation capacitance value distribution.

In one embodiment, the compensation signal generating unit is a digital-to-analog converter or a non-inverting amplifier.

In one embodiment, the N compensation capacitors in each column satisfy the following mathematical inequality: … … ; Among them, CB1 is the capacitance value of the M compensation capacitors in the first row, CB2 is the capacitance value of the M compensation capacitors in the second row, CBc is the capacitance value of the M compensation capacitors in the middle row, CBc+1 is the capacitance value of the M compensation capacitors in the adjacent rows of the middle row, and the capacitance value of the M compensation capacitors in the last row of CBN.

In one embodiment, each of the compensation signals has a compensation voltage, and the high-level voltage of the N compensation signals in each column satisfies the following mathematical inequality: … … ; Wherein, Vc1 is the high-level voltage of the compensation signal transmitted to the M compensation capacitors in the first row, and Vc2 is the high-level voltage of the compensation signal transmitted to the M compensation capacitors in the second row. , Vcc is the high-level voltage of the compensation signal transmitted to the M compensation capacitors in the middle row, Vcc+1 is the high-level voltage of the compensation signal transmitted to the M compensation capacitors in the adjacent row of the middle row voltage, and VcN is the high-level voltage of the compensation signal transmitted to the M compensation capacitors in the last row.

The present invention also provides a fingerprint identification device, which includes a capacitive sensing module, a micro control unit and the sensing signal reading circuit of the present invention as described above.

The present invention also provides an information processing device, which has the fingerprint identification device of the present invention as described above. In one embodiment, the information processing device is selected from the group consisting of smart phones, smart watches, smart bracelets, smart TVs, tablet computers, notebook computers, all-in-one computers, access control devices, electronic door locks, An electronic device among the group consisting of automatic teller machines and fingerprint punch-in machines.

In order to enable the review committee to further understand the structure, characteristics, purpose, and advantages of the present invention, drawings and detailed descriptions of preferred embodiments are attached below.

Figure 9 is a side view of a smart phone equipped with a fingerprint identification device of the present invention. Moreover, FIG. 10 is a schematic perspective view of a fingerprint identification device according to the present invention. As shown in Figures 9 and 10, the fingerprint identification device 2 of the present invention is applied in a smart phone 1, thereby serving as a side-type capacitive fingerprint identification device, and includes: a capacitive sensing module 20 and A fingerprint identification circuit 21, wherein the fingerprint identification circuit 21 includes a circuit substrate 210 and a fingerprint identification chip 211, and the fingerprint identification chip 211 contains a sensing signal reading circuit and a micro control unit. Further, FIG. 11 is a schematic side cross-sectional view of the capacitive sensing module 20 shown in FIG. 10 . As shown in FIGS. 10 and 11 , the capacitive sensing module 20 includes: a substrate 201 , a capacitive sensor array 202 disposed on the substrate 201 , and covering the capacitive sensor array 202 A surface coating (Passivation) 203.

FIG. 12 is a side cross-sectional view of the capacitive sensor array 202 shown in FIG. 11 , and FIG. 13 is a top view of the substrate 201 and the capacitive sensor array 202 shown in FIG. 11 . As shown in FIGS. 12 and 13 , in the capacitive sensor array 202 , M×N first metal plates M1 serve as M×N sensing pixels, where M and N are both positive integers. According to this design, when a finger presses on the surface coating 203, an inductive capacitance (Cs1, Cs2,..., Csn) will be formed between the first metal plate M1 and the finger. Therefore, the M×N first metal plates M1 are the M×N sensing pixels of the capacitive sensing module 20 .

To explain in more detail, the fingerprint identification circuit 21 shown in FIG. 10 includes a sensing signal reading circuit and a micro control unit. In a feasible embodiment, the sensing signal reading circuit and the micro control unit are integrated into a fingerprint recognition chip 211 as shown in Figure 10, where the sensing signal reading circuit includes M×N charge amplifiers unit and M×N capacitance compensation units respectively coupled to the M×N charge amplifier units. FIG. 14 shows a first circuit topology diagram of a charge amplifier unit and a capacitance compensation unit. As shown in FIG. 14 , the charge amplifier unit 212 includes: an operational amplifier 21OP, a feedback capacitor CF, a first switch SW1, and a second switch SW2. On the other hand, the capacitance compensation unit 213 includes: a compensation capacitor CB, a third switch SW3, and a fourth switch SW4.

As shown in FIG. 14 and FIG. 13 , the sensing signal readout circuit further includes: M×N compensation signal generating units 214, which are used to generate M×N compensation signals to be respectively transmitted to the M×N Compensation capacitor CB. According to the design of the present invention, each of the compensation signals has a compensation voltage Vc, and the N compensation voltages Vc of each column have a voltage value distribution.

At the same time, FIG. 14 also depicts the so-called parasitic capacitance Cp, where the parasitic capacitance Cp represents the parasitic capacitance of a first metal plate M1 to ground. Practical experience has found that the parasitic capacitance attached to the sensing pixel (first metal plate M1) closer to the edge of the capacitive sensing module 20 is greater; conversely, the sensing pixel closer to the center of the capacitive sensing module 20 has a larger parasitic capacitance. The attached parasitic capacitance is smaller. At the same time, due to the influence of the edge effect, the signal amount of the sensing capacitance Cs of the sensing pixel closer to the edge of the capacitive sensing module 20 will also be relatively large. As shown in Figure 7, after reading the signal amount of the sensing capacitance Cs from the 1st to the Nth row, it can be found that the grayscale intensity of the sensing data is low in the middle and high on both sides. Finally, it will appear in the collected grayscale image. Black borders form on both sides of the image.

According to the circuit diagram in Figure 14, it can be deduced that △Vc=△V _STIM ((Cf＋CB)∕CB)＋△V _STIM (Cp∕CB). Among them, △V _STIM is the change in the excitation voltage, Cf is the capacitance value of the feedback capacitor, CB is the capacitance value of the compensation capacitor, Cp is the capacitance value of the parasitic capacitor, and △Vc is the change in the high-level voltage of the compensation signal . That is, with the physical quantities of the feedback capacitance CF and the compensation capacitance CB fixed, the relationship between ΔVc and the parasitic capacitance Cp can be determined. Therefore, black edge compensation (elimination) can be achieved by selecting different compensation voltages (Vc1,...Vcc,...VcN) according to different parasitic capacitances (Cp1,...Cpc,...CpN).

Therefore, in order to compensate (eliminate) the black edges, the present invention makes the compensation signal generation unit 214 be a digital-to-analog converter (DAC) or a non-inverting amplifier, and controls N compensation signal generation units 214 in each column. N compensation signals are generated, wherein the high-level voltages of the N compensation signals satisfy the following mathematical inequality (I): … … …………(I)

In the mathematical inequality (I), as shown in Figure 13 and Figure 14, Vc1 is the high-level voltage of the compensation signal transmitted to the M compensation capacitors CB in the first row, and Vc2 is transmitted to the second row The high-level voltage of the compensation signal of the M compensation capacitors CB, Vcc is the high-level voltage of the compensation signal transmitted to the M compensation capacitors CB of the middle row, and Vcc+1 is the high-level voltage of the compensation signal transmitted to the middle row. The high-level voltage of the compensation signal of the M compensation capacitors CB in the adjacent row, and VcN is the high-level voltage of the compensation signal transmitted to the M compensation capacitors CB in the last row. Therefore, when mathematical inequality (I) is satisfied, the high-level voltages of the N compensation signals in each column have a voltage value distribution as shown in FIG. 15 .

According to the collected grayscale image in Figure 8, it can be seen that the black edges are usually the sensing pixels in the 1st to 3rd rows and the 1st to 3rd rows from the bottom. Therefore, when applying the present invention, you can only choose to perform black edge compensation on the sensing pixels in the 1st to 3rd rows and the 1st to 3rd rows from the bottom of the capacitive sensing module 20, thereby eliminating the grayscale image collected in Figure 8. The image has black edges. In addition, since the black edges are symmetrical, close compensation voltages Vc can also be combined to reduce the chip area.

Further, FIG. 16 shows a second circuit topology diagram of a charge amplifier unit and a capacitance compensation unit. As shown in FIG. 16 , in a feasible embodiment, the capacitance compensation unit 213 further includes a fifth switch SW5 and a bias voltage VDDA. Therefore, the following mathematical formula can be deduced based on the circuit diagram in Figure 16:

Among them, V _STIM is the excitation voltage, Cs is the capacitance value of the sensing capacitor, CF is the capacitance value of the feedback capacitor, CB is the capacitance value of the compensation capacitor, Cp is the capacitance value of the parasitic capacitor, V _DDA is the bias voltage, and Vc is The high level voltage of the compensation signal. That is, when the physical quantities of the feedback capacitor CF, the compensation capacitor CB, and the bias voltage VDDA are fixed, the relationship between the high-level voltage Vc of the compensation signal and the parasitic capacitance Cp can be determined. Therefore, black edge compensation (elimination) can be achieved by selecting different compensation voltages (Vc1,...Vcc,...VcN) according to different parasitic capacitances (Cp1,...Cpc,...CpN). Therefore, in order to compensate (eliminate) the black edges, the present invention allows the compensation signal generation unit 214 to be a digital-to-analog converter (DAC) or a non-inverting amplifier, and controls N compensation signal generation units in each column. 214 generates N compensation signals, and the high-level voltages of the N compensation signals satisfy mathematical inequality (I) as shown above.

It can be seen from the foregoing description that regardless of whether the sensing signal readout circuit has the charge amplifier unit 212 and the capacitance compensation unit 213 as shown in Figure 14 or Figure 16, the technical solution of the present invention can be used in the sensing signal readout circuit from a capacitive inductor. The measurement module 20 provides compensation during the process of reading the sensing capacitance value. Finally, after the sensing signal readout circuit of the present invention is used to read out the sensing capacitance value from the capacitance sensing module and convert it into a grayscale image, so-called black edges will not appear on both sides of the grayscale image. Therefore, there is no need to use image processing software to perform any repair processing on the grayscale image.

Further, FIG. 17 shows the compensation capacitance value distribution curve of the compensation capacitor. In a feasible embodiment, whether the sensing signal readout circuit has the charge amplifier unit 212, the capacitance compensation unit 213 and the compensation signal generation unit 214 as shown in Figure 14 or Figure 16, it can be achieved by changing the upper plate and lower plate of the capacitor. The area of the plate is such that the N compensation capacitors CB in each column have a compensation capacitance value distribution as shown in Figure 17. Such a design can further improve the compensation for the capacitance measurement of rows 1 to 3 on both sides, ensuring that the outer compensation is more and the middle compensation is low.

In this way, the above has completely and clearly described a sensing signal readout circuit of the present invention; and from the above, it can be seen that the present invention has the following advantages:

(1) The present invention discloses a sensing signal readout circuit that is controlled by a microcontrol unit to read out the sensing capacitance value from the capacitance sensing module. After the sensing signal readout circuit of the present invention is used to read out the sensing capacitance value from the capacitance sensing module and convert it into a grayscale image, so-called black edges will not appear on both sides of the grayscale image. Therefore, There is no need to use image processing software to perform any repair processing on the grayscale image.

(2) The present invention also provides a fingerprint identification device, which includes a capacitive sensing module, a micro control unit and the sensing signal reading circuit of the present invention as described above.

(3) The present invention also provides an information processing device, which has the fingerprint identification device of the present invention as described above. Moreover, the information processing device is selected from the group consisting of smart phones, smart watches, smart bracelets, smart TVs, tablet computers, notebook computers, all-in-one computers, access control devices, electronic door locks, and ATM machines. , and an electronic device in the group consisting of fingerprint punch-in machines.

It must be emphasized that the foregoing disclosed in this case are preferred embodiments. Any partial changes or modifications derived from the technical ideas of this case and easily inferred by those familiar with the art do not deviate from the patent of this case. category of rights.

To sum up, regardless of the purpose, means and effects of this case, it shows that it is completely different from the conventional technology, and that the invention is practical first, and indeed meets the patent requirements for inventions. I sincerely ask the review committee to take a clear look and grant the patent as soon as possible for your benefit. Society is a prayer for the Supreme Being.

1a: Full screen smartphone 2a: Capacitive fingerprint recognition device 20a: Capacitive sensing module 201a:Substrate 202a: Capacitive sensing module 203a: Surface coating 21a: Fingerprint recognition circuit 210a: Circuit substrate 211a: Fingerprint recognition chip 212a: Charge amplifier unit 21OPa: Operational amplifier M1a: first metal plate CFa: feedback capacitor Cpa: parasitic capacitance Csa: sensing capacitance SW1a: first switch SW2a: Second switch 1: Full screen smartphone 2:Fingerprint identification device 20: Capacitive sensing module 201:Substrate 202: Capacitive sensing module 203: Surface coating 21:Fingerprint recognition circuit 210:Circuit substrate 211:Fingerprint recognition chip 212: Charge amplifier unit 21OP: Operational amplifier 213: Capacitor compensation unit 214: Compensation signal generation unit M1: First Metal Plate CF: feedback capacitor CB: compensation capacitor Cp: parasitic capacitance Cs: sensing capacitance Cs1～Csn: Inductive capacitance SW1: first switch SW2: Second switch SW3: The third switch SW4: The fourth switch SW5: The fifth switch

Figure 1 is a side view showing a conventional full-screen smartphone; Figure 2 is a schematic three-dimensional view of the side-type capacitive fingerprint recognition device shown in Figure 1; FIG. 3 is a side cross-sectional view of the capacitive sensing module shown in FIG. 2 . Figure 4 is a side cross-sectional view of the capacitive sensor array shown in Figure 3; Figure 5 is a top view of the capacitive sensing module shown in Figure 2; Figure 6 is a circuit topology diagram of a conventional charge amplifier unit; Figure 7 is a graph of sensing data read from the capacitive sensing module in sequence; Figure 8 is a grayscale image of the sensing data read out by the self-capacitance sensing module; Figure 9 is a side view of a smartphone equipped with a fingerprint identification device of the present invention; Figure 10 is a schematic three-dimensional view of a fingerprint identification device according to the present invention; Figure 11 is a schematic side cross-sectional view of the capacitive sensing module shown in Figure 10; Figure 12 is a side cross-sectional view of the capacitive sensor array 202 shown in Figure 11; Figure 13 is a top view of the substrate and capacitive sensor array shown in Figure 11; Figure 14 is a first circuit topology diagram of a charge amplifier unit and a capacitance compensation unit; Figure 15 is the voltage value distribution curve of the compensation voltage; Figure 16 is a second circuit topology diagram of the charge amplifier unit and capacitance compensation unit; and Figure 17 is a voltage value distribution curve diagram of the compensation voltage.

212: Charge amplifier unit

21OP: Operational amplifier

213: Capacitor compensation unit

214: Compensation signal generation unit

M1: First Metal Plate

CF: feedback capacitor

CB: compensation capacitor

Cp: parasitic capacitance

Cs: sensing capacitance

SW1: first switch

SW2: Second switch

SW3: The third switch

SW4: The fourth switch

Claims (10)

A sensing signal readout circuit is controlled by a microcontrol unit to read out a plurality of sensing capacitance values from a capacitive sensing module containing M×N sensing pixels, and includes: M×N charges Amplifier units and M×N capacitance compensation units respectively coupled to M×N charge amplifier units, where M and N are both positive integers, and the capacitance compensation unit has a compensation capacitor; characterized in that, The sensing signal readout circuit further includes: M×N compensation signal generating units, used to generate M×N compensation signals to respectively transmit to the M×N compensation capacitors; Wherein, the N compensation signals in each column have a voltage value distribution. The sensing signal readout circuit of claim 1, wherein the compensation signal generating unit is a digital-to-analog converter or a non-inverting amplifier. The sensing signal readout circuit as described in claim 1, wherein the high-level voltages of the N compensation signals in each column satisfy the following mathematical inequality: … … ; Wherein, Vc1 is the high-level voltage of the compensation signal transmitted to the M compensation capacitors in the first row, and Vc2 is the high-level voltage of the compensation signal transmitted to the M compensation capacitors in the second row. , Vcc is the high-level voltage of the compensation signal transmitted to the M compensation capacitors in the middle row, Vcc+1 is the high-level voltage of the compensation signal transmitted to the M compensation capacitors in the adjacent row of the middle row voltage, and VcN is the high-level voltage of the compensation signal transmitted to the M compensation capacitors in the last row. The sensing signal readout circuit of claim 1, wherein the N compensation capacitors in each column have a compensation capacitance value distribution. A sensing signal readout circuit is controlled by a microcontrol unit to read out a plurality of sensing capacitance values from a capacitive sensing module containing M×N sensing pixels, and includes: M×N charges Amplifier units and M×N capacitance compensation units respectively coupled to M×N charge amplifier units, where M and N are both positive integers, and the capacitance compensation unit has a compensation capacitor; characterized in that, The sensing signal readout circuit further includes: M×N compensation signal generating units, used to generate M×N compensation signals to respectively transmit to the M×N compensation capacitors; Wherein, the N compensation capacitors in each column have a compensation capacitance value distribution. The sensing signal readout circuit of claim 5, wherein the compensation signal generating unit is a digital-to-analog converter or a non-inverting amplifier. The sensing signal readout circuit as described in claim 5, wherein the N compensation capacitors in each column satisfy the following mathematical inequality: … … ; Among them, CB1 is the capacitance value of the M compensation capacitors in the first row, CB2 is the capacitance value of the M compensation capacitors in the second row, CBc is the capacitance value of the M compensation capacitors in the middle row, CBc+1 is the capacitance value of the M compensation capacitors CB transmitted to the adjacent row of the middle row, and the capacitance value of the M compensation capacitors in the last row of CBN. The sensing signal readout circuit of claim 5, wherein the high-level voltages of the N compensation signals in each column satisfy the following mathematical inequality: … … ; Wherein, Vc1 is the high-level voltage of the compensation signal transmitted to the M compensation capacitors in the first row, and Vc2 is the high-level voltage of the compensation signal transmitted to the M compensation capacitors in the second row. , Vcc is the high-level voltage of the compensation signal transmitted to the M compensation capacitors in the middle row, Vcc+1 is the high-level voltage of the compensation signal transmitted to the M compensation capacitors in the adjacent row of the middle row voltage, and VcN is the high-level voltage of the compensation signal transmitted to the M compensation capacitors in the last row. A fingerprint identification device includes a capacitive sensing module, a microcontrol unit and a sensing signal reading circuit as described in any one of claims 1 to 4. An information processing device having a fingerprint identification device as described in claim 9.

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