TW202347111A - Adaptive data encoding for memory systems - Google Patents

Abstract

Systems and methods for adaptive data encoding for memory systems are disclosed. In one aspect, a memory bus replaces a data bus inversion encoding technique with a more flexible encoding scheme which periodically calculates cluster centers based on pending data transactions. The dynamic cluster centers are used with an exclusive OR (XOR) function to minimize the number of bits that consume power sent over a memory bus. For example, in some standards, sending a one involves a state transition and consumes power. In other standards, sending a zero involves a state transition and consumes power. The present disclosure is applicable to both situations. By minimizing the power consuming bits sent over the memory bus, less power is consumed.

Description

Self-tuning data encoding for memory systems

The technology involved in this case relates generally to sending and receiving data to and from memory devices, and specifically to encoding schemes used in memory devices.

Computing devices are abundant in modern society, and mobile communication devices in particular have become increasingly common. The popularity of such mobile communication devices is driven in part by the many functions now implemented on such devices. The increased processing power in such devices means that mobile communication devices have evolved from pure communication tools to sophisticated mobile entertainment centers, enabling an enhanced user experience. With the vast number of features available for such devices, there is increasing pressure to find ways to reduce power consumption. Memory systems that support processing power provide opportunities for innovation and power reduction.

Aspects disclosed in the detailed description include systems and methods for self-adjusting data encoding for memory systems. Specifically, exemplary aspects of this content contemplate replacing the data bus inversion encoding technique with a more flexible encoding scheme that periodically calculates the cluster center based on pending data transactions (pending data transactions). cluster center). Dynamic Cluster Center is used with the exclusive OR (XOR) function to minimize the number of power-consuming bits sent on the memory bus. For example, in some standards, sending one involves a state transition and consumes power. In other standards, sending zeros involves state transitions and consumes power. The content of this case applies to both situations. By minimizing the number of power bits sent over the memory bus, less power is consumed.

At this point, in one aspect, an integrated circuit (IC) is disclosed. The IC includes a bus interface configured to couple to a memory bus. The IC also includes a memory controller coupled to the bus interface. The memory controller is configured to send one or more data masks from a plurality of data masks to the memory device via the bus interface. The one or more data masks include corresponding patterns to be used when decoding encoded data sent to the memory device.

In another aspect, an IC is disclosed. The IC includes a bus interface configured to couple to a memory bus. The IC also includes a memory controller coupled to the bus interface. The memory controller is configured to send one or more data masks from a plurality of data masks to the memory device via the bus interface. The one or more data masks include an encoding mask used by the memory device to encode data to be sent to the memory controller.

In another aspect, an IC is disclosed. The IC includes a bus interface configured to couple to a memory bus. The IC also includes a pattern register that includes a plurality of data masks stored therein. The IC also includes encoding circuitry configured to use at least one data mask of the plurality of data masks to encode data to be sent to the memory controller via the bus interface.

In another aspect, an IC is disclosed. The IC includes a bus interface configured to couple to a memory bus. The IC also includes a mode register configured to have one or more data masks stored therein for decoding data sent from the memory controller.

Several illustrative aspects of the subject matter will now be described with reference to the accompanying drawings. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspects described herein as "exemplary" are not necessarily to be construed as better or advantageous over other aspects.

Aspects disclosed in the detailed description include systems and methods for self-adjusting data encoding for memory systems. Specifically, exemplary aspects of this disclosure contemplate replacing the data bus inversion encoding technique with a more flexible encoding scheme that periodically calculates the cluster center based on pending data transactions. Dynamic Cluster Center is used with the exclusive OR (XOR) function to minimize the number of power-consuming bits sent on the memory bus. For example, in some standards, sending one involves a state transition and consumes power. In other standards, sending zeros involves state transitions and consumes power. The content of this case applies to both situations. By minimizing the number of power bits sent over the memory bus, less power is consumed.

Before addressing the details of the content of this case, a brief overview of an exemplary environment that may benefit from the content of this case is provided with reference to Figures 1 and 2. The discussion of self-adjusting encoding technology will begin with reference to Figure 3 below.

In this aspect, FIG. 1 is a block diagram of a memory system 100 that includes a host 102 and a plurality of memory devices 104 ( 1 )-104(N). In exemplary aspects, host 102 may be an integrated circuit (IC) that acts as a system on a chip (SoC), an applications processor, a primary data machine, or is designed to access memory devices 104(1)-104( N) other control circuits to execute. The host 102 may include a neural processing unit 108 , a graphics processing unit (GPU) and a multimedia engine 110 and/or a multi-core central processing unit (CPU) 112 . Neural processing unit 108 , GPU and multimedia engine 110 and/or multi-core CPU 112 may communicate with memory controller 114 via system bus 116 . Memory controller 114 may send data across data line 120 to physical layer (PHY) 118 . PHY 118 is a memory bus interface and may include encoding logic 122 that routes data from data lines 120 to appropriate pins coupled to memory bus 106 (eg, data pins).

Memory devices 104(1)-104(N) may be identical, and discussion of general memory device 104 is provided accordingly. Memory device 104 may include an input-output (I/O) block 124 . The I/O block 124 is a memory bus interface and communicates with the bank 126 of the data cell array 128 using read and write commands, as is well known. I/O block 124 may also include encoding logic 130 that routes data from the data lines to the appropriate pins coupled to memory bus 106 . Memory bus 106 may include twenty-four data conductors, four clock conductors, and four read clock strobe (RDQS) conductors. Accordingly, memory bus interfaces 118, 124 may include twenty-four pins corresponding to data conductors (eg, data pins), four pins corresponding to clock conductors (eg, clock pins), and Four pins corresponding to the RDQS conductors. Additional conductors may be provided for command and address signals, additional clock signals, die select signals, and/or reset signals.

In one exemplary aspect, the conductors of memory bus 106 are arranged in a specific layout. That is, starting from the first edge and moving inward, there is a data conductor (DQ0), a differential clock channel with two conductors (WCK0_t, WCK0_c), a differential RDQS channel with two conductors (RDQS0_t, RDQS0_c) and more data Conductors (DQ0), shown generally as first group 132. In the center portion of memory bus 106, the command and address (CA[0:k]) channel conductors, a differential command clock channel with two conductors (CK_t, CK_c), the die select channel conductor, and the reset channel conductor may be located, shown generally as middle group 134. Then, moving outward toward the second edge of the memory bus 106, there is the data conductor (DQ1), a differential clock channel with two conductors (WCK1_t, WCK1_c), a differential RDQS with two conductors (RDQS1_t, RDQS1_c) channels and further data conductors (DQ1), which are shown in their entirety as second group 136. While there are various reasons for this arrangement in terms of ease of routing, electromagnetic interference (EMI), and/or electromagnetic compatibility (EMC), it should be understood that other arrangements may be used.

Additionally, as an additional feature, memory controller 114 may include error correction code (ECC) circuitry 140 that may encode and decode ECC signals. Additionally, the data cell array 128 may include an ECC cell 142 that stores parity bits and works with the ECC circuit 140 for error correction. In an exemplary aspect, the ECC parity bit (p, as opposed to data 2*n) may be transmitted from the host 102 to the memory device 104 on the RDQS pin (eg, RDQS_t, RDQS_c, or both), such as during a write during operation. For reverse operations, ECC parity bits can be transferred in the data mask slot during read operations. Alternatively, instead of using the RDQS signal, the host 102 can use the data mask slot (eg, M[0:31]) for write operations.

Each memory device 104(1)-104(N) may have a mode register 146 and encoding circuitry (not shown) that will be used to identify whether various aspects of the content are in use, as described in more detail below. explained.

For further context, FIG. 2 is the system level of an exemplary mobile communications device or mobile terminal 200 (such as a smartphone, mobile computing device tablet, etc.) in which a memory system (such as the memory system 100 of FIG. 1 ) may be found. Block diagram. Although mobile terminals are specifically envisioned as exemplary aspects that can benefit from the contents of this document, it should be understood that the contents of this document are not so limited and may be useful in any system with a memory bus that complies with existing or emerging memory standards. of.

Continuing with reference to FIG. 2 , the mobile terminal 200 includes an application processor 204 (sometimes referred to as a host or SoC) that communicates with a large storage device 206 via a universal flash storage (UFS) bus 208 . More relatedly, according to exemplary aspects of the disclosure, application processor 204 may communicate with double data rate (DDR) memory device 104 via memory bus 106 . The applications processor 204 may also be connected to the display 210 via a display serial interface (DSI) bus 212 and to the camera 214 via a camera serial interface (CSI) bus 216 . Various audio components, such as microphone 218 , speaker 220 , and audio transcoder 222 , may be coupled to applications processor 204 via serial low-power inter-chip multimedia bus (SLIMbus) 224 . Additionally, audio components can communicate with each other via SOUNDWIRE bus 226. Modem 228 may also be coupled to SLIMbus 224 and/or SOUNDWIRE bus 226. The modem 228 may also be connected to the application processor 204 via a Peripheral Component Interconnect (PCI) or PCI Express (PCIe) bus 230 and/or a System Power Management Interface (SPMI) bus 232 .

Continuing with Figure 2, the SPMI bus 232 may also be coupled to a local area network (LAN or WLAN) IC (LAN IC or WLAN IC) 234, a power management integrated circuit (PMIC) 236, a companion IC (sometimes referred to as a bridge chip) 238 and radio frequency IC (RFIC) 240. It should be appreciated that separate PCI buses 242 and 244 may also couple application processor 204 to companion IC 238 and WLAN IC 234. Application processor 204 may also be connected to sensor 246 via sensor bus 248 . Modem 228 and RFIC 240 may communicate using bus 250.

Continuing with reference to FIG. 2 , RFIC 240 may be coupled via radio frequency front end (RFFE) bus 258 to one or more RFFE components, such as antenna tuner 252 , switch 254 , and power amplifier 256 . Additionally, RFIC 240 can be coupled to an envelope tracking power supply (ETPS) 260 via bus 262 , and ETPS 260 can communicate with power amplifier 256 . The RFFE components including RFIC 240 may collectively be considered RFFE system 264 . It should be appreciated that RFFE bus 258 may be formed from clock lines and data lines (not shown).

In the past, data communication between the memory controller 114 and the memory device 104 may have been one of the largest power consumers. Specifically, in low power double data rate (LPDDR) systems, power is consumed when transmitting a logic high or logic one. To reduce power consumption, existing LPDDR systems can use a data bus inversion (DBI) encoding scheme, where if there are more ones than zeros in a block of eight bits, the data is inverted and the data is The Mask Inversion (DMI) bit is sent with the signal to the memory device to indicate to the memory device that an inversion has occurred. While DBI does provide some power savings over unencoded signaling, the subtleties of DBI encoding are relatively crude and may not encode ones and zeros optimally. It should be noted that DBI can also be used in other systems, such as ordinary DDR memory, graphics DDR (GDDR) memory, high bandwidth memory (HBM), etc. It is also possible that DBI can be used outside of memory configurations. Additionally, while many systems are designed so that sending a logic one involves a logic high or state transition that consumes power on the line, some systems may consume power when sending a zero. The content of this case works by replacing one with zero in any case. Therefore, all such environments can benefit from various aspects of this case.

As a nomenclature, Double Data Rate (DDR) is a technical term within the JEDEC specification and the general memory community. As used herein, DDR is defined as a signaling technology that uses both the falling and rising edges of a clock signal. This use of two edges is independent of frequency, and changes in frequency (e.g., doubling) do not fall within the DDR unless two edges are used. DDR is also compared to single data rate (SDR), which can transmit data on either the rising edge or the falling edge, but not both at the same time.

Exemplary aspects of the present content provide a self-adjusting encoding scheme that provides greater nuance by allowing data to be encoded using better data masks. DMI bits can be repurposed to indicate which data mask is being used so that the memory device can use the correct data mask for decoding.

The techniques described herein are readily expressed as procedures, and are specifically shown in procedure 300 in Figure 3, where additional explanation of the steps is provided with reference to Figures 4A-4F. At this point, the process 300 begins by calculating an optimal mask based on the observed traffic (block 302). That is, the memory controller 114 is aware of the data included in any write command, and may be aware of certain types of read data (eg, weights in a machine learning system). Accordingly, as shown in FIG. 4A , the memory controller 114 may have a plurality of write transactions in the queue 400 , and periodically (eg, every sixty-four (64) transactions), the memory controller 114 may based on Queue the transactions to calculate a set of cluster centers 402(0)-402(N) (where N is 3 as shown). This calculation may be accomplished via having up/down counters 408 (see Figure 4C) representing the center of each cluster (eg, one counter per data line per cluster for the sixty-four counters in the exemplary system). For each sixteen-bit chunk of data 404, the memory controller 114 may find the nearest cluster center 402(0) based on finding the minimum Hamming distance 406(0)-406(3), see also Figure 4B, in which cluster center 402(0) is identified. It should be noted that other cluster sizes can be selected. So, for example, instead of sixteen-bit data blocks, four, eight, thirty-two, sixty-four or more could be used. Likewise, although powers of two are anticipated, other values are possible.

It should be noted that because in some cases the memory controller 114 may know what patterns are within the material being read, the memory controller 114 may instruct the memory device 104 to encode the material using a data mask. That is, the data mask may serve as an encoding mask that includes values that are inserted into a function (eg, XOR) that encodes the data to be sent to the memory device 104 .

As shown in Figure 4C, if one is indicated in the profile 404, the corresponding counter 408 for the sought cluster center 402(0) is incremented, and if zero is indicated, the corresponding counter 408 is decremented. Based on the results of counter 408, a new cluster 410 is calculated, as shown in Figure 4D. In certain aspects, the new cluster 410 is selected based on whether the updated counter is greater than five. Therefore, for example, as shown in Figure 4D, elements 412(1)-412(2), 412(4)-412(6), 412(9)-412(14), and 412(16) are less than five, so the The equal bit is 0, and elements 412(3), 412(7), 412(8), and 412(15) are greater than five, and the equal bit is 1. It will be appreciated that upon startup or configuration, a preset set of cluster centers may be initially provided.

Returning to Figure 3, the memory controller 114 communicates the new data mask based on the updated cluster 410 to the memory device 104, and specifically to the mode register 146 (block 304, see also Figure 4E). For subsequent write commands, the memory controller 114 may The footer is repurposed to indicate the selected mask to convey which cluster center the memory device 104 will use (block 308 ).

The memory device 104 then XORs the received bits with the identified mask to recover the data and execute the write command (block 310).

In this manner, the number of ones transferred on the memory bus 106 is minimized, which results in power savings. In the worst case, the mask occasionally ends up being the same as the DBI, and there is no power saving for that window, but within a large enough time window, the power saving can be considerable, on the order of almost 50% for CPU write traffic % savings, compared with approximately 10% savings for other forms of writing services.

Self-adjusting data encoding for memory systems according to aspects disclosed herein may be provided in or integrated into any processor-based device. Examples include, but are not limited to, set-top boxes, entertainment units, navigation equipment, communication equipment, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smart phones, communication period activation Protocol (SIP) phones, tablet devices, phablets, servers, computers, laptops, mobile computing devices, wearable computing devices (e.g., smart watches, health or fitness trackers, glasses, etc.), desktop computers , personal digital assistant (PDA), monitor, computer monitor, television, tuner, radio unit, satellite radio unit, music player, digital music player, portable music player, digital video player, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones and multi-rotor helicopters.

Those skilled in the art will also appreciate that the various illustrative logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, in memory, or elsewhere. A computer may read instructions stored on the medium (where any such instructions are executed by a processor or other processing device), or a combination of the two. By way of example, the master and slave devices described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be any type and size of memory and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in conjunction with their functionality. How this functionality is implemented depends on the specific application, design choices, and/or design constraints imposed on the overall system. Those skilled in the art may implement the described functions in varying ways for each specific application, but such implementation decisions should not be interpreted as causing a departure from the scope of this case.

The various illustrative logic blocks, modules and circuits described in connection with the aspects disclosed herein may utilize processors, digital signal processors (DSPs), application special integrated circuits (ASICs) designed to perform the functions described herein ), a field programmable gate array (FPGA) or other programmable logic device, individual gate or transistor logic, individual hardware components, or any combination thereof. The processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller or state machine. A processor may also be implemented as a combination of computing devices (eg, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors and a DSP core, or any other such configuration).

The aspects disclosed herein may be embodied in hardware and instructions stored in the hardware, and may be located in, for example, random access memory (RAM), flash memory, read only memory (ROM), electrically programmable Design ROM (EPROM), Electronically Erasable Programmable ROM (EEPROM), scratchpad, hard disk, removable disk, CD-ROM, or any other form of computer readable media known in the art middle. An exemplary storage medium is coupled to the processor such that the processor can read information from the storage medium and write information to the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and storage media may be located in an ASIC. The ASIC can be located in the remote station. In the alternative, the processor and storage medium may be located as separate components in a remote station, base station, or server.

It should also be noted that the operational steps described in any of the exemplary aspects herein are described to provide example and discussion. The operations described may be performed in many different orders than that illustrated. Furthermore, operations described in a single operating step may actually be performed in multiple different steps. Additionally, one or more of the operational steps discussed in the exemplary aspects may be combined. It should be understood that the operational steps illustrated in the flowcharts are susceptible to many different modifications, as will be apparent to those skilled in the art. Those skilled in the art will also understand that information and signals may be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

The foregoing description of the content of this case is provided to enable anyone skilled in the art to implement or use the content of this case. Various modifications to the teachings herein will be apparent to those skilled in the art, and the overall principles defined herein may be applied to other variations. Accordingly, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Implementation examples are described in the following numbered clauses: 1. An integrated circuit (IC), including: a bus interface configured to be coupled to the memory bus; and A memory controller coupled to the bus interface and configured to: Send one or more data masks from a plurality of data masks to a memory device via the bus interface, wherein the one or more data masks include encoded data to be sent to the memory device. The corresponding mode to use when decoding. 2. An IC according to clause 1, wherein the one or more data masks include differences between the encoded data being decoded by the memory device and the data to be sent to the memory device via the bus interface. Or (XOR) value. 3. The IC of clause 2, wherein the memory controller is also configured to XOR outgoing data with at least one data mask to encode the data to be sent to the memory device. 4. The IC of clause 3, wherein the memory controller is also configured to send the encoded data to the memory device via the bus interface. 5. An IC according to any of the preceding clauses, wherein the memory controller is also configured to write the one or more data masks into a mode register in the memory device. 6. An IC according to any of the preceding clauses, wherein the memory controller is also configured to send an identifier indicating which of the one or more data masks is used for data sent to the memory device Encode. 7. An IC according to any of the preceding clauses, wherein the memory controller is also configured to determine the one or more data masks to be sent. 8. An IC according to clause 7, wherein the one or more data masks are based on cluster centers associated with patterns in data to be sent to the memory device. 9. The IC of clause 8, wherein the memory controller is also configured to calculate a new cluster center based on the Hamming distance of bits in the data to be sent to the memory device to an existing cluster center. 10. The IC of clause 9, wherein the memory controller is also configured to periodically calculate the new cluster centers. 11. The IC of clause 9, wherein the memory controller is also configured to compute the new cluster centers every sixty-four transactions. 12. The IC of clause 9, wherein the memory controller is also configured to calculate the new cluster centers based on sixteen-bit blocks of the data to be sent to the memory device. 13. An IC according to any of the preceding clauses, wherein the bus interface includes a Low Power Double Data Rate (LPDDR) bus interface. 14. An IC according to any preceding clause, wherein the memory controller is also configured to use one of the plurality of data masks to decode data sent from the memory device. 15. An IC according to any one of clauses 9, 13 or 14, wherein the memory controller is also configured to calculate the new data based on eight-bit blocks of the data to be sent to the memory device. cluster center. 16. An integrated circuit (IC), including: a bus interface configured to be coupled to the memory bus; and A memory controller coupled to the bus interface and configured to: Sending one or more data masks from a plurality of data masks to a memory device via the bus interface, wherein the one or more data masks include data used by the memory device to be sent to the memory The controller's data is encoded by the encoding mask. 17. An integrated circuit (IC), including: a bus interface configured to be coupled to the memory bus; A pattern register including a plurality of data masks stored therein; and Encoding circuitry configured to use at least one data mask of the plurality of data masks to encode data to be sent to the memory controller via the bus interface. 18. An integrated circuit (IC), including: a bus interface configured to be coupled to the memory bus; and A mode register configured to have one or more data masks stored therein for decoding data sent from the memory controller.

100:Memory system 102:Host 104:Memory device 104(1):Memory device 104(N):Memory device 106:Memory bus 108: Neural processing unit 110:GPU and multimedia engine 112:Multi-core CPU 114:Memory controller 116:System bus 118:Physical layer (PHY) 120:Data line 122: Coding logic 124:I/O block 126:Storage body 128:Data unit array 130: Coding logic 132:First group 134:Intermediate group 136:Second group 140:ECC circuit 142:ECC unit 146:Mode register 200:Mobile terminal 204:Application processor 206:Large storage components 208:Universal Flash Storage (UFS) bus 210:Display 212:Display Serial Interface (DSI) bus 214:Camera 216:Camera Serial Interface (CSI) bus 218:Microphone 220: Speaker 222: Audio transcoder 224:SLIMbus 226:SOUNDWIRE bus 228: Modem 230: Peripheral Component Interconnect (PCI)/PCI Express (PCIe) bus 232:SPMI bus 234:WLAN IC 236:Power management integrated circuit (PMIC) 238: Accompanying IC 240:RFIC 242: PCI bus 244: PCI bus 246: Sensor 248: Sensor bus 250:Bus 252:Antenna tuner 254:switch 256:Power amplifier 258:RFFE bus 260:ETPS 262:Bus 264:RFFE system 300:Program 302: Square 304:Block 306: Square 308: Square 310:block 400:queuing 402(0):Cluster center 402(1):Cluster center 402(2):Cluster center 402(3):Cluster center 404:Data block 406(0): Minimum Hamming distance 406(1): Minimum Hamming distance 406(2): Minimum Hamming distance 406(3): Minimum Hamming distance 408: Counter 410:New cluster 412(1):Element 412(2):Element 412(3):Element 412(4):Element 412(5):Element 412(6):Element 412(7):Element 412(8):Element 412(9):Element 412(10):Element 412(11):Element 412(12):Element 412(13):Element 412(14):Element 412(15):Element 412(16):Element

Figure 1 is a block diagram of an exemplary memory system that could benefit from the self-adjusting encoding techniques described in this case;

FIG. 2 is a block diagram of a mobile terminal that may include the memory system of FIG. 1;

3 is a flowchart illustrating an exemplary process for self-adjusting encoding of data transmission in accordance with an exemplary aspect of the subject matter; and

Figures 4A-4F illustrate the steps of the procedure of Figure 3.

Domestic storage information (please note in order of storage institution, date and number) without Overseas storage information (please note in order of storage country, institution, date, and number) without

400:queuing

402(0):Cluster center

402(1):Cluster center

402(2):Cluster center

402(3):Cluster center

404:Data block

406(0): Minimum Hamming distance

406(1): Minimum Hamming distance

406(2): Minimum Hamming distance

406(3): Minimum Hamming distance

Claims (18)

An integrated circuit (IC) consisting of: a bus interface configured to be coupled to a memory bus; and A memory controller coupled to the bus interface and configured to: Sending one or more data masks from a plurality of data masks to a memory device via the bus interface, wherein the one or more data masks include information to be used on the encoded data sent to the memory device. The corresponding mode used when decoding the data. The IC of claim 1, wherein the one or more data masks include XORing data to be sent to the memory device via the bus interface when the memory device decodes the encoded data. (XOR) value. The IC of claim 2, wherein the memory controller is also configured to XOR outgoing data with at least one data mask to encode the data to be sent to the memory device. The IC of claim 3, wherein the memory controller is also configured to send the encoded data to the memory device via the bus interface. The IC of claim 1, wherein the memory controller is also configured to write the one or more data masks into a mode register in the memory device. The IC of claim 1, wherein the memory controller is also configured to send an identifier indicating which of the one or more data masks is used to perform processing on data sent to the memory device. Encoding. The IC of claim 1, wherein the memory controller is also configured to determine the one or more data masks to be sent. The IC of claim 7, wherein the one or more data masks are based on cluster centers associated with patterns in data to be sent to the memory device. The IC of claim 8, wherein the memory controller is also configured to calculate a new cluster center based on a Hamming distance of bits in the data to be sent to the memory device to an existing cluster center. The IC of claim 9, wherein the memory controller is also configured to periodically calculate the new cluster centers. The IC of claim 9, wherein the memory controller is also configured to compute the new cluster centers every sixty-four transactions. The IC of claim 9, wherein the memory controller is also configured to calculate the new cluster centers based on sixteen-bit chunks of the data to be sent to the memory device. The IC of claim 1, wherein the bus interface includes a low power double data rate (LPDDR) bus interface. The IC of claim 1, wherein the memory controller is also configured to use one of the plurality of data masks to decode data sent from the memory device. The IC of claim 9, wherein the memory controller is also configured to calculate the new cluster centers based on octets in the data to be sent to the memory device. An integrated circuit (IC) consisting of: a bus interface configured to be coupled to a memory bus; and A memory controller coupled to the bus interface and configured to: Send one or more data masks from a plurality of data masks to a memory device via the bus interface, wherein the one or more data masks include data used by the memory device to be sent to the memory. An encoding mask for encoding body controller data. An integrated circuit (IC) consisting of: a bus interface configured to be coupled to a memory bus; a pattern register including a plurality of data masks stored therein; and An encoding circuit configured to use at least one data mask of the plurality of data masks to encode data to be sent to a memory controller via the bus interface. An integrated circuit (IC) consisting of: a bus interface configured to be coupled to a memory bus; and A mode register configured to have one or more data masks stored therein for decoding data sent from a memory controller.