TW202345394A - Sic p-type, and low resistivity, crystals, boules, wafers and devices, and methods of making the same - Google Patents
Sic p-type, and low resistivity, crystals, boules, wafers and devices, and methods of making the same Download PDFInfo
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Landscapes
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Abstract
Description
本申請案根據專利法主張2021年7月9日申請的美國臨時申請案第63/220,132號及2022年4月30日申請的美國臨時申請案第63/337,088號的優先權及權益,該等申請案中之每一者的全部揭示內容以引用的方式併入本文中。This application claims the priority and rights of U.S. Provisional Application No. 63/220,132 filed on July 9, 2021 and U.S. Provisional Application No. 63/337,088 filed on April 30, 2022, in accordance with the patent law. The entire disclosure of each of these applications is incorporated herein by reference.
本發明係關於p型SiC晶體、晶錠、晶棒及晶圓;低電阻率SiC晶體、晶錠、晶棒及晶圓;用於製造p型SiC晶體、晶錠、晶棒及晶圓之方法;用於製造低電阻率SiC晶體、晶錠、晶棒及晶圓之方法;以及由此等晶圓製成的元件及此等晶圓的用途。The present invention relates to p-type SiC crystals, crystal ingots, crystal rods and wafers; low resistivity SiC crystals, crystal ingots, crystal rods and wafers; and methods for manufacturing p-type SiC crystals, crystal ingots, crystal rods and wafers. Methods; methods for manufacturing low resistivity SiC crystals, ingots, rods and wafers; as well as components made from such wafers and uses of such wafers.
純結晶碳化矽(silicon carbide,SiC)係電中性的,即,結晶材料中存在正電荷及負電荷的平衡。通常,為了在半導體二極體及電晶體的製造中有用,在SiC晶體生長製程期間將雜質添加至SiC晶體以在晶體內產生電荷不平衡,這會影響SiC的導電率。向SiC添加正電荷的雜質原子被稱為施體原子。一般而言,施體原子由週期表中在包含Si及C的欄右側那一欄(例如,第15 (VA)欄)識別。用於SiC的典型施體原子為氮(N)及磷(P)。向SiC添加負電荷的雜質原子被稱為受體原子。一般而言,受體原子由週期表中在包含Si及C的欄左側那一欄(例如,13或IIIA)識別。用於SiC的典型受體原子為硼(B)及鋁(Al)。SiC晶體通常將包含施體及受體原子雜質兩者。為了使施體或受體雜質原子影響晶體中的淨電荷且變成電活性的(即,影響晶體的導電率/電阻率),雜質原子通常必須取代位於其在晶體中的位置中的Si或C原子,且在此情況下,雜質原子被稱為取代型雜質。雜質原子亦可位於Si原子與C原子之間的位置中。在此情況下,雜質原子被稱為填隙型原子且可能不影響晶體中的淨電荷,可對電荷具有較少的影響,且在一些情形中不影響晶體中的淨電荷。因此,術語「電活性原子雜質」、「電活性雜質」及「電活性」用於描述向SiC結晶材料添加的會影響材料(例如,晶體)的淨電荷的原子,包括取代型原子及填隙型原子。因此,所有取代型雜質係電活性雜質,且填隙型雜質可為電活性或非電活性雜質。因此,施體或受體雜質的原子濃度(晶體中雜質原子數與原子總數的比)可等於或大於電活性雜質(例如,取代型雜質原子)的原子濃度。當存在的電活性(例如,取代型)施體原子多於電活性(例如,取代型)受體原子時,SiC晶體為n型,n代表負,即,存在過量的負電荷。相反,當存在的電活性(例如,取代型)受體原子多於施體原子時,SiC晶體為p型,p代表正,即,晶體中存在過量的正電荷。Pure crystalline silicon carbide (SiC) is electrically neutral, that is, there is a balance of positive and negative charges in the crystalline material. Typically, to be useful in the fabrication of semiconductor diodes and transistors, impurities are added to SiC crystals during the SiC crystal growth process to create a charge imbalance within the crystal, which affects the conductivity of SiC. Impurity atoms that add a positive charge to SiC are called donor atoms. Generally speaking, donor atoms are identified by the column in the periodic table to the right of the column containing Si and C (eg, column 15 (VA)). Typical donor atoms for SiC are nitrogen (N) and phosphorus (P). Impurity atoms that add negative charge to SiC are called acceptor atoms. Generally, acceptor atoms are identified by the column in the periodic table to the left of the column containing Si and C (eg, 13 or IIIA). Typical acceptor atoms for SiC are boron (B) and aluminum (Al). SiC crystals will typically contain both donor and acceptor atomic impurities. In order for a donor or acceptor impurity atom to affect the net charge in the crystal and become electrically active (i.e., affect the conductivity/resistivity of the crystal), the impurity atom typically must replace the Si or C in its position in the crystal atoms, and in this case, the impurity atoms are called substituted impurities. Impurity atoms can also be located in positions between Si atoms and C atoms. In this case, the impurity atoms are called interstitial atoms and may not affect the net charge in the crystal, may have less effect on the charge, and in some cases do not affect the net charge in the crystal. Therefore, the terms "electroactive atomic impurity", "electroactive impurity" and "electroactive" are used to describe the addition of atoms to SiC crystalline materials that affect the net charge of the material (e.g., crystal), including substituted atoms and interstitials. type atom. Therefore, all substituted impurities are electroactive impurities, and interstitial impurities can be electroactive or non-electroactive impurities. Therefore, the atomic concentration of a donor or acceptor impurity (the ratio of the number of impurity atoms to the total number of atoms in the crystal) may be equal to or greater than the atomic concentration of an electroactive impurity (eg, substituted impurity atoms). When there are more electroactive (eg, substituted) donor atoms than electroactive (eg, substituted) acceptor atoms, the SiC crystal is n-type, where n represents negative, that is, there is an excess of negative charge. In contrast, when there are more electroactive (e.g., substituted) acceptor atoms than donor atoms, the SiC crystal is p-type, with p representing positive, that is, there is an excess of positive charge in the crystal.
在本發明之前,還沒有直徑>100 mm的工業製造的、可購得的p型SiC基板可用,該p型SiC基板可用於製造SiC半導體元件。人們相信,現有的對製造p型SiC晶體的先前嘗試不能提供生產高品質、低缺陷的p型SiC材料(諸如SiC晶體、SiC晶棒及自彼等晶棒切割的p型SiC晶圓)之可製造製程。因此,在本發明之前,具有p型SiC材料的SiC半導體元件的益處基本上不可用且無法購得。Prior to the present invention, there were no industrially produced, commercially available p-type SiC substrates >100 mm in diameter that could be used for the fabrication of SiC semiconductor components. It is believed that existing prior attempts at fabricating p-type SiC crystals have not provided the means to produce high quality, low defect p-type SiC materials, such as SiC crystals, SiC ingots, and p-type SiC wafers cut from the same. Manufacturing process available. Therefore, prior to the present invention, the benefits of SiC semiconductor components with p-type SiC materials were essentially unavailable and unavailable.
如本文所使用,除非另有規定,否則半導體材料中存在兩種類型的電荷載子:電洞及電子。電洞可被視為電子的「相反面」。與具有負電荷的電子不同的是,電洞具有量值與電子相等、但極性與電子的電荷相反的正電荷。電洞有時可能容易混淆,因為它們不像電子那樣是實體粒子,而是原子中電子的缺失。當電子離開其位置時,電洞可在半導體中自原子移動至原子。因此,以類比的方式,轉向在一組台階上站成一條線的人。若在線的前方的人走上一個台階,則該人留下一個電洞。當每個人走上一個台階時,可用的台階(電洞)沿該等台階向下移動。當原子中的電子自原子的價帶(通常為由電子完全填充的最外電子殼層)移動至導帶(原子中電子可輕易逃逸的區域)中時,形成電洞,該移動在半導體中無處不在。As used herein, unless otherwise specified, there are two types of charge carriers in semiconductor materials: holes and electrons. A hole can be thought of as the "opposite" of an electron. Unlike electrons, which have a negative charge, holes have a positive charge equal in magnitude but opposite in polarity to the electron's charge. Holes can sometimes be confused because they are not physical particles like electrons, but rather the absence of electrons in atoms. When electrons leave their positions, holes can move from atom to atom in a semiconductor. So, by analogy, turn to the people standing in a line on a set of steps. If the person in front of the line walks up a step, that person leaves an electric hole. As each person walks up a step, the available steps (holes) move down the steps. A hole is formed in a semiconductor when electrons in an atom move from the atom's valence band (usually the outermost electron shell that is completely filled with electrons) into the conduction band (the region in the atom where electrons can easily escape). Everywhere.
如本文所使用,除非另有規定,否則術語「p型」、「p型晶圓」、「p型晶體」、「p型晶棒」及類似的此類術語應當被給予其最廣泛的可能含義,且將包括所具有的電活性受體原子雜質(例如,取代型受體原子雜質)多於電活性施體原子雜質(例如,取代型施體雜質原子)的SiC晶體材料。因此,例如,每單位體積電活性受體原子淨數量為1x10 10/cm 3至1x10 22/cm 3、約1x10 18/cm 3至1x10 20/cm 3、約1x10 18/cm 3至1x10 23/cm 3、約1x10 18/cm 3至1x10 24/cm 3、大於約1x10 9/cm 3、大於約1x10 15/cm 3、大於約1x10 18/cm 3及大於約1x10 19/cm 3的SiC結晶材料被表徵為p型SiC晶體材料。 As used herein, unless otherwise specified, the terms "p-type", "p-type wafer", "p-type crystal", "p-type ingot" and similar such terms shall be given the broadest possible meaning. meaning, and will include SiC crystal materials having more electroactive acceptor atomic impurities (eg, substituted acceptor atomic impurities) than electroactive donor atomic impurities (eg, substituted donor impurity atoms). Thus, for example, the net number of electroactive acceptor atoms per unit volume is 1x10 10 /cm 3 to 1x10 22 /cm 3 , about 1x10 18 /cm 3 to 1x10 20 /cm 3 , and about 1x10 18 /cm 3 to 1x10 23 / cm 3 , about 1x10 18 /cm 3 to 1x10 24 /cm 3 , greater than about 1x10 9 /cm 3 , greater than about 1x10 15 /cm 3 , greater than about 1x10 18 /cm 3 and greater than about 1x10 19 /cm 3 SiC crystals The material is characterized as a p-type SiC crystal material.
另外,除非另有規定,否則為了被視為p型SiC結晶材料,淨載子濃度將具有過量的受體原子雜質,如方程式(1)所給出Additionally, unless otherwise specified, in order to be considered a p-type SiC crystalline material, the net carrier concentration will have an excess of acceptor atomic impurities, as given by equation (1)
(1) Nc = N D-N A (1) Nc = N D -N A
其中Nc為淨載子濃度。N D為電活性施體雜質原子的濃度。N A為電活性受體雜質原子的濃度。根據慣例,Nc針對p型材料為負,表明缺少電子。 where Nc is the net carrier concentration. ND is the concentration of electroactive donor impurity atoms. NA is the concentration of electroactive acceptor impurity atoms. By convention, Nc is negative for p-type materials, indicating a lack of electrons.
如本文所使用,除非另有規定,否則術語「p型元件」、「p型半導體」及類似的此類術語應當被給予其最廣泛的可能含義,且包括具有p型層或者基於p型晶圓、晶片或基板的任何半導體、微電子元件或電子元件。As used herein, unless otherwise specified, the terms "p-type element", "p-type semiconductor" and similar such terms shall be given the broadest possible meaning and include having p-type layers or being based on p-type crystals. Any semiconductor, microelectronic component or electronic component on a wafer, wafer or substrate.
如本文所使用,除非另有規定,否則術語「p +」、「p +型」及類似的此類術語指代具有高摻雜劑數量(例如,重摻雜的,N D>10 18/cm 3)且因此具有低電阻率(<0.03 ohm-cm)的p型結晶SiC材料,例如p型晶棒、晶圓等。因此,p +型材料可具有10 18/cm 3至約10 20/cm 3的N A,10 18/cm 3至約10 21/cm 3的N A,>10 19/cm 3、約1x10 18/cm 3至1x10 23/cm 3、約1x10 18/cm 3至1x10 24/cm 3的N D,及約10 20/cm 3的N A。通常,p +型材料的電阻率可處於或低於0.03 ohm- cm、小於約0.025 ohm-cm、小於約0.020 ohm-cm、小於約0.015 ohm-cm、約0.030 ohm-cm至約0.01 ohm-cm、約0.025 ohm-cm至約0.008 ohm-cm,及約0.020 ohm-cm至約0.005 ohm-cm。 As used herein, unless otherwise specified, the terms "p + ", "p + -type" and similar such terms refer to materials with high dopant counts (e.g., heavily doped, N D > 10 18 / cm 3 ) and therefore have low resistivity (<0.03 ohm-cm) p-type crystalline SiC materials, such as p-type crystal rods, wafers, etc. Therefore, a p + type material can have an NA of 10 18 /cm 3 to about 10 20 /cm 3 , an NA of 10 18 /cm 3 to about 10 21 /cm 3 , >10 19 /cm 3 , about 1x10 18 /cm 3 to 1x10 23 /cm 3 , ND of about 1x10 18 /cm 3 to 1x10 24 /cm 3 , and N A of about 10 20 /cm 3 . Typically, p + -type materials may have a resistivity at or below 0.03 ohm-cm, less than about 0.025 ohm-cm, less than about 0.020 ohm-cm, less than about 0.015 ohm-cm, about 0.030 ohm-cm to about 0.01 ohm-cm. cm, about 0.025 ohm-cm to about 0.008 ohm-cm, and about 0.020 ohm-cm to about 0.005 ohm-cm.
如本文所使用,除非另有規定,否則術語「p -」、「p -型」及類似的此類術語指代具有低摻雜劑數量(例如,輕摻雜的,N D<10 18/cm 3)且因此具有更高電阻率的p型結晶材料,例如p型晶棒、晶圓等。通常,此等電阻率高於0.03 ohm-cm。因此,p -型材料可具有10 18/cm 3至約10 10/cm 3及類似值的N A。通常,p -型材料的電阻率可為0.03 ohm-cm至10 8ohm-cm及更大。 As used herein, unless otherwise specified, the terms " p- ", "p - type" and similar such terms refer to materials with low dopant quantities (e.g., lightly doped, N D <10 18 / cm 3 ) and therefore have higher resistivity p-type crystalline materials, such as p-type crystal rods, wafers, etc. Typically, these resistivities are above 0.03 ohm-cm. Thus, a p - type material may have an NA from 10 18 /cm 3 to about 10 10 /cm 3 and similar values. Typically, the resistivity of p - type materials can range from 0.03 ohm-cm to 10 ohm-cm and larger.
如本文所使用,除非另有規定,否則術語「n型」、「n型晶圓」、「n型晶體」、「n型晶棒」及類似的此類術語應當被給予其最廣泛的可能含義,且將包括所具有的電活性施體原子(例如,取代型施體原子雜質)多於其他類型的雜質原子的具有負電荷之SiC結晶材料。因此,例如,每單位體積電活性施體原子淨數量為1x10 10/cm 3至1x10 22/cm 3、約1x10 18/cm 3至1x10 20/cm 3、大於約1x10 9/cm 3、大於約1x10 15/cm 3、大於約1x10 18/cm 3及大於約1x10 19/cm 3的SiC結晶材料被表徵為n型SiC晶體材料。 As used herein, unless otherwise specified, the terms "n-type", "n-type wafer", "n-type crystal", "n-type ingot" and similar such terms shall be given the broadest possible meaning. meaning, and would include negatively charged SiC crystalline materials that have more electroactive donor atoms (eg, substituted donor atomic impurities) than other types of impurity atoms. Thus, for example, the net number of electroactive donor atoms per unit volume is 1x10 10 /cm 3 to 1x10 22 /cm 3 , about 1x10 18 /cm 3 to 1x10 20 /cm 3 , greater than about 1x10 9 /cm 3 , greater than about 1x10 9 /cm 3 SiC crystalline materials of 1x10 15 /cm 3 , greater than about 1x10 18 /cm 3 and greater than about 1x10 19 /cm 3 are characterized as n-type SiC crystalline materials.
另外,除非另有規定,否則為了被視為n型SiC結晶材料,淨載子濃度將指示過量的施體原子雜質,如方程式所給出。根據慣例,Nc針對n型材料為正,表明過量的電子。Additionally, unless otherwise specified, in order to be considered an n-type SiC crystalline material, the net carrier concentration will indicate an excess of donor atomic impurities, as given by Eq. By convention, Nc is positive for n-type materials, indicating an excess of electrons.
術語「n +」、「n +型」及類似的此類術語指代具有高摻雜劑量(例如,重摻雜的,N A>10 18/cm 3)且因此具有低電阻率(<0.03 ohm-cm)的n型材料,例如n型晶棒、晶圓等。通常,此等電阻率可處於或低於0.03 ohm-cm。 The terms "n + ", "n + type" and similar such terms refer to having a high doping dose (e.g., heavily doped, N A >10 18 /cm 3 ) and therefore having a low resistivity (<0.03 ohm-cm) n-type materials, such as n-type crystal rods, wafers, etc. Typically, these resistivities can be at or below 0.03 ohm-cm.
術語「n -」、「n -型」及類似的此類術語指代具有低摻雜劑量(例如,輕摻雜的,N A<10 18/cm 3)且因此具有更高電阻率的n型材料,例如n型晶棒、晶圓等。通常,此等電阻率可高於0.03 ohm-cm,且一般處於或高於0.03 ohm-cm。 The terms "n - ", "n -type " and similar such terms refer to n having low doping dosage (e.g., lightly doped, N A <10 18 /cm 3 ) and therefore higher resistivity Type materials, such as n-type crystal rods, wafers, etc. Typically, these resistivities can be higher than 0.03 ohm-cm, and are typically at or above 0.03 ohm-cm.
如本文所使用,除非另有規定,否則術語「實體孔」、「實體空隙」及「實體凹穴」指代物理性質而非電性質,且以常見的普通方式使用,諸如意謂固體或表面中的中空處、結構或表面中的材料缺失及表面或固體內的空白空間。As used herein, unless otherwise specified, the terms "physical pores," "physical voids," and "physical pockets" refer to physical properties rather than electrical properties, and are used in a common, ordinary way, such as to mean a solid or surface Hollows in structures, absences of material in structures or surfaces, and empty spaces within surfaces or solids.
如本文所使用,除非另有規定,否則術語「氣相沉積」(「Vapor Deposition,VD」)、「氣相沉積技術」、「氣相沉積製程」及類似的此類術語應當被給予其最廣泛的可能含義,且將包括例如以下製程:其中將固體或液體起始材料轉化成氣體或蒸氣狀態,然後沉積氣體或蒸氣以形成(例如,生長)固體材料。如本文所使用,氣相沉積技術將包括藉由磊晶術生長,其中層係自蒸氣或氣相提供。其他類型的氣相沉積技術包括:化學氣相沉積(「Chemical Vapor Deposition,CVD」);物理氣相沉積(「Physical Vapor Deposition,PVD」)、電漿增強CVD、物理氣相傳輸(「Physical Vapor Transport,PVT」)及其他技術。氣相沉積元件的實例將包括熱壁化學氣相沉積反應器、多晶圓化學氣相沉積反應器、化學氣相沉積煙囪反應器。物理氣相傳輸(Physical Vapor Transport,PVT)意謂且需要使用至少一種固體起始材料,該材料經昇華以提供用於生長晶體的蒸氣(例如,通量)。As used herein, unless otherwise specified, the terms "Vapor Deposition" (VD), "Vapor Deposition Technology", "Vapor Deposition Process" and similar such terms shall be given their most appropriate meaning. A wide range of possible meanings, and would include, for example, processes in which a solid or liquid starting material is converted into a gas or vapor state and the gas or vapor is then deposited to form (eg, grow) the solid material. As used herein, vapor deposition techniques will include growth by epitaxy, where layers are provided from the vapor or gas phase. Other types of vapor deposition technologies include: chemical vapor deposition ("Chemical Vapor Deposition, CVD"); physical vapor deposition ("Physical Vapor Deposition, PVD"), plasma enhanced CVD, physical vapor transport ("Physical Vapor") Transport, PVT") and other technologies. Examples of vapor deposition elements would include hot wall chemical vapor deposition reactors, multi-wafer chemical vapor deposition reactors, chemical vapor deposition stack reactors. Physical Vapor Transport (PVT) means and requires the use of at least one solid starting material that sublimates to provide vapor (eg, flux) for growing crystals.
如本文所使用,除非另有規定,否則術語「氣化溫度」應當被給予其最廣泛的可能含義,且包括材料自液體轉變成氣體狀態、自固體轉變成氣體狀態或兩種轉變的溫度(例如,固體至液體至氣體轉變發生在很小的溫度範圍內,例如,小於約20℃、小於約10℃及小於約5℃的範圍)。除非另有特別說明,否則氣化溫度將為對應於發生此種轉變的任何特定壓力(例如,一個大氣壓、0.5個大氣壓)的溫度。當在特定應用、方法中論述材料的氣化溫度,或者在特定元件(諸如PVT元件)中使用時,除非另有明確說明,否則氣化溫度將在該應用、方法或元件中所使用或通常所使用的壓力下。As used herein, unless otherwise specified, the term "vaporization temperature" shall be given its broadest possible meaning and includes the temperature at which a material transitions from a liquid to a gaseous state, from a solid to a gaseous state, or both ( For example, the solid-to-liquid-to-gas transition occurs over a small temperature range, eg, a range of less than about 20°C, less than about 10°C, and less than about 5°C). Unless otherwise specifically stated, the vaporization temperature will be the temperature corresponding to any specific pressure at which such transition occurs (eg, one atmosphere, 0.5 atmospheres). When the vaporization temperature of a material is discussed in a particular application, method, or for use in a particular element (such as a PVT element), unless expressly stated otherwise, the vaporization temperature will be that used or commonly used in that application, method, or element. under the pressure used.
碳化矽通常不具有液相,且在典型的PVT製程條件下不處於液相,而是在高於約1,700℃的溫度下在真空下昇華。(應注意,在很高的壓力下,SiC可存在於液相中。)通常,在工業及商業應用中,建立條件以便在約2,500℃及以上的溫度下發生昇華。當碳化矽昇華時,其通常形成由各種矽及碳物質組成的蒸氣通量,其蒸氣通量的組分隨源材料以及溫度及壓力而變。然而,除其他事項外,本發明提供了除了使用源材料(例如,成形裝藥)以及PVT製程期間的溫度及壓力之外還經由選擇液體起始材料(例如,聚矽碳前驅物)來控制此等組分的比率的能力。Silicon carbide does not typically have a liquid phase and is not in a liquid phase under typical PVT process conditions, but rather sublimates under vacuum at temperatures above approximately 1,700°C. (It should be noted that at very high pressures, SiC can exist in the liquid phase.) Typically, in industrial and commercial applications, conditions are established so that sublimation occurs at temperatures of about 2,500°C and above. When silicon carbide sublimates, it typically forms a vapor flux composed of various silicon and carbon species, with the composition of the vapor flux varying with the source material as well as temperature and pressure. However, the present invention provides, among other things, control over the use of source materials (e.g., shaped charges) and the temperature and pressure during the PVT process through the selection of liquid starting materials (e.g., polysilica precursors) The ratio of these components.
如本文所使用,除非另有規定,否則術語「晶體」、「晶錠」、及「晶棒」及類似的此類術語應當被給予其最廣泛的可能含義,且指代具有約50 mm至約250 mm的直徑、大於100 mm的直徑、大於250 mm的直徑及通常約150 mm的直徑;且具有約25 mm至約250 mm的高度(即,晶種端至尾端的距離)、約75 mm至約150 mm的高度、75 mm及更大的高度、約100 mm及更大的高度、約150 mm及更大的高度及通常約100 mm至約150 mm的高度的結晶結構。術語「晶體」通常指代最初生長且隨後自生長裝置移除的結構。術語「晶錠」通常指代其末端中之一者或兩者已經處理(例如,平坦化)的晶體。術語「晶棒」通常指代已經進一步處理(例如,在晶棒上形成平面)且準備好進行切片製程(即,由晶棒製造晶圓)的晶錠。通常,晶體係在氣相沉積裝置中使用氣相沉積製程(特定而言,PVT裝置及製程)生長的。As used herein, unless otherwise specified, the terms "crystal," "ingot," and "rod" and similar such terms shall be given their broadest possible meanings and shall refer to objects having a diameter of about 50 mm to About 250 mm in diameter, greater than 100 mm in diameter, greater than 250 mm in diameter, and typically about 150 mm in diameter; and having a height of about 25 mm to about 250 mm (i.e., the distance from the seed end to the tail end), about 75 Crystalline structures with a height of mm to about 150 mm, 75 mm and greater, about 100 mm and greater, about 150 mm and greater, and typically a height of about 100 mm to about 150 mm. The term "crystal" generally refers to a structure that is initially grown and subsequently removed from the growth device. The term "boule" generally refers to a crystal that has one or both of its ends treated (eg, planarized). The term "wafer ingot" generally refers to an ingot that has been further processed (eg, forming flat surfaces on the ingot) and is ready for a slicing process (ie, making wafers from the ingot). Typically, crystals are grown in a vapor deposition apparatus using a vapor deposition process (specifically, a PVT apparatus and process).
除非另外明確提供或自上下文顯而易見,否則術語晶體、晶錠及晶棒在本說明書中使用時通常係可互換的;且特定而言,本說明書中對一者的性質、結晶結構、巨大及微小的缺陷及組合物的描述通常適用於其他者。Unless otherwise expressly provided or obvious from the context, the terms crystal, ingot and rod are generally used interchangeably in this specification; and in particular, the nature, crystalline structure, macroscopic and microscopic nature of one is used in this specification. The descriptions of defects and compositions generally apply to others.
如本文所使用,除非另有規定,否則術語「晶圓」、「SiC晶圓」、「p型SiC晶圓」、「n型SiC晶圓」及類似的此類術語指代的結晶材料係自相同結晶材料的更大結構切割的結構(例如,p型SiC晶圓係自p型SiC晶棒切割的)。通常,晶圓700係圓盤狀結構,且可為圓形的或者圓形或半圓形的形狀705,且可具有一平面或者超過一個平面。晶圓具有頂部或頂部表面、底部或底部表面及厚度。晶圓的外邊緣可為錐形的、傾斜的、倒角的、正方形的、圓的等。As used herein, unless otherwise specified, the terms "wafer", "SiC wafer", "p-type SiC wafer", "n-type SiC wafer" and similar such terms refer to crystalline material systems A structure cut from a larger structure of the same crystalline material (eg, a p-SiC wafer cut from a p-type SiC ingot). Typically, the wafer 700 is a disk-shaped structure, and may be circular or circular or semi-circular in shape 705, and may have one plane or more than one plane. A wafer has a top or bottom surface, a bottom or bottom surface, and a thickness. The outer edge of the wafer can be tapered, beveled, chamfered, square, round, etc.
通常,藉由大體上橫向於更大晶體(例如,晶棒)的c軸線(生長軸線)切割晶圓來形成SiC晶圓。通常,晶圓可在生長軸線上(即,軸上)或從此軸線偏離幾度(即,偏軸),通常,針對偏軸晶圓,從生長軸線偏離約0.1度至約5度。晶圓可具有約80 μm至約600 μm的厚度,及約50 mm至約250 mm的直徑,其中約150 mm的直徑為較佳的。當在軸上或略微偏軸切割時,SiC晶圓通常具有碳面或表面及矽面或表面。亦可沿著生長軸線及在相對於生長軸線的任何其他定向中切割晶圓。 Typically, SiC wafers are formed by cutting the wafer generally transversely to the c-axis (growth axis) of a larger crystal (eg, a wafer rod). Typically, the wafer may be on or off the growth axis (i.e., on-axis) by several degrees (i.e., off-axis), typically about 0.1 degrees to about 5 degrees from the growth axis for off-axis wafers. The wafer may have a thickness of about 80 μm to about 600 μm , and a diameter of about 50 mm to about 250 mm, with a diameter of about 150 mm being preferred. When cut on-axis or slightly off-axis, SiC wafers typically have a carbon side or surface and a silicon side or surface. The wafer can also be cut along the growth axis and in any other orientation relative to the growth axis.
一般而言,在開發出商用SiC MOSFET之前,電力工業(>500V)主要基於矽(Si) IGBT的使用。此等係雙極元件且具有低傳導損耗,從而允許它們處理高的電流(安培)及功率(瓦特或W)。然而,它們在切斷階段(傳導與阻斷之間的轉變)期間經受高功率損耗,從而限制可操作它們的頻率。操作頻率很重要,因為頻率越高,轉換器/反相器的被動元件越小(例如,電感器),這有助於減小元件的體積及重量。減小此等元件(MOSFET及IGBT)的體積、重量及兩者係此項技術中長期存在的問題,且對於終端使用者係重要的衡量標準。MOFET係單極元件,因此它們提供更低的開關損耗(特別是在切斷階段期間)。然而,它們經受更高的導通電阻(傳導損耗),導通電阻隨著電壓增大,因此,在更高的電壓(對於Si為>500V)下,IGBT係有利的。因此,對此項技術提出的長期存在且未解決的問題是最佳化(即,最小化)半導體元件中的傳導損耗及轉變損耗。Generally speaking, before the development of commercial SiC MOSFETs, the power industry (>500V) was mainly based on the use of silicon (Si) IGBTs. These are bipolar devices and have low conduction losses, allowing them to handle high currents (amps) and power (watts or W). However, they suffer high power losses during the cut-off phase (transition between conduction and blocking), thus limiting the frequencies at which they can be operated. The operating frequency is important because the higher the frequency, the smaller the passive components of the converter/inverter (for example, the inductor), which helps reduce the size and weight of the components. Reducing the size, weight and both of these components (MOSFETs and IGBTs) is a long-standing problem in this technology and an important metric for end users. MOFETs are unipolar components, so they offer lower switching losses (especially during the turn-off phase). However, they suffer from higher on-resistance (conduction losses), which increases with voltage, so at higher voltages (>500V for Si) IGBT systems are advantageous. Therefore, a long-standing and unsolved problem posed to this technology is optimizing (ie, minimizing) conduction losses and transition losses in semiconductor components.
另外,矽基元件至SiC基元件的轉變已面臨實質性且長期存在的問題。特定而言,p型矽型元件至SiC型元件(例如,對於此等初始的先前嘗試為n型)的轉變需要大量的費用、時間及難度來重新設計p型矽型元件,例如,電路系統、遮罩、組態等,以便可使用n型SiC。先前技術不能提供高品質p型SiC晶圓已留下此長期存在的問題及需要未解決。In addition, the transition from silicon-based devices to SiC-based devices has faced substantial and long-standing problems. In particular, the transition from p-type silicon devices to SiC-type devices (e.g., n-type for these initial prior attempts) requires significant expense, time, and difficulty in redesigning the p-type silicon devices, e.g., circuit systems , masks, configurations, etc. so that n-type SiC can be used. The inability of previous technologies to provide high quality p-type SiC wafers has left this long-standing problem and need unsolved.
功率電子元件及電路的歷史開始於由矽製成的半元件。The history of power electronic components and circuits begins with semi-components made of silicon.
功率電路的許多設計採用設計以及p通道及n通道場效電晶體,最常見的電晶體為MOSFET或金氧半場效電晶體。如本文所使用,除非另有規定,否則p通道MOSFET係一種類型的MOSFET,其中MOSFET的通道由作為電流載子的大部分電洞組成。當MOSFET被啟動且接通時,大部分流動的電流為移動穿過通道的電洞。另一種類型的MOSFET為n通道MOSFET,其中大部分電流載子為電子。n通道或p通道MOSFET可以兩種不同的方式製成:增強型MOSFET或空乏型MOSFET。Many designs of power circuits use p-channel and n-channel field effect transistors. The most common transistors are MOSFETs or metal oxide semi-field effect transistors. As used herein, unless otherwise specified, a p-channel MOSFET is a type of MOSFET in which the MOSFET's channel consists of a majority of the holes as current carriers. When a MOSFET is activated and turned on, most of the current flowing is holes moving through the channel. Another type of MOSFET is the n-channel MOSFET, in which most of the current carriers are electrons. n-channel or p-channel MOSFETs can be made in two different ways: enhancement-mode MOSFET or depletion-mode MOSFET.
空乏型MOSFET通常在閘極端子與源極端子之間不存在電壓差時接通(最大電流自源極流動至汲極)。然而,若電壓施加至其閘極引線,則汲極-源極通道變得電阻更大,直至閘極電壓如此高,電晶體完全切斷為止。增強型MOSFET則相反。它通常在閘極-源極電壓為0V (VGS=0)時切斷。然而,若電壓施加至其閘極引線,則汲極-源極通道變得電阻更小。A depletion MOSFET usually turns on when there is no voltage difference between the gate and source terminals (maximum current flows from source to drain). However, if a voltage is applied to its gate lead, the drain-source channel becomes more resistive until the gate voltage is so high that the transistor shuts down completely. The opposite is true for enhancement mode MOSFETs. It usually cuts off when the gate-source voltage is 0V (VGS=0). However, if a voltage is applied to its gate lead, the drain-source channel becomes less resistive.
功率元件的典型應用係功率電路(即,反相器、轉換器及電源供應器)的設計及製造。使用n通道MOSFET或p通道MOSFET或兩者來設計此等電路。需要兩種類型的實例為H電橋功率驅動電路,其中功能為在任一方向上驅動電流通過負載(即,諸如在電氣自動導引車輛中或全電氣車輛中的馬達中向前或向後驅動DC馬達)。Typical applications of power components are the design and manufacturing of power circuits (ie, inverters, converters, and power supplies). Design these circuits using n-channel MOSFETs or p-channel MOSFETs, or both. An example of where two types are needed is an H-bridge power drive circuit where the function is to drive current through a load in either direction (i.e. drive a DC motor forward or backward such as in an electric automated guided vehicle or a motor in a fully electric vehicle ).
為了增大現代功率管理電路中的能量效率,當今的設計現在採用基於4H-SiC結晶基板的碳化矽MOSFET。碳化矽MOSFET提供了設計出與使用矽MOSFET的電路相比在更高電壓及高頻率下操作之電路的可能性。藉由SiC MOSFET,通常上文所論述的功率電路可在600 V至高於10 kV的電壓範圍及5 A至高於200 A的安培數範圍內操作。To increase energy efficiency in modern power management circuits, today's designs now use silicon carbide MOSFETs based on 4H-SiC crystalline substrates. Silicon carbide MOSFETs offer the possibility to design circuits that operate at higher voltages and frequencies than circuits using silicon MOSFETs. With SiC MOSFETs, typically the power circuits discussed above can operate in the voltage range of 600 V to greater than 10 kV and the amperage range of 5 A to greater than 200 A.
當今由SiC製成的MOSFET僅可由n型SiC基板製成,因為當前沒有可用的p型SiC基板商業供應。因此,大多數SiC MOSFET被製造為n通道元件。因為至今為止僅可購得使用n型基板的SiC MOSFET,所以SiC MOSFET不能在功率電路應用的全範圍內部署。Today's MOSFETs made of SiC can only be made from n-type SiC substrates, as there is currently no commercial supply of p-type SiC substrates available. Therefore, most SiC MOSFETs are manufactured as n-channel components. Because only SiC MOSFETs using n-type substrates have been commercially available so far, SiC MOSFETs cannot be deployed in the full range of power circuit applications.
對商業上可行的n通道IGBT(MOSFET電晶體的變體)有長期存在的需要,因為此元件相比其p通道相對物可提供更低的導通電阻及/或更高的阻斷電壓。此外,具有正電壓極性及與習知功率MOSFET的相似性的n通道元件從系統的角度來看可能更有吸引力。至今為止,已使用形成為n型SiC基板上的磊晶層之p型SiC材料,然後藉由研磨移除基板,來製造此類元件。此等元件已經證明是不令人滿意的,這是由於若干原因,包括由於需要基板移除的難度。除其他事項外,本發明提供了提供容易製造且商業上可接受的此類SiC IGBT元件的能力。There is a long-standing need for commercially viable n-channel IGBTs (variants of MOSFET transistors) because this device offers lower on-resistance and/or higher blocking voltage than its p-channel counterpart. Furthermore, n-channel components with positive voltage polarity and similarity to conventional power MOSFETs may be more attractive from a system perspective. Until now, such devices have been manufactured using p-type SiC material formed as an epitaxial layer on an n-type SiC substrate and then removing the substrate by grinding. Such components have proven unsatisfactory for several reasons, including due to the difficulty of substrate removal required. Among other things, the present invention provides the ability to provide such SiC IGBT components that are easy to manufacture and commercially acceptable.
對SiC LDMOSFET (橫向金氧半場效電晶體)有長期存在的需要。此等元件係在用於高功率應用(諸如蜂巢式)的矽中開發出的且UHF廣播傳輸已大大增加。此係因為Si LDMOSFET相比雙極元件提供更高的增益及更好的線性。然而,在本發明之前,此設計不能在SiC中實現,因為僅有n型SiC基板且歷史上任何p型磊晶形成的SiC基板與矽相比都具有太高的電阻率,從而導致LDMOSFET元件效能不合意。There is a long-standing need for SiC LDMOSFETs (lateral metal-oxide semi-field effect transistors). These components were developed in silicon for high power applications such as cellular and UHF broadcast transmissions have increased significantly. This is because Si LDMOSFETs provide higher gain and better linearity than bipolar components. However, prior to this invention, this design could not be implemented in SiC because there were only n-type SiC substrates and historically any p-type epitaxially formed SiC substrate had too high a resistivity compared to silicon, resulting in LDMOSFET elements Performance is unsatisfactory.
通常,功率MOSFET在由n通道而非p通道製成時往往展示出更好的效能。然而,為達成甚至更為增強的效能,此類元件通常需要磊晶生長於低電阻率p型基板上。然而,目前可購得的p型4H-SiC基板具有相對高的電阻率(~2.5 ohm-cm),比n型基板的電阻率高出約兩個數量級。n通道SiC元件的優點已長期受到追捧,但還未實現,這是由於在先前p型基板中發現的高電阻率。因此,本發明的p型晶圓提供了解決此種長期存在的需要的低電阻率且實現了相對於由n型SiC基板製成的元件具有改良的效能之n通道SiC元件。Generally, power MOSFETs tend to exhibit better performance when made from n-channel rather than p-channel. However, to achieve even greater performance, such devices typically require epitaxial growth on low-resistivity p-type substrates. However, currently available p-type 4H-SiC substrates have relatively high resistivities (~2.5 ohm-cm), which are approximately two orders of magnitude higher than those of n-type substrates. The advantages of n-channel SiC components have long been touted but have not been realized due to the high resistivity found in previous p-type substrates. The p-type wafers of the present invention therefore provide low resistivity that addresses this long-standing need and enables n-channel SiC devices with improved performance relative to devices made from n-type SiC substrates.
如本文所使用,除非另有規定,否則術語「比重」(亦稱為「視密度」)應當被給予其最廣泛的可能含義,且通常意謂結構的每單位體積重量,例如,材料的體積形狀。此性質將包括粒子的內部孔隙度作為其體積的一部分。除其他技術外,可利用潤濕粒子表面的低黏度流體對其進行量測。As used herein, unless otherwise specified, the term "specific gravity" (also known as "apparent density") shall be given its broadest possible meaning and generally means the weight per unit volume of a structure, e.g., the volume of a material shape. This property will include the internal porosity of the particle as a fraction of its volume. Among other techniques, low-viscosity fluids that wet the particle surface can be used to measure them.
如本文所使用,除非另有規定,否則術語「實際密度」(亦可稱為「真實密度」)應當被給予其最廣泛的可能含義,且通常意謂當材料中不存在空隙時該材料的每單位體積重量。此量測及性質基本上自材料消除了任何內部孔隙度(即,低於標準量測技術的可偵測水準),例如,不包括材料中的任何空隙。As used herein, unless otherwise specified, the term "actual density" (also referred to as "true density") shall be given its broadest possible meaning and generally means the density of a material when voids are not present in the material. Weight per unit volume. This measurement and property essentially eliminates any internal porosity from the material (i.e., below detectable levels with standard measurement techniques), ie, does not include any voids in the material.
如本文所使用,除非另有說明,否則「室溫」為25℃。且「標準環境溫度及壓力」為25℃及1個大氣壓。除非另有明確說明,否則與溫度相關的、與壓力相關的或與兩者相關的所有測試、測試結果、物理性質及值係在標準環境溫度及壓力下提供的,這將包括黏度。As used herein, "room temperature" is 25°C unless otherwise stated. And the "standard ambient temperature and pressure" is 25℃ and 1 atmosphere. Unless otherwise expressly stated, all tests, test results, physical properties and values related to temperature, pressure or both are provided at standard ambient temperature and pressure, which will include viscosity.
通常,如本文所使用,除非另有說明,否則術語「約」及符號「~」意圖包含±10%的變量或範圍及與獲得所述值相關聯的實驗或儀器誤差中之較大者。Generally, as used herein, unless otherwise stated, the term "about" and the symbol "~" are intended to encompass the greater of a variable or range of ±10% and the experimental or instrumental error associated with obtaining the stated value.
如本文所使用,除非另有規定,否則術語%、重量%及質量%可互換地使用且指代第一組分作為總體(例如,配方、混合物、預製件、材料、結構或產品)的重量之百分比的重量。除非另外明確提供,否則使用X/Y或XY指示配方中X的重量%及Y的重量%。除非另外明確提供,否則使用X/Y/Z或XYZ指示配方中X的重量%、Y的重量%及Z的重量%。As used herein, unless otherwise specified, the terms %, weight %, and mass % are used interchangeably and refer to the weight of the first component as a whole (e.g., a formulation, mixture, preform, material, structure, or product) percentage of weight. Unless otherwise explicitly provided, use X/Y or XY to indicate the weight % of X and the weight % of Y in the formulation. Unless otherwise explicitly provided, use X/Y/Z or XYZ to indicate the weight % of X, the weight % of Y, and the weight % of Z in the formulation.
如本文所使用,除非另有規定,否則「體積%」及「%體積」及類似的此類術語指代第一組分作為總體(例如,配方、混合物、預製件、材料、結構或產品)的體積之百分比的體積。As used herein, unless otherwise specified, "% volume" and "% volume" and similar such terms refer to the first component as a whole (e.g., a formulation, mixture, preform, material, structure, or product) The volume as a percentage of the volume.
如本文所使用,除非另有明確說明,否則術語「源材料」在晶棒生長、氣相沉積裝置、磊晶術及晶體生長與沉積製程的上下文中使用時應當被給予其最廣泛的可能定義,且指代置放於生長室中或以其他方式置放於用於晶體生長、磊晶術或SiC氣相沉積的裝置中且形成通量的粉末狀SiC材料、SiC體積形狀(例如,成形裝藥)或其他形式的固體SiC。As used herein, unless otherwise expressly stated, the term "source material" shall be given its broadest possible definition when used in the context of ingot growth, vapor deposition apparatus, epitaxy, and crystal growth and deposition processes. , and refers to a powdered SiC material, SiC volume shape (e.g., formed charge) or other forms of solid SiC.
如本文所使用,諸如「純度」、「純度等級」、「雜質」及「污染物」的術語應當聯繫起來看,且通常與不合意的且不是有意添加至用於製造SiC晶體的SiC材料或聚合物衍生製程的材料有關。此等術語不包括摻雜劑(例如,雜質原子、原子雜質、取代型雜質、填隙型雜質、電活性雜質及類似的此類術語),或者有意添加至或併入至SiC晶體中以提供或實現SiC晶體之電荷、半導體性質或其他性質的其他元素或材料。此等術語不包括有意併入至起始材料、聚矽碳前驅物、固化材料、第一陶瓷材料、源材料及此等材料中之一或多者中或與之組合以向SiC晶體(特定而言,SiC晶圓)提供特徵的任何預定材料。在判定純度及純度等級時,摻雜劑的量將被視為(即,計數為)SiOC或SiC材料的一部分。因此,在如此定義時,且如本文所使用,摻雜劑或摻雜材料不是「雜質」。以此方式,例如,具有僅摻雜劑及Si、O及C或者摻雜劑及僅Si及C之(例如,由原子雜質)摻雜的SiOC材料或(例如,由原子雜質)摻雜的SiC材料將為100%純的。As used herein, terms such as "purity," "purity grade," "impurities," and "contaminants" are to be viewed in conjunction and generally are associated with undesirable and not intentionally added to SiC materials used to make SiC crystals or Material related to the polymer derivatization process. These terms do not include dopants (e.g., atomic impurities, atomic impurities, substituted impurities, interstitial impurities, electroactive impurities, and similar such terms) that are intentionally added to or incorporated into the SiC crystal to provide Or other elements or materials that realize the charge, semiconductor properties or other properties of SiC crystals. These terms do not include intentional incorporation into or combination with starting materials, polysilica precursors, cured materials, first ceramic materials, source materials, and one or more of these materials to contribute to SiC crystals (specifically SiC wafers) provide the characteristics of any predetermined material. When determining purity and purity levels, the amount of dopant will be considered (ie, counted as) part of the SiOC or SiC material. Therefore, when so defined, and as used herein, a dopant or doping material is not an "impurity." In this way, for example, a SiOC material doped (e.g., by atomic impurities) with dopants only and Si, O and C or dopants and only Si and C The SiC material will be 100% pure.
如本文所使用,除非另有明確說明,否則術語「現有材料」、「先前材料」、「當前材料」、「當前可用材料」、「現有氣相沉積裝置」、「當前氣相沉積裝置」及類似的此類術語指代在本發明之前存在的源材料及裝置。此術語的使用不應被視為且不是對先前技術的承認。它僅僅為了描述當前技術水平作為可藉以評估、對比及量測本發明之實施例的顯著及開創性改良的基準線或參考點。As used herein, unless expressly stated otherwise, the terms "existing materials", "prior materials", "current materials", "currently available materials", "existing vapor deposition apparatus", "current vapor deposition apparatus" and Similar such terms refer to source materials and devices that existed prior to the present invention. Use of this term should not be considered and is not an admission of prior art. It is intended merely to describe the current state of the art as a baseline or reference point against which significant and groundbreaking improvements to embodiments of the invention may be evaluated, compared, and measured.
此[技術領域]章節意欲介紹本發明的各個態樣,其可與本發明的實施例相關聯。因此,此章節中的先前論述提供了用於更好地理解本發明的框架,且不應被視為對先前技術的承認。This [Technical Field] section is intended to introduce various aspects of the invention, which may be associated with embodiments of the invention. Accordingly, the preceding discussion in this section provides a framework for better understanding the present invention and should not be considered an admission of prior art.
對於高溫、高容量及高效能半導體元件、功率元件及電子元件有未滿足的、長期存在的且不斷增長的需要。碳化矽(Silicon Carbide,SiC)晶圓提供的基板滿足對於此等應用而言較佳的且需要的效能特徵,例如,高溫、功率及能帶間隙等。然而,在本發明之前,p型SiC晶體、p-SiC晶錠、p型SiC晶棒及由此種晶棒製成的p型SiC晶圓不是商業上可獲得的且基本上無法獲得。特定而言,此類p型材料不是可藉由PVT製程獲得的。因此,基於p型SiC晶圓的半導體元件的優點、益處及潛力還未實現,且特定而言,未以商業上及經濟上可接受的方式利用。There is an unmet, long-standing and growing need for high temperature, high capacity and high performance semiconductor components, power components and electronic components. Silicon Carbide (SiC) wafers provide substrates that meet the preferred and required performance characteristics for these applications, such as high temperature, power, and band gap. However, prior to the present invention, p-type SiC crystals, p-SiC ingots, p-type SiC ingots and p-type SiC wafers made from such ingots were not commercially available and essentially unobtainable. Specifically, such p-type materials are not available through the PVT process. Therefore, the advantages, benefits and potential of semiconductor components based on p-type SiC wafers have not yet been realized and, in particular, have not been exploited in a commercially and economically acceptable manner.
對SiC進行摻雜的先前嘗試(包括將電活性受體原子併入至SiC晶體)的額外長期存在的問題為,晶體或晶圓中缺少側對側及頂部至底部的均勻性。本發明藉由在本發明之摻雜SiC晶體及晶圓的實施例中提供方法、源材料來化解並解決此種長期存在的問題,該等方法、源材料提供的晶體具有電活性原子雜質的側對側及頂部至底部的非常均勻的分佈。An additional long-standing problem with previous attempts to dope SiC, including incorporating electroactive acceptor atoms into SiC crystals, is the lack of side-to-side and top-to-bottom uniformity in the crystal or wafer. The present invention resolves and solves this long-standing problem by providing methods and source materials in embodiments of doped SiC crystals and wafers of the present invention that provide crystals with electroactive atomic impurities. Very even distribution side to side and top to bottom.
除其他事項外,本發明藉由提供用於獲得p型SiC材料及利用彼等p型SiC材料的半導體元件之配方、方法及裝置來解決此等長期存在的需要。The present invention addresses these long-standing needs by, among other things, providing formulations, methods and apparatus for obtaining p-type SiC materials and semiconductor devices utilizing them.
除其他事項外,本發明藉由提供本文中所教示、揭示並主張的組合物、材料、製品、元件及製程來解決此等問題及長期存在的需要。The present invention solves these problems and long-standing needs by, among other things, providing the compositions, materials, articles, components and processes taught, disclosed and claimed herein.
除其他事項外,本發明藉由提供高品質、低缺陷的p型SiC材料來解決此等問題及長期存在的需要,該等p型SiC材料包括p型SiC晶體、p型SiC晶錠、p型SiC晶棒及由彼等晶棒獲得的p型SiC晶圓。除其他事項外,本發明藉由提供對於半導體元件的經濟製造、商業製造或兩者適合或可行的p型SiC材料來解決此等問題及長期存在的需要,該等p型SiC材料包括p型SiC晶體、p型SiC晶錠、p型晶棒及p型晶圓。除其他事項外,本發明藉由提供具有p型SiC材料的SiC半導體元件的益處,特定而言,以經濟上及商業上可行的方式提供此等元件以便其使用及益處可廣泛可用,來解決此等問題及長期存在的需要。The present invention solves these problems and long-standing needs by, among other things, providing high quality, low defect p-type SiC materials, including p-type SiC crystals, p-type SiC ingots, p-type SiC type SiC ingots and p-type SiC wafers obtained from those ingots. The present invention addresses these problems and long-standing needs by, among other things, providing p-type SiC materials that are suitable or feasible for economical fabrication, commercial fabrication, or both of semiconductor devices, including p-type SiC crystal, p-type SiC ingot, p-type crystal rod and p-type wafer. The present invention addresses, among other things, the benefits of SiC semiconductor devices having p-type SiC material, and in particular, providing such devices in an economically and commercially viable manner so that their use and benefits are widely available. These issues and long-standing needs.
對於低電阻率SiC材料,且特定而言低電阻率SiC晶圓及可在此等晶圓上或由此等晶圓構建的元件有長期存在的且未解決的需要,該等低電阻率SiC材料包括低電阻率SiC晶體、SiC晶錠、SiC晶棒及由彼等晶棒獲得的SiC晶圓。此等低電阻率晶圓可為p型或n型晶圓。除其他事項外,本發明藉由提供對於半導體元件的經濟製造、商業製造或兩者適合或可行的低電阻率SiC材料來解決此等問題及長期存在的需要,該等低電阻率SiC材料包低電阻率SiC晶體、SiC晶錠、晶棒及晶圓。There is a long-standing and unsolved need for low-resistivity SiC materials, and specifically low-resistivity SiC wafers and devices that can be built on or from such wafers. Materials include low resistivity SiC crystals, SiC ingots, SiC ingots and SiC wafers obtained from these ingots. These low resistivity wafers may be p-type or n-type wafers. The present invention addresses these problems and long-standing needs by, among other things, providing low resistivity SiC materials that are suitable or feasible for economical fabrication, commercial fabrication, or both of semiconductor devices, including Low resistivity SiC crystal, SiC ingot, ingot and wafer.
因此,提供了一種p型SiC晶圓,其具有約4” (100 mm)至約6” (150 mm)的直徑;約300 μm至約600 μm的厚度;受體原子;及約0.015 ohm-cm至約0.028 ohm-cm的電阻率。 Accordingly, a p-type SiC wafer is provided having a diameter of about 4" (100 mm) to about 6" (150 mm); a thickness of about 300 μm to about 600 μm ; acceptor atoms; and about 0.015 ohm-cm to about 0.028 ohm-cm resistivity.
此外,提供了一種p型SiC晶圓,其具有約4” (100 mm)至約6” (150 mm)的直徑;約325 μm至約500 μm的厚度;受體原子;及約2.0 ohm-cm及更小的電阻率。 Additionally, a p-type SiC wafer is provided, having a diameter of about 4" (100 mm) to about 6" (150 mm); a thickness of about 325 μm to about 500 μm ; acceptor atoms; and about 2.0 ohm-cm and smaller resistivity.
另外,提供了一種低電阻率n型SiC晶圓,其具有約4” (100 mm)至約6” (150 mm)的直徑;約300 μm至約600 μm的厚度;施體原子;及0.03 ohm-cm及更小的電阻率。 Additionally, a low resistivity n-type SiC wafer is provided, having a diameter of about 4" (100 mm) to about 6" (150 mm); a thickness of about 300 μm to about 600 μm ; donor atoms; and resistivity of 0.03 ohm-cm and less.
另外,提供了一種低電阻率n型SiC晶圓,其具有約300 μm至約600 μm的厚度;包含磷的施體原子;<40 μm的彎曲;<60 μm的翹曲;及0.03 ohm-cm及更小的電阻率。 Additionally, a low resistivity n-type SiC wafer is provided, having a thickness of about 300 μm to about 600 μm ; containing donor atoms of phosphorus; a bend of <40 μm ; and a warpage of <60 μm ; and resistivity of 0.03 ohm-cm and less.
再另外,提供了一種p型SiC晶棒,其具有至少約4” (100 mm)的直徑;及至少約1” (25 mm)的高度。Still additionally, a p-type SiC ingot is provided having a diameter of at least about 4" (100 mm); and a height of at least about 1" (25 mm).
另外,提供了一種p型晶棒,其具有約4” (100 mm)至約6” (150 mm)的直徑及約1” (25 mm)至約6” (150 mm)的高度。Additionally, a p-type ingot is provided having a diameter of about 4" (100 mm) to about 6" (150 mm) and a height of about 1" (25 mm) to about 6" (150 mm).
此外,提供了一種低電阻率n型SiC晶棒,其具有至少約4” (100 mm)的直徑及至少約1” (25 mm)的高度;且包含施體原子,其中施體原子基本上由磷組成。Additionally, a low resistivity n-type SiC rod is provided, having a diameter of at least about 4" (100 mm) and a height of at least about 1" (25 mm); and comprising donor atoms, wherein the donor atoms are substantially Composed of phosphorus.
此外,提供了一種低電阻率n型晶棒,其具有約4” (100 mm)至約6” (150 mm)的直徑;及約1” (25 mm)至約6” (150 mm)的高度,且包含施體原子,其中施體原子基本上由磷組成。Additionally, a low resistivity n-type crystal rod is provided having a diameter of about 4" (100 mm) to about 6" (150 mm); and a diameter of about 1" (25 mm) to about 6" (150 mm). height, and contains donor atoms, wherein the donor atoms consist essentially of phosphorus.
另外,提供了一種p型SiC晶圓,其具有約300 μm至約600 μm的厚度;受體原子;<40 μm的彎曲;<60 μm的翹曲;及2.0 ohm-cm至約0.004 ohm-cm的電阻率。 Additionally, a p-type SiC wafer is provided having a thickness of about 300 μm to about 600 μm ; acceptor atoms; bending of <40 μm ; warpage of <60 μm ; and 2.0 ohm-cm to Resistivity of approximately 0.004 ohm-cm.
因此,提供了一種製造具有預定電氣性質的SiC晶體的方法,該方法包括以下步驟:將SiC源材料置放於氣相沉積裝置中;SiC源材料包括矽、碳及摻雜劑;其中摻雜劑經選擇以向SiC晶體提供預定電氣性質;其中摻雜劑在源材料中相對於矽及碳的位置係固定的;將惰性氣體添加至氣相沉積裝置中,且控制氣相沉積裝置中的壓力;加熱SiC源材料,從而形成通量,其中通量包括矽、碳及摻雜劑;及將通量沉積於SiC晶體的生長面上,從而使SiC晶體生長;其中SiC晶體具有預定電氣性質。Therefore, a method for manufacturing SiC crystals with predetermined electrical properties is provided. The method includes the following steps: placing SiC source material in a vapor deposition device; the SiC source material includes silicon, carbon and dopants; wherein doping The agent is selected to provide predetermined electrical properties to the SiC crystal; wherein the position of the dopant in the source material is fixed relative to the silicon and carbon; an inert gas is added to the vapor deposition device, and the dopant in the vapor deposition device is controlled. pressure; heating the SiC source material, thereby forming a flux, wherein the flux includes silicon, carbon and dopants; and depositing the flux on the growth surface of the SiC crystal, thereby growing the SiC crystal; wherein the SiC crystal has predetermined electrical properties .
此外,提供了一種製造p型SiC晶體的方法,該方法包括以下步驟:將成形裝藥SiC源材料置放於氣相沉積裝置中;成形裝藥SiC源材料基本上由矽、碳及一定量的受體原子組成,該等受體原子在成形裝藥SiC源材料中保持在位置中;其中受體原子在成形裝藥源材料中相對於矽及碳的位置係固定的;加熱成形裝藥SiC源材料,從而經由成形裝藥源材料的昇華形成通量;其中通量包括矽、碳及該量的受體原子的一部分;及將通量沉積於p型SiC晶體的生長面上,從而使p型SiC晶體生長;其中通量中的受體原子中之至少一些在p型SiC晶體中形成取代型原子雜質。In addition, a method for manufacturing p-type SiC crystals is provided, which method includes the following steps: placing a shaped charge SiC source material in a vapor deposition device; the shaped charge SiC source material is basically composed of silicon, carbon and a certain amount of The acceptor atoms are composed of acceptor atoms that remain in position in the shaped charge SiC source material; the position of the acceptor atoms relative to silicon and carbon in the shaped charge source material is fixed; the shaped charge is heated SiC source material, thereby forming a flux through sublimation of the shaped charge source material; wherein the flux includes silicon, carbon and a portion of the amount of acceptor atoms; and depositing the flux on the growth surface of the p-type SiC crystal, thereby A p-type SiC crystal is grown; wherein at least some of the acceptor atoms in the flux form substituted atomic impurities in the p-type SiC crystal.
另外,提供了一種用於製造低電阻率n型SiC晶體的方法,該方法包括以下步驟:將成形裝藥SiC源材料置放於氣相沉積裝置中;成形裝藥SiC源材料基本上由矽、碳及一定量的施體原子組成,該等施體原子在成形裝藥SiC源材料中保持在位置中;其中施體原子在成形裝藥源材料中相對於矽及碳的位置係固定的;加熱成形裝藥SiC源材料,從而經由成形裝藥源材料的昇華形成通量;其中通量包括矽、碳及該量的施體原子的一部分;及將通量沉積於n型SiC晶體的生長面上,從而使n型SiC晶體生長;其中通量中的施體原子中之至少一些在n型SiC晶體中形成取代型原子雜質In addition, a method for manufacturing low-resistivity n-type SiC crystals is provided, which method includes the following steps: placing a shaped charge SiC source material in a vapor deposition device; the shaped charge SiC source material is basically composed of silicon It consists of , carbon and a certain amount of donor atoms. These donor atoms are maintained in position in the shaped charge SiC source material; the position of the donor atoms in the shaped charge source material relative to silicon and carbon is fixed. ; heating the shaped charge SiC source material, thereby forming a flux via sublimation of the shaped charge source material; wherein the flux includes silicon, carbon and a portion of the donor atoms in that amount; and depositing the flux on an n-type SiC crystal on the growth surface, thereby growing n-type SiC crystal; at least some of the donor atoms in the flux form substituted atomic impurities in the n-type SiC crystal
再另外,提供了一種用於製造p型SiC晶體的液體摻雜聚矽碳前驅物材料,該液體摻雜聚矽碳前驅物材料具有:摻雜劑,其中摻雜劑具有選自週期表的第13族的一或多個元素,藉此,所選元素提供數個受體原子;矽、碳及氧;其中摻雜劑為液體摻雜聚矽碳前驅物材料的總重量的小於10重量%;且其中液體摻雜聚矽碳前驅物材料定義負的潛在淨載子濃度(pNc);其中pNc = 施體原子的數目 - 受體原子的數目。Still further, a liquid-doped polysilica precursor material for manufacturing p-type SiC crystals is provided, the liquid-doped polysilica precursor material having: a dopant, wherein the dopant has a dopant selected from the periodic table. One or more elements of Group 13 whereby the selected element provides several acceptor atoms; silicon, carbon and oxygen; wherein the dopant is less than 10% by weight of the total weight of the liquid doped polysilica precursor material %; and the liquid-doped polysilica precursor material defines a negative potential net carrier concentration (pNc); where pNc = the number of donor atoms - the number of acceptor atoms.
另外,提供了一種用於製造低電阻率n型SiC晶體的液體摻雜聚矽碳前驅物材料,該液體摻雜聚矽碳前驅物材料具有:摻雜劑,其中摻雜劑具有選自週期表的第15族的一或多個元素,藉此,所選元素提供數個施體原子;矽、碳及氧;其中摻雜劑為液體摻雜聚矽碳前驅物材料的總重量的小於10重量%;且其中液體摻雜聚矽碳前驅物材料定義正的潛在淨載子濃度(pNc);其中pNc = 施體原子的數目 - 受體原子的數目。In addition, a liquid-doped polysilicon precursor material for manufacturing low-resistivity n-type SiC crystals is provided. The liquid-doped polysilicon precursor material has: a dopant, wherein the dopant has a period selected from the group consisting of: One or more elements of Group 15 of the table, whereby the selected element provides several donor atoms; silicon, carbon and oxygen; wherein the dopant is less than the total weight of the liquid doped polysilica precursor material 10% by weight; and the liquid-doped polysilica precursor material defines a positive potential net carrier concentration (pNc); where pNc = the number of donor atoms - the number of acceptor atoms.
進一步提供了具有以下特徵中之一或多者的此等方法、組合物材料、晶體、晶棒及晶圓:進一步具有選自由4H及6H組成的組的多型體;其中晶圓係均勻摻雜的晶圓;其中晶棒係均勻摻雜的晶棒;其中受體原子包含鋁、硼或鋁及硼的組合;其中晶圓具有至少10 18/cm 3的N A;其中晶圓具有約10 18/cm 3至約10 20/cm 3的N A;其中晶圓具有約10 18/cm 3至約10 21/cm 3的N A;進一步具有<0001>+/-0.5度的定向;進一步具有<40 μm的彎曲;進一步具有<60 μm的翹曲;進一步具有<15 μm的TTV;進一步具有<4 μm的SBIR (LTV) (平均為10mm x 10mm);進一步具有<0.2 cm -2的MPD (微管);進一步具有<500 cm -2的TSD (螺紋螺釘密度);且進一步具有<500 cm -2的BPD (基面錯位)。 Further provided are such methods, composition materials, crystals, ingots and wafers having one or more of the following characteristics: further having a polytype selected from the group consisting of 4H and 6H; wherein the wafer is uniformly doped A hybrid wafer; wherein the ingot is a uniformly doped ingot; wherein the acceptor atoms comprise aluminum, boron, or a combination of aluminum and boron; wherein the wafer has an N A of at least 10 18 /cm 3 ; wherein the wafer has approximately 10 18 /cm 3 to about 10 20 /cm 3 NA ; wherein the wafer has an NA of about 10 18 /cm 3 to about 10 21 /cm 3 ; further having an orientation of <0001> +/-0.5 degrees; Further having a bend of <40 μm ; further having a warp of <60 μm ; further having a TTV of <15 μm ; further having a SBIR (LTV) of <4 μm (10mm x 10mm average); further having MPD (microtubules) of 0.2 cm -2 ; further having a TSD (threaded screw density) of <500 cm -2 ; and further having a BPD (basal plane dislocation) of <500 cm -2 .
另外,提供了具有以下特徵中之一或多者的此等方法、組合物材料、晶體、晶棒及晶圓:其中電阻率為約2.0 ohm-cm至約0.1 ohm-cm;其中電阻率為0.13 ohm-cm及更小;其中電阻率為0.013 ohm-cm至約0.004 ohm-cm;其中電阻率為約0.010 ohm-cm及更小;其中電阻率為約0.01 ohm-cm至約0.001 ohm-cm;其中電阻率為約0.009 ohm-cm至約0.004 ohm-cm;其中受體原子包含鋁、硼或鋁及硼的組合;其中晶圓具有至少10 18/cm 3的N A;其中晶圓具有10 18/cm 3至約10 20/cm 3的N A;其中晶圓具有10 18/cm 3至約10 21/cm 3的N A;其中晶圓具有10 18/cm 3至約10 22/cm 3的N A;其中晶圓具有10 18/cm 3至約10 23/cm 3的N A;及,其中晶圓具有10 18/cm 3至約10 24/cm 3的N A。 Additionally, such methods, composition materials, crystals, rods, and wafers are provided having one or more of the following characteristics: wherein the resistivity is from about 2.0 ohm-cm to about 0.1 ohm-cm; wherein the resistivity is 0.13 ohm-cm and less; wherein the resistivity is 0.013 ohm-cm to about 0.004 ohm-cm; wherein the resistivity is about 0.010 ohm-cm and less; wherein the resistivity is about 0.01 ohm-cm to about 0.001 ohm-cm cm; wherein the resistivity is from about 0.009 ohm-cm to about 0.004 ohm-cm; wherein the acceptor atoms comprise aluminum, boron, or a combination of aluminum and boron; wherein the wafer has an N A of at least 10 18 /cm 3 ; wherein the wafer Having an N A of 10 18 /cm 3 to about 10 20 /cm 3 ; wherein the wafer has an N A of 10 18 /cm 3 to about 10 21 /cm 3 ; wherein the wafer has an N A of 10 18 /cm 3 to about 10 22 /cm 3 NA ; wherein the wafer has an NA 10 18 /cm 3 to about 10 23 /cm 3 ; and, wherein the wafer has an NA 10 18 /cm 3 to about 10 24 /cm 3 .
此外,提供了具有以下特徵中之一或多者的此等方法、組合物材料、晶體、晶棒及晶圓:其中電阻率為約0.01 ohm-cm至約0.004 ohm-cm;其中電阻率為0.010 ohm-cm及更小;其中電阻率為約0.009 ohm-cm至約0.002 ohm-cm;其中電阻率為約0.009 ohm-cm至約0.004 ohm-cm;其中施體原子包含磷、氮或磷及氮的組合;及其中取代型施體原子基本上由磷組成。Additionally, such methods, composition materials, crystals, rods, and wafers are provided having one or more of the following characteristics: wherein the resistivity is from about 0.01 ohm-cm to about 0.004 ohm-cm; wherein the resistivity is 0.010 ohm-cm and less; wherein the resistivity is from about 0.009 ohm-cm to about 0.002 ohm-cm; wherein the resistivity is from about 0.009 ohm-cm to about 0.004 ohm-cm; wherein the donor atoms comprise phosphorus, nitrogen or phosphorus and a combination of nitrogen; and wherein the substituted donor atoms consist essentially of phosphorus.
另外,提供了具有以下特徵中之一或多者的此等方法、組合物材料、晶體、晶棒及晶圓:其中晶圓具有至少10 18/cm 3的N D;其中晶圓具有至少約10 19/cm 3的N D;其中晶圓具有10 18/cm 3至10 21/cm 3的N D;其中晶圓具有10 18/cm 3至10 22/cm 3的N D;其中晶圓具有10 18/cm 3至10 23/cm 3的N D;及,其中晶圓具有10 18/cm 3至10 24/cm 3的N D。 Additionally, such methods, composition materials, crystals, ingots, and wafers are provided having one or more of the following characteristics: wherein the wafer has an ND of at least 10 18 /cm 3 ; wherein the wafer has an ND of at least about ND of 10 19 /cm 3 ; where the wafer has an ND of 10 18 /cm 3 to 10 21 /cm 3 ; where the wafer has an ND of 10 18 /cm 3 to 10 22 /cm 3 ; where the wafer has an ND of 10 18 /cm 3 to 10 21 /cm 3 ; where the wafer has an ND having an ND of 10 18 /cm 3 to 10 23 /cm 3 ; and, wherein the wafer has an ND of 10 18 /cm 3 to 10 24 /cm 3 .
另外,提供了具有以下特徵中之一或多者的此等方法、組合物材料、晶體、晶棒及晶圓:其中多型體選自由4H及6H組成的組的多型體;其中多型體貫穿晶體、晶棒或晶圓的整個區域保持相同;及,其中在晶體、晶棒或晶圓中沒有多型體變換。Additionally, such methods, composition materials, crystals, ingots, and wafers are provided having one or more of the following characteristics: wherein the polytype is selected from the group consisting of 4H and 6H; wherein the polytype The body remains the same throughout the entire area of the crystal, rod, or wafer; and, wherein there is no polytype body transformation in the crystal, rod, or wafer.
另外,提供了具有以下特徵中之一或多者的此等方法、組合物材料、晶體、晶棒及晶圓:包括在SiC種晶的C面上的p型晶體生長;包括在SiC種晶的S面上的p型晶體生長;包括在SiC種晶的C面上的p型晶體生長,其中SiC種晶具有4H或6H多型體;包括在SiC種晶的S面上的p型晶體生長,其中SiC種晶具有4H或6H多型體。Additionally, such methods, composition materials, crystals, ingots and wafers are provided having one or more of the following characteristics: including p-type crystal growth on the C-face of the SiC seed crystal; including on the SiC seed crystal p-type crystal growth on the S face of the SiC seed crystal; including p-type crystal growth on the C face of the SiC seed crystal, where the SiC seed crystal has a 4H or 6H polytype; including p-type crystal growth on the S face of the SiC seed crystal Growth, in which SiC seed crystals have 4H or 6H polytypes.
此外,提供了一種半導體元件,其包含此等晶圓或此等晶圓的一部分或構建於此等晶圓或此等晶圓的一部分上。Furthermore, a semiconductor component is provided that includes or is built on such wafers or portions of such wafers.
另外,提供了一種半導體元件,其包含此等晶圓或此等晶圓的一部分或構建於此等晶圓或此等晶圓的一部分上,且其中元件選自由N通道E-MOSFET、P通道E-MOSFET及N通道D-MOSFET組成的組。In addition, a semiconductor component is provided, which includes or is built on the wafers or a portion of the wafers, and wherein the component is selected from the group consisting of N-channel E-MOSFET, P-channel A group consisting of E-MOSFET and N-channel D-MOSFET.
另外,提供了一種半導體元件,其包含此等晶圓或此等晶圓的一部分或構建於此等晶圓或此等晶圓的一部分上,且其中元件選自由P通道D-MOSFET、IGBT、LDMOS、VMOS MOSFET、UMOS MOSFET及CMOS化合物元件組成的組。In addition, a semiconductor component is provided, which includes or is built on the wafers or a portion of the wafers, and wherein the component is selected from the group consisting of P-channel D-MOSFET, IGBT, A group consisting of LDMOS, VMOS MOSFET, UMOS MOSFET and CMOS compound components.
此外,提供了一種快閃記憶體元件,其包含此等晶圓或此等目前的晶圓的一部分或構建於此等晶圓或此等目前的晶圓的一部分上。Additionally, a flash memory device is provided that includes or is built on such wafers or portions of such current wafers.
另外,提供了一種製造p型SiC半導體元件的方法,該p型SiC半導體元件經組態以取代矽p型半導體元件,該方法包括以下步驟:評估電路平面圖,該電路平面圖定義用於p型矽半導體元件的電路系統;製定SiC電路平面圖;其中該SiC電路平面圖定義可操作以用於p型SiC半導體元件的SiC電路系統;且其中該SiC電路平面圖基本上由該電路平面圖組成。Additionally, a method of manufacturing a p-type SiC semiconductor element configured to replace a silicon p-type semiconductor element is provided, the method comprising the steps of: evaluating a circuit floor plan defined for p-type silicon A circuit system for a semiconductor element; formulating a SiC circuit plan; wherein the SiC circuit plan defines a SiC circuit system operable for a p-type SiC semiconductor element; and wherein the SiC circuit plan consists essentially of the circuit plan.
再另外,提供了此種製造p型SiC半導體元件的方法,該p型SiC半導體元件經組態以取代矽p型半導體元件,該方法進一步包含以下特徵中之一或多者:在p型SiC材料上或使用p型SiC材料製造SiC電路系統,其中p型SiC材料包含此等晶圓的至少一部分;其中SiC電路平面圖與電路平面圖至少90%相同;及,其中SiC電路平面圖與電路平面圖至少95%相同。Still additionally, a method of manufacturing a p-type SiC semiconductor element configured to replace a silicon p-type semiconductor element is provided, the method further comprising one or more of the following features: in the p-type SiC Materials or using p-type SiC material to manufacture SiC circuit systems, wherein the p-type SiC material includes at least a portion of such wafers; wherein the SiC circuit plan and the circuit plan are at least 90% identical; and, wherein the SiC circuit plan and the circuit plan are at least 90% identical %same.
一般而言,本發明係關於碳化矽(Silicon Carbide,SiC)晶體、晶錠、晶棒及晶圓,用於製造彼等物品的製程,及由彼等晶圓製成的或基於彼等晶圓的元件。Generally speaking, the present invention relates to silicon carbide (SiC) crystals, ingots, ingots and wafers, processes used to manufacture them, and products made from or based on these wafers. Round elements.
一般而言,本發明之實施例係關於使用諸如物理氣相傳輸(physical vapor transport,PVT)之昇華生長製程製成的此等晶體、晶錠、晶棒及晶圓,及用於在基於聚合物衍生陶瓷的製程中利用包含聚矽碳前驅物材料的起始材料執行昇華生長製程的裝置(例如,PVT裝置)。Generally speaking, embodiments of the present invention relate to such crystals, ingots, ingots, and wafers made using sublimation growth processes such as physical vapor transport (PVT), and for use in polymerization-based In the process of manufacturing material-derived ceramics, a starting material including a polysilica precursor material is used to perform a sublimation growth process (eg, a PVT device).
一般而言,本發明之實施例係關於p型SiC晶體(其包括晶錠、晶棒及晶圓),用於製造彼等p型物品的製程,及由彼等p型晶圓製成的或基於彼等p型晶圓的元件。一特定而言,本發明之實施例係關於立方p型SiC晶體、晶錠、晶棒及晶圓,用於製造彼等p型物品的製程,及由彼等p型晶圓製成的或基於彼等p型晶圓的元件。特定而言,本發明之實施例係關於六方p型SiC晶體(包括晶錠、晶棒及晶圓),用於製造彼等p型物品的製程,及由彼等p型晶圓製成的或基於彼等p型晶圓的元件。Generally speaking, embodiments of the present invention relate to p-type SiC crystals (which include ingots, rods, and wafers), processes for making those p-type articles, and devices made from those p-type wafers. or devices based on those p-type wafers. In particular, embodiments of the present invention relate to cubic p-type SiC crystals, ingots, ingots and wafers, processes for making the same p-type articles, and products made from the p-type wafers or devices based on their p-type wafers. Specifically, embodiments of the present invention relate to hexagonal p-type SiC crystals (including ingots, rods, and wafers), processes for making those p-type articles, and articles made from those p-type wafers. or devices based on those p-type wafers.
一般而言,本發明之實施例係關於低電阻率SiC晶體(包括晶錠、晶棒及晶圓),用於製造彼等物品的製程,及由彼等晶圓製成的或基於彼等晶圓的元件。特定而言,在實施例中,本發明係關於具有0.010 ohm-cm及更小的電阻率且較佳地具有0.005 ohm-cm及更小的電阻率的n型及p型SiC晶圓。此等低電阻率晶圓可為p型或n型晶圓。在實施例中,此等低電阻率晶圓具有立方或六方結晶結構,其中每一者亦為p型或n型晶圓。Generally speaking, embodiments of the present invention relate to low resistivity SiC crystals (including ingots, rods, and wafers), processes used to make the same, and articles made from or based on the same. wafer components. Specifically, in embodiments, the present invention relates to n-type and p-type SiC wafers having a resistivity of 0.010 ohm-cm and less, and preferably having a resistivity of 0.005 ohm-cm and less. These low resistivity wafers may be p-type or n-type wafers. In embodiments, these low resistivity wafers have cubic or hexagonal crystal structures, each of which is also a p-type or n-type wafer.
一般而言,本發明之實施例係基於或包括聚合物衍生陶瓷(「PDC」)材料,使用、基於PDC材料或大體上由PDC構成的產品及應用。PDC材料、配方、前驅物、起始材料以及用於製造此類材料的裝置及方法之實例例如在美國專利第9,657,409號、第9,815,943號、第10,091,370號、第10,322,936號及第11,014,819號,以及美國專利公開案第2018/0290893號,以及美國專利第9,499,677號、第9,481,781號、第8,742,008號、第8,119,057號、第7,714,092號、第7,087,656號、第5,153,295號及第4,657,991號中發現,其中每一者的全部揭示內容以引用的方式併入本文中。Generally speaking, embodiments of the present invention are based on or include polymer-derived ceramic ("PDC") materials and products and applications that use, are based on, or consist essentially of PDC materials. Examples of PDC materials, formulations, precursors, starting materials, and devices and methods for making such materials are found, for example, in U.S. Patent Nos. 9,657,409, 9,815,943, 10,091,370, 10,322,936, and 11,014,819, and in the U.S. Each of these is found in Patent Publication No. 2018/0290893, as well as U.S. Patent Nos. 9,499,677, 9,481,781, 8,742,008, 8,119,057, 7,714,092, 7,087,656, 5,153,295, and 4,657,991. The entire disclosure of is incorporated herein by reference.
較佳的PDC為「聚矽碳」材料,「聚矽碳」材料係包含矽(Si)、氧(O)及碳(C)的PDC材料。聚矽碳材料及製造彼等材料的方法在美國專利第9,815,943號、第9,657,409號、第10,322,936號、第10,753,010號、第11,014,819號及第11,091,370號以及美國專利公開案第2018/0290893號中揭示並教示,其中每一者的全部揭示內容以引用的方式併入本文中。The preferred PDC is "polysilicone" material, which is a PDC material containing silicon (Si), oxygen (O) and carbon (C). Polysilica materials and methods of making them are disclosed and disclosed in U.S. Patent Nos. 9,815,943, 9,657,409, 10,322,936, 10,753,010, 11,014,819, and 11,091,370, and U.S. Patent Publication No. 2018/0290893. teachings, the entire disclosure of each of which is incorporated herein by reference.
一般而言,本發明之實施例涉及液體至固體至陶瓷至晶體的製程,該等製程使用PDC液體前驅物材料,該材料然後被固化成固體材料(例如,塑膠狀材料、固化材料)。將此種固化的固體PDC材料轉換(例如,熱解)成第一PDC陶瓷材料,然後將此種第一陶瓷材料轉換(例如,熱解)成PDC SiC源材料。通常,此等步驟或轉變係作為單獨的加熱操作執行,然而,它們可在單個加熱操作中執行。可將PDC SiC源材料進一步形成為形狀電荷源材料。然後可使用PDC SiC源材料來生長(例如,藉由氣相沉積且較佳為PVT)PDC SiC晶體。通常,前驅物材料為液體,然而,它們可為固體、溶解固體及熔融物。Generally speaking, embodiments of the invention relate to liquid-to-solid to ceramic-to-crystalline processes that use PDC liquid precursor materials that are then solidified into solid materials (eg, plastic-like materials, cured materials). The solidified PDC material is converted (eg, pyrolyzed) into a first PDC ceramic material, and the first ceramic material is then converted (eg, pyrolyzed) into a PDC SiC source material. Typically, these steps or transformations are performed as separate heating operations, however, they can be performed in a single heating operation. The PDC SiC source material can be further formed into a shaped charge source material. The PDC SiC source material can then be used to grow (eg, by vapor deposition and preferably PVT) PDC SiC crystals. Typically, precursor materials are liquids, however, they can be solids, dissolved solids, and melts.
一般而言,可將一或多種摻雜劑(例如,意欲給予SiC結晶材料(例如,晶體、晶錠、晶棒及晶圓)一或多種預定性質的添加材料,諸如原子雜質)添加至PDC材料。此等摻雜劑經選擇以向由PDC前驅物生長或製成的SiC晶體提供預定的性質、特徵或兩者(例如,電氣或半導體相關性質或特徵),SiC晶體隨後包括晶體、晶錠、晶棒及晶圓。在較佳實施例中,預定的電氣或半導體性質或特徵包括例如:電阻率;導電率;施體原子(即,電子缺失)及電子的晶體位置(取代型或填隙型)及分佈;電活性原子雜質的濃度、晶體位置及分佈;取代型原子雜質及填隙型原子雜質的濃度、晶體位置、比率及分佈;Nc值;N A值;及N D值、載子濃度Ne、Nh;及電子能帶結構內向價帶或導帶能量或費米能量的變化。此等特徵將包括p型晶體,以及低電阻率n型或p型晶體,以及具有立方或六方結晶結構的此類物品。 In general, one or more dopants (eg, additive materials intended to impart one or more predetermined properties, such as atomic impurities) to SiC crystalline materials (eg, crystals, ingots, rods, and wafers) may be added to the PDC Material. Such dopants are selected to provide predetermined properties, characteristics, or both (e.g., electrical or semiconductor-related properties or characteristics) to SiC crystals grown or made from PDC precursors, which subsequently include crystals, ingots, Crystal ingots and wafers. In preferred embodiments, the predetermined electrical or semiconductor properties or characteristics include, for example: resistivity; conductivity; donor atoms (i.e., missing electrons) and crystal position (substituted or interstitial) and distribution of electrons; electrical conductivity; The concentration, crystal position and distribution of active atomic impurities; the concentration, crystal position, ratio and distribution of substituted atomic impurities and interstitial atomic impurities; Nc value; N A value; and N D value, carrier concentration Ne, Nh; And the change in the electronic band structure toward the valence band or conduction band energy or Fermi energy. Such characteristics would include p-type crystals, as well as low resistivity n-type or p-type crystals, and such items having cubic or hexagonal crystal structures.
摻雜劑可被添加至液體PDC前驅物材料、固體固化的PDC材料、第一PDC陶瓷,以及此等的組合及變化。摻雜劑亦可被添加至黏結劑或為黏結劑的一部分,黏結劑用於形成成形裝藥,例如SiC的體積形狀,以在用於生長SiC晶體的氣相沉積製程(例如,PVT)中用作源材料。用於SiC晶體的氣相沉積(例如,PVT)生長的成形裝藥SiC源材料的製備及使用在美國專利公開案第2018/0290893號中揭示並教示,該案的全部揭示內容以引用的方式併入本文中。Dopants can be added to the liquid PDC precursor material, the solid cured PDC material, the first PDC ceramic, and combinations and variations of these. Dopants may also be added to or part of the binder used to form a shaped charge, such as the volumetric shape of SiC, in a vapor deposition process (e.g., PVT) used to grow SiC crystals used as source material. The preparation and use of shaped charge SiC source materials for vapor deposition (eg, PVT) growth of SiC crystals is disclosed and taught in U.S. Patent Publication No. 2018/0290893, the entire disclosure of which is incorporated by reference. incorporated herein.
一般而言,在本發明之實施例中,摻雜劑較佳為PDC材料、SiC源材料及兩者的整體部分。因此,摻雜劑可能:(i)被化學鍵結至PDC材料(例如,液體PDC材料中的聚合物鏈的一部分、固體固化的PDC材料中的固化聚合物的一部分或兩者);(ii)它可(化學地、機械地或兩者)保持在PDC材料的基質(例如,奈米複合物)內,諸如美國專利第10,633,400號中揭示並教示,該案的全部揭示內容以引用的方式併入本文中;(iii)它可(化學地、機械地或兩者)保持在SiC源材料內;及(iv)此等的組合及變化。Generally speaking, in embodiments of the present invention, the dopant is preferably a PDC material, a SiC source material, or an integral part of both. Accordingly, the dopant may: (i) be chemically bonded to the PDC material (e.g., part of a polymer chain in a liquid PDC material, part of a cured polymer in a solid cured PDC material, or both); (ii) It can be maintained (chemically, mechanically, or both) within a matrix of PDC materials (e.g., nanocomposites) such as disclosed and taught in U.S. Patent No. 10,633,400, the entire disclosure of which is incorporated by reference. Incorporated herein; (iii) it can be retained (chemically, mechanically, or both) within the SiC source material; and (iv) combinations and variations of these.
具有作為SiC源材料的整體部分的摻雜劑相比將摻雜劑引入至晶體生長氣相沉積製程中的先前方式提供了若干益處。例如,具有作為SiC源材料的整體部分的摻雜劑允許摻雜劑與Si及C一起自源材料昇華以在氣相沉積製程及裝置(例如,PVT)中形成通量。以此方式,摻雜劑並非在通量形成之後單獨地添加至通量。相反,摻雜劑與通量一起形成,且形成為通量的一部分。在通量形成中且作為通量形成的整體部分具有摻雜劑相比在通量已形成之後將摻雜劑添加至通量(諸如摻雜劑的氣流或單獨昇華)提供了對整個製程的更大控制。因此,一般而言,本發明之較佳實施例避免對具有與SiC源材料分開的摻雜劑源的需要。這將包括避免使用進入氣相沉積裝置的基於摻雜劑的氣流、在氣相沉積裝置中使用單獨的固體摻雜劑源及此等的組合。但是應理解,在其他實施例中,可使用例如具有第二種類型的摻雜劑之單獨的基於摻雜劑的氣流。Having dopants as an integral part of the SiC source material provides several benefits over previous ways of introducing dopants into the crystal growth vapor deposition process. For example, having the dopant as an integral part of the SiC source material allows the dopant to sublimate from the source material along with Si and C to create flux in vapor deposition processes and devices (eg, PVT). In this way, the dopants are not added to the flux separately after the flux is formed. Instead, the dopants are formed with the flux and are formed as part of the flux. Having the dopant during and as an integral part of the flux formation provides greater control over the overall process than adding the dopant to the flux after the flux has been formed (such as gas flow or separate sublimation of the dopant). Greater control. Therefore, in general, preferred embodiments of the present invention avoid the need to have a separate dopant source from the SiC source material. This would include avoiding the use of dopant-based gas flows into the vapor deposition apparatus, using separate solid dopant sources in the vapor deposition apparatus, and combinations thereof. However, it should be understood that in other embodiments, a separate dopant-based gas stream, for example with a second type of dopant, may be used.
一般而言,摻雜劑(例如,原子雜質)在SiC源材料(例如,成形裝藥源材料)內及貫穿SiC源材料的位置、分佈及兩者係固定的。另外,且較佳地,摻雜劑在該預定的位置及分佈上保持固定,且較佳地貫穿用於生長SiC晶體的大部分及整個氣相沉積製程係固定的。以此方式,摻雜劑可穿過SiC源材料均勻地分佈。它可在SiC源材料內按濃度、位置及分佈變化,以考慮到通量形成及SiC晶體生長中的變化。以此後一種方式,摻雜劑的預定置放並不均勻,但是導致摻雜劑在SiC晶體中均勻分佈。以此方式,且在摻雜成形裝藥源材料的實施例中,提供了Si、C及原子雜質(例如,施體原子、受體原子或兩者)的基質。摻雜成形裝藥為Si、C及原子雜質的此種多孔基質,其中基質保持原子雜質,固定原子雜質或兩者。Generally speaking, the location, distribution, and both of dopants (eg, atomic impurities) within and throughout the SiC source material (eg, shaped charge source material) are fixed. Additionally, and preferably, the dopants remain fixed in the predetermined location and distribution, and preferably are fixed throughout most and throughout the vapor deposition process used to grow the SiC crystal. In this way, dopants can be evenly distributed through the SiC source material. It can be varied in concentration, location and distribution within the SiC source material to account for changes in flux formation and SiC crystal growth. In this latter manner, the intended placement of the dopants is not uniform, but results in a uniform distribution of the dopants in the SiC crystal. In this manner, and in embodiments where the shaped charge source material is doped, a matrix of Si, C and atomic impurities (eg, donor atoms, acceptor atoms, or both) is provided. The doped shaped charge is such a porous matrix of Si, C and atomic impurities, where the matrix retains the atomic impurities, immobilizes the atomic impurities, or both.
當使用成形裝藥SiC源材料的實施例時,摻雜劑(例如,原子雜質)的預定的位置及分佈在固體源材料中保持固定,直至摻雜劑與固體源一起昇華為止。因此,針對氣相沉積(例如,PVT)製程及裝置中的晶體生長循環的至少60%、70%、80%、90%及100%,摻雜劑可在固體源材料中保持固定,以致於此種固體源材料尚未昇華。換言之,在此等實施例中,固體摻雜劑在晶體生長循環期間不會變換其相對於固體SiC在成形裝藥中的位置。When embodiments of shaped charge SiC source materials are used, the predetermined location and distribution of the dopants (eg, atomic impurities) remain fixed in the solid source material until the dopants sublime with the solid source. Therefore, for at least 60%, 70%, 80%, 90%, and 100% of the crystal growth cycle in the vapor deposition (eg, PVT) process and apparatus, the dopant can remain fixed in the solid source material such that Such solid source materials have not yet been sublimated. In other words, in these embodiments, the solid dopant does not change its position relative to the solid SiC in the shaped charge during the crystal growth cycle.
另外,使摻雜劑(例如,原子雜質)在SiC源材料(例如,SiC成形裝藥源材料)中的預定的位置及分佈上固定提供了在SiC晶體中獲得取代型雜質與填隙型雜質之高比率(即,原子雜質之更大或更高效率的使用)的能力。原子雜質的此種更高效率的使用減少了填隙型雜質可在SiC晶體中造成的不良影響(例如,應力)。因為當摻雜劑原子在表面上顯露時,SiC及摻雜元素共同昇華,所以在貫穿生長的均勻濃度下,併入至生長晶棒上得到更好的保證。In addition, fixing dopants (eg, atomic impurities) at predetermined positions and distributions in SiC source materials (eg, SiC shaped charge source materials) provides for obtaining substitutional and interstitial impurities in SiC crystals. The ability to achieve high ratios (i.e., greater or more efficient use of atomic impurities). This more efficient use of atomic impurities reduces the adverse effects (eg, stress) that interstitial impurities can cause in the SiC crystal. Because SiC and doping elements co-sublimate when dopant atoms are exposed on the surface, incorporation into the growing ingot is better guaranteed at a uniform concentration throughout growth.
應理解,使摻雜劑(例如,原子雜質)在晶體生長循環期間保持「固定」係相對於該源材料的未昇華部分(即,保持尚未昇華的部分)。當源材料在氣相沉積製程期間昇華時,摻雜劑亦昇華。以此方式,摻雜劑在通量中且作為通量的一部分與通量的Si基組分及C基組分一起形成。另外,以此方式,且較佳地,摻雜劑並非在通量形成之後單獨地添加至通量。相反,摻雜劑為通量的整體部分且甚至為通量形成的整體部分。It will be understood that keeping dopants (eg, atomic impurities) "fixed" during a crystal growth cycle is relative to the non-sublimated portion of the source material (ie, remains the portion that has not yet sublimated). When the source material sublimates during the vapor deposition process, the dopants also sublimate. In this manner, the dopant is formed in the flux and as part of the flux together with the Si-based and C-based components of the flux. Additionally, in this manner, and preferably, the dopants are not added to the flux separately after formation of the flux. Rather, the dopant is an integral part of the flux and even of the formation of the flux.
一般而言,本發明之實施例係關於用於提供製造預定類型的SiC晶圓的摻雜源材料之配方及方法。在此等實施例中,起始材料(例如,前驅物)通常為液體,液體隨後被固化成固體材料。固體起始材料通常包含摻雜劑(例如,原子雜質)。固體起始材料隨後被熱解成包含摻雜劑的陶瓷。此陶瓷隨後被進一步轉換成SiC,其包含摻雜劑且形成用於生長預定類型的SiC晶體(例如,p型、低電阻率p型及低電阻率n型)的源材料之基礎。此等預定晶體類型中之每一者隨後被製造成SiC晶圓,例如,p型、低電阻率p型及低電阻率n型。Generally speaking, embodiments of the present invention relate to providing formulations and methods for doping source materials for fabricating predetermined types of SiC wafers. In such embodiments, the starting material (eg, precursor) is typically a liquid that is subsequently solidified into a solid material. Solid starting materials often contain dopants (eg, atomic impurities). The solid starting material is then pyrolyzed into a ceramic containing dopants. This ceramic is then further converted into SiC, which contains dopants and forms the basis of the source material for growing predetermined types of SiC crystals (eg, p-type, low resistivity p-type, and low resistivity n-type). Each of these predetermined crystal types are then fabricated into SiC wafers, for example, p-type, low resistivity p-type, and low resistivity n-type.
一般而言,本發明之較佳實施例係關於使用包含Si、O及C的液體來形成液體前驅物材料的配方,該液體前驅物材料具有添加至它的一種或超過一種摻雜劑(例如,原子雜質),因此該液體前驅物材料包含摻雜劑。該摻雜劑或該等摻雜劑係選自意欲向最終由此液體前驅物材料製成的SiC晶體及晶圓提供特定的電氣性質、半導體性質或兩種性質的元素及化合物。Generally speaking, preferred embodiments of the present invention relate to formulations using a liquid containing Si, O, and C to form a liquid precursor material having one or more than one dopants added thereto (e.g., , atomic impurities), so the liquid precursor material contains dopants. The dopant or dopants are selected from elements and compounds intended to provide specific electrical properties, semiconducting properties, or both properties to the SiC crystals and wafers ultimately made from this liquid precursor material.
摻雜劑可為或者可基於:可在SiC晶體及晶圓中形成電活性原子雜質的任何元素,向SiC晶體及晶圓提供預定的電氣性質、半導體性質或物理性質中之一或多者的任何元素。舉例而言,摻雜劑可為或者可基於:選自週期表的第13 (IIIA)族的元素(硼(B)、鋁(Al)等),選自第2 (IIA)族的元素(鈹(Be)等),及選自第15 (VA)族的元素(氮(N)、磷(P)、砷(As)、銻(Ab)等)。摻雜劑亦可選自第16 (VIA)族中的元素(氧(O)、硫(S)等)。摻雜劑可選自過渡金屬,諸如Ti、Cr、Mn、Ni、Fe、Co等。在實施例中,過渡金屬元素可向結晶材料且因此向摻雜SiC晶圓添加性質,該等性質在諸如自旋電子、光子能帶間隙及電化學元件之元件中提供一類新的效能。The dopant may be or may be based on any element that can form electrically active atomic impurities in the SiC crystals and wafers, providing one or more of predetermined electrical, semiconducting or physical properties to the SiC crystals and wafers. any element. For example, the dopant may be or may be based on: an element selected from group 13 (IIIA) of the periodic table (boron (B), aluminum (Al), etc.), an element selected from group 2 (IIA) ( Beryllium (Be), etc.), and elements selected from Group 15 (VA) (nitrogen (N), phosphorus (P), arsenic (As), antimony (Ab), etc.). The dopant may also be selected from elements in Group 16 (VIA) (oxygen (O), sulfur (S), etc.). The dopant may be selected from transition metals such as Ti, Cr, Mn, Ni, Fe, Co, etc. In embodiments, transition metal elements can add properties to the crystalline material, and thus the doped SiC wafer, that provide a new class of performance in devices such as spintronics, photonic band gaps, and electrochemical devices.
製造p型SiC晶體、晶錠、晶棒及晶圓的較佳摻雜劑形式為鋁及硼。用於製造n型低電阻率晶圓的較佳摻雜劑為磷、氮,且在一些情況下為硫及磷、硫及氮的組合。The preferred dopant forms for manufacturing p-type SiC crystals, ingots, rods and wafers are aluminum and boron. Preferred dopants for making n-type low resistivity wafers are phosphorus, nitrogen, and in some cases sulfur and combinations of phosphorus, sulfur, and nitrogen.
儘管本說明書專注於SiC氣相沉積技術,且特定而言SiC PVT技術,但是應理解,本發明不受此限制且可應用於其他SiC結晶生長製程、接合製程以及其他應用。 前驅物及源材料- 一般而言 Although this specification focuses on SiC vapor deposition technology, and specifically SiC PVT technology, it should be understood that the invention is not so limited and may be applied to other SiC crystal growth processes, bonding processes, and other applications. Precursors and source materials - in general
本發明之實施例較佳地使用、基於或構成PDC,PDC係「聚矽碳」材料,即包含矽(Si)、氧(O)及碳(C)的材料,以及已固化的此類材料的實施例、已熱解的此類材料的實施例及已轉換成SiC以用作源材料的此類材料的實施例。除非另有特別說明,否則碳氧化矽材料、SiOC組合物及類似的此類術語指代聚矽碳材料,且將包括液體材料、固體未固化材料、固化材料、陶瓷材料,以及此等的組合及變化。聚矽碳材料及製造彼等材料的方法在美國專利第9,815,943號、第9,657,409號、第10,322,936號、第10,753,010號、第11,014,819號及第11,091,370號以及美國專利公開案第2018/0290893號中揭示並教示,其中每一者的全部揭示內容以引用的方式併入本文中。Embodiments of the present invention preferably use, are based on or constitute PDC, which is a "polysilicone" material, that is, a material containing silicon (Si), oxygen (O) and carbon (C), and such materials that have been cured , examples of such materials that have been pyrolyzed, and examples of such materials that have been converted to SiC for use as source materials. Unless specifically stated otherwise, silicon oxycarbide materials, SiOC compositions, and similar such terms refer to polysilica materials and will include liquid materials, solid uncured materials, cured materials, ceramic materials, and combinations thereof and changes. Polysilica materials and methods of making them are disclosed and disclosed in U.S. Patent Nos. 9,815,943, 9,657,409, 10,322,936, 10,753,010, 11,014,819, and 11,091,370, and U.S. Patent Publication No. 2018/0290893. teachings, the entire disclosure of each of which is incorporated herein by reference.
聚矽碳材料可具有高的及異常高的純度。因此,它們可為99.99%純的、99.999%純的及99.9999%純的。聚矽碳材料亦可包含其他元素。特定而言,在較佳實施例中,聚矽碳材料包含摻雜劑(例如,原子雜質)。(在進行此等百分比純度計算時不將摻雜劑計數為雜質,而是為了進行純度百分比計算將摻雜劑計數為SiC材料的一部分)。聚矽碳材料由一或多種聚矽碳前驅物或前驅物配方製成。聚矽碳前驅物配方包含一或多種官能基化矽聚合物或單體、非矽基交聯劑,以及可能的其他成分,諸如例如抑制劑、催化劑、摻雜劑及其他添加劑。摻雜劑可包括例如金屬、類金屬、金屬錯合物、合金及非金屬以及此等的組合及變化中之一者或一者以上。Polysilica materials can have high and exceptionally high purity. Therefore, they can be 99.99% pure, 99.999% pure and 99.9999% pure. Polysilica materials can also contain other elements. Specifically, in preferred embodiments, the polysilica material includes dopants (eg, atomic impurities). (The dopants are not counted as impurities in these percent purity calculations, but are counted as part of the SiC material for purposes of the percent purity calculations). Polysilica materials are made from one or more polysilica precursors or precursor formulations. Polysilica precursor formulations include one or more functionalized silicon polymers or monomers, non-silicon-based crosslinkers, and possibly other ingredients such as, for example, inhibitors, catalysts, dopants, and other additives. Dopants may include, for example, one or more of metals, metalloids, metal complexes, alloys, and non-metals, as well as combinations and variations thereof.
因此,例如p型摻雜劑可包括或可基於選自第13族的元素(硼等)中之一者或一者以上。用於製造p型SiC晶體、晶錠、晶棒及晶圓的特別較佳的摻雜劑為鋁。Thus, for example, the p-type dopant may include or may be based on one or more elements selected from Group 13 (boron, etc.). A particularly preferred dopant for making p-type SiC crystals, ingots, rods and wafers is aluminum.
為了製造低電阻率p型晶體及晶圓,起始聚矽碳材料中包含的摻雜劑的數量應足以在製程中推進以在SiC源材料中提供足夠的摻雜劑,從而在p型結晶材料中提供足夠的電活性原子雜質以具有低電阻率。如本文所使用,除非另有規定,否則「低電阻率」SiC p型晶體、晶錠、晶棒及晶圓具有0.03 ohm-cm及更小、約0.010 ohm-cm及更小、約0.007 ohm-cm及更小、約0.005 ohm-cm及更小、約0.003 ohm-cm及更小、約0.01 ohm-cm至約0.001 ohm-cm、約0.009 ohm-cm至約0.004 ohm-cm及約0.006 ohm-cm至約0.002 ohm-cm的電阻率。In order to fabricate low resistivity p-type crystals and wafers, the amount of dopants contained in the starting polysilica material should be sufficient to advance in the process to provide sufficient dopants in the SiC source material to crystallize in the p-type Providing sufficient electrically active atomic impurities in the material to have low resistivity. As used herein, unless otherwise specified, "low resistivity" SiC p-type crystals, ingots, rods and wafers have 0.03 ohm-cm and less, about 0.010 ohm-cm and less, about 0.007 ohm -cm and smaller, about 0.005 ohm-cm and smaller, about 0.003 ohm-cm and smaller, about 0.01 ohm-cm to about 0.001 ohm-cm, about 0.009 ohm-cm to about 0.004 ohm-cm and about 0.006 ohm-cm to about 0.002 ohm-cm resistivity.
用於低電阻率n型SiC結晶材料的較佳摻雜劑為磷、氮及硫(作為雙施體)及此等的組合。Preferred dopants for low resistivity n-type SiC crystalline materials are phosphorus, nitrogen and sulfur (as dual donors) and combinations thereof.
為了製造低電阻率n型晶體及晶圓,起始聚矽碳材料中包含的摻雜劑的數量應足以在製程中推進以在SiC源材料中提供足夠的摻雜劑,從而在n型結晶材料中提供足夠的電活性原子雜質以具有低電阻率。如本文所使用,除非另有規定,否則「低電阻率」SiC n型晶體、晶錠、晶棒及晶圓具有0.03 ohm-cm及更小、約0.010 ohm-cm及更小、約0.007 ohm-cm及更小、約0.005 ohm-cm及更小、約0.003 ohm-cm及更小、約0.01 ohm-cm至約0.001 ohm-cm、約0.009 ohm-cm至約0.004 ohm-cm及約0.006 ohm-cm至約0.002 ohm-cm的電阻率。In order to fabricate low resistivity n-type crystals and wafers, the amount of dopants contained in the starting polysilica material should be sufficient to advance in the process to provide sufficient dopants in the SiC source material to crystallize in the n-type. Providing sufficient electrically active atomic impurities in the material to have low resistivity. As used herein, unless otherwise specified, "low resistivity" SiC n-type crystals, ingots, rods, and wafers have 0.03 ohm-cm and less, about 0.010 ohm-cm and less, about 0.007 ohm -cm and smaller, about 0.005 ohm-cm and smaller, about 0.003 ohm-cm and smaller, about 0.01 ohm-cm to about 0.001 ohm-cm, about 0.009 ohm-cm to about 0.004 ohm-cm and about 0.006 ohm-cm to about 0.002 ohm-cm resistivity.
一般而言,聚矽碳前驅物配方最初為液體。液體前驅物被固化成固體或半固體SiOC (即,「固化材料」)。固體或半固體SiOC隨後被熱解成陶瓷SiOC,陶瓷SiOC隨後被轉換(進一步熱解)成SiC。此等製程及轉變可發生在單個步驟中,單獨的或個別的步驟中,以及此等的組合及變化。Generally, silicone precursor formulations start out as liquids. The liquid precursor is solidified into solid or semi-solid SiOC (i.e., the "cured material"). The solid or semi-solid SiOC is then pyrolyzed into ceramic SiOC, which is then converted (further pyrolyzed) into SiC. These processes and transformations can occur in single steps, in separate or individual steps, and in combinations and variations of these.
可向其添加摻雜劑(例如,施體原子、受體原子或兩種原子的來源)的可用作起始材料的前驅物配方及製造彼等前驅物配方的方法在美國專利第11,091,370號中揭示並教示,該案的全部揭示內容以引用的方式併入本文中。此等配方可提供富碳的SiC源材料及缺碳的SiC源材料。根據施體或受體原子的類型及其他條件,源材料中的預定化學計量(例如,富碳的、缺碳的)可為有益的,例如,預定化學計量可引起在SiC晶體中併入更多的摻雜劑作為填隙型雜質。Precursor formulations that can be used as starting materials, to which dopants (eg, donor atoms, acceptor atoms, or sources of both atoms) can be added, and methods of making the same are disclosed in U.S. Patent No. 11,091,370 All disclosures in this case are incorporated herein by reference. These formulations can provide carbon-rich SiC source materials and carbon-deficient SiC source materials. Depending on the type of donor or acceptor atoms and other conditions, a predetermined stoichiometry (e.g., carbon-rich, carbon-poor) in the source material may be beneficial, e.g., a predetermined stoichiometry may result in the incorporation of more energy into the SiC crystal. Many dopants act as interstitial impurities.
前驅物配方可由各種前驅物製成。Precursor formulations can be made from a variety of precursors.
前驅物可為矽氧烷主幹添加劑,諸如甲基氫(methyl hydrogen,MH),以下展示其化學式。 The precursor may be a siloxane backbone additive, such as methyl hydrogen (MH), the chemical formula of which is shown below.
MH可具有約400 mw至約10,000 mw、約600 mw至約3,000 mw的分子量(「mw」,其可被量測為重量平均分子量,以amu為單位,或量測為g/mol),且可具有較佳約20 cps至約60 cps的黏度。甲基矽氧烷單元「X」的百分比可為1%至100%。二甲基矽氧烷單元「Y」的百分比可為0%至99%。此前驅物可用於向固化的預製件及陶瓷材料提供交聯結構的主幹,以及其他特徵及特性。除其他事項外,此前驅物亦可藉由與不飽和碳化合物反應而被修改以產生新的或額外的前驅物。通常,甲基氫流體(methyl hydrogen fluid,MHF)具有最少量的「Y」,且更佳地,出於所有實踐的目的,「Y」為零。MH may have a molecular weight of about 400 mw to about 10,000 mw, about 600 mw to about 3,000 mw ("mw", which may be measured as weight average molecular weight in amu, or measured as g/mol), and It can preferably have a viscosity of about 20 cps to about 60 cps. The percentage of methylsiloxane units "X" can range from 1% to 100%. The percentage of dimethylsiloxane units "Y" can range from 0% to 99%. This precursor can be used to provide the backbone of the cross-linked structure, as well as other features and properties, to cured preforms and ceramic materials. Such precursors may also be modified by reaction with unsaturated carbon compounds to produce new or additional precursors, among other things. Typically, methyl hydrogen fluid (MHF) has a minimal amount of "Y", and preferably, for all practical purposes, "Y" is zero.
前驅物可為乙烯基取代的聚二甲基矽氧烷,以下展示其化學式。 The precursor may be vinyl-substituted polydimethylsiloxane, the chemical formula of which is shown below.
此前驅物可具有約400 mw至約10,000 mw的分子量(molecular weight,mw),且可具有較佳約50 cps至約2,000 cps的黏度。甲基乙烯基矽氧烷單元「X」的百分比可為1%至100%。二甲基矽氧烷單元「Y」的百分比可為0%至99%。較佳地,X為約100%。此前驅物可用於減小交聯密度且改良韌性,以及固化的預製件及陶瓷材料的其他特徵及特性。The precursor may have a molecular weight (mw) of about 400 mw to about 10,000 mw, and may preferably have a viscosity of about 50 cps to about 2,000 cps. The percentage of methylvinylsiloxane units "X" can range from 1% to 100%. The percentage of dimethylsiloxane units "Y" can range from 0% to 99%. Preferably, X is about 100%. This precursor can be used to reduce cross-link density and improve toughness, as well as other features and properties of cured preforms and ceramic materials.
前驅物可為乙烯基取代的且乙烯基終端化的聚二甲基矽氧烷,以下展示其化學式。 The precursor may be vinyl-substituted and vinyl-terminated polydimethylsiloxane, the chemical formula of which is shown below.
此前驅物可具有約500 mw至約15,000 mw的分子量(molecular weight,mw),且可較佳地具有約500 mw至1,000 mw的分子量,且可具有較佳約10 cps至約200 cps的黏度。甲基乙烯基矽氧烷單元「X」的百分比可為1%至100%。二甲基矽氧烷單元「Y」的百分比可為0%至99%。此前驅物可用於提供分枝且減小固化溫度,以及固化的預製件及陶瓷材料的其他特徵及特性。The precursor may have a molecular weight (mw) of about 500 mw to about 15,000 mw, and preferably has a molecular weight of about 500 mw to 1,000 mw, and may have a viscosity of about 10 cps to about 200 cps. . The percentage of methylvinylsiloxane units "X" can range from 1% to 100%. The percentage of dimethylsiloxane units "Y" can range from 0% to 99%. This precursor can be used to provide branching and reduced curing temperatures, as well as other features and properties of cured preforms and ceramic materials.
前驅物可為四乙烯基環四矽氧烷(「TV」),以下展示其化學式。 The precursor may be tetravinylcyclotetrasiloxane (“TV”), the chemical formula of which is shown below.
前驅物可為矽氧烷主幹添加劑,諸如甲基終端化的苯乙基聚矽氧烷,(亦可稱為苯乙烯乙烯基苯二甲基聚矽氧烷),以下展示其化學式。 The precursor can be a siloxane backbone additive, such as methyl-terminated phenethyl polysiloxane, (also known as styrene vinyl benzene dimethyl polysiloxane), the chemical formula of which is shown below.
此前驅物可具有可為約800 mw至至少約10,000 mw至至少約20,000 mw的分子量(molecular weight,mw),且可具有較佳約50 cps至約350 cps的黏度。苯乙烯乙烯基矽氧烷單元「X」的百分比可為1%至60%。二甲基矽氧烷單元「Y」的百分比可為40%至99%。此前驅物可用於提供改良的韌性,減少反應固化放熱,可改變或更改折射率,調整聚合物的折射率以與各種類型的玻璃的折射率匹配,用於提供例如透明的玻璃纖維,以及固化的預製件及陶瓷材料的其他特徵及特性。The precursor may have a molecular weight (mw) of about 800 mw to at least about 10,000 mw to at least about 20,000 mw, and may preferably have a viscosity of about 50 cps to about 350 cps. The percentage of styrenevinylsiloxane units "X" can range from 1% to 60%. The percentage of dimethylsiloxane units "Y" can range from 40% to 99%. This precursor can be used to provide improved toughness, reduce reaction cure exotherms, can alter or alter the refractive index, tailor the refractive index of the polymer to match that of various types of glass, be used to provide, for example, transparent glass fibers, and cure Other characteristics and properties of prefabricated parts and ceramic materials.
前驅物可為二乙烯苯。The precursor may be divinylbenzene.
前驅物亦可為美國專利第11,091,370號中揭示並教示的前驅物及液體起始材料中之任一者。The precursor may also be any of the precursors and liquid starting materials disclosed and taught in US Pat. No. 11,091,370.
可向其添加摻雜劑(例如,施體原子、受體原子或兩種原子的來源)以提供摻雜SiC源材料的前驅物配方包括例如以下前驅物配方。Precursor formulations to which dopants (eg, sources of donor atoms, acceptor atoms, or both atoms) can be added to provide a doped SiC source material include, for example, the following precursor formulations.
藉由將41 wt%的線性甲基氫聚矽氧烷(methyl-hydrogen polysiloxane,MHF)及59 wt%的四乙烯基環四矽氧烷(tetravinylcycloterasiloxane,TV)混合在一起製成的前驅物配方。Precursor formulation made by mixing together 41 wt% linear methyl-hydrogen polysiloxane (MHF) and 59 wt% tetravinylcycloterasiloxane (TV) .
藉由在室溫下將90%的甲基終端化的苯乙基聚矽氧烷(具有27%的X)與10%的TV混合在一起製成的前驅物配方。此前驅物配方具有1.05莫耳的氫化物、0.38莫耳的乙烯基、0.26莫耳的苯基及1.17莫耳的甲基。基於100 g的配方,前驅物配方具有以下莫耳量的Si、C及O。
如所計算,由此配方衍生的SiOC在已移除所有CO之後將具有計算出的2.31莫耳的C,且具有98%的過量C。As calculated, the SiOC derived from this formulation would have a calculated mole of C of 2.31 after all CO has been removed, with 98% excess C.
藉由在室溫下將70%的甲基終端化的苯乙基聚矽氧烷(具有14%的X)與30%的TV混合在一起製成的前驅物配方。此前驅物配方具有0.93莫耳的氫化物、0.48莫耳的乙烯基、0.13莫耳的苯基及1.28莫耳的甲基。基於100 g的配方,前驅物配方具有以下莫耳量的Si、C及O。
如所計算,由此配方衍生的SiOC在已移除所有CO之後將具有計算出的1.77莫耳的C,且具有38%的過量C。As calculated, the SiOC derived from this formulation would have a calculated mole of C of 1.77 after all CO has been removed, with an excess of C of 38%.
藉由在室溫下將50%的甲基終端化的苯乙基聚矽氧烷(具有20%的X)與50%的TV混合在一起製成的前驅物配方。此前驅物配方具有0.67莫耳的氫化物、0.68莫耳的乙烯基、0.10莫耳的苯基及1.25莫耳的甲基。基於100 g的配方,前驅物配方具有以下莫耳量的Si、C及O。
如所計算,由此配方衍生的SiOC在已移除所有CO之後將具有計算出的1.93莫耳的C,且具有55%的過量C。As calculated, the SiOC derived from this formulation would have a calculated mole of C of 1.93, with 55% excess C after all CO has been removed.
藉由在室溫下將65%的甲基終端化的苯乙基聚矽氧烷(具有40%的X)與35%的TV混合在一起製成的前驅物配方。此前驅物配方具有0.65莫耳的氫化物、0.66莫耳的乙烯基、0.25莫耳的苯基及1.06莫耳的甲基。基於100 g的配方,前驅物配方具有以下莫耳量的Si、C及O。
如所計算,由此配方衍生的SiOC在已移除所有CO之後將具有計算出的2.81莫耳的C,且具有166%的過量C。As calculated, the SiOC derived from this formulation would have a calculated mole of C of 2.81 after all CO has been removed, with an excess of C of 166%.
藉由在室溫下將65%的MHF與35%的二環戊二烯(dicyclopentadiene,DCPD)混合在一起製成的前驅物配方。此前驅物配方具有1.08莫耳的氫化物、0.53莫耳的乙烯基、0.0莫耳的苯基及1.08莫耳的甲基。基於100 g的配方,前驅物配方具有以下莫耳量的Si、C及O。
如所計算,由此配方衍生的SiOC在已移除所有CO之後將具有計算出的2.65莫耳的C,且具有144%的過量C。As calculated, the SiOC derived from this formulation would have a calculated mole of C of 2.65 after all CO has been removed, with an excess of C of 144%.
藉由在室溫下將82%的MHF與18%的二環戊二烯(dicyclopentadiene,DCPD)混合在一起製成的前驅物配方。此前驅物配方具有1.37莫耳的氫化物、0.27莫耳的乙烯基、0.0莫耳的苯基及1.37莫耳的甲基。基於100 g的配方,前驅物配方具有以下莫耳量的Si、C及O。
如所計算,由此配方衍生的SiOC在已移除所有CO之後將具有計算出的1.37莫耳的C,且具有0%的過量C。As calculated, the SiOC derived from this formulation would have a calculated mole of C of 1.37, with 0% excess C after all CO has been removed.
藉由在室溫下將46%的MHF、34%的TV與20%的VT混合在一起製成的前驅物配方。此前驅物配方具有0.77莫耳的氫化物、0.40莫耳的乙烯基、0.0莫耳的苯基及1.43莫耳的甲基。基於100 g的配方,前驅物配方具有以下莫耳量的Si、C及O。
如所計算,由此配方衍生的SiOC在已移除所有CO之後將具有計算出的0.53莫耳的C,且具有63%的C缺失或63%的C不足。As calculated, the SiOC derived from this formulation would have a calculated C of 0.53 moles after all CO has been removed, with a 63% C deficiency or a 63% C deficiency.
藉由在室溫下將70%的MHF、20%的TV與10%的VT混合在一起製成的前驅物配方。此前驅物配方具有1.17莫耳的氫化物、0.23莫耳的乙烯基、0.0莫耳的苯基及1.53莫耳的甲基。基於100 g的配方,前驅物配方具有以下莫耳量的Si、C及O。
如所計算,由此配方衍生的SiOC在已移除所有CO之後將具有計算出的0.33莫耳的C,且具有78%的C缺失或78%的C不足。As calculated, the SiOC derived from this formulation would have a calculated C of 0.33 moles after all CO has been removed, with either a 78% C deficiency or a 78% C deficiency.
具有50%的甲基終端化的苯乙基聚矽氧烷(具有20%的X)及50%的TV、95%的MHF的前驅物配方。Precursor formulation with 50% methyl-terminated phenethyl polysiloxane (with 20% X) and 50% TV, 95% MHF.
具有54%的甲基終端化的苯乙基聚矽氧烷(具有25%的X)及46%的TV的前驅物配方。Precursor formulation with 54% methyl-terminated phenethyl polysiloxane (with 25% X) and 46% TV.
具有57%的甲基終端化的苯乙基聚矽氧烷(具有30%的X)及43%的TV的前驅物配方。Precursor formulation with 57% methyl-terminated phenethyl polysiloxane (with 30% X) and 43% TV.
前驅物配方亦可為美國專利第11,091,370號中揭示並教示的前驅物配方中之任一者。The precursor formula may also be any of the precursor formulas disclosed and taught in US Pat. No. 11,091,370.
一或多種摻雜劑(例如,用於在晶體生長製程期間提供施體原子或受體原子的基於或包括原子雜質的組合物或材料)可被添加至液體前驅物中之一或多者,且因此添加至液體前驅物配方,至此情況下摻雜劑將變成固化的SiOC材料及因此SiOC陶瓷及SiC的一部分。摻雜劑可在液態下發生化學反應,即,化學鍵結至液體前驅物的組分。摻雜劑可為液體聚矽碳前驅物的混合物(例如,溶液或懸混液)的一部分。在此情形中,摻雜劑可在固化步驟期間化學鍵結至聚矽碳材料,且因此化學鍵結至固化的SiOC材料(熱解步驟),且因此化學鍵結至陶瓷SiOC材料(或轉換成SiC的步驟),且因此(化學地或機械地)保持在摻雜SiC源材料中,以及此等的組合及變化。p型摻雜SiC源材料(其提供或生長p型晶體)或低電阻率摻雜SiC源材料(其提供或生長n型或p型的低電阻率晶體)將是此種情況。One or more dopants (e.g., compositions or materials based on or including atomic impurities used to provide donor atoms or acceptor atoms during the crystal growth process) may be added to one or more of the liquid precursors, And thus added to the liquid precursor formulation, the dopant will now become part of the solidified SiOC material and therefore the SiOC ceramic and SiC. The dopant can react chemically in the liquid state, ie, chemically bond to components of the liquid precursor. The dopant may be part of a mixture (eg, a solution or suspension) of liquid polysilica precursors. In this case, the dopant may be chemically bonded to the polysilica material during the curing step, and thus to the cured SiOC material (pyrolysis step), and thus to the ceramic SiOC material (or converted to SiC steps) and thus remain (chemically or mechanically) in the doped SiC source material, as well as combinations and variations thereof. This will be the case for p-type doped SiC source materials (which provide or grow p-type crystals) or low-resistivity doped SiC source materials (which provide or grow low-resistivity crystals of n-type or p-type).
摻雜劑可為混合物(例如,與固化材料、SiOC陶瓷或兩者混合的固體)的一部分,在此情況下,摻雜劑可在後續步驟中之一或多者期間化學鍵結至SiOC材料以提供p型摻雜SiC源材料或低電阻率SiC源材料。The dopant may be part of a mixture (e.g., a solid mixed with the cured material, the SiOC ceramic, or both), in which case the dopant may chemically bond to the SiOC material during one or more of the subsequent steps to Available in p-type doped SiC source material or low resistivity SiC source material.
一般而言,在本發明之實施例中,摻雜劑較佳為SiOC材料、SiC源材料及兩者的整體部分。因此,摻雜劑可能:(i)被化學鍵結至SiOC材料(例如,液體SiOC材料中之一或多者的聚合物鏈或組合物的一部分、固化的SiOC材料中的固化聚合物的一部分或兩者);(ii)它可(化學地、機械地或兩者)保持在SiOC材料的基質(例如,奈米複合物)內,諸如美國專利第10,633,400號中揭示並教示,該案的全部揭示內容以引用的方式併入本文中;(iii)它可(化學地、機械地或兩者)保持在SiC源材料內;及(iv)此等的組合及變化。Generally speaking, in embodiments of the present invention, the dopant is preferably a SiOC material, a SiC source material, or an integral part of both. Accordingly, the dopant may: (i) be chemically bonded to the SiOC material (e.g., a polymer chain or part of the composition of one or more of the liquid SiOC materials, a part of the cured polymer in the cured SiOC material, or both); (ii) it can be retained (chemically, mechanically, or both) within a matrix of SiOC materials (e.g., nanocomposites) such as disclosed and taught in U.S. Patent No. 10,633,400, all of which The disclosure is incorporated herein by reference; (iii) it can be retained (chemically, mechanically, or both) within the SiC source material; and (iv) combinations and variations of these.
在用於提供p型SiC材料的起始材料、中間材料及製程的實施例中,摻雜劑被共價鍵結至SiOC組合物中的Si、C、O原子中之一或多者。因此,例如,將固化的SiOC材料轉換成SiC導致摻雜劑被共價鍵結至Si、C或兩者,且貫穿SiC源材料(即,粉末)、SiC成形裝藥(若使用)均勻地分佈,以便氣相沉積製程(例如,PVT)生長p型SiC晶體。In embodiments for providing starting materials, intermediate materials and processes for p-type SiC materials, the dopant is covalently bonded to one or more of Si, C, O atoms in the SiOC composition. Thus, for example, converting a solidified SiOC material to SiC results in the dopant being covalently bonded to Si, C, or both, uniformly throughout the SiC source material (i.e., powder), the SiC shaped charge (if used) Distributed so that p-type SiC crystals can be grown by a vapor deposition process (eg, PVT).
通常,可採用兩種類型的反應將摻雜劑分子共價併入至聚合物網中:氫矽化反應及縮合反應。一般而言,氫矽化反應將採用摻雜劑分子中的至少一個烯基的官能基。較佳實施例例如將具有兩個此類官能基,最佳為3至4個。縮合反應將採用烷氧基、醇基或羥基(-OR),其中R通常為小的烷烴或氫。In general, two types of reactions can be used to covalently incorporate dopant molecules into the polymer network: hydrosiliconation reactions and condensation reactions. Generally speaking, the hydrosilication reaction will employ at least one alkenyl functionality in the dopant molecule. Preferred embodiments will, for example, have two such functional groups, most preferably 3 to 4. The condensation reaction will use an alkoxy, alcohol or hydroxyl group (-OR), where R is usually a small alkane or hydrogen.
在一些實施例中,在熱解後,石墨烯結構、石墨結構、非晶碳結構以及此等的組合及變化存在於Si-O-C陶瓷中。由SiOxCy結構(其產生SiO 4、SiO 3C、SiO 2C 2、SiOC 3及SiC 4)組成的矽物質的分佈以不同的比率形成,該等比率源自於前驅物的選擇及其處理歷史。在此等實施例中,摻雜劑可與非晶碳結構一起束縛在相鄰的碳原子與矽原子之間。一般而言,對於SiOC,在陶瓷狀態下,碳基本上不與氧原子配位,因此氧基本上與矽配位,且摻雜劑將根據其起始結構基本上與矽或碳配位。 In some embodiments, graphene structures, graphite structures, amorphous carbon structures, and combinations and variations thereof are present in the Si-OC ceramic after pyrolysis. The distribution of silicon species consisting of the SiOxCy structure (which yields SiO 4 , SiO 3 C, SiO 2 C 2 , SiOC 3 and SiC 4 ) forms in different ratios resulting from the choice of precursors and their processing history . In such embodiments, the dopants may be bound together with the amorphous carbon structure between adjacent carbon atoms and silicon atoms. Generally speaking, for SiOC, in the ceramic state, the carbon is essentially not coordinated with the oxygen atoms, so the oxygen is essentially coordinated with the silicon, and the dopant will be essentially coordinated with the silicon or carbon depending on its starting structure.
在較佳實施例中,用於氣相沉積製程(例如,PVT)生長p型晶體的起始材料具有選自週期表的第13族的元素(硼等)中之一或多者的摻雜劑。摻雜劑被共價鍵結至源材料的Si、C或兩者,且貫穿源材料均勻地分佈。在更佳的實施例中,起始材料經組態為成形裝藥,其中摻雜劑貫穿成形裝藥、不同濃度的層等以預定方式(例如,均勻地)分佈。然後使用此種源材料執行氣相沉積製程,例如,如本說明書的子章節「晶體生長-一般而言」中所描述。In a preferred embodiment, the starting material used for growing p-type crystals in a vapor deposition process (eg, PVT) has doping with one or more elements selected from group 13 of the periodic table (boron, etc.) agent. The dopant is covalently bonded to the Si, C, or both of the source material and is evenly distributed throughout the source material. In a more preferred embodiment, the starting material is configured as a shaped charge, wherein the dopant is distributed in a predetermined manner (eg, uniformly) throughout the shaped charge, layers of varying concentrations, and the like. This source material is then used to perform a vapor deposition process, for example, as described in the subsection "Crystal Growth - Generally" of this specification.
在較佳實施例中,用於氣相沉積製程(例如,PVT)生長低電阻率n型晶體的起始材料具有選自週期表的第15族的元素(氮等)中之一或多者的摻雜劑。摻雜劑被共價鍵結至源材料的Si、C或兩者,且貫穿源材料均勻地分佈。在更佳的實施例中,起始材料經組態為成形裝藥,其中摻雜劑貫穿成形裝藥、不同濃度的層等以預定方式(例如,均勻地)分佈。然後使用此種源材料執行氣相沉積製程,例如,如本說明書的子章節「晶體生長-一般而言」中所描述。In a preferred embodiment, the starting material for growing low-resistivity n-type crystals using a vapor deposition process (eg, PVT) has one or more elements selected from Group 15 of the periodic table (nitrogen, etc.) of dopants. The dopant is covalently bonded to the Si, C, or both of the source material and is evenly distributed throughout the source material. In a more preferred embodiment, the starting material is configured as a shaped charge, wherein the dopant is distributed in a predetermined manner (eg, uniformly) throughout the shaped charge, layers of varying concentrations, and the like. This source material is then used to perform a vapor deposition process, for example, as described in the subsection "Crystal Growth - Generally" of this specification.
在目前的p型材料及製程的實施例中,摻雜劑、受體雜質原子係SiC源材料的一部分,例如,化學鍵結至、共價鍵結至或困在SiC基質中。此外,在此實施例中,摻雜劑及其受體雜質原子不是以合金的形式存在於起始材料中。例如,摻雜劑可為鋁,且鋁存在於源材料中而不是作為合金存在。因此,且以此方式,在氣相沉積(例如,通量形成)期間及其後,摻雜劑及受體雜質原子不是合金或者並未以其他方式形成為合金。人們相信,避免使用合金、此合金化步驟或合金形成相比先前技術提供了顯著的優點,且提供了改良的晶體生長、形成及性質。(如本文所使用,合金為由兩種或更多種金屬組成或者由非緊密結合(通常藉由在熔化時融合在一起且溶解在彼此中)的金屬及非金屬組成的物質。合金可具有以99:1、90:10、80:20至50:50的比率存在的不同金屬)。術語不含合金或沒有形成合金將指代不具有或不形成具有比率90:10、80:20至50:50的任何合金。在實施例中,亦可避免具有99:1至91:9的比率的合金,且因此該等合金不存在於起始材料中,且在氣相沉積裝置中未發現或未形成。In current embodiments of p-type materials and processes, dopant, acceptor impurity atoms are part of the SiC source material, eg, chemically bonded to, covalently bonded to, or trapped in the SiC matrix. Furthermore, in this example, the dopant and its acceptor impurity atoms are not present in the starting material in the form of an alloy. For example, the dopant may be aluminum and the aluminum is present in the source material rather than as an alloy. Therefore, and in this manner, the dopant and acceptor impurity atoms are not alloyed or otherwise formed into an alloy during and after vapor deposition (eg, flux formation). It is believed that avoiding the use of alloys, this alloying step or alloy formation provides significant advantages over prior art and provides improved crystal growth, formation and properties. (As used herein, an alloy is a substance composed of two or more metals or metals and nonmetals that are not tightly bound (usually by fusing together and dissolving in each other when melted). An alloy may have Different metals present in ratios of 99:1, 90:10, 80:20 to 50:50). The term unalloyed or not alloyed will refer to any alloy that does not have or does not form with a ratio of 90:10, 80:20 to 50:50. In embodiments, alloys with ratios of 99:1 to 91:9 are also avoided and are therefore not present in the starting material and are not found or formed in the vapor deposition apparatus.
在實施例中,摻雜劑可為作為前驅物組分的高純度鋁/矽合金或摻鋁矽粉末。摻雜矽粉末可為反應碳以形成摻Al SiC粉末。此粉末可製成為成形裝藥源材料。In embodiments, the dopant may be a high purity aluminum/silicon alloy or aluminum-doped silicon powder as a precursor component. The doped silicon powder may be reacted carbon to form Al-doped SiC powder. This powder can be made into shaped charge source material.
轉至第3圖,提供了用於製造摻雜SiC源材料(p型摻雜源材料、低電阻率p型摻雜源材料或低電阻率n型源材料)的系統及方法之實施例的示意性透視流程圖,該摻雜SiC源材料包括摻雜SiC源材料的成形裝藥(例如,體積形狀)。SiC源材料由摻雜SiOC前驅物及中間材料衍生。摻雜SiC源材料及成形裝藥較佳地具有高純度(例如,3個九、4個九、5個九及更大,且較佳地為6個九或更大)。系統的包含前驅物及其他材料的線路、閥及內部表面由將不會污染SiOC、衍生SiC及SiC的體積形狀(例如,向其提供污染物的來源)的材料製成或由該等材料覆蓋。Turning to Figure 3, embodiments of systems and methods for fabricating doped SiC source materials (p-type doped source materials, low resistivity p-type doped source materials, or low resistivity n-type source materials) are provided. Schematic perspective flow diagram of doped SiC source material including a shaped charge (eg, volumetric shape) of doped SiC source material. SiC source materials are derived from doped SiOC precursors and intermediate materials. The doped SiC source material and shaped charge are preferably of high purity (eg, 3 nines, 4 nines, 5 nines and greater, and preferably 6 nines or greater). The lines, valves, and internal surfaces of the system containing precursors and other materials are made of or covered with materials that will not contaminate SiOC, derived SiC, and the bulk shape of SiC (e.g., provide a source of contamination thereto) .
在僅使用p型摻雜劑(即,提供受體原子的來源的摻雜劑)的實施例中,應最小化、減輕並消除將被視為或者為施體原子的來源的任何材料(諸如氮)的存在。(應注意,在其他實施例中,氮可以小於p型摻雜劑的量存在,且仍然獲得p型源材料,即,經組態以生長具有負Nc的晶體。)In embodiments using only p-type dopants (i.e., dopants that provide a source of acceptor atoms), any materials that would be considered or be a source of donor atoms should be minimized, mitigated, and eliminated (such as nitrogen). (It should be noted that in other embodiments, nitrogen may be present in an amount less than the p-type dopant and still obtain a p-type source material, i.e., configured to grow a crystal with negative Nc.)
類似地,在僅使用n型摻雜劑(即,提供施體原子的來源的摻雜劑)的實施例中,應最小化、減輕並消除將被視為或者為受體原子的來源的任何材料(諸如硼及鋁)的存在。(應注意,在其他實施例中,硼或鋁可以小於n型摻雜劑的量存在,且仍然獲得n型源材料,即,經組態以生長具有正Nc的晶體。)Similarly, in embodiments using only n-type dopants (i.e., dopants that provide a source of donor atoms), any dopants that would be considered or be a source of acceptor atoms should be minimized, mitigated, and eliminated. The presence of materials such as boron and aluminum. (It should be noted that in other embodiments, boron or aluminum may be present in an amount less than the n-type dopant and still obtain an n-type source material, i.e., configured to grow a crystal with positive Nc.)
儲存罐150a、150b保存液體聚矽碳前驅物,且摻雜劑可裝在單獨的儲存罐、鬥或倉150c中。若使用多種摻雜劑,則亦可存在多個罐、鬥或倉。可將摻雜劑添加至儲存罐或混合器152。在此實施例中,可使前驅物中之一者或兩者或都不通過蒸餾裝置151a及蒸餾裝置151b,以自液體前驅物移除任何污染物。應小心不要損壞摻雜劑或以其他方式影響其性質。Storage tanks 150a, 150b hold the liquid polysilica precursor, and the dopants may be contained in a separate storage tank, hopper or bin 150c. If multiple dopants are used, multiple tanks, hoppers or bins may also be present. Dopants may be added to storage tank or mixer 152. In this embodiment, one, both, or neither of the precursors may be passed through distillation device 151a and distillation device 151b to remove any contaminants from the liquid precursor. Care should be taken not to damage the dopants or otherwise affect their properties.
然後將液體前驅物及摻雜劑傳送至混合容器152,在其中將它們混合以形成摻雜前驅物批次(例如,p型、低電阻率p型或低電阻率n型)並進行催化。然後將前驅物批次澆注至容器153中(較佳地在無塵室環境157a中)以便置放於爐154中。爐154可具有掃氣入口161及廢氣排放線路162。通常,掃氣為惰性氣體,諸如氬氣。爐使液體聚矽碳材料固化且使摻雜劑與聚矽碳材料反應以將摻雜劑鍵結至固化的聚矽碳材料中或鍵結為固化的聚矽碳材料的一部分。The liquid precursor and dopant are then transferred to mixing vessel 152 where they are mixed to form a doping precursor batch (eg, p-type, low resistivity p-type, or low resistivity n-type) and catalyzed. The precursor batch is then poured into container 153 (preferably in a clean room environment 157a) for placement in furnace 154. Furnace 154 may have a scavenge inlet 161 and an exhaust gas exhaust line 162 . Typically, the scavenge gas is an inert gas such as argon. The furnace solidifies the liquid polysilica material and reacts the dopant with the polysilica material to bond the dopant into or as part of the cured polysilica material.
然後將固化材料,即,固體摻雜SiOC (例如,p型、低電阻率p型或低電阻率n型),較佳地在無塵室條件下傳送至一個且較佳地若干熱解爐155a、155b、155c,在其中將它自摻雜SiOC轉變成摻雜SiC源材料(例如,p型、低電阻率p型或低電阻率n型)。(應注意,在此實施例中,SiOC陶瓷將為在例如155a的爐中轉變成SiC時形成的相)該等爐分別具有掃氣入口線路158a、158b、158c,且分別具有兩個廢氣排放線路159a及160a、159b及160b以及159c及160c。通常,掃氣為惰性氣體,諸如氬氣。可在具有入口線路164的廢氣處理總成163中處理、清潔廢氣且恢復起始材料,該入口線路自系統中的各個單元收集廢氣。The cured material, i.e., solid doped SiOC (eg, p-type, low resistivity p-type, or low resistivity n-type), is then transferred to one and preferably several pyrolysis furnaces, preferably under clean room conditions 155a, 155b, 155c, where it is converted from doped SiOC to doped SiC source material (eg, p-type, low resistivity p-type, or low resistivity n-type). (It should be noted that in this embodiment, the SiOC ceramic will be the phase formed when converted to SiC in a furnace such as 155a) The furnaces each have scavenge inlet lines 158a, 158b, 158c, and each has two exhaust exhausts. Lines 159a and 160a, 159b and 160b and 159c and 160c. Typically, the scavenge gas is an inert gas such as argon. The exhaust gases may be treated, cleaned, and starting materials recovered in an exhaust gas treatment assembly 163 having an inlet line 164 that collects exhaust gases from various units in the system.
然後將為粉末的所得摻雜SiC源材料(例如,p型、低電阻率p型或低電阻率n型)傳送至較佳地處於無塵室條件下的體積形狀形成區域190。在區域190中,將摻雜SiC材料提供至具有混合元件173 (例如,葉片、槳葉、攪拌器等)的混合容器172。將來自黏結劑罐170的黏結劑經由線路171添加至容器172。在混合容器172中,將SiC與黏結劑混合以形成漿料或摻合物。漿料的稠度應如此以促進後續形成操作。然後將SiC-黏結劑漿料傳送至形成裝置175,在其中將漿料形成為體積形狀,例如,丸粒、圓盤、方塊等,且較佳地形成為摻雜成形裝藥源材料(例如,p型、低電阻率p型或低電阻率n型),且將它饋送至烘箱177,在其中使黏結劑固化以給予體積形狀所要的強度且較佳地進行熱解。The resulting doped SiC source material (eg, p-type, low-resistivity p-type, or low-resistivity n-type) as a powder is then transferred to a volume shape forming region 190, preferably under clean room conditions. In region 190, doped SiC material is provided to a mixing vessel 172 having mixing elements 173 (eg, blades, paddles, stirrers, etc.). Binder from binder tank 170 is added to container 172 via line 171 . In mixing vessel 172, the SiC is mixed with the binder to form a slurry or blend. The consistency of the slurry should be such as to facilitate subsequent forming operations. The SiC-binder slurry is then transferred to a forming device 175 where the slurry is formed into volumetric shapes, e.g., pellets, discs, cubes, etc., and preferably into doped shaped charge source materials (e.g., p-type, low-resistivity p-type or low-resistivity n-type) and feeds it to oven 177 where the binder is cured to give the desired strength to the volumetric shape and is preferably pyrolyzed.
然後亦可將體積形狀傳輸至包裝元件180,在其中對它們進行包裝。較佳地,此等操作係在無塵室條件下執行,且更佳地,操作係在單獨的無塵室或無塵室區域190a、190b、190c中執行。亦可將成形裝藥直接提供至氣相沉積裝置(例如,PVT),用於生長摻雜SiC晶體(例如,p型、低電阻率p型或低電阻率n型)。The volumetric shapes can then also be transferred to packaging elements 180 where they are packaged. Preferably, these operations are performed under clean room conditions, and more preferably, the operations are performed in separate clean rooms or clean room areas 190a, 190b, 190c. The shaped charge can also be provided directly to a vapor deposition apparatus (eg, PVT) for growing doped SiC crystals (eg, p-type, low resistivity p-type, or low resistivity n-type).
較佳地,在製造p型摻雜SiC、低電阻率p型摻雜或低電阻率n型摻雜SiC源材料時,在較佳實施例中,可在清潔的空氣中在約1個大氣壓下混合聚矽碳前驅物及摻雜劑。Preferably, when manufacturing p-type doped SiC, low-resistivity p-type doping or low-resistivity n-type doped SiC source material, in a preferred embodiment, the source material can be made in clean air at about 1 atmosphere. Mix the polysilicon precursor and dopants.
較佳地,在製造SiC及用於製造SiC的材料時,經摻雜的且較佳地經催化前驅物材料的固化發生的溫度在以下範圍內:約20℃至約150℃、約75℃至約125℃及約80℃至90℃以及此等溫度的變化及組合,以及在此等溫度的範圍內的所有值。固化係在一時間段內進行,其較佳地導致硬固化材料。固化可在空氣或惰性氣氛中發生,且較佳地,固化在環境壓力下在氬氣氛中發生。較佳地,為了得到高純度材料,爐、容器、處理設備及固化裝置的其他組件係清潔的,基本上不含且不向固化材料貢獻將被視為雜質或污染物的任何元素或材料。應注意,在較佳實施例中,根據正在生長的晶體的類型,施體原子的來源或受體原子的來源可被視為污染物。Preferably, in making SiC and materials used to make SiC, the curing of the doped and preferably catalyzed precursor material occurs at a temperature in the following range: about 20°C to about 150°C, about 75°C to about 125°C and about 80°C to 90°C and variations and combinations of these temperatures, and all values within the range of such temperatures. Curing is carried out over a period of time which preferably results in a hard set material. Curing may occur in air or an inert atmosphere, and preferably curing occurs in an argon atmosphere at ambient pressure. Preferably, in order to obtain high purity materials, the furnaces, vessels, processing equipment and other components of the curing apparatus are clean, substantially free of and do not contribute any elements or materials to the cured material that would be considered impurities or contaminants. It should be noted that in preferred embodiments, depending on the type of crystal being grown, the source of donor atoms or the source of acceptor atoms may be considered a contaminant.
較佳地,在製造摻雜SiC源材料(例如,p型、低電阻率p型或低電阻率n型)時,熱解發生的溫度在以下範圍內:約800℃至約1300℃、約900℃至約1200℃及約950℃至1150℃,以及在此等溫度的範圍內的所有值。熱解係在一時間段內進行,其較佳地導致固化的摻雜SiOC材料完全熱解成p型摻雜SiC源材料。較佳地,熱解在例如氬氣的惰性氣體中發生,且更佳地在大氣壓下或大約在大氣壓下在流動的氬氣中發生。氣體可在約1,200 cc/min至約200 cc/min、約800 cc/min至約400 cc/min及約500 cc/min,以及在此等流量的範圍內的所有值下流動。較佳地,處理爐的初始抽真空完成至至少低於1x10 -3托的降低的壓力,且利用例如氬氣的惰性氣體再增壓至大於或等於100托。更佳地,在利用惰性氣體再增壓之前,抽真空完成至低於1x10 -5托。在前進之前,抽真空製程可在零至>4次的任何地方完成。較佳地,為了得到高純度材料,爐、容器、處理設備及固化裝置的其他組件係清潔的,基本上不含、不含且不向熱解材料貢獻將被視為污染物的任何元素或材料。 Preferably, when fabricating doped SiC source materials (eg, p-type, low-resistivity p-type, or low-resistivity n-type), pyrolysis occurs at a temperature in the following range: about 800°C to about 1300°C, about 900°C to about 1200°C and about 950°C to 1150°C, and all values within these temperature ranges. Pyrolysis is performed over a period of time which preferably results in complete pyrolysis of the cured doped SiOC material into p-type doped SiC source material. Preferably, pyrolysis occurs in an inert gas such as argon, and more preferably in flowing argon at or about atmospheric pressure. The gas may flow at about 1,200 cc/min to about 200 cc/min, about 800 cc/min to about 400 cc/min, and about 500 cc/min, and all values within such flow ranges. Preferably, initial evacuation of the treatment furnace is accomplished to a reduced pressure of at least less than 1x10 -3 Torr and repressurized to greater than or equal to 100 Torr using an inert gas such as argon. More preferably, evacuation is accomplished to less than 1x10 -5 Torr before repressurization with an inert gas. The evacuation process can be completed anywhere from zero to >4 times before moving forward. Preferably, in order to obtain high purity materials, the furnaces, vessels, processing equipment and other components of the curing unit are clean, substantially free of, do not contain and do not contribute to the pyrolytic material any elements that would be considered contaminants or Material.
熱解可在保持請求的溫度及環境控制的任何加熱裝置中進行。因此,例如,熱解可利用高壓爐、箱式爐、管式爐、晶體生長爐、石墨箱式爐、電弧熔化爐、感應電爐、窯、MoSi 2加熱元件爐、碳爐、真空爐、燃氣爐、電爐、直接加熱、間接加熱、流體化床、RF爐、窯、隧道窯、箱式窯、梭子窯、煉焦型裝置、雷射、微波、其他電磁輻射,以及可獲得熱解的請求溫度的此等及其他加熱裝置及系統的組合及變化進行。 Pyrolysis can be performed in any heating device that maintains the requested temperature and environmental controls. Thus, for example, pyrolysis can utilize high-pressure furnaces, box furnaces, tube furnaces, crystal growth furnaces, graphite box furnaces, arc melting furnaces, induction furnaces, kilns, MoSi 2 heating element furnaces, carbon furnaces, vacuum furnaces, combustion furnaces Gas furnaces, electric furnaces, direct heating, indirect heating, fluidized beds, RF furnaces, kilns, tunnel kilns, box kilns, shuttle kilns, coking type units, lasers, microwaves, other electromagnetic radiation, and pyrolysis is available on request Combinations and changes in temperature of these and other heating devices and systems are carried out.
較佳地,在製造摻雜SiC源材料時,在後續或繼續的熱解或轉換步驟中將陶瓷摻雜SiOC轉換成SiC。自摻雜SiOC轉換的步驟可為摻雜SiOC固化材料的熱解的一部分,例如,為熱解的繼續,或者它可為在時間、位置及兩者上完全單獨的步驟。根據所要的摻雜SiC的類型,轉換步驟(自SiOC至SiC)可在約1,200℃至約2,550℃及約1,300℃至1,700℃,以及在此等溫度的範圍內的所有值下執行。Preferably, when manufacturing the doped SiC source material, the ceramic doped SiOC is converted into SiC in a subsequent or continuing pyrolysis or conversion step. The step of converting from doped SiOC may be part of the pyrolysis of the doped SiOC cured material, for example, a continuation of pyrolysis, or it may be an entirely separate step in time, location, and both. Depending on the type of doped SiC desired, the conversion step (from SiOC to SiC) can be performed at about 1,200°C to about 2,550°C and about 1,300°C to 1,700°C, and all values within these temperature ranges.
通常,在約1,600℃至約1,900℃的溫度下,隨時間流逝,β型的形成係較佳的。在高於1900℃的溫度下,隨時間流逝,α型的形成係較佳的。較佳地,轉換在例如氬氣的惰性氣體中發生,且更佳地在大氣壓下或大約在大氣壓下在流動的氬氣中發生。氣體可在約600 cc/min至約10 cc/min、約300 cc/min至約50 cc/min及約80 cc/min至約40 cc/min,以及在此等流量的範圍內的所有值下流動。較佳地,為了得到高純度材料,爐、容器、處理設備及固化裝置的其他組件係清潔的,基本上不含且不向SiC貢獻將被視為雜質或污染物的任何元素或材料。Generally, the formation of the beta form is preferred over time at a temperature of about 1,600°C to about 1,900°C. At temperatures above 1900°C, the formation of the α form is preferred over time. Preferably, the conversion occurs in an inert gas such as argon, and more preferably in flowing argon at or about atmospheric pressure. The gas may have a flow rate of about 600 cc/min to about 10 cc/min, about 300 cc/min to about 50 cc/min, and about 80 cc/min to about 40 cc/min, and all values within such flow ranges. flow down. Preferably, in order to obtain high purity materials, the furnaces, vessels, processing equipment and other components of the curing apparatus are clean, substantially free of and do not contribute any elements or materials to the SiC that would be considered impurities or contaminants.
摻雜SiOC衍生的摻雜SiC的後續產率通常為約10%至50%,通常為30%至40%,但是可獲得更高及更低的範圍,以及在此等百分比的範圍內的所有值。Subsequent yields of doped SiOC derived doped SiC are typically about 10% to 50%, typically 30% to 40%, but higher and lower ranges are available, and all within these percentage ranges value.
應進一步理解,在抑制將要存在於摻雜SiOC前驅物材料中(例如,在混合器152中或在固化的固體SiOC中)的摻雜劑的量時,應考慮貫穿整個製程(包括在晶體生長期間)的摻雜劑損耗。因此,足夠的摻雜劑應存在於SiC源材料中,達到預定的摻雜劑水準,例如,由該源材料生長的晶體及因此由該晶體製成的晶圓中預定量的電活性原子,以提供晶體及晶圓的預定及預期的電氣性質及半導體性質。It should be further understood that when suppressing the amount of dopant that will be present in the doped SiOC precursor material (e.g., in mixer 152 or in cured solid SiOC), considerations should be made throughout the entire process, including during crystal growth. dopant loss during the period. Accordingly, sufficient dopant should be present in the SiC source material to achieve a predetermined dopant level, e.g., a predetermined amount of electrically active atoms in a crystal grown from the source material and therefore a wafer made from the crystal, To provide predetermined and expected electrical and semiconductor properties of crystals and wafers.
用於形成體積摻雜成形源材料(例如,摻雜成形裝藥源材料)的黏結劑可為用於在體積形狀的處理、固化及後續使用期間保持SiC處於預定形狀的任何黏結劑。黏結劑的實施例可較佳地不含氧。黏結劑的實施例可較佳地由僅具有碳及氫的材料構成。黏結劑的實施例可由具有氧的材料製成。黏結劑的實施例可為用於燒結SiC的任何燒結助劑。黏結劑的實施例可為熔融矽石。黏結劑的實施例可為聚矽碳前驅物材料,包括本說明書中陳述的所有液體前驅物。此等及其他材料的組合及變化亦可用作黏結劑。黏結劑亦可包含摻雜劑,此摻雜劑可為與用於製造成形裝藥的SiC粉末的摻雜劑相同或不同。The binder used to form the volumetric doped shaped source material (eg, the doped shaped charge source material) can be any binder used to maintain the SiC in a predetermined shape during processing, curing, and subsequent use of the volumetric shape. Embodiments of the binder may preferably be oxygen-free. Embodiments of the binder may preferably be composed of materials having only carbon and hydrogen. Embodiments of the adhesive may be made of materials containing oxygen. An example of a binder may be any sintering aid used for sintering SiC. An example of a binder may be fused silica. Examples of binders may be polysilica precursor materials, including all liquid precursors stated in this specification. Combinations and variations of these and other materials can also be used as binders. The binder may also contain dopants, which may be the same or different from the dopants used to make the SiC powder of the shaped charge.
黏結劑可在用於使聚矽碳前驅物固化的條件下或在將黏結劑轉化成足夠硬(例如,堅韌)的材料以保持體積形狀的形狀所需要的條件下固化並熱解至所需的程度。因此,固化、硬化、形成或建構視情況而定應基於黏結劑的特性來進行。The binder may be cured and pyrolyzed to the desired temperature under conditions used to cure the polysilica precursor or under conditions required to convert the binder into a material that is hard enough (e.g., tough) to maintain the shape of the bulk shape. Degree. Curing, hardening, forming or structuring, as appropriate, should therefore be based on the properties of the binder.
不具有氧的黏結劑的實施例之實例將包括聚乙烯、矽金屬、烴蠟、聚苯乙烯及聚丙烯,以及此等的組合及變化。Examples of embodiments of binders that do not have oxygen would include polyethylene, silicon metal, hydrocarbon waxes, polystyrene, and polypropylene, as well as combinations and variations of these.
僅包含碳及氫的黏結劑的實施例之實例將包括聚乙烯、烴蠟、碳或石墨粉末、碳黑、HDPE、LDPE、UHDPE及PP,以及此等的組合及變化。Examples of embodiments of binders containing only carbon and hydrogen would include polyethylene, hydrocarbon waxes, carbon or graphite powders, carbon black, HDPE, LDPE, UHDPE and PP, as well as combinations and variations of these.
包含氧的黏結劑的實施例之實例將包括硼酸、氧化硼、二氧化矽、多元醇、聚乳酸、纖維素材料、糖及糖類、聚酯、環氧樹脂、矽氧烷、矽酸鹽、矽烷、矽倍半氧烷、諸如醋酸乙烯酯(ethylvinylacetate,EVA)的醋酸酯、諸如PMMA的聚丙烯酸酯及聚合物衍生陶瓷前驅物,以及此等的組合及變化。Examples of embodiments of oxygen-containing binders would include boric acid, boron oxide, silica, polyols, polylactic acid, cellulosic materials, sugars and sugars, polyesters, epoxy resins, siloxanes, silicates, Silanes, silsesquioxanes, acetates such as ethylvinylacetate (EVA), polyacrylates such as PMMA, and polymer-derived ceramic precursors, as well as combinations and variations of these.
作為燒結助劑的黏結劑的實施例之實例將包括矽、氧化硼、硼酸、碳化硼、矽及碳粉末、矽石、矽酸鹽及聚合物衍生陶瓷前驅物,以及此等的組合和變化。Examples of embodiments of binders that are sintering aids would include silicon, boron oxide, boric acid, boron carbide, silicon and carbon powders, silica, silicate and polymer derived ceramic precursors, and combinations thereof. change.
黏結劑應被選擇以便不會干擾或以其他方式抑制摻雜劑、摻雜SiC晶體的生長及摻雜SiC晶體及晶圓的性質。The binder should be selected so as not to interfere with or otherwise inhibit the growth of the dopant, the doped SiC crystal, and the properties of the doped SiC crystal and wafer.
黏結劑的實施例將包括催化的及未催化的前驅物配方,如美國專利第9,815,943號、第9,657,409號、第10,322,936號、第10,753,010號、第11,014,819號及第11,091,370號以及美國專利公開案第2018/0290893號中揭示並教示,其中每一者的全部揭示內容以引用的方式併入本文中。使此等黏結劑固化的方法在此等專利及公開申請案找那個揭示並教示,其中每一者的全部揭示內容以引用的方式併入本文中。Examples of binders would include catalyzed and uncatalyzed precursor formulations such as U.S. Patent Nos. 9,815,943, 9,657,409, 10,322,936, 10,753,010, 11,014,819, and 11,091,370 and U.S. Patent Publication No. 2018 /0290893, the entire disclosure of each of which is incorporated herein by reference. Methods of curing such adhesives are disclosed and taught in these patents and published applications, the entire disclosures of each of which are incorporated herein by reference.
Ashbys催化劑及其他可能基本上不受摻鋁前驅物配方的影響。含磷前驅物配方可導致一些催化劑抑制。可藉由非催化手段(例如,儘管沒有催化劑也驅動反應),例如藉由在固化製程期間補償更多熱能,來克服來自摻雜劑的催化劑抑制。Ashbys catalysts and others may be essentially unaffected by aluminum-doped precursor formulations. Phosphorus-containing precursor formulations can cause some catalyst inhibition. Catalyst inhibition from dopants can be overcome by non-catalytic means (eg, driving the reaction despite the absence of a catalyst), such as by compensating for more thermal energy during the curing process.
在較佳實施例中,摻雜體積成形(例如,成形裝藥)源材料(例如,p型、低電阻率p型或低電阻率n型)係使用前文列出的專利及公開申請案中所揭示並教示的聚矽碳前驅物配方中之一或多者製成。黏結劑被熱解成SiC以提供硬的且耐久的摻雜成形裝藥源材料。在此成形裝藥源材料中的摻雜劑係固定的。In preferred embodiments, doped volume shaped (eg, shaped charge) source materials (eg, p-type, low resistivity p-type, or low resistivity n-type) are used in the patents and published applications listed above. Made from one or more of the polysilica precursor formulations disclosed and taught. The binder is pyrolyzed into SiC to provide a hard and durable doped shaped charge source material. The dopant in the shaped charge source material is fixed here.
在實施例中,黏結劑係用於製造SiC源材料的相同聚矽碳前驅物,具有或沒有摻雜劑。因此,存在於黏結劑中的摻雜劑的量可為0%至約50%。黏結劑中的摻雜劑可用於調整或微調存在於特定摻雜SiC成形裝藥源材料中的摻雜劑的量。In embodiments, the binder is the same polysilica precursor used to make the SiC source material, with or without dopants. Accordingly, the amount of dopant present in the binder may range from 0% to about 50%. Dopants in the binder can be used to adjust or fine-tune the amount of dopant present in a particular doped SiC shaped charge source material.
應理解,儘管較佳,但是摻雜SiC晶體及晶棒可在不使用成形裝藥的情況下例如直接由摻雜SiC聚合物衍生粉末裝藥或起始材料生長。另外,不太理想的SiC粉末形式(例如,不是由聚合物衍生陶瓷製成的)可用於形成摻雜SiC成形裝藥源材料。It will be appreciated that, although preferred, doped SiC crystals and rods may be grown without the use of shaped charges, such as directly from doped SiC polymer derived powder charges or starting materials. Additionally, less ideal SiC powder forms (eg, not made from polymer-derived ceramics) may be used to form doped SiC shaped charge source materials.
由摻雜液體材料(例如,具有製造摻雜SiC源材料粉末(例如,不是由聚合物衍生陶瓷製成的)所需要的基本上所有構建塊(例如,Si及C及摻雜劑)的前驅物批次)開始的能力在以下方面提供的顯著優點:控制污染,及在摻雜源材料中形成Si、C及摻雜劑的預定比率以控制並影響PVT製程及裝置中的通量形成及晶體生長。部分地基於目前的聚合物衍生p型摻雜SiC在氣相沉積裝置中及生長p型晶體中的效能,亦理論化的是:聚合物衍生SiC不同於非聚合物衍生SiC,及金屬合金、金屬玻璃或兩者在晶體生長製程中的先前使用。因此,晶體生長及純度、晶圓產率及元件產率中的協同益處進一步源自於聚合物衍生陶瓷源材料的個別益處中之一或多者,該等益處包括:體密度、粒度、摻雜SiC的相(β對α)、化學計量、氧含量(極低至無,亦沒有氧化物層)、高(例如,99.999%純的)純度及超高(99.9999%)純度。 摻雜劑材料- 一般而言 A precursor made from a doped liquid material (e.g., having essentially all the building blocks (e.g., Si and C and dopants) required to make a doped SiC source material powder (e.g., not made from a polymer-derived ceramic) The ability to start from batches of materials provides significant advantages in controlling contamination and forming predetermined ratios of Si, C and dopants in doping source materials to control and influence flux formation in PVT processes and devices. Crystal growth. Based in part on the current performance of polymer-derived p-type doped SiC in vapor deposition equipment and growing p-type crystals, it is also theorized that polymer-derived SiC differs from non-polymer-derived SiC, and that metal alloys, Previous use of metallic glasses or both in crystal growth processes. Therefore, synergistic benefits in crystal growth and purity, wafer yield, and device yield further arise from one or more of the individual benefits of the polymer-derived ceramic source material, including: bulk density, particle size, doping Phase (beta versus alpha), stoichiometry, oxygen content (very low to none, no oxide layer), high (e.g., 99.999% pure) and ultra-high (99.9999%) purity of SiC. Dopant Materials - Generally speaking
一般而言,摻雜劑可為可在用於形成SiC源材料的PDC製程(例如,聚矽碳基PDC)中使用且不會干擾PDC製程,在SiC源材料中提供預定的原子雜質(例如,施體原子、受體原子及此等的組合)的任何材料或材料組合,該材料隨後在氣相沉積製程中用於產生具有此等原子雜質的通量且由該通量生長晶體,其中晶體亦具有此等原子雜質作為電活性原子雜質。Generally speaking, the dopant can be one that can be used in a PDC process for forming the SiC source material (e.g., polysilica-based PDC) and does not interfere with the PDC process, providing predetermined atomic impurities in the SiC source material (e.g., polysilica-based PDC). , donor atoms, acceptor atoms, and combinations thereof), which material is subsequently used in a vapor deposition process to generate a flux with such atomic impurities and to grow crystals from the flux, wherein Crystals also have these atomic impurities as electrically active atomic impurities.
對於p型晶體、晶錠、晶棒及晶圓以及p型低電阻率晶體、晶錠、晶棒及晶圓,鋁及硼為較佳的原子雜質,且因此較佳的摻雜劑為可提供此等原子雜質的彼等材料。For p-type crystals, ingots, ingots, and wafers, and for p-type low resistivity crystals, ingots, ingots, and wafers, aluminum and boron are the better atomic impurities, and therefore the better dopants are available Those materials that provide these atomic impurities.
例如在源材料中提供鋁的摻雜劑材料(其隨後可向SiC結晶結構中提供鋁原子電活性雜質)通常為:反應性鋁材料、非反應性鋁材料及純鋁材料。For example, dopant materials that provide aluminum in the source material (which can subsequently provide electroactive impurities of aluminum atoms into the SiC crystal structure) are typically: reactive aluminum materials, non-reactive aluminum materials, and pure aluminum materials.
通常,反應性鋁材料被添加至液體前驅物材料(例如,前驅物配方),然後在固化步驟期間與彼等前驅物材料發生化學反應。反應性鋁材料包括例如: (i) 烷氧化鋁:Al(OR) 3,其中R為烷基或苯基。與聚矽碳前驅物材料的反應通常為:2 Al(OR) 3+ 6 SiH → 2Al-(O-Si~) 3+ 6 RH;(應注意,「~Si」及「Si~」在此等反應中使用時表示附接至諸如聚合物主幹或配體主幹之更大結構的反應性Si官能基,該更大結構在反應中未展示。) (ii) 氫氧化鋁(R為氫)。與聚矽碳前驅物材料的反應通常為:2 Al(OH) 3+ 6 SiH →2Al- (O-Si~) 3+ 3 H 2; (iii) 鋁礬土、三水鋁石、水鋁石、一水硬鋁石。與聚矽碳前驅物材料的反應通常為:經由此等礦物質的氫氧化物官能性,類似於(ii);及 (iv) 三甲基鋁。與聚矽碳前驅物材料的反應通常為:2 (Al(Me) 3) + 3 H 2O → Al 2O 3+ 6 CH 4。 Typically, reactive aluminum materials are added to liquid precursor materials (eg, precursor formulations) and then chemically react with those precursor materials during the curing step. Reactive aluminum materials include, for example: (i) Aluminum alkoxides: Al(OR) 3 , where R is alkyl or phenyl. The reaction with polysilica precursor material is usually: 2 Al(OR) 3 + 6 SiH → 2Al-(O-Si~) 3 + 6 RH; (It should be noted that "~Si" and "Si~" are used here When used in a reaction, it means a reactive Si functional group attached to a larger structure such as a polymer backbone or a ligand backbone that is not shown in the reaction.) (ii) Aluminum hydroxide (R is hydrogen) . The reaction with polysilica precursor materials is usually: 2 Al(OH) 3 + 6 SiH → 2Al- (O-Si~) 3 + 3 H 2 ; (iii) bauxite, gibbsite, allophane stone, diaspore. The reaction with polysilica precursor materials is typically: via the hydroxide functionality of such minerals, similar to (ii); and (iv) trimethylaluminum. The reaction with polysilica precursor material is usually: 2 (Al(Me) 3 ) + 3 H 2 O → Al 2 O 3 + 6 CH 4 .
通常,非反應性鋁材料被添加至液體前驅物材料(例如,「前驅物配方」),但可被添加至固化材料、陶瓷SiOC、SiC源材料,以及此等的組合及變化。非反應性材料在熱解期間由SiOC及SiC陶瓷材料保持或併入至該等材料中。非反應性材料包括例如鋁矽酸鹽材料。此類材料的實例包括:莫來石、藍晶石、矽線石、紅柱石、藍線石及其他島狀矽酸鹽粉末;高嶺石、埃洛石及葉臘石;架狀矽酸鹽(長石);及沸石。Typically, non-reactive aluminum materials are added to liquid precursor materials (eg, "precursor formulations"), but can be added to solidified materials, ceramic SiOC, SiC source materials, and combinations and variations of these. Non-reactive materials are retained by or incorporated into SiOC and SiC ceramic materials during pyrolysis. Non-reactive materials include, for example, aluminosilicate materials. Examples of such materials include: mullite, kyanite, sillimanite, andalusite, kyanite and other island silicate powders; kaolinite, halloysite and pyrophyllite; shelf silicate (feldspar); and zeolite.
通常,純鋁材料被添加至液體前驅物材料(例如,前驅物配方),但可被添加至固化材料、陶瓷SiOC、SiC源材料,以及此等的組合及變化。純鋁材料在熱解期間由SiOC及SiC陶瓷材料保持或併入至該等材料中。純鋁材料包括例如氧化鋁粉末Al 2O 3及剛玉(包括藍寶石、紅寶石等)。 Typically, pure aluminum material is added to liquid precursor materials (eg, precursor formulations), but can be added to solidified materials, ceramic SiOC, SiC source materials, and combinations and variations of these. Pure aluminum material is retained by or incorporated into SiOC and SiC ceramic materials during pyrolysis. Pure aluminum materials include, for example, alumina powder Al 2 O 3 and corundum (including sapphire, ruby, etc.).
所有前述的鋁摻雜劑材料在SiC源材料中例如以陶瓷氧化物的形式而不是作為合金提供鋁。All the aforementioned aluminum dopant materials provide aluminum in the SiC source material, for example in the form of ceramic oxides rather than as alloys.
例如在源材料中提供硼的摻雜劑材料(其隨後可向SiC結晶結構中提供硼原子電活性雜質)通常為:反應性硼材料、非反應性硼材料。For example, dopant materials that provide boron in the source material (which can subsequently provide boron atoms as electroactive impurities into the SiC crystal structure) are generally: reactive boron materials, non-reactive boron materials.
通常,反應性硼材料被添加至液體前驅物材料(例如,前驅物配方(1)),然後在固化步驟期間與彼等前驅物材料發生化學反應。反應性硼材料包括例如: (i) 硼酸B(OH) 3。與聚矽碳前驅物材料的反應通常為:2 B(OH) 3+ 6 SiH → 2B-(O-Si~) 3+ 3 H 2; (ii) 硼砂(Na 2B 4O 7·10H 2O)。與Si O C前驅物材料的反應通常為:縮合反應。 (iii) 硼酸R-B(OH) 2,其中R為烯基,諸如乙烯基。與聚矽碳前驅物材料的反應通常為:縮合反應;及 (iv) 二乙烯基硼酸Vi-B(OH)-Vi。與聚矽碳前驅物材料的反應通常為:B-Vi+ ~SiH → B-C-C-Si~。 Typically, reactive boron materials are added to liquid precursor materials (eg, precursor formulation (1)) and then chemically react with those precursor materials during the curing step. Reactive boron materials include, for example: (i) Boric acid B(OH) 3 . The reaction with polysilica precursor material is usually: 2 B(OH) 3 + 6 SiH → 2B-(O-Si~) 3 + 3 H 2 ; (ii) Borax (Na 2 B 4 O 7 ·10H 2 O). The reaction with Si OC precursor material is usually: condensation reaction. (iii) Boric acid RB(OH) 2 , where R is alkenyl, such as vinyl. The reaction with the polysilica precursor material is usually: condensation reaction; and (iv) divinylboronic acid Vi-B(OH)-Vi. The reaction with polysilica precursor materials is usually: B-Vi+ ~SiH → BCC-Si~.
通常,非反應性硼材料被添加至液體前驅物材料(例如,前驅物配方),但可被添加至固化材料、陶瓷SiOC、SiC源材料,以及此等的組合及變化。非反應性材料在熱解期間由SiOC及SiC陶瓷材料保持或併入至該等材料中。非反應性材料包括例如:硼矽酸鹽玻璃;B 2O 3;碳化硼。 Typically, non-reactive boron materials are added to liquid precursor materials (eg, precursor formulations), but can be added to solidified materials, ceramic SiOC, SiC source materials, and combinations and variations of these. Non-reactive materials are retained by or incorporated into SiOC and SiC ceramic materials during pyrolysis. Non-reactive materials include, for example: borosilicate glass; B2O3 ; boron carbide.
對於n型晶體、晶錠、晶棒及晶圓以及n型低電阻率晶體、晶錠、晶棒及晶圓,氮及磷為較佳的原子雜質,其中磷為特別較佳的原子雜質,且因此較佳的摻雜劑為可提供此等原子雜質的彼等材料。For n-type crystals, crystal ingots, crystal rods and wafers, and n-type low resistivity crystals, crystal ingots, crystal rods and wafers, nitrogen and phosphorus are better atomic impurities, among which phosphorus is a particularly better atomic impurity. And therefore preferred dopants are materials that can provide these atomic impurities.
含氮或提供氮的材料可被添加至液體前驅物材料(例如,前驅物配方)。此等摻雜劑將包括胺類;醯胺類;偶氮及重氮;胺甲酸酯;胺甲酸乙酯;碳醯亞胺;C及N的雜環;尿素;異氰酸酯;作為潛在的候選官能基併入。尼龍或其他含N的碳基聚合物亦可被添加至配方以在熱解期間發生反應。然而,應注意,添加太大量的氮會向晶體引入不合意的應力、疊差及相關缺陷。Nitrogen-containing or nitrogen-providing materials may be added to the liquid precursor material (eg, precursor formulation). Such dopants would include amines; amides; azo and diazo; urethane; urethane; carboimide; C and N heterocycles; urea; isocyanate; as potential candidates Functional groups are incorporated. Nylon or other N-containing carbon-based polymers may also be added to the formulation to react during pyrolysis. However, it should be noted that adding too much nitrogen can introduce undesirable stresses, stacking, and related defects into the crystal.
通常,反應性磷材料被添加至液體前驅物材料(例如,前驅物配方),然後在固化步驟期間與彼等前驅物材料發生化學反應。反應性磷材料包括例如:Typically, reactive phosphorus materials are added to liquid precursor materials (eg, precursor formulations) and then chemically react with those precursor materials during the curing step. Reactive phosphorus materials include, for example:
(i) P的反應性氧化物,諸如(R) 3-膦氧化物(R= 烷基、苯基、苯乙烯基),包括以下展示的三苯膦氧化物 及以下展示的五氧化二磷。 聚矽碳前驅物材料與此等摻雜劑的反應通常為: R 3-P=O* + ~Si-H → ~Si-O-P-R 3 (i) Reactive oxides of P, such as (R) 3 -phosphine oxides (R = alkyl, phenyl, styryl), including triphenylphosphine oxides shown below and phosphorus pentoxide shown below. The reaction of polysilica precursor materials with these dopants is usually: R 3 -P=O* + ~Si-H → ~Si-OPR 3
(ii) 反應性有機膦,諸如(R1) n- (R2) 3-n有機膦(其中R1=烯基、苯乙烯基,且R2= 烷基、苯基)。例如,以下展示的二苯基乙烯基膦 以下展示的二乙烯基苯基膦 以下展示的二苯基苯乙烯基膦 以下展示的三烯丙基膦,它係其中n=3的材料的實例 聚矽碳前驅物材料與此等摻雜劑的反應通常為: R 3-P-C=C + ~Si-H → ~Si-C-C-P-R 3 (ii) Reactive organophosphines, such as (R1) n - (R2) 3-n organophosphines (where R1 = alkenyl, styryl and R2 = alkyl, phenyl). For example, diphenylvinylphosphine shown below Divinylphenylphosphine shown below Diphenylstyrylphosphine shown below Triallylphosphine shown below is an example of a material where n=3 The reaction of the polysilica precursor material with these dopants is usually: R 3 -PC=C + ~Si-H → ~Si-CCPR 3
(iii) 膦,包括PH 3、PCl 3、PF 3及PBr 3。聚矽碳前驅物材料與此等摻雜劑的反應通常為: PX 3+ 3 -SiH → P-(Si~) 3+ 3 HX,其中X為鹵素或氫 (iii) Phosphines, including PH 3 , PCl 3 , PF 3 and PBr 3 . The reaction of polysilica precursor materials with these dopants is usually: PX 3 + 3 -SiH → P-(Si~) 3 + 3 HX, where X is halogen or hydrogen
(iv) 酸,包括磷酸(H 3PO 4);聚磷酸(CAS# 8017-16-1);聚磷酸銨(CAS# 68333-79-9);P(OR) 3,其中R為任何烷基或苯基或氫;O=P(OR)3,其中R為任何烷基或苯基或氫;以下展示的亞磷酸三異丙酯 (iv) Acids, including phosphoric acid (H 3 PO 4 ); polyphosphoric acid (CAS# 8017-16-1); ammonium polyphosphate (CAS# 68333-79-9); P(OR) 3 , where R is any alkane alkyl or phenyl or hydrogen; O=P(OR)3, where R is any alkyl or phenyl or hydrogen; triisopropyl phosphite shown below
以下展示的磷酸三異丙酯Triisopropyl phosphate shown below
聚矽碳前驅物材料與此等摻雜劑的反應通常為:The reaction of polysilica precursor materials with these dopants is usually:
2(OH) 3P=O + 6~Si-H → 2 (~Si-O) 3-P=O +3 H 2 2(OH) 3 P=O + 6~Si-H → 2 (~Si-O) 3 -P=O +3 H 2
通常,非反應性磷材料被添加至液體前驅物材料(例如,前驅物配方),但可被添加至固化材料、陶瓷SiOC、SiC源材料,以及此等的組合及變化。非反應性材料在熱解期間由SiOC及SiC陶瓷材料保持或併入至該等材料中。非反應性材料包括例如:磷酸鹽化合物,諸如以下展示的Typically, non-reactive phosphorus materials are added to liquid precursor materials (eg, precursor formulations), but can be added to solidified materials, ceramic SiOC, SiC source materials, and combinations and variations of these. Non-reactive materials are retained by or incorporated into SiOC and SiC ceramic materials during pyrolysis. Non-reactive materials include, for example: phosphate compounds such as those shown below
其中M+為鈉、鉀、鈣、鋰、銨等。Among them, M+ is sodium, potassium, calcium, lithium, ammonium, etc.
以下展示的五氧化二磷Phosphorus pentoxide shown below
諸如來自Apatitie族的磷酸鹽礦物質(Ca 5(PO 4) 3R,其中R為F、Cl或OH), Phosphate minerals such as (Ca 5 (PO 4 ) 3 R, where R is F, Cl or OH) from the Apatitie family,
亦可使用包含N及P兩者的無機摻雜劑。此等被添加至液體前驅物材料(例如,前驅物配方(1)),但可被添加至固化材料、陶瓷SiOC、SiC源材料,以及此等的組合及變化。無機材料在熱解期間由SiOC及SiC陶瓷材料保持或併入至該等材料中。此等材料提供共摻雜能力,從而自單一摻雜劑來源提供N及P兩者。共摻雜劑包括例如鳥糞石((NH 4)MgPO 4• 8H 2O)、材料的磷氮化物基團、五氮化三磷(P 3N 5), Inorganic dopants containing both N and P may also be used. These are added to liquid precursor materials (eg, precursor formulation (1)), but can be added to solidified materials, ceramic SiOC, SiC source materials, and combinations and variations of these. Inorganic materials are retained by or incorporated into SiOC and SiC ceramic materials during pyrolysis. These materials provide co-doping capabilities, providing both N and P from a single dopant source. Co-dopants include, for example, struvite ((NH 4 )MgPO 4 • 8H 2 O), phosphorus nitride groups of the material, phosphorus pentanitride (P 3 N 5 ),
其他共摻雜劑(N及P的來源)為環磷腈化合物、聚磷腈化合物及六氯環三磷腈化合物。此等共摻雜劑被添加至液體前驅物(例如,前驅物配方),然後在固化步驟、熱解步驟或這兩個步驟期間與彼等前驅物材料發生化學反應。Other co-dopants (sources of N and P) are cyclophosphazene compounds, polyphosphazene compounds and hexachlorocyclotriphosphazene compounds. These co-dopants are added to a liquid precursor (eg, precursor formulation) and then chemically react with the precursor materials during the curing step, the pyrolysis step, or both steps.
另外,如先前所述,前述摻雜劑中之任一者可被添加至用於形成摻雜SiC成形裝藥源材料的黏結劑。Additionally, as previously described, any of the aforementioned dopants may be added to the binder used to form the doped SiC shaped charge source material.
摻雜劑可以約1%、約2%、約2.5%、約5%、約2%至約10%、約1%至約10%、小於15%、小於10%、小於8%及約2%至約8%的重量百分比被添加至前驅物配方。摻雜劑可以約1%、約1%至約10%、約2%、約2.5%、約5%、約2%至約10%、小於15%、小於10%及小於8%及約2%至約8%的重量百分比被添加至黏結劑。The dopant may be about 1%, about 2%, about 2.5%, about 5%, about 2% to about 10%, about 1% to about 10%, less than 15%, less than 10%, less than 8%, and about 2 % to about 8% by weight is added to the precursor formulation. The dopant may be about 1%, about 1% to about 10%, about 2%, about 2.5%, about 5%, about 2% to about 10%, less than 15%, less than 10% and less than 8% and about 2 % to about 8% by weight is added to the binder.
在固化步驟及每一熱解期間將存在一些材料損耗,例如,產率損耗。此等產率損耗將包括摻雜劑材料的損耗。因此,應添加足夠量的摻雜劑以考慮到此等產率損耗,以提供在通量形成及晶體生長中使用的SiC來源中所需的摻雜劑原子的量。 摻雜晶體生長- 一般而言 There will be some material loss during the curing step and during each pyrolysis, for example, yield loss. These yield losses will include losses of dopant material. Therefore, a sufficient amount of dopant should be added to account for these yield losses to provide the required amount of dopant atoms in the SiC source used in flux formation and crystal growth. Doped crystal growth - in general
碳化矽通常不具有液相,而是在真空下、在高於約1,700℃至1,800℃的溫度下昇華。通常,在工業及商業應用中,建立條件以便在約2,500℃及以上的溫度下發生昇華。當碳化矽昇華時,它通常形成由若干不同的矽及碳物質組成的蒸氣。通常,應理解,源材料(例如,成形裝藥)的組合物及形式、溫度及壓力決定了碳化矽蒸氣中的氣相組分的比率。Silicon carbide generally does not have a liquid phase but sublimates under vacuum at temperatures above about 1,700°C to 1,800°C. Typically, in industrial and commercial applications, conditions are established so that sublimation occurs at temperatures of about 2,500°C and above. When silicon carbide sublimates, it typically forms a vapor composed of several different silicon and carbon species. In general, it is understood that the composition and form of the source material (eg, shaped charge), temperature, and pressure determine the ratio of gas phase components in the silicon carbide vapor.
除其他事項外,本發明提供用於預先判定、預先選擇並控制摻雜劑(例如,意欲向SiC晶圓提供特定的預定性質的添加劑、元素、化合物)在SiOC源材料中的存在,該等摻雜劑隨後存在於SiC源材料(例如,在氣相沉積晶體生長製程中使用的粉末)中。Among other things, the present invention provides for predetermining, preselecting, and controlling the presence of dopants (e.g., additives, elements, compounds intended to provide specific predetermined properties to SiC wafers) in SiOC source materials, which The dopant is then present in the SiC source material (eg, the powder used in the vapor deposition crystal growth process).
當碳化矽昇華時,它通常形成由若干矽及碳物質(例如,Si、C、SiC、Si 2C及SiC 2)組成的蒸氣。 When silicon carbide sublimates, it typically forms a vapor composed of several silicon and carbon species (eg, Si, C, SiC, Si2C , and SiC2 ).
一般而言,為了生長目前的p型晶體、低電阻率p型晶體及低電阻率n型晶體,本發明使用此項技術中已很好地理解且已知的PVT方法及裝置(例如,美國專利第4.866,005號,該案的全部揭示內容以引用的方式併入本文中)。在昇華晶體生長期間,通常使由矽及碳或SiC粉末組成的元素源昇華以產生Si及C原子的蒸氣通量,該蒸氣通量隨後在種晶上凝結且最終形成更大的晶體。為了控制SiC晶體的電氣性質(例如,電阻率/導電率),將雜質原子添加至蒸氣流中,其中雜質原子將與矽及碳原子一起併入至晶體中。雜質至晶體中的併入受晶種溫度、壓力、晶種面(矽或碳)及蒸氣流中的碳-矽原子比的影響。蒸氣流中的碳-矽比與源材料、來源處的溫度及壓力的設計有關。Generally speaking, in order to grow current p-type crystals, low resistivity p-type crystals and low resistivity n-type crystals, the present invention uses PVT methods and equipment that are well understood and known in the art (e.g., the United States No. 4.866,005, the entire disclosure of which is incorporated herein by reference). During sublimation crystal growth, an elemental source consisting of silicon and carbon or SiC powder is typically sublimated to produce a vapor flux of Si and C atoms that subsequently condenses on the seed crystal and ultimately forms larger crystals. To control the electrical properties (eg, resistivity/conductivity) of the SiC crystal, impurity atoms are added to the vapor stream where they are incorporated into the crystal along with the silicon and carbon atoms. The incorporation of impurities into the crystal is affected by the seed temperature, pressure, seed face (silicon or carbon), and the carbon-to-silicon atomic ratio in the vapor stream. The carbon-to-silicon ratio in the vapor stream is related to the design of the source material, temperature and pressure at the source.
矽及鋁具有類似的原子大小,且因此鋁雜質原子將主要位於晶體中的矽位置處(作為電活性原子雜質),或位於填隙型位置處。為了提高鋁原子位於矽位點處的可能性,需要帶有過量碳的蒸氣流。Silicon and aluminum have similar atomic sizes, and therefore the aluminum impurity atoms will be located primarily at silicon sites in the crystal (as electroactive atomic impurities), or at interstitial sites. To increase the likelihood of aluminum atoms being located at silicon sites, a vapor flow with an excess of carbon is required.
在使用先前非PDC源材料的SiC的典型昇華生長中,蒸氣流通常具有比碳多的矽。因此,鋁原子必須與矽原子競爭來佔據矽位點。基於無機來源(諸如矽金屬、石墨或SiC磨料來源)的SiC昇華生長的此種特性導致難以在晶體中併入足夠的鋁,因此自晶體切割的晶圓的導電率對於半導體元件製造係有用的。In typical sublimation growth of SiC using previously non-PDC source materials, the vapor stream typically has more silicon than carbon. Therefore, aluminum atoms must compete with silicon atoms to occupy silicon sites. This characteristic of SiC sublimation growth based on inorganic sources (such as silicon metal, graphite or SiC abrasive sources) makes it difficult to incorporate sufficient aluminum into the crystal, so the conductivity of wafers cut from the crystal is useful for semiconductor component manufacturing. .
除其他事項外,本發明之實施例藉由有能力具有帶有過量碳的源材料,以及使摻雜劑併入至源材料中且由源材料保持了克服此問題。因此,此等摻雜PDC源材料可出乎意料地提供較佳的通量條件以便在SiC晶體中高效地併入p型摻雜劑。這繼而增強p型晶體的電氣性質,且使得自此晶體切割的晶圓能夠係有用的、具有更高的品質及優異的電氣性質、且特定而言對於半導體元件製造係商業上有用的。Embodiments of the present invention overcome this problem by, among other things, having the ability to have source materials with excess carbon, and having dopants incorporated into and retained by the source materials. Therefore, such doped PDC source materials can unexpectedly provide better flux conditions for efficient incorporation of p-type dopants into SiC crystals. This in turn enhances the electrical properties of the p-type crystal, and enables wafers cut from this crystal to be useful, of higher quality and with excellent electrical properties, and in particular commercially useful for semiconductor device manufacturing.
在實施例中,源自於PDC成形裝藥源材料的使用的出乎意料的地方在於,它們影響並控制通量的Si/C比的能力提供了產生更有可能增強當在晶體的C面上生長時p型摻雜劑原子雜質至晶體中的併入之Si/C比的能力。雖然在晶種處的通量中的Si/C比可隨時間減小,但是它不可能下降至值1以下,而p型摻雜劑併入的增強仍然發生。因此,目前的成形裝藥源材料的實施例提供了在PVT製程中使用C或Si面晶種生長p型SiC晶體的能力。特定而言,p型晶體可生長於C或Si面4H或6H晶種上。In the embodiments, what is unexpected about the use of PDC shaped charge source materials is that their ability to influence and control the Si/C ratio of the flux provides the possibility of producing enhancements that are more likely to occur when at the C-plane of the crystal. The ability of the Si/C ratio to incorporate p-type dopant atomic impurities into the crystal during growth. Although the Si/C ratio in the flux at the seed can decrease with time, it cannot drop below a value of 1 while enhancement of p-type dopant incorporation still occurs. Therefore, current embodiments of shaped charge source materials provide the ability to grow p-type SiC crystals using C or Si face seeds in PVT processes. Specifically, p-type crystals can be grown on C or Si plane 4H or 6H seeds.
晶棒之較佳實施例為單晶體且僅具有單個多型體。應理解,本說明書亦設想了具有多個多型體、具有多個晶體及兩者的晶棒之實施例。Preferred embodiments of the ingot are single crystals and have only a single polytype. It should be understood that this specification also contemplates embodiments of ingots having multiple polytypes, having multiple crystals, and both.
在實施例中,液體PDC起始材料,較佳地聚矽碳前驅物,且更佳地液體聚矽碳前驅物,具有添加至它們的或包含(例如,化學鍵結的、化學錯合物、在溶液中、在聚合物的主幹中、在混合物中,等等)預定摻雜劑,以向SiC晶體提供預定性質。In embodiments, liquid PDC starting materials, preferably polysilica precursors, and more preferably liquid polysilica precursors, have added to them or comprise (e.g., chemically bonded, chemical complexes, Dopants are predetermined (in solution, in the backbone of the polymer, in a mixture, etc.) to provide predetermined properties to the SiC crystal.
雖然較佳地使摻雜劑存在於液體起始材料中,但是亦可將摻雜劑添加至固化的SiOC材料、陶瓷SiOC材料及成形裝藥(例如,與之組合或混合)。在諸如氮的一些情形中,亦可在SiC晶體生長製程期間作為氣體添加摻雜劑。Although it is preferred that the dopant be present in the liquid starting material, the dopant may also be added to (eg, combined or mixed with) the cured SiOC material, the ceramic SiOC material, and the shaped charge. In some cases, such as nitrogen, dopants may also be added as a gas during the SiC crystal growth process.
摻雜劑可為單種材料,例如元素,或者摻雜劑可為通常選自週期表中的同一欄的兩種、三種或更多種元素。人們相信,使用來自週期表中的同一欄(且因此具有類似的電子價結構、但略有不同的大小)的不同材料的組合減小了SiC晶體中的應力。這繼而提供了更好的、高品質、更有用的晶棒及晶圓。The dopant may be a single material, such as an element, or the dopant may be two, three or more elements, typically selected from the same column in the periodic table. It is believed that using a combination of different materials from the same column in the periodic table (and therefore having similar electron valence structures, but slightly different sizes) reduces stress in the SiC crystal. This in turn provides better, higher quality, more useful ingots and wafers.
用於製造p型SiC晶體、晶棒及晶圓的較佳摻雜劑為選自第13族的元素(硼等)。用於製造p型SiC晶體、晶棒及晶圓的較佳摻雜劑為鋁。Preferred dopants for manufacturing p-type SiC crystals, rods and wafers are elements selected from Group 13 (boron, etc.). The preferred dopant for manufacturing p-type SiC crystals, ingots and wafers is aluminum.
用於製造n型SiC晶體、晶棒及晶圓的較佳摻雜劑為選自第15族的元素(氮等)。用於製造n型SiC晶體、晶棒及晶圓的較佳摻雜劑為氮、磷及此等的組合。Preferred dopants for manufacturing n-type SiC crystals, rods and wafers are elements selected from Group 15 (nitrogen, etc.). Preferred dopants for making n-type SiC crystals, rods, and wafers are nitrogen, phosphorus, and combinations thereof.
使用磷及氮與磷的組合作為摻雜劑(較佳地在液體聚矽碳起始材料中)提供了具有低電阻率SiC晶圓的能力。The use of phosphorus and combinations of nitrogen and phosphorus as dopants (preferably in the liquid polysilica starting material) provides the ability to have low resistivity SiC wafers.
在摻雜晶體(例如,p型、低電阻率p型、低電阻率n型)之較不佳的實施例中,摻雜劑在晶體的長度上並不均勻。在此實施例中,摻雜劑(作為電活性原子雜質)的濃度自晶種底部(晶體生長開始的一側)至尾部頂側(生長結束的一側)變化,其中此變化且可跨晶體的直徑徑向變化在約300%至5%的範圍內。In less favorable embodiments of doped crystals (eg, p-type, low resistivity p-type, low resistivity n-type), the dopants are not uniform across the length of the crystal. In this embodiment, the concentration of the dopant (which is an electrically active atomic impurity) varies from the bottom of the seed (the side where crystal growth begins) to the top of the tail (the side where growth ends), where this variation can occur across the crystal. The radial variation in diameter ranges from approximately 300% to 5%.
在較佳實施例中,摻雜成形裝藥源材料的實施例的使用將針對尾部至晶種(即,晶體的長度或高度)及徑向(跨晶體的直徑)兩者的此等變化減小為約100%至5%、小於200%、小於150%、小於100%、小於50%及小於25%及小於105。變化的此種減小可進一步以一致的方式獲得,其中在PVT裝置中生長的大部分且基本上所有(即,大於90%)的晶體具有相同的更低變化。In preferred embodiments, the use of embodiments of doped shaped charge source materials will reduce these variations both tail-to-seed (i.e., the length or height of the crystal) and radially (across the diameter of the crystal). Small is about 100% to 5%, less than 200%, less than 150%, less than 100%, less than 50% and less than 25% and less than 105. This reduction in variation can further be achieved in a consistent manner, with most and substantially all (ie, greater than 90%) of the crystals grown in the PVT device having the same lower variation.
在實施例中,摻雜SiC晶體(例如,p型、低電阻率p型、低電阻率n型)具有摻雜劑貫穿晶體結構的基本上均勻的分佈,此係藉由使用預定的摻雜成形裝藥源材料獲得,該摻雜成形裝藥源材料具有以提供摻雜劑至晶體中的併入的均勻性的方式分佈在成形裝藥中的摻雜劑。因此,晶體、晶錠、晶棒或晶圓之實施例中的摻雜劑濃度或電活性原子雜質濃度跨長度(例如,尾部側至晶種側(「頂部至底部」))及徑向(如沿著直徑移動時側對側量測的(「側對側」))的變化小於約10%、小於約5%及小於約2%及小於1%。因此,此等結晶材料的整體表現出預期的電氣性質且達到相同的程度(例如,p型電氣行為、p型低電阻率電氣行為、n型低電阻率電氣行為)且達到相同的程度。這允許晶體(例如,晶棒)轉換成SiC晶圓,其中預期的電氣行為貫穿整個晶圓,且特定而言貫穿晶圓的厚度存在。具有貫穿材料基本上均勻地分佈(即,如上文所描述,頂部至底部、側對側的小於10%的變化)的摻雜劑或電活性雜質的此等材料在本文中將被稱為「均勻的」或「均勻地」摻雜的SiC晶圓、晶錠、晶體或晶棒。In embodiments, doped SiC crystals (eg, p-type, low resistivity p-type, low resistivity n-type) have a substantially uniform distribution of dopants throughout the crystal structure by using predetermined doping A shaped charge source material is obtained that has a dopant distributed in the shaped charge in a manner that provides uniformity of incorporation of the dopant into the crystal. Accordingly, dopant concentrations or electroactive atomic impurity concentrations in embodiments of a crystal, ingot, ingot, or wafer span the length (e.g., tail side to seed side ("top to bottom")) and radial direction ( For example, the variation measured side-to-side ("side-to-side") when moving along the diameter is less than about 10%, less than about 5%, less than about 2%, and less than 1%. Accordingly, such crystalline materials as a whole exhibit expected electrical properties to the same extent (eg, p-type electrical behavior, p-type low resistivity electrical behavior, n-type low resistivity electrical behavior) to the same extent. This allows a crystal (eg, a rod) to be converted into a SiC wafer in which the expected electrical behavior exists throughout the entire wafer, and specifically throughout the thickness of the wafer. Such materials having dopants or electrically active impurities that are substantially uniformly distributed throughout the material (i.e., less than 10% variation top to bottom, side to side, as described above) will be referred to herein as " Uniformly or uniformly doped SiC wafers, ingots, crystals or rods.
因此,在實施例中,p型SiC晶圓不具有任何n型材料層。另外,在較佳實施例中,此p型SiC晶圓(以及p型晶體及p型晶棒)具有貫穿整個晶圓(以及p型晶體及p型晶棒),且特定而言貫穿晶圓的厚度分佈的電活性施體原子。另外,在較佳實施例中,此p型SiC晶圓(以及p型晶體及p型晶棒)具有貫穿整個晶圓(以及p型晶體及p型晶棒),且特定而言貫穿晶圓的厚度分佈的電活性原子雜質。具有貫穿材料基本上均勻地分佈(即,如上文所大體描述,頂部至底部、側對側的小於10%的變化)的摻雜劑或電活性雜質的此等材料在本文中將被稱為「均勻的p型SiC」晶圓、晶錠、晶體或晶棒。此等均勻的p型SiC晶體、晶錠、晶棒及晶圓亦包括p+及p-型。Therefore, in embodiments, the p-type SiC wafer does not have any n-type material layer. In addition, in a preferred embodiment, the p-type SiC wafer (and p-type crystal and p-type ingot) has a structure that penetrates the entire wafer (and p-type crystal and p-type ingot), and specifically through the wafer Thickness distribution of electroactive donor atoms. In addition, in a preferred embodiment, the p-type SiC wafer (and p-type crystal and p-type ingot) has a structure that penetrates the entire wafer (and p-type crystal and p-type ingot), and specifically through the wafer The thickness distribution of electroactive atomic impurities. Such materials having dopants or electroactive impurities distributed substantially uniformly throughout the material (i.e., less than 10% variation top to bottom, side to side, as generally described above) will be referred to herein as "Uniform p-type SiC" wafer, ingot, crystal or rod. These uniform p-type SiC crystals, ingots, rods and wafers also include p+ and p- types.
低電阻率SiC晶圓可為n型及p型。較佳地,對於n型低電阻率SiC晶圓,摻雜劑為磷或磷與氮的混合物。較佳地,低電阻率晶體、晶錠、晶棒及晶圓中的摻雜劑貫穿晶體基質分佈,具有小於100%、小於50%、小於25%的變化,且更佳地為均勻的低電阻率SiC材料。Low resistivity SiC wafers can be n-type or p-type. Preferably, for n-type low resistivity SiC wafers, the dopant is phosphorus or a mixture of phosphorus and nitrogen. Preferably, the dopants in low-resistivity crystals, crystal ingots, crystal rods and wafers are distributed throughout the crystal matrix with changes of less than 100%, less than 50%, and less than 25%, and more preferably are uniformly low. Resistivity SiC material.
本發明提供了用於生長晶棒的方法及製程的實施例,例如,用於形成p型SiC或低電阻率p型或n型SiC的單晶體晶棒的SiC氣相沉積,該SiC氣相沉積在晶棒的面處提供非常平坦,例如,具有有限量的曲率或弧度。晶棒的非常平坦的輪廓主要係藉由使用置放於氣相沉積裝置中的SiC圓片的預先選擇的形狀來達成。預先選擇的形狀(例如,成形裝藥)經組態以使得在氣相沉積製程期間,通量的區域及該區域內的流量在整個晶棒生長製程內保持恆定。以此方式,在晶棒生長時沉積於晶棒的面上的SiC的速率及量在晶棒生長製程期間保持一致且均勻。因此,例如在生長6吋直徑的晶棒時,通量流的區域將為28.27吋 2,且跨該區域流動的SiC的流率及量在晶棒(例如,3吋長度的晶棒、4吋長度的晶棒等)的生長期間跨該整個區域將係均勻的。即使當可用於昇華的SiC的量及位置在圓片內、在製程期間變化時,圓片的形狀以保持通量流跨緊鄰晶棒的面之區域為均勻的方式引導通量(例如,「定向通量」)。用於生長SiC晶體的成形裝藥及裝藥用途在美國專利公開案第2018/0290893號中揭示並教示,該案的全部揭示內容以引用的方式併入本文中。 The present invention provides examples of methods and processes for growing crystal ingots, such as SiC vapor deposition for forming single crystal ingots of p-type SiC or low resistivity p-type or n-type SiC. The SiC vapor deposition Providing a very flat surface at the face of the crystal rod, for example, with a limited amount of curvature or camber. The very flat profile of the ingot is mainly achieved by using a pre-selected shape of the SiC wafer placed in the vapor deposition apparatus. The preselected shape (eg, shaped charge) is configured such that during the vapor deposition process, the area of flux and the flow rate within the area remain constant throughout the ingot growth process. In this manner, the rate and amount of SiC deposited on the face of the ingot as the ingot grows remains consistent and uniform during the ingot growth process. Therefore, for example, when growing a 6-inch diameter ingot, the area of flux flow would be 28.27 inches , and the flow rate and amount of SiC flowing across this area would be different from that of the ingot (e.g., a 3-inch length ingot, 4 inch length ingot, etc.) will be uniform across the entire area. Even when the amount and location of SiC available for sublimation changes within the wafer during the process, the shape of the wafer directs the flux in a manner that keeps the flux flow uniform across the area immediately adjacent to the face of the ingot (e.g., ""Directedflux"). Shaped charges for growing SiC crystals and their uses are disclosed and taught in U.S. Patent Publication No. 2018/0290893, the entire disclosure of which is incorporated herein by reference.
在實施例中,通量貫穿生長製程並未保持恆定。因此,在此實施例中,管理(例如,以預定方式控制)通量跨生長面的速率、分佈以提供晶棒的區或生長面的預定生長。因此,例如,在後期生長階段中,可以預定方式引導通量以補償已在晶棒生長中發生的不均勻性。在此實例中,在早期生長階段中通量更大的區域在後期生長階段中具有更小的通量;類似地,在早期生長階段中通量更小的區域在後期生長階段中具有更大的通量。以此方式,最終的晶棒生長面使晶棒面的曲率最小化,或者使晶棒面的曲率半徑最大化。In embodiments, the flux does not remain constant throughout the growth process. Thus, in this embodiment, the rate, distribution of flux across the growth surface is managed (eg, controlled in a predetermined manner) to provide predetermined growth of a region or growth surface of the ingot. Thus, for example, in later growth stages, the flux can be directed in a predetermined manner to compensate for inhomogeneities that have occurred in the ingot growth. In this example, areas with greater flux in early growth stages have smaller fluxes in later growth stages; similarly, areas with smaller flux in early growth stages have greater flux in later growth stages. of flux. In this way, the final crystal rod growth surface minimizes the curvature of the crystal rod face, or maximizes the radius of curvature of the crystal rod face.
在實施例中,使用受控通量、且更佳地方向通量可提供4至8吋直徑的p型SiC或低電阻率SiC晶棒,該晶棒具有由在定向在晶種端上方時具有正曲率半徑的尾端界定的特徵形狀。對於具有4至8吋直徑的SiC晶體,該半徑的範圍通常為10至200吋。In embodiments, the use of controlled flux, and more preferably directional flux, can provide a 4 to 8 inch diameter p-type SiC or low resistivity SiC ingot that has the characteristics of when oriented over the seed end. A characteristic shape defined by a tail end with a positive radius of curvature. For SiC crystals with diameters of 4 to 8 inches, this radius typically ranges from 10 to 200 inches.
在實施例中,尾部的曲率半徑(即,曲率的倒數)可為至少約6吋、至少約8吋、至少約20吋、至少約60吋,及接近無限(即,平面),以及在此等值的範圍內的所有值。在6吋晶棒的實施例中,曲率半徑(即,曲率的倒數)將為至少約10吋、至少約15吋、至少約25吋、至少約60吋,及接近無限(即,平面),以及在此等值的範圍內的所有值。在實施例中,晶棒面的曲率半徑為晶棒長度的至少2倍、晶棒長度的至少5倍、晶棒長度的至少10倍及晶棒長度的至少25倍、高達且包括晶棒面為平面的情況,以及在此範圍內的所有值。In embodiments, the radius of curvature (i.e., the reciprocal of the curvature) of the tail can be at least about 6 inches, at least about 8 inches, at least about 20 inches, at least about 60 inches, and approaching infinity (i.e., planar), and where All values within the range of equivalent values. In the embodiment of a 6-inch ingot, the radius of curvature (i.e., the reciprocal of curvature) will be at least about 10 inches, at least about 15 inches, at least about 25 inches, at least about 60 inches, and close to infinity (i.e., planar), and all values within this range of equivalent values. In an embodiment, the radius of curvature of the crystal rod face is at least 2 times the crystal rod length, at least 5 times the crystal rod length, at least 10 times the crystal rod length, and at least 25 times the crystal rod length, up to and including the crystal rod face. for the flat case, and all values within this range.
在實施例中,除了PDC源材料的組合物及構成之外,可利用壓力以及溫度來操縱通量。對於給定的生長溫度,可藉由增大室壓力來減緩生長。最快的速率通常在「全」真空下(例如,真空泵開啟且保持室壓力儘可能低)。因此,舉例而言,為了在400 μm/hr下生長晶棒,生長可在溫度T1下、全真空的P1下,或者可在溫度T2>T1下,具有幾毫巴至幾十毫巴的氬氣分壓(P2>P1)。以此方式,可「調整」通量及生長速率。 In embodiments, in addition to the composition and composition of the PDC source material, pressure and temperature may be utilized to manipulate flux. For a given growth temperature, growth can be slowed by increasing chamber pressure. The fastest rates are usually at "full" vacuum (i.e., the vacuum pump is on and the chamber pressure is kept as low as possible). Therefore, for example, to grow a crystal rod at 400 μm /hr, the growth can be at temperature T1, P1 in full vacuum, or can be at temperature T2>T1, with a few millibars to tens of millibars. Argon partial pressure (P2>P1). In this way, the flux and growth rate can be "tuned".
在實施例中,由於隨時間流逝更一致的通量組合物,聚合物衍生摻雜SiC在p型SiC或低電阻率SiC晶棒中給予更好的多型體穩定性。此實施例,即受控的多型體穩定性,對於晶棒製造商係有價值且重要的,因為多型體變換中期生長意謂晶棒的僅一部分為原始多型體,這通常對影響由此構建的晶片的元件效能的電子性質有不利的影響。In embodiments, polymer-derived doped SiC gives better polytype stability in p-type SiC or low resistivity SiC ingots due to more consistent flux composition over time. This embodiment, i.e., controlled polytype stability, is valuable and important to the ingot manufacturer because the polytype transformation mid-growth means that only a portion of the ingot is the original polytype, which usually affects The electronic properties of the device performance of the thus constructed wafers are adversely affected.
轉至第4圖,展示了用於生長p型、或者低電阻率p型或n型SiC晶體及結晶結構的裝置之示意性橫截面表示。氣相沉積裝置及製程,且特定而言用於使用PDC SiC源材料的PVT裝置及製程在美國專利第10,753,010號及公開專利申請案第2018/0290893號中揭示並教示,其中每一者的全部揭示內容以引用的方式併入本文中。氣相沉積元件1800係具有側壁1808、底部或底部壁1809及頂部或頂部壁1810的容器。壁1808、1809、1810可具有埠1806/1807/1805,該等埠可為可控制或允許進入及離開元件1800的氣流的開口、噴嘴、閥。元件1800具有與之相關聯的加熱元件1804。加熱元件可經組態及操作以在元件1800內部提供單個溫度區或多個溫度區。在元件1800內部存在成形裝藥1801,該成形裝藥由已經共同形成為摻雜SiC體積形狀的摻雜SiC粒子製成(注意,在實施例中,摻雜劑可併入至用於製造SiC體積形狀的黏結劑中或者為黏結劑的一部分)。Turning to Figure 4, a schematic cross-sectional representation of an apparatus for growing p-type, or low resistivity p-type or n-type SiC crystals and crystallographic structures is shown. Vapor deposition apparatus and processes, and specifically PVT apparatus and processes for use with PDC SiC source materials, are disclosed and taught in U.S. Patent No. 10,753,010 and Published Patent Application No. 2018/0290893, the entirety of each of which The disclosure is incorporated herein by reference. Vapor deposition element 1800 is a vessel having side walls 1808, a bottom or bottom wall 1809, and a top or top wall 1810. Walls 1808, 1809, 1810 may have ports 1806/1807/1805, which may be openings, nozzles, valves that may control or allow airflow into and out of element 1800. Element 1800 has associated therewith a heating element 1804 . The heating element may be configured and operated to provide a single temperature zone or multiple temperature zones within element 1800. Inside element 1800 there is a shaped charge 1801 made from doped SiC particles that have been collectively formed into the shape of a doped SiC volume (note that in embodiments, dopants may be incorporated into the doped materials used to make the SiC volumetric shape of the adhesive or as part of the adhesive).
成形裝藥1801可具有預定的孔隙度及密度。SiC粒子可具有預定的孔隙度及密度。SiC粒子較佳地由黏結劑保持在一起。成形裝藥1801可為富碳的、碳不足的或化學計量的。成形裝藥1801可具有為富碳的、碳不足的或化學計量的區或層。較佳地,SiC粒子為SiOC聚合物衍生SiC。非聚合物衍生SiC亦可用作成形裝藥的一部分或全部。成形裝藥1801具有由箭頭1821展示的高度,及橫截面或直徑1820。成形裝藥1801具有上表面或頂部表面1823及底部表面1824。在此實施例中,成形裝藥1801被展示為平頂及平底圓柱體;應理解,可在元件1800中使用本說明書所設想的體積形狀中之任一者。The shaped charge 1801 may have a predetermined porosity and density. SiC particles can have predetermined porosity and density. The SiC particles are preferably held together by a binder. The shaped charge 1801 may be carbon rich, carbon poor, or stoichiometric. The shaped charge 1801 may have regions or layers that are carbon rich, carbon poor, or stoichiometric. Preferably, the SiC particles are SiOC polymer-derived SiC. Non-polymer derived SiC can also be used as part or all of the shaped charge. The shaped charge 1801 has a height shown by arrow 1821, and a cross-section or diameter 1820. The shaped charge 1801 has an upper or top surface 1823 and a bottom surface 1824. In this embodiment, the shaped charge 1801 is shown as a flat-top and flat-bottomed cylinder; it should be understood that any of the volumetric shapes contemplated by this specification may be used in the element 1800 .
在元件1800的頂部1810處存在種晶1802,該種晶所具有的摻雜的類型及量可與意欲在生長於種晶1800上的晶體中發現的相同。種晶1800具有表面1802a。種晶1802具有橫截面或直徑1822及高度1823。在一些實施例中,可將種晶安裝於可移動平台1803上以調整表面1802a與表面1823之間的距離。At the top 1810 of the element 1800 there is a seed crystal 1802 that may have the same type and amount of doping that is intended to be found in the crystal grown on the seed crystal 1800 . Seed crystal 1800 has surface 1802a. The seed crystal 1802 has a cross-section or diameter 1822 and a height 1823. In some embodiments, the seed crystal can be mounted on the movable platform 1803 to adjust the distance between the surface 1802a and the surface 1823.
成形裝藥1801的直徑1820可大於、小於種晶1802的直徑或與之相同。The diameter 1820 of the shaped charge 1801 may be larger, smaller, or the same as the diameter of the seed crystal 1802.
在操作中,加熱元件1804將成形裝藥1801的溫度升高至SiC及摻雜劑昇華的點。此昇華導致形成具有各種矽及碳物質及摻雜劑的氣體。此氣體,即通量,存在於在表面1802a與表面1823之間的區域1850中。根據孔隙度或其他因素,通量亦可存在於成形裝藥1801中。通量在元件1800中穿過區域1850上升,其中它將p型SiC或者n型或p型低電阻率SiC沉積於表面1802a上。表面1802a必須保持在足夠冷的溫度以致使氣態矽碳物質及摻雜劑原子雜質沉積於其表面上,從而形成摻雜SiC晶體。以此方式,藉由以多型體匹配定向將生長的SiC與摻雜劑不斷添加至其表面上,將晶種1802生長為p型、或者n型或p型低電阻率SiC晶體。因此,除非由元件1803 (展示於完全收起的位置)調整,否則在晶棒生長期間,表面1803將朝向底部1809生長且因此減小表面1802a與底部1809之間的距離。成形裝藥的形狀可用於在氣相沉積製程期間在成形裝藥內產生預定的溫度差。此預定的溫度差可化解、減少並消除鈍化作用的不利影響,鈍化作用係物質在製程期間構建在成形裝藥中的狀況,該狀況減少或阻止蒸氣形成。In operation, the heating element 1804 increases the temperature of the shaped charge 1801 to the point where the SiC and dopants sublime. This sublimation results in the formation of gases with various silicon and carbon species and dopants. This gas, the flux, exists in region 1850 between surface 1802a and surface 1823. Depending on porosity or other factors, flux may also be present in the shaped charge 1801. Flux rises in element 1800 through region 1850 where it deposits p-type SiC or n-type or p-type low resistivity SiC on surface 1802a. Surface 1802a must be maintained at a sufficiently cold temperature to allow gaseous silicon carbon species and dopant atomic impurities to be deposited on its surface, thereby forming a doped SiC crystal. In this manner, the seed crystal 1802 is grown into a p-type, or n-type, or p-type low resistivity SiC crystal by continuously adding growing SiC and dopants to its surface in a polytype body matching orientation. Therefore, unless adjusted by element 1803 (shown in the fully retracted position), during ingot growth, surface 1803 will grow toward bottom 1809 and thus reduce the distance between surface 1802a and bottom 1809. The shape of the shaped charge can be used to create a predetermined temperature difference within the shaped charge during the vapor deposition process. This predetermined temperature difference resolves, reduces, and eliminates the adverse effects of passivation, a condition in which matter is built into the shaped charge during the manufacturing process, which reduces or prevents vapor formation.
在僅使用p型摻雜劑的實施例中,應最小化、減輕並消除將被視為或者為施體原子的來源的任何材料(諸如氮)的存在。(應注意,在其他實施例中,氮可以小於p型摻雜劑的量存在,且仍然獲得p型源材料,即,經組態以生長具有負Nc的晶體)In embodiments using only p-type dopants, the presence of any material, such as nitrogen, that would be considered or be a source of donor atoms should be minimized, mitigated and eliminated. (It should be noted that in other embodiments, nitrogen may be present in an amount less than the p-type dopant and still obtain a p-type source material, i.e., configured to grow a crystal with negative Nc)
已理論化的是,昇華及沉積製程發生在源材料本身的體積形狀(例如,成形裝藥)的表面上及內部,且遵循源材料中的熱梯度,該熱梯度係自然產生的,或者該熱梯度可由體積形狀的形狀決定。在實施例中,黏結材料可較佳地在昇華溫度期間保持存在且保持體積形狀的形狀及完整性,且因此在SiC的昇華溫度處或以下不會昇華。此熱梯度通常係自外部朝向內部及向上。已理論化的是,材料持續昇華且再沉積於相鄰的粒子上,且以此方式經歷Si-C物質以及摻雜劑的回流或者固態「分餾」或「分昇華」。It has been theorized that the sublimation and deposition processes occur on and within the volumetric shape of the source material itself (e.g., a shaped charge) and follow thermal gradients in the source material that are naturally occurring or that The thermal gradient can be determined by the shape of the volume shape. In embodiments, the bonding material may preferably remain present and maintain the shape and integrity of the volumetric shape during the sublimation temperature, and therefore will not sublime at or below the sublimation temperature of SiC. This thermal gradient is usually from the outside to the inside and upward. It has been theorized that the material continues to sublimate and redeposit on adjacent particles, and in this way undergoes reflux or solid-state "fractionation" or "fractional sublimation" of Si-C species and dopants.
進一步理論化的是,在實施例中,體積形狀及其預定梯度可允許一些更重的雜質困在生長室的底部後面、在體積形狀的結構內,而更輕的元素與Si-C蒸氣一起昇華且被帶至晶種。這在理論上提供了在製程或生長循環中的預定時間使摻雜劑或其他添加劑釋放的能力。It is further theorized that in embodiments, the volume shape and its predetermined gradient may allow some of the heavier impurities to become trapped behind the bottom of the growth chamber, within the structure of the volume shape, while the lighter elements remain with the Si-C vapor Sublimated and brought to the seed crystal. This theoretically provides the ability to release dopants or other additives at predetermined times during the process or growth cycle.
在實施例中,成形裝藥針對給定的溫度提供更一致的通量形成速率。成形裝藥的形狀可經定製以提供貫穿形狀更均勻的溫度,從而允許一次昇華該形狀的更高體積分率,在給定溫度下在晶種/蒸氣界面處驅動速率比標準粉末堆或圓柱形粉末形狀高的通量。因此,需要更低溫度生長製程的多型體生長將不會因此限於更慢的生長速率。In embodiments, the shaped charge provides a more consistent rate of flux formation for a given temperature. The shape of the shaped charge can be tailored to provide a more uniform temperature throughout the shape, thereby allowing a higher volume fraction of the shape to be sublimed at one time, driving the rate at the seed/vapor interface at a given temperature than standard powder piles or Cylindrical powder shape for high throughput. Therefore, the growth of polytypes that require lower temperature growth processes will not therefore be limited to slower growth rates.
昇華速率以克/小時為單位來量測。通量係按克/cm 2-hr (即,穿過面積的材料的速率)給出。因此,關鍵面積為對應於晶棒生長表面(例如,SiC被沉積的晶棒面)的瞬時表面積的通量面積。通常,通量面積及晶棒面的面積大致相同,且此等面積通常略小於氣相沉積裝置的生長室的橫截面積。 Sublimation rate is measured in grams per hour. Flux is given in grams/cm 2 -hr (ie, the rate of material passing through an area). Therefore, the critical area is the flux area corresponding to the instantaneous surface area of the ingot growth surface (eg, the ingot face where SiC is deposited). Typically, the flux area and the area of the ingot face are approximately the same, and these areas are usually slightly smaller than the cross-sectional area of the growth chamber of the vapor deposition apparatus.
出於計算及此分析的目的,為了計算方便起見,假定生長室的橫截面積與通量的面積及晶棒面的面積相同。因此,晶棒的生長速率( μm/hr)可等效於蒸氣通量以及 μm/hr -> g/hr (全緻密SiC的密度為3.21g/cc),穿過晶棒表面的面積(cm 2)。可經由X射線成像或X射線電腦斷層造影(computed tomography,CT)進行現場量測。另外,可藉由在生長之前/之後對晶棒稱重來判定平均生長速率。 For the purposes of calculations and this analysis, it is assumed for ease of calculation that the cross-sectional area of the growth chamber is the same as the area of the flux and the area of the rod face. Therefore, the growth rate of the crystal rod ( μ m/hr) can be equivalent to the vapor flux and μ m/hr -> g/hr (the density of fully dense SiC is 3.21g/cc), passing through the area of the rod surface (cm 2 ). On-site measurement can be performed via X-ray imaging or X-ray computed tomography (CT). Additionally, the average growth rate can be determined by weighing the ingot before/after growth.
典型的商業生長速率在200 μm/hr至500 μm/hr的範圍內。目前的製程及體積形狀的實施例遠超此等現有商業速率,而同時提供具有相等且優異的品質的晶棒。例如,本發明之實施例在高溫及低壓力下可具有約550 μm/hr至約1,1000 μm/hr、約800 μm/hr至約1,000 μm/hr、約900 μm/hr至約1,100 μm/hr、約700 μm/hr、約800 μm/hr、約900 μm/hr、約1,000 μm/hr、1,100 μm/hr的生長速率。設想了更高的速率且亦可使用更慢的速率,以及在此等範圍內的所有速率。 Typical commercial growth rates range from 200 μm /hr to 500 μm /hr. Current process and volumetric shape embodiments far exceed these current commercial rates while providing ingots of equivalent and superior quality. For example, embodiments of the present invention may have about 550 μm /hr to about 1,1000 μm /hr, about 800 μm /hr to about 1,000 μm /hr, and about 900 μm /hr under high temperature and low pressure. hr to a growth rate of about 1,100 μm /hr, about 700 μm /hr, about 800 μm /hr, about 900 μm /hr, about 1,000 μm /hr, 1,100 μm /hr. Higher rates are contemplated and slower rates may be used, as well as all rates within such ranges.
通常,生長速率由1)溫度及2)供應氣體壓力(Ar、N 2等)驅動。針對任何給定的溫度,更大的氣體壓力會稀釋晶種及晶棒面處的矽碳物質的蒸氣壓力,且減緩生長速率。因此,壓力可用於「撥入」生長速率。 Typically, the growth rate is driven by 1) temperature and 2 ) supply gas pressure (Ar, N, etc.). For any given temperature, greater gas pressure dilutes the vapor pressure of the silicon carbon species at the seed and rod faces and slows the growth rate. Therefore, pressure can be used to "dial in" the growth rate.
因此,在給定恆定溫度的情況下,體積形狀(例如,成形裝藥)的實施例可保持一致的通量產生速率,例如,在p型SiC或低電阻率SiC晶體生長的整個操作內恆定,包括具有約4吋至約10吋直徑、約6吋至約8吋直徑、約4吋直徑、約6吋直徑、約8吋直徑以及更大及更小,以及在此等值的範圍內的所有直徑的此類晶體。在給定恆定溫度的情況下,在給出針對整個p型SiC或低電阻率SiC晶體生長製程恆定的溫度的情況下,體積形狀的實施例可保持通量產生速率及因此晶棒生長速率在晶體生長期間處於恆定的速率、恆定的速率、處於具有小於約0.001%的變化的速率、處於具有小於約0.01%的變化的速率、處於具有小於約1%的變化的速率、處於具有小於約5%的變化的速率、處於具有約0.001%的變化至約15%的變化的速率、處於具有約0.01%的變化至約5%的變化的速率、以及此等的組合及變化,以及在此等值的範圍內的所有值。在實施例中,在恆定的溫度下,通量形成速率在晶棒生長期間保持在:其最大速率的約99.999%至約60%;其最大速率的約99%至約95%;其最大速率的約99.99%至約80%;其最大速率的約99%至約70%;其最大速率的約95%至約70%;其最大速率的約99%至約95%;以及此等的組合及變化,以及在此等百分比的範圍內的所有值。Thus, embodiments of volumetric shapes (e.g., shaped charges) can maintain a consistent flux generation rate, e.g., constant throughout the entire operation of p-type SiC or low resistivity SiC crystal growth given a constant temperature. , including those having a diameter of about 4 inches to about 10 inches, a diameter of about 6 inches to about 8 inches, a diameter of about 4 inches, a diameter of about 6 inches, a diameter of about 8 inches, and larger and smaller, and within the range of equivalents thereof of such crystals of all diameters. Embodiments of the volumetric shape can maintain flux generation rates and therefore ingot growth rates at a given constant temperature for the entire p-type SiC or low resistivity SiC crystal growth process. At a constant rate during crystal growth, at a constant rate, at a rate with a change of less than about 0.001%, at a rate with a change of less than about 0.01%, at a rate with a change of less than about 1%, at a rate with a change of less than about 5 % change, at a rate having a change of about 0.001% to about 15% change, at a rate having a change of about 0.01% to about 5% change, and combinations and changes thereof, and in the All values within the range of values. In embodiments, at constant temperature, the flux formation rate during ingot growth is maintained at: about 99.999% to about 60% of its maximum rate; about 99% to about 95% of its maximum rate; its maximum rate from about 99.99% to about 80% of its maximum speed; from about 99% to about 70% of its maximum speed; from about 95% to about 70% of its maximum speed; from about 99% to about 95% of its maximum speed; and combinations thereof and changes, and all values within the range of these percentages.
實施例提供用於粉末的不同化學計量、黏結劑含量、摻雜劑含量及兩者貫穿形狀(例如,具有不同類型的粉末起始材料、不同黏結劑以及此等的組合及變化的層、區、區域)的分佈。不同化學計量、黏結劑含量及兩者的此種預定分佈提供若干優點,包括:昇華組合物的客製化,因為源材料係自外部消耗進來,這使得組合物中的變換自生長循環的開始至結束能夠更少。由於蒸氣的一致的組合物,不同化學計量、黏結劑含量及兩者的此種預定分佈亦可增強多型體穩定性。Examples provide different stoichiometry for powders, binder content, dopant content, and both through shapes (e.g., layers, regions with different types of powder starting materials, different binders, and combinations and variations of these). , region) distribution. This predetermined distribution of different stoichiometry, binder content, and both offers several advantages, including: Customization of the sublimation composition, since the source material is consumed externally, which enables changes in the composition from the beginning of the growth cycle By the end it could be less. Polymorph stability can also be enhanced due to a consistent composition of vapors, different stoichiometry, binder content, and such predetermined distribution of both.
本發明之實施例包括在製造應用於電子元件及半導體應用中的p型SiC或低電阻率SiC晶圓中使用摻雜SiC。在用於產生p型SiC或低電阻率SiC晶體及p型SiC或低電阻率SiC晶圓以供後續使用的氣相沉積裝置及製程兩者中,都需要摻雜(且較佳地高純度) SiC。Embodiments of the invention include the use of doped SiC in the fabrication of p-type SiC or low resistivity SiC wafers for use in electronic components and semiconductor applications. Doping (and preferably high purity) is required in both the vapor deposition apparatus and processes used to produce p-type SiC or low-resistivity SiC crystals and p-type SiC or low-resistivity SiC wafers for subsequent use. ) SiC.
目前的聚矽碳p型SiC或低電阻率SiC、及p型SiC或低電阻率SiC晶棒、p型SiC或低電阻率SiC晶圓及由聚矽碳衍生SiC製成的其他結構之實施例表現出多態性,且一維多態性通常被稱為多型性。因此,聚矽碳衍生p型SiC或低電阻率SiC可存在於許多(理論上無限的)不同多型體中。如本文所使用,除非另外明確提供,否則術語多型性、多型體及類似的此類術語應當被給予其最廣泛的可能含義,且將包括各種不同的框架、結構或配置,用來組態碳化矽四面體(SiC 4)。通常,此等多型體分為兩個類別:α ( α)及β ( β)。 Current implementation of polysilica p-SiC or low-resistivity SiC, and p-type SiC or low-resistivity SiC ingots, p-type SiC or low-resistivity SiC wafers, and other structures made from polysilica-derived SiC Examples exhibit polymorphism, and one-dimensional polymorphism is often referred to as polymorphism. Therefore, polysilica-derived p-type SiC or low-resistivity SiC can exist in many (theoretically infinite) different polytypes. As used herein, unless expressly provided otherwise, the terms polymorphism, polymorphism and similar such terms shall be given their broadest possible meanings and will include various different frameworks, structures or configurations used to assemble State silicon carbide tetrahedron (SiC 4 ). Generally, these polytypes are divided into two categories: alpha ( α ) and beta ( β ).
α類別的聚矽碳衍生p型SiC或低電阻率SiC之實施例通常包含六方(H)、菱面體(R)、三方(T)結構且可包含此等的組合。β類別通常包含立方(C)或閃鋅礦結構。因此,例如,聚矽碳衍生p型SiC或低電阻率SiC的多型體將包括:3C-SiC ( β- SiC或 β3C-SiC ),其具有堆疊序列ABCABC...;2H-SiC,其具有堆疊序列ABAB...;4H-SiC,其具有堆疊序列ABCBABCB...;及6H-SiC (α碳化矽的常見形式, α6H-SiC),其具有堆疊序列ABCACBABCACB...。α碳化矽的其他形式將包括8H、10H、16H、18H、19H、15R、21R、24H、33R、39R、27R、48H及51R。 Examples of alpha-type silicone-derived p-type SiC or low-resistivity SiC typically include hexagonal (H), rhombohedral (R), trigonal (T) structures and may include combinations of these. The beta category usually contains cubic (C) or sphalerite structures. So, for example, a polytype of polysilica-derived p-type SiC or low-resistivity SiC would include: 3C-SiC ( β -SiC or β3C -SiC ) , which has the stacking sequence ABCABC...; 2H-SiC, It has the stacking sequence ABAB...; 4H-SiC, which has the stacking sequence ABCBABCB...; and 6H-SiC (a common form of alpha silicon carbide, α6H -SiC), which has the stacking sequence ABCACBABCACB.... Other forms of alpha silicon carbide would include 8H, 10H, 16H, 18H, 19H, 15R, 21R, 24H, 33R, 39R, 27R, 48H and 51R.
聚矽碳衍生p型SiC或低電阻率SiC的實施例可為多晶或單(single/mono)晶的。通常,在多晶材料中存在晶粒邊界,作為材料的兩個晶粒或微晶之間的界面。此等晶粒邊界可在具有不同定向的相同多型體之間,或者在具有相同或不同定向的不同多型體之間,以及此等的組合及變化。單晶結構由單個多型體構成且基本上不具有晶粒邊界。在較佳實施例中,p型SiC或低電阻率SiC為單晶的。Embodiments of polysilica-derived p-type SiC or low-resistivity SiC may be polycrystalline or single/mono-crystalline. Typically, grain boundaries exist in polycrystalline materials as the interface between two grains or crystallites of the material. These grain boundaries can be between the same polytype with different orientations, or between different polytypes with the same or different orientations, as well as combinations and variations of these. Single crystal structures consist of a single polytype and have essentially no grain boundaries. In preferred embodiments, p-type SiC or low resistivity SiC is single crystal.
目前的方法的實施例產生晶棒,較佳地為單晶體p型SiC或低電阻率SiC晶棒。此等晶棒可具有約½吋至約5吋、約½吋至約3吋、約1吋至約2吋、大於約½吋、大於約1吋及大於約2吋的長度。設想了更大及更小的大小以及在此等大小的範圍內的所有值。晶棒可具有約½吋至約9吋、約2吋至約8吋、約1吋至約6吋、大於約1吋、大於約2吋、大於約4吋、約4吋、約6吋及約8吋、約12吋及約18吋的橫截面,例如直徑。設想了其他大小以及在此等大小的範圍內的所有值。 P 型及低電阻率型晶圓- 一般而言 Embodiments of the present method produce ingots, preferably monocrystalline p-type SiC or low resistivity SiC ingots. The ingots may have lengths of about ½ inch to about 5 inches, about ½ inch to about 3 inches, about 1 inch to about 2 inches, greater than about ½ inch, greater than about 1 inch, and greater than about 2 inches. Larger and smaller sizes and all values within the range of such sizes are contemplated. The crystal ingot can have a diameter of about ½ inch to about 9 inches, about 2 inches to about 8 inches, about 1 inch to about 6 inches, greater than about 1 inch, greater than about 2 inches, greater than about 4 inches, about 4 inches, about 6 inches. and cross-sections, such as diameters, of about 8 inches, about 12 inches, and about 18 inches. Other sizes and all values within the range of such sizes are contemplated. P -type and low-resistivity wafers - generally speaking
一般而言,用於由p型SiC或低電阻率SiC晶棒製造電子組件的製程涉及將p型SiC或低電阻率SiC SiC單晶晶棒切割成薄的晶圓。產生的SiC晶圓為製造SiC基半導體元件的起點。SEMI (www.semi.org)已開發並公開高達150 mm的各種直徑的SiC晶圓規範之標準。此等標準係熟習此項技術者熟知的且理解的。由於使p型SiC晶體及晶圓商業化且僅使n型摻氮SiC晶體及晶圓商業化的SiC工業的先前限制,用於製造適合於在製造半導體元件中使用的SiC晶圓之最有名的方法係基於SiC n型晶圓且可用於製造p型、n型低電阻率及p型低電阻率晶圓。Generally speaking, processes for manufacturing electronic components from p-type SiC or low resistivity SiC ingots involve slicing p-type SiC or low resistivity SiC single crystal ingots into thin wafers. The resulting SiC wafers are the starting point for manufacturing SiC-based semiconductor components. SEMI (www.semi.org) has developed and published standards for SiC wafer specifications for various diameters up to 150 mm. These standards are well known and understood by those skilled in the art. Due to previous limitations of the SiC industry in commercializing p-type SiC crystals and wafers and only n-type nitrogen-doped SiC crystals and wafers, the most well-known The method is based on SiC n-type wafers and can be used to manufacture p-type, n-type low resistivity and p-type low resistivity wafers.
本發明的摻雜晶圓的實施例具有晶棒(該等晶圓係自晶棒切割)的直徑,且通常具有約100 μm至約500 μm的厚度。較佳地,p型電氣性質或低電阻率性質貫穿晶棒的整個長度或晶圓的整個厚度分佈。更佳地,p型電氣性質或低電阻率性質貫穿晶棒的整個長度或晶圓的整個厚度均勻地分佈。然後在一側或兩側上對p型SiC或低電阻率SiC晶圓進行拋光。經拋光的晶圓然後用作製造微電子半導體元件的基板。因此,p型SiC或低電阻率SiC晶圓用作構建在晶圓上的微電子元件的基板。此等微電子元件的製造包括微製造處理步驟,舉幾個例子,諸如磊晶生長、摻雜或離子植入、蝕刻、沉積各種材料及微影圖案化。一旦由p型SiC或低電阻率SiC晶圓製成,就在稱為切塊的製程中將晶圓及因此個別微電路分離成個別半導體元件。此等元件然後用於製造各種更大的半導體及電子元件(例如,併入至其中)。 Embodiments of the doped wafers of the present invention have a diameter of the ingot from which the wafers are cut, and typically have a thickness of about 100 μm to about 500 μm . Preferably, the p-type electrical properties or low resistivity properties are distributed throughout the entire length of the ingot or the entire thickness of the wafer. More preferably, the p-type electrical properties or low resistivity properties are evenly distributed throughout the entire length of the ingot or the entire thickness of the wafer. The p-type SiC or low-resistivity SiC wafer is then polished on one or both sides. The polished wafers are then used as substrates for the fabrication of microelectronic semiconductor components. Therefore, p-type SiC or low-resistivity SiC wafers are used as substrates for microelectronic components built on the wafer. The fabrication of these microelectronic components includes microfabrication process steps such as epitaxial growth, doping or ion implantation, etching, deposition of various materials, and lithographic patterning, to name a few. Once made from a p-type SiC or low-resistivity SiC wafer, the wafer and therefore the individual microcircuits are separated into individual semiconductor components in a process called dicing. These components are then used to fabricate (eg, incorporated into) a variety of larger semiconductor and electronic components.
除其他事項外,目前的方法及所得p型SiC或低電阻率SiC晶圓的實施例包括:約2吋直徑的晶圓及更小、約3吋直徑的晶圓、約4吋直徑的晶圓、約5吋直徑的晶圓、約6吋直徑的晶圓、約7吋直徑的晶圓、約12吋直徑的晶圓及可能更大、具有約2吋至約8吋的直徑的晶圓、具有約4吋至約6吋的直徑、正方形、圓形及其他形狀、約1平方吋、約4平方吋、約8平方吋、約10平方吋、約12平方吋、約30平方吋、約50平方吋以及更大及更小的每側表面積、約100 μm的厚度、約200 μm的厚度、約300 μm的厚度、約500 μm的厚度、約700 μm的厚度、約50 μm至約800 μm的厚度、約100 μm至約700 μm的厚度、約100 μm至約400 μm的厚度、約100 μm至約300 μm的厚度、約100 μm至約200 μm的厚度以及更大及更小的厚度,以及此等的組合及變化以及在此等尺寸的範圍內的所有值的晶圓。 Examples of current methods and resulting p-type SiC or low-resistivity SiC wafers include, among other things: approximately 2-inch diameter wafers and smaller, approximately 3-inch diameter wafers, approximately 4-inch diameter wafers. Rounds, approximately 5-inch diameter wafers, approximately 6-inch diameter wafers, approximately 7-inch diameter wafers, approximately 12-inch diameter wafers, and possibly larger wafers with diameters from approximately 2 inches to approximately 8 inches Round, having a diameter of about 4 inches to about 6 inches, square, round and other shapes, about 1 square inch, about 4 square inches, about 8 square inches, about 10 square inches, about 12 square inches, about 30 square inches , approximately 50 square inches and larger and smaller surface areas per side, approximately 100 μm thickness, approximately 200 μm thickness, approximately 300 μm thickness, approximately 500 μm thickness, approximately 700 μm thickness , a thickness of about 50 μm to about 800 μm , a thickness of about 100 μm to about 700 μm , a thickness of about 100 μm to about 400 μm , a thickness of about 100 μm to about 300 μm , a thickness of about Wafers with thicknesses from 100 μm to about 200 μm and greater and smaller thicknesses, as well as combinations and variations of these and all values within the range of these sizes.
目前的方法及所得經切割及拋光的p型SiC或低電阻率SiC晶圓的實施例亦可包括:用於開始晶棒的生長(即,作為「晶種」),由此生長的晶棒的其餘部分與結構匹配。除其他事項外,p型SiC或低電阻率SiC晶圓及p型SiC或低電阻率SiC晶種可為:約2吋直徑的晶圓及更小、約3吋直徑的晶圓、約4吋直徑的晶圓、約5吋直徑的晶圓、約6吋直徑的晶圓、約7吋直徑的晶圓、約12吋直徑的晶圓及可能更大、具有約2吋至約8吋的直徑的晶圓、具有約4吋至約6吋的直徑、正方形、圓形及其他形狀、約4平方吋、約8平方吋、約12平方吋、約30平方吋、約50平方吋以及更大及更小的每側表面積、約100 μm的厚度、約200 μm的厚度、約300 μm的厚度、約500 μm的厚度、約1500 μm的厚度、約2500 μm的厚度、約50 μm至約2000 μm的厚度、約500 μm至約1800 μm的厚度、約800 μm至約1500 μm的厚度、約500 μm至約1200 μm的厚度、約200 μm至約2000 μm的厚度、約50 μm至約2500 μm的厚度以及更大及更小的厚度,以及此等的組合及變化以及在此等尺寸的範圍內的所有值的晶圓。 The current methods and embodiments of the resulting cut and polished p-type SiC or low resistivity SiC wafers may also include: used to initiate the growth of a crystal ingot (i.e., as a "seed") from which the ingot is grown. The rest of it matches the structure. Among other things, p-type SiC or low-resistivity SiC wafers and p-type SiC or low-resistivity SiC seeds may be: approximately 2-inch diameter wafers and smaller, approximately 3-inch diameter wafers, approximately 4 inch diameter wafers, approximately 5 inch diameter wafers, approximately 6 inch diameter wafers, approximately 7 inch diameter wafers, approximately 12 inch diameter wafers and possibly larger, with approximately 2 inches to approximately 8 inches wafers having diameters of about 4 inches to about 6 inches, squares, circles and other shapes, about 4 square inches, about 8 square inches, about 12 square inches, about 30 square inches, about 50 square inches and Larger and smaller surface area per side, thickness of about 100 μm , thickness of about 200 μm , thickness of about 300 μm , thickness of about 500 μm , thickness of about 1500 μm , thickness of about 2500 μm Thickness, thickness of about 50 μm to about 2000 μm , thickness of about 500 μm to about 1800 μm , thickness of about 800 μm to about 1500 μm , thickness of about 500 μm to about 1200 μm , Thicknesses from about 200 μm to about 2000 μm , thicknesses from about 50 μm to about 2500 μm and greater and smaller thicknesses, as well as combinations and variations of these and all values within the range of these dimensions of wafers.
目前的p型SiC或低電阻率SiC晶棒、p型SiC或低電阻率SiC晶圓及由彼此晶圓製成的微電子元件的實施例除其他事項外可在二極體、寬頻放大器、軍用通信、雷達、電信、資料鏈路及戰術資料鏈路、衛星通信及點對點無線電功率電子元件、LED、雷射、照明及感測器中得到應用及利用。另外,此等實施例可在諸如高電子遷移率電晶體(High- electron-mobility transisitor,HEMT)的電晶體中得到應用及使用,包括基於HEMT的單片式微波積體電路(monolithic microwave integrated circuit,MMIC)及IGBT。此等電晶體可採用分佈式(行波)放大器設計方法,且藉由SiC的更大能帶間隙,使得能夠在小佔據面積中達成極寬的頻寬。因此,本發明之實施例將包括此等元件及由以下製成的或以其他方式基於以下的製品:目前的方法、氣相沉積技術,及聚合物衍生SiC、SiC晶棒、SiC晶圓,及由此等晶圓製成的微電子元件。Current embodiments of p-type SiC or low-resistivity SiC ingots, p-type SiC or low-resistivity SiC wafers and microelectronic components made from each other's wafers can be used in, among other things, diodes, broadband amplifiers, It is applied and utilized in military communications, radar, telecommunications, data links and tactical data links, satellite communications and point-to-point radio power electronic components, LEDs, lasers, lighting and sensors. In addition, these embodiments may be applied and used in transistors such as high-electron-mobility transistors (HEMTs), including HEMT-based monolithic microwave integrated circuits. , MMIC) and IGBT. These transistors can use distributed (traveling wave) amplifier design methods, and through the larger energy band gap of SiC, they can achieve extremely wide bandwidths in a small footprint. Accordingly, embodiments of the present invention will include such components and articles made from or otherwise based on current methods, vapor deposition techniques, and polymer-derived SiC, SiC ingots, and SiC wafers, and microelectronic components made from such wafers.
聚矽碳衍生p型SiC或低電阻率SiC SiC,特定而言高純度SiC的實施例具有許多獨特的性質,除其他事項外,該等性質使它們有利地且合意地用於電子元件、雷達及功率傳輸工業及應用中。它們可用作非常穩定且適合於若干高需求應用的p型或低電阻率半導體材料,該等高需求應用包括高功率、高頻、高溫及腐蝕性環境及使用。聚合物衍生p型SiC或低電阻率SiC係楊氏模數為424 GPa的非常硬的材料。Embodiments of polysilica-derived p-type SiC or low-resistivity SiC, and in particular high-purity SiC, have a number of unique properties that make them advantageous and desirable for use in electronic components, radars, among other things and power transmission industries and applications. They serve as p-type or low-resistivity semiconductor materials that are very stable and suitable for certain high-demand applications, including high power, high frequency, high temperature and corrosive environments and uses. Polymer-derived p-type SiC or low-resistivity SiC is a very hard material with a Young's modulus of 424 GPa.
在實施例中,若需要將摻雜劑添加至材料,則它們可藉由前驅物添加且因此以受控的方式及量存在以便生長至晶棒或其他結構中。前驅物配方的實施例可具有摻雜劑或者將摻雜劑攜帶並黏結至陶瓷(然後至經轉換的SiC)中的錯合物,因此在氣相沉積製程後,摻雜劑係可用的且處於可使用的形式。In embodiments, if dopants need to be added to the material, they can be added by precursors and thus present in a controlled manner and amount for growth into the ingot or other structure. Embodiments of precursor formulations may have dopants or complexes that carry and bond the dopants to the ceramic (and then to the converted SiC) so that after the vapor deposition process, the dopants are available and In a usable form.
另外,摻雜劑或其他添加劑用於向由聚合物衍生SiC製成的晶圓、層及結構提供客製化或預定的性質。在此等實施例中,此種性質增強添加劑將不被視為雜質,因為它們意欲處於、有必要處於最終產品中。性質增強添加劑可併入至液體前驅物材料中。根據性質增強添加劑的本質,它可為前驅物主幹的一部分,它可被錯合或為錯合物的一部分,以將其併入至液體前驅物中,或者它可以將使其能夠倖存的其他形式存在(例如,處於使其功能按預期留在最終材料中的形式)。舉幾個例子,性質增強添加劑亦可作為塗層添加至SiC或SiOC粉末材料,可在處理期間作為蒸氣或氣體添加,或者可處於粉末形式且與聚合物衍生SiC或SiOC粒子混合。在實施例中,性質增強添加劑包含用於體積形狀的黏結劑或為該黏結劑的一部分。在實施例中,性質增強添加劑可為體積形狀上的塗層。另外,性質增強添加劑存在的形式及方式應較佳地為使得它對處理條件、處理時間及最終產品的品質具有最少的不利影響、且更佳地沒有不利影響。 P 型元件- 一般而言 Additionally, dopants or other additives are used to provide customized or predetermined properties to wafers, layers and structures made from polymer-derived SiC. In these examples, such property enhancing additives would not be considered impurities as they are intended to be, and need to be, in the final product. Property enhancing additives can be incorporated into the liquid precursor material. Depending on the nature of the property-enhancing additive, it can be part of the precursor backbone, it can be complexed or part of a complex to incorporate it into the liquid precursor, or it can be other elements that enable it to survive Form exists (e.g., in a form such that its function remains in the final material as intended). To name a few examples, property-enhancing additives can also be added to SiC or SiOC powder materials as a coating, can be added as a vapor or gas during processing, or can be in powder form and mixed with polymer-derived SiC or SiOC particles. In embodiments, the property enhancing additives comprise or are part of the binder for the volumetric shape. In embodiments, the property enhancing additive may be a coating on the volumetric shape. Furthermore, the property-enhancing additive should preferably be present in a form and in a manner such that it has minimal and preferably no adverse effect on processing conditions, processing time and quality of the final product. P -type components - generally speaking
此等p型SiC晶圓提供了製造先前用矽p型晶圓設計的電路、半導體元件及晶片、且在對重寫或重做電路或晶片設計的需要最小之情況下如此做的能力。因此,在實施例中,提供了使用p型矽基板設計的電路或元件的直接構建,且改為使用由SiC p型晶圓製成的元件,而不需要修改或者組態或調適基於矽元件的電路。These p-type SiC wafers provide the ability to fabricate circuits, semiconductor components and wafers previously designed using silicon p-type wafers, and do so with minimal need to rewrite or rework the circuit or wafer design. Thus, in embodiments, direct construction of circuits or components designed using p-type silicon substrates is provided, and instead components made from SiC p-type wafers are provided without the need to modify or configure or adapt the silicon-based components circuit.
以此方式,本發明之實施例化解了功率電路設計者在利用使用SiC元件的全範圍益處中面臨的間隙,此係藉由提供用於生產具有與當前要求一致的低缺陷、電阻率性質及基板直徑之4H-SiC或6H-SiC p型基板(例如,晶圓)的可製造方法來製造元件,諸如肖特基障壁二極體(Schottky barrier diode,SBD)、接面障壁肖特基二極體(junction barrier Schottky diode,JBS)及MOSFET,以及電晶體,諸如閘極關斷電晶體(gate-turn off transistor,GTO)及積體閘極雙極電晶體(integrated gate bipolar transistor,IGBT),以及此等電晶體及元件的變體及其他類型。本發明之實施例使得能夠製造具有匹配且較佳地超過當今在商業上由n型SiC晶體生產的基板的直徑及電阻率之p型基板。本文中揭示並教示的p型晶圓給元件製造商提供能力來且因此使得元件製造商能夠將SiC的效用擴展至當今由n型SiC至p型SiC製成的所有電壓範圍及安培範圍元件。基於本文中揭示並教示的p型晶圓,功率電路的設計者現在將能夠將SiC元件的益處擴展至用於所有電壓範圍、電壓極性及安培電路設計以及其他的所有功率管理應用。In this manner, embodiments of the present invention resolve the gap faced by power circuit designers in leveraging the full range of benefits of using SiC components by providing a means for producing devices with low defectivity, resistivity properties and performance consistent with current requirements. Methods for fabricating 4H-SiC or 6H-SiC p-type substrates (e.g., wafers) with a substrate diameter to fabricate components such as Schottky barrier diodes (SBD), junction barrier Schottky diodes Junction barrier Schottky diode (JBS) and MOSFET, as well as transistors, such as gate-turn off transistor (GTO) and integrated gate bipolar transistor (IGBT) , as well as variations and other types of such transistors and components. Embodiments of the present invention enable the fabrication of p-type substrates with diameters and resistivities that match and preferably exceed today's substrates commercially produced from n-type SiC crystals. The p-type wafers disclosed and taught herein provide component manufacturers with the ability to, and thus enable, extend the utility of SiC to all voltage range and ampere range components today made from n-type SiC to p-type SiC. Based on the p-type wafers disclosed and taught in this article, power circuit designers will now be able to extend the benefits of SiC components to all voltage ranges, voltage polarities, and ampere circuit designs, as well as all other power management applications.
本發明之實施例可具有或利用在本說明書的前驅物及源材料-一般而言、摻雜劑材料-一般而言、摻雜晶體生長-一般而言、P型及低電阻率型晶圓-一般而言及P型元件-一般而言教示中陳述的實施例、特徵、功能、參數、組件、製程或系統中之一或多者,以及在實例及圖中的實施例、特徵、功能、參數、組件、製程或系統中之一或多者。Embodiments of the present invention may have or utilize the precursors and source materials - generally speaking, dopant materials - generally speaking, doped crystal growth - generally speaking, P-type and low-resistivity type wafers described herein. - Generally speaking and P-type components - One or more of the embodiments, features, functions, parameters, components, processes or systems set forth in the teachings generally, and the embodiments, features, functions, One or more of a parameter, component, process, or system.
實例Example
提供以下實例以說明本發明之系統、製程、組合物、應用及材料的各種實施例。此等實例係出於說明目的,可為預言的,且不應被視為且不會以其他方式限制本發明之範疇。除非另外明確提供,否則實例中使用的百分比為總體(例如,配方、混合物、產品或結構)的重量百分比。除非另外明確提供,否則使用X/Y或XY指示配方中X的重量%及Y的重量%。除非另外明確提供,否則使用X/Y/Z或XYZ指示配方中X的重量%、Y的重量%及Z的重量%。The following examples are provided to illustrate various embodiments of the systems, processes, compositions, applications, and materials of the invention. These examples are for illustrative purposes, may be prophetic, and should not be considered and do not otherwise limit the scope of the invention. Unless otherwise explicitly provided, percentages used in the examples are weight percent of the totality (eg, formulation, mixture, product, or structure). Unless otherwise explicitly provided, use X/Y or XY to indicate the weight % of X and the weight % of Y in the formulation. Unless otherwise explicitly provided, use X/Y/Z or XYZ to indicate the weight % of X, the weight % of Y, and the weight % of Z in the formulation.
實例1Example 1
在實施例中,將2.5 wt%的5 μm莫來石粉末(MU-101,微米金屬)的分散添加至具有30 ppb的Pt作為Ashbys催化劑的41% MHF 59% TV配方的前驅物配方。使摻雜前驅物配方固化,然後熱解成SiC。然後藉由使用摻雜前驅物配方作為成形裝藥黏結劑、模製成形狀且然後使該形狀固化成生坯而將SiC粉末製成成形裝藥。將生坯熱解並轉換成摻雜SiC成形裝藥源材料。在實例1A至1D中陳述另外的細節。 In the example, a dispersion of 2.5 wt% of 5 μm mullite powder (MU-101, Micron Metal) was added to a precursor formulation of a 41% MHF 59% TV formulation with 30 ppb Pt as Ashbys catalyst. The doping precursor formulation is cured and then pyrolyzed to SiC. The SiC powder is then made into a shaped charge by using a doping precursor formulation as a shaped charge binder, molding into a shape, and then solidifying the shape into a green body. The green body is pyrolyzed and converted into a doped SiC shaped charge source material. Additional details are set forth in Examples 1A-1D.
實例1AExample 1A
如表1中所陳述的液體摻Al前驅物配方,用於製造用於生長p型SiC晶體的p型SiC源材料。
表(1)
實例1BExample 1B
將來自實例1A的固化的摻Al前驅物配方熱解以提供如表2中所陳述的摻Al SiC材料。
表2.
實例1CExample 1C
將來自實例1B的陶瓷摻Al SiC材料形成為體積形狀且固化,如表3所示。在形成體積形狀時將莫來石與黏結劑一起添加。
表3
實例1DExample 1D
將實例1C的固化體積形狀熱解,如表4中所陳述,以提供在p型SiC晶體的PVT生長中使用的摻Al SiC成形裝藥源材料。
表4
實例2Example 2
遵循實例1A至1D的相同的一般配方及前驅物,只不過代替鋁摻雜劑,將三烯丙基膦添加至液體前驅物配方(三烯丙基膦佔前驅物配方的1重量%至15重量%),且三烯丙基膦亦可與黏結劑一起添加(三烯丙基膦佔摻P SiC粉末及黏結劑的1重量%至15重量%),以形成固化的摻P SiC體積形狀,然後將其熱解以形成摻P SiC成形裝藥源材料。摻P SiC成形裝藥源材料在低電阻率n型SiC晶體的PVT生長中使用。The same general formulations and precursors of Examples 1A to 1D were followed except that in place of the aluminum dopant, triallylphosphine was added to the liquid precursor formulation (triallylphosphine comprised 1 to 15% by weight of the precursor formulation Weight %), and triallyl phosphine can also be added together with the binder (triallyl phosphine accounts for 1 to 15 weight % of the P-doped SiC powder and binder) to form the solidified P-doped SiC volume shape , which is then pyrolyzed to form a P-doped SiC shaped charge source material. P-doped SiC shaped charge source material is used in PVT growth of low resistivity n-type SiC crystals.
實例3Example 3
轉至第1圖,展示了具有約150 mm的直徑的p型SiC晶體的相片。該晶體係使用PVT製程及裝置且使用實例1D中之類型的摻Al SiC成形裝藥源材料生長的。p型晶體具有70 ppm的Al。p型晶體具有5.5 x 10 18個Al原子/cc。晶體具有約23 mm的長度。製備晶體的薄切片並對其進行拋光,且在傳輸中觀察時為藍色/紫色。未觀察到多型體自4H切換至另一多型體的證據。 Turning to Figure 1, a photograph of a p-type SiC crystal with a diameter of approximately 150 mm is shown. The crystals were grown using a PVT process and equipment using an Al-doped SiC shaped charge source material of the type in Example ID. The p-type crystal has 70 ppm Al. A p-type crystal has 5.5 x 10 18 Al atoms/cc. The crystal has a length of approximately 23 mm. Thin sections of crystals were prepared and polished, and were blue/purple when viewed in transmission. No evidence of polytype switching from 4H to another polytype was observed.
實例4Example 4
轉至第2A圖,展示了摻雜SiC晶圓700的平面圖示意圖。第2B圖係晶圓700之沿著線B-B的橫截面視圖。晶圓700可為p型SiC晶圓,晶圓700可為低電阻率p型SiC晶圓,或者晶圓700可為低電阻率n型SiC晶圓。晶圓700為圓盤狀結晶結構,其形狀705為半圓形的、具有平面706。應理解,晶圓可為圓形的,或者可具有超過一個平面。晶圓700具有邊緣730。晶圓700具有頂部或頂部表面710、底部或底部表面711及由箭頭712展示的厚度。晶圓700的頂部表面及底部表面兩者以及整個厚度712係摻雜SiC晶體。應理解,一個表面通常為SiC晶體的C面且另一表面為SiC晶體的Si面。可對一個表面或兩個表面進行拋光及表面光製以便用於元件製造。晶圓700的外邊緣730可為錐形的、傾斜的、倒角的、正方形的、圓的等。Turning to Figure 2A, a schematic plan view of a doped SiC wafer 700 is shown. Figure 2B is a cross-sectional view of wafer 700 along line B-B. Wafer 700 may be a p-type SiC wafer, wafer 700 may be a low resistivity p-type SiC wafer, or wafer 700 may be a low resistivity n-type SiC wafer. The wafer 700 has a disc-shaped crystal structure, and its shape 705 is semicircular and has a flat surface 706 . It should be understood that the wafer may be circular, or may have more than one plane. Wafer 700 has edge 730 . Wafer 700 has a top or bottom surface 710 , a bottom or bottom surface 711 and a thickness shown by arrow 712 . Both the top and bottom surfaces of wafer 700 and the entire thickness 712 are doped with SiC crystal. It will be understood that one surface is typically the C-face of the SiC crystal and the other surface is the Si-face of the SiC crystal. One or both surfaces can be polished and surface finished for component manufacturing. The outer edge 730 of the wafer 700 may be tapered, beveled, chamfered, square, rounded, etc.
晶圓700係自摻雜SiC晶棒切割的,該摻雜SiC晶棒的長度顯著大於(例如,10倍、20倍、50倍、70倍及更大)晶圓700的厚度712。Wafer 700 is cut from a doped SiC ingot having a length that is significantly greater (eg, 10x, 20x, 50x, 70x, and more) than thickness 712 of wafer 700 .
因此,晶圓700不是生長或沉積於不同類型的材料之基板層上的薄的摻雜型SiC層,然後自其移除基板層。此種薄的(例如,小於1 mm、小於0.5 mm)基板生長摻雜SiC層(基板已移除)具有與自摻雜SiC晶棒切割的摻雜SiC晶圓大為不同的電氣性質及物理性質。此類基板生長薄摻雜層具有材料內不可接受的應力,表現出翹曲及曲率,且一般而言不適合於任何種類的半導體元件製造。Therefore, wafer 700 does not have a thin doped SiC layer grown or deposited on a substrate layer of a different type of material, from which the substrate layer is then removed. Such thin (e.g., less than 1 mm, less than 0.5 mm) substrate-grown doped SiC layers (with the substrate removed) have electrical and physical properties that are significantly different from doped SiC wafers cut from self-doped SiC ingots. nature. Such substrates growing thin doped layers have unacceptable stresses within the material, exhibit warping and curvature, and are generally unsuitable for any kind of semiconductor device manufacturing.
實例5Example 5
6” (150 mm)的p型SiC晶圓。多型體為4H。摻雜劑為Al。定向為<0001>+/-0.5度。厚度為325 μm至500 μm。彎曲<40 μm。翹曲<60 μm。TTV <15 μm。SBIR (LTV) (平均為10mm x 10mm) <4 μm。MPD (微管) <0.2 cm -2。TSD (螺紋螺釘密度) <500 cm -2。BPD (基面錯位) <500 cm -2。電阻率為0.015 ohm-cm至0.028 ohm-cm。 6” (150 mm) p-type SiC wafer. Polytype is 4H. Dopant is Al. Orientation is <0001> +/-0.5 degrees. Thickness is 325 μm to 500 μm . Bend <40 μm m. Warpage <60 μm . TTV <15 μm . SBIR (LTV) (average 10mm x 10mm) <4 μm . MPD (Microtube) <0.2 cm -2 . TSD (Threaded Screw Density) <500 cm -2 . BPD (basal plane dislocation) <500 cm -2 . Resistivity 0.015 ohm-cm to 0.028 ohm-cm.
實例6Example 6
6” (150 mm)的低電阻率p型SiC晶圓。多型體為4H。摻雜劑為Al。定向為<0001>+/-0.5度。厚度為325 μm至500 μm。彎曲<40 μm。翹曲<60 μm。TTV <15 μm。SBIR (LTV) (平均為10mm x 10mm) <4 μm。MPD (微管) <0.2 cm -2。TSD (螺紋螺釘密度) <500 cm -2。BPD (基面錯位) <500 cm -2。電阻率為0.010 ohm-cm至0.003 ohm-cm。 6” (150 mm) low resistivity p-type SiC wafer. Polytype is 4H. Dopant is Al. Orientation is <0001> +/-0.5 degrees. Thickness is 325 μm to 500 μm . Bend <40 μm. Warpage <60 μm . TTV <15 μm . SBIR (LTV) (average 10mm x 10mm) <4 μm . MPD (Microtube) <0.2 cm -2 . TSD (Threaded Screw Density) <500 cm -2 . BPD (basal plane dislocation) <500 cm -2 . Resistivity 0.010 ohm-cm to 0.003 ohm-cm.
實例7Example 7
6” (150 mm)的p型SiC晶圓。多型體為6H。摻雜劑為Al。定向為<0001>+/-0.5度。厚度為325 μm至500 μm。彎曲<40 μm。翹曲<60 μm。TTV <15 μm。SBIR (LTV) (平均為10mm x 10mm) <4 μm。MPD (微管) <0.2 cm -2。TSD (螺紋螺釘密度) <500 cm -2。BPD (基面錯位) <500 cm -2。電阻率為0.015 ohm-cm至0.028 ohm-cm。 6” (150 mm) p-type SiC wafer. Polytype is 6H. Dopant is Al. Orientation is <0001> +/-0.5 degrees. Thickness is 325 μm to 500 μm . Bend <40 μm .Warp <60 μm . TTV <15 μm . SBIR (LTV) (average 10mm x 10mm) <4 μm . MPD (Microtube) <0.2 cm -2 .TSD (Threaded Screw Density) <500 cm -2 . BPD (basal plane dislocation) <500 cm -2 . Resistivity 0.015 ohm-cm to 0.028 ohm-cm.
實例8Example 8
6” (150 mm)的低電阻率p型SiC晶圓。多型體為6H。摻雜劑為Al。定向為<0001>+/-0.5度。厚度為325 μm至500 μm。彎曲<40 μm。翹曲<60 μm。TTV <15 μm。SBIR (LTV) (平均為10mm x 10mm) <4 μm。MPD (微管) <0.2 cm -2。TSD (螺紋螺釘密度) <500 cm -2。BPD (基面錯位) <500 cm -2。電阻率為0.010 ohm-cm至0.003 ohm-cm。 6” (150 mm) low resistivity p-type SiC wafer. Polytype is 6H. Dopant is Al. Orientation is <0001> +/-0.5 degrees. Thickness is 325 μm to 500 μm . Bend <40 μm. Warpage <60 μm . TTV <15 μm . SBIR (LTV) (average 10mm x 10mm) <4 μm . MPD (Microtube) <0.2 cm -2 . TSD (Threaded Screw Density) <500 cm -2 . BPD (basal plane dislocation) <500 cm -2 . Resistivity 0.010 ohm-cm to 0.003 ohm-cm.
實例9Example 9
6” (150 mm)的低電阻率n型SiC晶圓。多型體為4H。摻雜劑為P。定向為<0001>+/-0.5度。厚度為325 μm至500 μm。彎曲<40 μm。翹曲<60 μm。TTV <15 μm。SBIR (LTV) (平均為10mm x 10mm) <4 μm。MPD (微管) <0.2 cm -2。TSD (螺紋螺釘密度) <500 cm -2。BPD (基面錯位) <500 cm -2。電阻率為0.010 ohm-cm至0.003 ohm-cm。 6” (150 mm) low resistivity n-type SiC wafer. Polytype is 4H. Dopant is P. Orientation is <0001> +/-0.5 degrees. Thickness is 325 μm to 500 μm . Bend <40 μm. Warpage <60 μm . TTV <15 μm . SBIR (LTV) (average 10mm x 10mm) <4 μm . MPD (Microtube) <0.2 cm -2 . TSD (Threaded Screw Density) <500 cm -2 . BPD (basal plane dislocation) <500 cm -2 . Resistivity 0.010 ohm-cm to 0.003 ohm-cm.
實例10Example 10
6” (150 mm)的低電阻率n型SiC晶圓。多型體為6H。摻雜劑為P。定向為<0001>+/-0.5度。厚度為325 μm至500 μm。彎曲<40 μm。翹曲<60 μm。TTV <15 μm。SBIR (LTV) (平均為10mm x 10mm) <4 μm。MPD (微管) <0.2 cm -2。TSD (螺紋螺釘密度) <500 cm -2。BPD (基面錯位) <500 cm -2。電阻率為0.010 ohm-cm至0.003 ohm-cm。 6” (150 mm) low resistivity n-type SiC wafer. Polytype is 6H. Dopant is P. Orientation is <0001> +/-0.5 degrees. Thickness is 325 μm to 500 μm . Bend <40 μm. Warpage <60 μm . TTV <15 μm . SBIR (LTV) (average 10mm x 10mm) <4 μm . MPD (Microtube) <0.2 cm -2 . TSD (Threaded Screw Density) <500 cm -2 . BPD (basal plane dislocation) <500 cm -2 . Resistivity 0.010 ohm-cm to 0.003 ohm-cm.
實例11Example 11
轉至第5圖,展示了使用p型SiC晶圓的N通道E-MOSFET元件500。元件500具有閘極512、金屬電極505、金屬氧化物層504。元件500具有源極509、汲極508及主體510。電路511形成於元件509與主體510之間。源極509經由金屬電極連接至n型SiC 502。汲極508經由金屬電極連接至n型SiC 503。元件500具有p型基板501,該基板由自p型晶棒切割的p型晶圓製成。金屬氧化物層507與p型基板501相鄰。主體510經由電極507連接至p型基板501。Turning to Figure 5, an N-channel E-MOSFET device 500 using a p-type SiC wafer is shown. Component 500 has gate 512, metal electrode 505, and metal oxide layer 504. Component 500 has source 509, drain 508 and body 510. Circuit 511 is formed between element 509 and body 510 . Source 509 is connected to n-type SiC 502 via a metal electrode. Drain 508 is connected to n-type SiC 503 via a metal electrode. Component 500 has a p-type substrate 501 made from a p-type wafer cut from a p-type ingot. The metal oxide layer 507 is adjacent to the p-type substrate 501 . The main body 510 is connected to the p-type substrate 501 via electrodes 507 .
實例12Example 12
轉至第6圖,展示了使用p型SiC晶圓的P通道E-MOSFET元件600。元件600具有閘極612、金屬電極605、金屬氧化物層604。元件600具有源極609、汲極608及主體610。電路611形成於源極609與主體610之間。源極609經由金屬電極連接至p型SiC 602。汲極608經由金屬電極連接至p型SiC 603。p型SiC 602、603由自p型晶棒切割的p型晶圓製成。元件600具有n型基板601。金屬氧化物層607與n型基板601相鄰。主體610經由電極607連接至n型基板601。Turning to Figure 6, a P-channel E-MOSFET device 600 using a p-type SiC wafer is shown. Component 600 has gate 612, metal electrode 605, and metal oxide layer 604. Component 600 has source 609, drain 608 and body 610. Circuit 611 is formed between source 609 and body 610 . Source 609 is connected to p-type SiC 602 via a metal electrode. Drain 608 is connected to p-type SiC 603 via a metal electrode. p-type SiC 602, 603 are made from p-type wafers cut from p-type ingots. The element 600 has an n-type substrate 601 . Metal oxide layer 607 is adjacent to n-type substrate 601 . The body 610 is connected to the n-type substrate 601 via electrodes 607 .
實例13Example 13
轉至第7圖,展示了使用p型SiC晶圓的N通道D-MOSFET元件750。元件750具有閘極762、金屬電極755、金屬氧化物層754。元件750具有源極759、汲極758及主體760。電路761形成於源極759與主體760之間。源極759經由金屬電極連接至n型SiC 752。汲極758經由金屬電極連接至n型SiC 753。元件750具有N通道751,該N通道具有如箭頭764所示的通道長度。元件750具有p型基板763,該基板由自p型晶棒切割的p型晶圓製成。金屬氧化物層756與p型基板763及N通道751的一部分相鄰。主體760經由電極757連接至p型基板763。Turning to Figure 7, an N-channel D-MOSFET device 750 using a p-type SiC wafer is shown. Component 750 has gate 762, metal electrode 755, and metal oxide layer 754. Component 750 has a source 759 , a drain 758 and a body 760 . Circuit 761 is formed between source 759 and body 760 . Source 759 is connected to n-type SiC 752 via a metal electrode. Drain 758 is connected to n-type SiC 753 via a metal electrode. Element 750 has N channels 751 with channel lengths as indicated by arrow 764. Component 750 has a p-type substrate 763 made from a p-type wafer cut from a p-type ingot. The metal oxide layer 756 is adjacent to the p-type substrate 763 and a portion of the N channel 751 . Body 760 is connected to p-type substrate 763 via electrode 757 .
實例14Example 14
轉至第8圖,展示了使用p型SiC晶圓的P通道D-MOSFET元件800。元件800具有閘極812、金屬電極805、金屬氧化物層804。元件800具有源極809、汲極808及主體810。電路811形成於源極809與主體810之間。源極809經由金屬電極連接至p型SiC 802。汲極808經由金屬電極連接至p型SiC 803。p型SiC 802及803由自p型晶棒切割的p型晶圓製成。元件800具有P通道801,該P通道由自p型晶棒切割的p型晶圓製成。箭頭814指示通道長度。元件800具有n型基板813。金屬氧化物層806與n型基板813及P通道801的一部分相鄰。基極810經由電極807連接至n型基板813。Turning to Figure 8, a P-channel D-MOSFET device 800 using a p-type SiC wafer is shown. Component 800 has gate 812, metal electrode 805, and metal oxide layer 804. Component 800 has a source 809 , a drain 808 and a body 810 . Circuit 811 is formed between source 809 and body 810 . Source 809 is connected to p-type SiC 802 via a metal electrode. Drain 808 is connected to p-type SiC 803 via a metal electrode. p-type SiC 802 and 803 are made from p-type wafers cut from p-type ingots. Component 800 has a P-channel 801 made from a p-type wafer cut from a p-type ingot. Arrow 814 indicates channel length. Element 800 has an n-type substrate 813 . Metal oxide layer 806 is adjacent to n-type substrate 813 and a portion of P channel 801 . Base 810 is connected to n-type substrate 813 via electrode 807 .
實例15Example 15
轉至第9圖,展示了SiC IGBT元件900的橫截面示意圖。元件900係基於自p+型晶棒切割的p+型晶圓,其形成層901,以及元件900的多層結構中的其他p型材料。元件的其他層亦可基於PDC n型SiC晶圓。Turning to Figure 9, a schematic cross-section of SiC IGBT element 900 is shown. Device 900 is based on a p+ type wafer cut from a p+ type ingot, which forms layer 901, as well as other p-type materials in the multi-layer structure of device 900. Other layers of the device can also be based on PDC n-type SiC wafers.
實例16Example 16
轉至第10圖,展示了SiC橫向擴散MOSFET (Laterally Diffused MOSFET,LDMOS)元件1000的橫截面示意圖。元件1000係基於自p+型晶棒切割的p+型晶圓,其形成層1001,以及元件1000的多層結構中的其他其他p型材料。元件的其他層亦可基於PDC n型SiC晶圓。Turning to Figure 10, a cross-sectional schematic diagram of a SiC laterally diffused MOSFET (LDMOS) device 1000 is shown. Device 1000 is based on a p+ type wafer cut from a p+ type ingot, which forms layer 1001, as well as other other p-type materials in the multilayer structure of device 1000. Other layers of the device can also be based on PDC n-type SiC wafers.
實例17Example 17
轉至第11圖,展示了SiC VMOS MOSFET元件1100的橫截面示意圖。元件1100係基於自p型晶棒切割的p型晶圓,其形成元件1100的多層結構中的p型材料。元件的其他層亦可基於PDC n型SiC晶圓。Turning to Figure 11, a schematic cross-section of SiC VMOS MOSFET element 1100 is shown. Device 1100 is based on a p-type wafer cut from a p-type ingot, which forms the p-type material in the multi-layer structure of device 1100 . Other layers of the device can also be based on PDC n-type SiC wafers.
實例18Example 18
轉至第12圖,展示了SiC UMOS MOSFET元件1200的橫截面示意圖。元件1200係基於自p型晶棒切割的p型晶圓,其形成元件1200的多層結構中的p型材料。元件的其他層亦可基於PDC n型SiC晶圓。Turning to Figure 12, a schematic cross-section of SiC UMOS MOSFET element 1200 is shown. Device 1200 is based on a p-type wafer cut from a p-type ingot, which forms the p-type material in the multi-layer structure of device 1200 . Other layers of the device can also be based on PDC n-type SiC wafers.
實例19Example 19
轉至第13圖,展示了SiC IGBT元件1300的橫截面示意圖。元件1000係基於自p型晶棒切割的p型晶圓,其形成p基板層,以及元件1300的多層結構中的其他其他p型材料。元件的其他層亦可基於PDC n型SiC晶圓。Turning to Figure 13, a schematic cross-section of SiC IGBT element 1300 is shown. Device 1000 is based on a p-type wafer cut from a p-type ingot, which forms the p-substrate layer, as well as other other p-type materials in the multi-layer structure of device 1300. Other layers of the device can also be based on PDC n-type SiC wafers.
實例20Example 20
轉至第14圖,展示了SiC CMOS化合物元件1400的橫截面示意圖。元件1400係基於自p型晶棒切割的p型晶圓,其形成元件1400的多層及組成結構中的p基板材料。此處,PMOS元件及NMOS元件構建於共同的p型基板上,該p型基板係基於自p型晶棒切割的p型晶圓。淺溝槽隔離(Shallow trench isolation,ST)提供此等元件之間的電氣隔離。多個位準的金屬線經路徑選擇以互連該等元件且因此在晶片上形成電路。電容器、電阻器及電感器亦可整合至化合物元件1400中。Turning to Figure 14, a schematic cross-section of SiC CMOS compound device 1400 is shown. Device 1400 is based on a p-type wafer cut from a p-type ingot, which forms the p-substrate material in the multi-layer and component structure of device 1400. Here, the PMOS device and the NMOS device are built on a common p-type substrate, which is based on a p-type wafer cut from a p-type ingot. Shallow trench isolation (ST) provides electrical isolation between these components. Multiple levels of metal lines are routed to interconnect the components and thus form circuits on the wafer. Capacitors, resistors, and inductors may also be integrated into compound device 1400.
實例21Example 21
轉至第15圖,展示了SiC快閃記憶體元件1500的橫截面示意圖。在本發明之前,人們相信,快閃記憶體元件不能由SiC構建而成。SiC快閃記憶體元件1500具有線源1501、位元線1502、字線控制閘極1503、浮動閘極1504、n型SiC組件1505、第二n型SiC組件1506及p型層1507,該p型層係基於自p型晶棒切割的p型晶圓。Turning to Figure 15, a schematic cross-sectional view of SiC flash memory device 1500 is shown. Prior to this invention, it was believed that flash memory devices could not be constructed from SiC. The SiC flash memory device 1500 has a line source 1501, a bit line 1502, a word line control gate 1503, a floating gate 1504, an n-type SiC component 1505, a second n-type SiC component 1506 and a p-type layer 1507. Type layers are based on p-type wafers cut from p-type ingots.
實例22Example 22
轉至第16圖,展示了SiC CMOS化合物元件1600的實施例。此種元件用作類比及混合信號元件。該元件具有p型基板層,該p型基板層係基於自p型晶棒切割的p型晶圓。Turning to Figure 16, an embodiment of a SiC CMOS compound device 1600 is shown. Such components are used as analog and mixed-signal components. The device has a p-type substrate layer based on a p-type wafer cut from a p-type ingot.
實例23Example 23
低電阻率SiC晶圓在用於生產元件時提供顯著的優點,此係藉由消除對成本高的處理步驟(例如,對SiC基板進行研磨或薄化)的需要,而同時需要對電路系統的設計變化最少,且較佳地不需要任何設計變化。Low-resistivity SiC wafers offer significant advantages when used to produce devices by eliminating the need for costly processing steps (such as grinding or thinning the SiC substrate) while requiring circuitry improvements. Design changes are minimal and preferably no design changes are required.
實例24Example 24
低電阻率SiC晶圓,亦具有介於1 milliohm-cm與5 milliohm-cm之間的電阻率。Low-resistivity SiC wafers also have a resistivity between 1 milliohm-cm and 5 milliohm-cm.
實例25Example 25
氮比矽小很多。因此,已理論化的是,在晶體中,更小的雜質原子很可能佔據碳位點,更大的雜質原子佔據矽位點。在SiC晶體生長期間,氮可在晶體中佔據Si或C位點中之任一者或兩者。Nitrogen is much smaller than silicon. Therefore, it has been theorized that in the crystal, smaller impurity atoms are likely to occupy carbon sites and larger impurity atoms occupy silicon sites. During SiC crystal growth, nitrogen can occupy either or both Si or C sites in the crystal.
通常,摻雜SiC晶圓可具有100至1,000百萬分點的氮摻雜劑。已理論化的是,在生長期間供應的每100個氮原子中只有一個被吸至晶體中,即,變成電活性原子雜質。因此,來源必須大大高於所要的摻雜劑水準。(摻雜劑被「吸」至晶格中被稱為位點競爭)。然而,對可放入晶體中的氮的量有限制,太多則會使晶體扭曲,從而產生應力。在過去,用於降低電阻率的更高濃度的氮摻雜已導致對磊晶及元件效能有不利的影響之大量疊差及其他晶體品質缺陷。磷的大小更接近矽原子。因此,已理論化的是,在SiC結晶晶格內,磷將取代矽(而不是氮取代碳)且將引入少得多的應力(及更少的缺陷,因為缺陷形成係由晶體中的應力造成)。因此,已理論化的是,基於所需的摻雜劑,在用於製造摻磷n型SiC晶圓的源材料中,磷摻雜劑的較佳量將為所需氮摻雜劑的<10%。在較佳實施例中,製程使來自源材料的磷的>1%作為電活性原子雜質進入SiC晶體。Typically, doped SiC wafers can have 100 to 1,000 parts per million of nitrogen dopant. It has been theorized that only one out of every 100 nitrogen atoms supplied during growth is attracted into the crystal, i.e., becomes an electrically active atomic impurity. Therefore, the source must be significantly higher than the desired dopant level. (The "drawing" of dopants into the crystal lattice is called site competition). However, there is a limit to the amount of nitrogen that can be put into a crystal, and too much can distort the crystal, creating stress. In the past, higher concentrations of nitrogen doping to reduce resistivity have resulted in large amounts of stacking and other crystal quality defects that adversely affect epitaxy and device performance. Phosphorus is closer in size to silicon atoms. Therefore, it has been theorized that within the SiC crystal lattice, phosphorus will replace silicon (rather than nitrogen replacing carbon) and will introduce much less stress (and fewer defects, since defects are formed by stress in the crystal cause). Therefore, it has been theorized that based on the required dopants, the optimal amount of phosphorus dopant in the source material used to fabricate phosphorus doped n-type SiC wafers will be < 10%. In preferred embodiments, the process causes >1% of the phosphorus from the source material to enter the SiC crystal as an electrically active atomic impurity.
實例26Example 26
在用於生長SiC晶體的昇華製程中,通常存在的Si蒸氣多於C蒸氣,從而使其適合於併入氮,但是同時高Si蒸氣濃度不會使其本身適合於併入鋁或硼以便製造p型材料。然而,已理論化的是,氮或磷(每100個原子中1個)作為摻雜劑被併入,針對硼或鋁,每1,000個原子中只有1個被併入。In the sublimation process used to grow SiC crystals, there is usually more Si vapor than C vapor present, making it suitable for incorporation of nitrogen, but at the same time the high Si vapor concentration does not make itself suitable for incorporation of aluminum or boron for fabrication p-type material. However, it has been theorized that nitrogen or phosphorus (1 in 100 atoms) is incorporated as a dopant, and only 1 in 1,000 atoms for boron or aluminum is incorporated.
因此,為了有效的併入,已理論化的是,摻雜來源應具有相等或比矽更高的蒸氣壓力。鋁係p型晶圓的良好摻雜劑,因為它具有比矽更高的蒸氣壓力。鋁及矽在週期表上彼此靠近(實際上為相同大小的原子)。Therefore, for efficient incorporation, it has been theorized that the doping source should have a vapor pressure equal to or higher than that of silicon. Aluminum is a good dopant for p-type wafers because it has a higher vapor pressure than silicon. Aluminum and silicon are close to each other on the periodic table (actually the same size atoms).
實例27Example 27
作為磊晶層生長於基板(通常為n型SiC)上、可用於製造n通道IGBT之先前的4H碳化矽p型材料通常缺少品質及導電率來在IGBT中很好地工作,且特定而言,缺少品質及導電率來用作商業上可接受的IGBT。除其他事項外,本發明藉由提供自p型SiC晶棒切割的p型SiC晶圓來化解並解決此問題,該等晶圓提供製造商業上可接受的且可操作的SiC IGBT元件的能力。Previous 4H silicon carbide p-type materials that can be used to make n-channel IGBTs, grown as an epitaxial layer on a substrate (usually n-type SiC), generally lacked the quality and conductivity to work well in IGBTs, and in particular , lacks the quality and conductivity to be used as a commercially acceptable IGBT. The present invention resolves and solves this problem by, among other things, providing p-type SiC wafers cut from p-type SiC ingots that provide the ability to fabricate commercially acceptable and operable SiC IGBT devices. .
實例28Example 28
對SiC LDMOSFET (橫向金氧半場效電晶體)有長期存在的需要。此等元件係在用於高功率應用(諸如蜂巢式及UHF廣播傳輸)的矽中開發出的,且對此種元件的需要不斷增加。此係因為矽LDMOSFET相比雙極元件提供更高的增益及更好的線性。然而,在本發明之前,此種設計或類型的元件不能由SiC製成或基於SiC,因為僅有n型SiC基板且歷史上任何p型磊晶形成的SiC基板與矽相比都具有太高的電阻率,從而導致LDMOSFET元件效能不合意。除其他事項外,本發明藉由提供自p型SiC晶棒切割的p型SiC晶圓來化解並解決此問題,該等晶圓提供製造商業上可接受的且可操作的SiC LDMOSFET元件的能力。There is a long-standing need for SiC LDMOSFETs (lateral metal-oxide semi-field effect transistors). These components were developed in silicon for high-power applications such as cellular and UHF broadcast transmissions, and the demand for such components continues to increase. This is because silicon LDMOSFETs provide higher gain and better linearity than bipolar components. However, prior to this invention, components of this design or type could not be made of or based on SiC because there were only n-type SiC substrates and historically any p-type epitaxially formed SiC substrates had too high a resistance compared to silicon. resistivity, resulting in unsatisfactory LDMOSFET device performance. The present invention resolves and solves this problem by, among other things, providing p-type SiC wafers cut from p-type SiC ingots that provide the ability to fabricate commercially acceptable and operable SiC LDMOSFET devices. .
實例29Example 29
具有一或多種摻雜劑的聚矽碳前驅物配方,其具有預定量的受體雜質原子及預定量的施體雜質原子。以此方式,SiC源材料具有預定量的受體及施體雜質原子,且因此具有受體雜質原子與施體雜質原子的預定比率。此預定比率繼而向由該源材料生長的摻雜SiC提供預定的Nc值。A polysilica precursor formulation with one or more dopants, which has a predetermined amount of acceptor impurity atoms and a predetermined amount of donor impurity atoms. In this manner, the SiC source material has a predetermined amount of acceptor and donor impurity atoms, and therefore a predetermined ratio of acceptor impurity atoms to donor impurity atoms. This predetermined ratio in turn provides a predetermined Nc value to the doped SiC grown from the source material.
實例30Example 30
在聚矽碳前驅物的實施例中,針對Al-OH、P-OH或B-OH官能基的大部分併入利用了Si-OH官能性矽氧烷及矽烷,而不會產生氫。例如,如以下反應所示:In embodiments of polysilica precursors, Si-OH functional siloxanes and silane are utilized for the majority incorporation of Al-OH, P-OH, or B-OH functional groups without the generation of hydrogen. For example, as shown in the following reaction:
~Si-OH + ~B-OH → ~Si-O-B~ + H2O~Si-OH + ~B-OH → ~Si-O-B~ + H2O
實例31Example 31
具有大於10 kV、大於100 kV的電壓容量的SiC IGBT。SiC IGBT with voltage capacity greater than 10 kV and greater than 100 kV.
實例32Example 32
具有約2 kV的電壓容量的中壓SiC IGBT。Medium voltage SiC IGBT with voltage capacity of approximately 2 kV.
實例33Example 33
4” (100 mm)的p型SiC晶圓。多型體為4H。摻雜劑為Al。定向為<0001>+/-0.5度。厚度為325 μm至500 μm。彎曲<40 μm。翹曲<60 μm。TTV <15 μm。SBIR (LTV) (平均為10mm x 10mm) <4 μm。MPD (微管) <0.2 cm -2。TSD (螺紋螺釘密度) <500 cm -2。BPD (基面錯位) <500 cm -2。電阻率為0.015 ohm-cm至0.028 ohm-cm。 4” (100 mm) p-type SiC wafer. Polytype is 4H. Dopant is Al. Orientation is <0001> +/-0.5 degrees. Thickness is 325 μm to 500 μm . Bend <40 μm m. Warpage <60 μm . TTV <15 μm . SBIR (LTV) (average 10mm x 10mm) <4 μm . MPD (Microtube) <0.2 cm -2 . TSD (Threaded Screw Density) <500 cm -2 . BPD (basal plane dislocation) <500 cm -2 . Resistivity 0.015 ohm-cm to 0.028 ohm-cm.
實例34Example 34
4r (100 mm)的低電阻率p型SiC晶圓。多型體為4H。摻雜劑為Al。定向為<0001>+/-0.5度。厚度為325 μm至500 μm。彎曲<40 μm。翹曲<60 μm。TTV <15 μm。SBIR (LTV) (平均為10mm x 10mm) <4 μm。MPD (微管) <0.2 cm -2。TSD (螺紋螺釘密度) <500 cm -2。BPD (基面錯位) <500 cm -2。電阻率為0.010 ohm-cm至0.003 ohm-cm。 4r (100 mm) low resistivity p-type SiC wafer. The polytype is 4H. The dopant is Al. Orientation is <0001> +/-0.5 degrees. Thickness ranges from 325 μm to 500 μm . Bend <40 μm . Warpage <60 μm . TTV <15 μ m. SBIR (LTV) (average 10mm x 10mm) <4 μm . MPD (microtubules) <0.2 cm -2 . TSD (Threaded Screw Density) <500 cm -2 . BPD (basal plane dislocation) <500 cm -2 . Resistivity is 0.010 ohm-cm to 0.003 ohm-cm.
實例35Example 35
6” (150 mm)的p型SiC晶圓。多型體為6H。摻雜劑為Al。定向為<0001>+/-0.5度。厚度為325 μm至500 μm。彎曲<40 μm。翹曲<60 μm。TTV <15 μm。SBIR (LTV) (平均為10mm x 10mm) <4 μm。MPD (微管) <0.2 cm -2。TSD (螺紋螺釘密度) <500 cm -2。BPD (基面錯位) <500 cm -2。電阻率為0.015 ohm-cm至0.028 ohm-cm。 6” (150 mm) p-type SiC wafer. Polytype is 6H. Dopant is Al. Orientation is <0001> +/-0.5 degrees. Thickness is 325 μm to 500 μm . Bend <40 μm m. Warpage <60 μm . TTV <15 μm . SBIR (LTV) (average 10mm x 10mm) <4 μm . MPD (Microtube) <0.2 cm -2 . TSD (Threaded Screw Density) <500 cm -2 . BPD (basal plane dislocation) <500 cm -2 . Resistivity 0.015 ohm-cm to 0.028 ohm-cm.
實例36Example 36
6” (150 mm)的低電阻率p型SiC晶圓。多型體為6H。摻雜劑為Al。定向為<0001>+/-0.5度。厚度為325 μm至500 μm。彎曲<40 μm。翹曲<60 μm。TTV <15 μm。SBIR (LTV) (平均為10mm x 10mm) <4 μm。MPD (微管) <0.2 cm -2。TSD (螺紋螺釘密度) <500 cm -2。BPD (基面錯位) <500 cm -2。電阻率為0.010 ohm-cm至0.003 ohm-cm。 6” (150 mm) low resistivity p-type SiC wafer. Polytype is 6H. Dopant is Al. Orientation is <0001> +/-0.5 degrees. Thickness is 325 μm to 500 μm . Bend <40 μm . Warpage <60 μm . TTV <15 μm . SBIR (LTV) (average 10mm x 10mm) <4 μm . MPD (Microtube) <0.2 cm -2 . TSD (Threaded Screw Density) ) <500 cm -2 . BPD (basal plane dislocation) <500 cm -2 . Resistivity 0.010 ohm-cm to 0.003 ohm-cm.
實例37Example 37
4” (100 mm)的p型SiC晶圓。多型體為4H。摻雜劑為Al。定向為<0001>+/-0.5度。厚度為325 μm至500 μm。彎曲<40 μm。翹曲<60 μm。TTV <15 μm。SBIR (LTV) (平均為10mm x 10mm) <4 μm。MPD (微管) <0.2 cm -2。TSD (螺紋螺釘密度) <500 cm -2。BPD (基面錯位) <500 cm -2。晶圓N A為10 18/cm 3至約10 19/cm 3。 4” (100 mm) p-type SiC wafer. Polytype is 4H. Dopant is Al. Orientation is <0001> +/-0.5 degrees. Thickness is 325 μm to 500 μm . Bend <40 μm m. Warpage <60 μm . TTV <15 μm . SBIR (LTV) (average 10mm x 10mm) <4 μm . MPD (Microtube) <0.2 cm -2 . TSD (Threaded Screw Density) <500 cm -2 . BPD (basal plane dislocation) <500 cm -2 . Wafer N A is 10 18 /cm 3 to about 10 19 /cm 3 .
實例38Example 38
6” (150 mm)的p型SiC晶圓。多型體為4H。摻雜劑為Al。定向為<0001>+/-0.5度。厚度為325 μm至500 μm。彎曲<40 μm。翹曲<60 μm。TTV <15 μm。SBIR (LTV) (平均為10mm x 10mm) <4 μm。MPD (微管) <0.2 cm -2。TSD (螺紋螺釘密度) <500 cm -2。BPD (基面錯位) <500 cm -2。晶圓N A為10 18/cm 3至約10 19/cm 3。 6” (150 mm) p-type SiC wafer. Polytype is 4H. Dopant is Al. Orientation is <0001> +/-0.5 degrees. Thickness is 325 μm to 500 μm . Bend <40 μm m. Warpage <60 μm . TTV <15 μm . SBIR (LTV) (average 10mm x 10mm) <4 μm . MPD (Microtube) <0.2 cm -2 . TSD (Threaded Screw Density) <500 cm -2 . BPD (basal plane dislocation) <500 cm -2 . Wafer N A is 10 18 /cm 3 to about 10 19 /cm 3 .
實例39Example 39
6” (150 mm)的p型SiC晶圓。多型體為6H。摻雜劑為Al。定向為<0001>+/-0.5度。厚度為325 μm至500 μm。彎曲<40 μm。翹曲<60 μm。TTV <15 μm。SBIR (LTV) (平均為10mm x 10mm) <4 μm。MPD (微管) <0.2 cm -2。TSD (螺紋螺釘密度) <500 cm -2。BPD (基面錯位) <500 cm -2。晶圓N A為10 18/cm 3至約10 19/cm 3。 6” (150 mm) p-type SiC wafer. Polytype is 6H. Dopant is Al. Orientation is <0001> +/-0.5 degrees. Thickness is 325 μm to 500 μm . Bend <40 μm m. Warpage <60 μm . TTV <15 μm . SBIR (LTV) (average 10mm x 10mm) <4 μm . MPD (Microtube) <0.2 cm -2 . TSD (Threaded Screw Density) <500 cm -2 . BPD (basal plane dislocation) <500 cm -2 . Wafer N A is 10 18 /cm 3 to about 10 19 /cm 3 .
實例40Example 40
4” (100 mm)的p型SiC晶圓。多型體為4H。摻雜劑為Al。定向為<0001>+/-0.5度。厚度為325 μm至500 μm。彎曲<40 μm。翹曲<60 μm。TTV <15 μm。SBIR (LTV) (平均為10mm x 10mm) <4 μm。MPD (微管) <0.2 cm -2。TSD (螺紋螺釘密度) <500 cm -2。BPD (基面錯位) <500 cm -2。晶圓N A為10 18/cm 3至約10 19/cm 3。 4” (100 mm) p-type SiC wafer. Polytype is 4H. Dopant is Al. Orientation is <0001> +/-0.5 degrees. Thickness is 325 μm to 500 μm . Bend <40 μm m. Warpage <60 μm . TTV <15 μm . SBIR (LTV) (average 10mm x 10mm) <4 μm . MPD (Microtube) <0.2 cm -2 . TSD (Threaded Screw Density) <500 cm -2 . BPD (basal plane dislocation) <500 cm -2 . Wafer N A is 10 18 /cm 3 to about 10 19 /cm 3 .
實例41Example 41
4” (100 mm)的p型SiC晶圓。多型體為6H。摻雜劑為Al。定向為<0001>+/-0.5度。厚度為325 μm至500 μm。彎曲<40 μm。翹曲<60 μm。TTV <15 μm。SBIR (LTV) (平均為10mm x 10mm) <4 μm。MPD (微管) <0.2 cm -2。TSD (螺紋螺釘密度) <500 cm -2。BPD (基面錯位) <500 cm -2。晶圓N A為10 18/cm 3至約10 19/cm 3。 4” (100 mm) p-type SiC wafer. Polytype is 6H. Dopant is Al. Orientation is <0001> +/-0.5 degrees. Thickness is 325 μm to 500 μm . Bend <40 μm m. Warpage <60 μm . TTV <15 μm . SBIR (LTV) (average 10mm x 10mm) <4 μm . MPD (Microtube) <0.2 cm -2 . TSD (Threaded Screw Density) <500 cm -2 . BPD (basal plane dislocation) <500 cm -2 . Wafer N A is 10 18 /cm 3 to about 10 19 /cm 3 .
實例42Example 42
4” (100 mm)的低電阻率n型SiC晶圓。多型體為4H。摻雜劑為P。定向為<0001>+/-0.5度。厚度為325 μm至500 μm。彎曲<40 μm。翹曲<60 μm。TTV <15 μm。SBIR (LTV) (平均為10mm x 10mm) <4 μm。MPD (微管) <0.2 cm -2。TSD (螺紋螺釘密度) <500 cm -2。BPD (基面錯位) <500 cm -2。電阻率為0.010 ohm-cm至0.003 ohm-cm。 4” (100 mm) low resistivity n-type SiC wafer. Polytype is 4H. Dopant is P. Orientation is <0001> +/-0.5 degrees. Thickness is 325 μm to 500 μm . Bend <40 μm . Warpage <60 μm . TTV <15 μm . SBIR (LTV) (average 10mm x 10mm) <4 μm . MPD (Microtube) <0.2 cm -2 . TSD (Threaded Screw Density) ) <500 cm -2 . BPD (basal plane dislocation) <500 cm -2 . Resistivity 0.010 ohm-cm to 0.003 ohm-cm.
實例43Example 43
4” (100 mm)的低電阻率p型SiC晶圓。多型體為6H。摻雜劑為P。定向為<0001>+/-0.5度。厚度為325 μm至500 μm。彎曲<40 μm。翹曲<60 μm。TTV <15 μm。SBIR (LTV) (平均為10mm x 10mm) <4 μm。MPD (微管) <0.2 cm -2。TSD (螺紋螺釘密度) <500 cm -2。BPD (基面錯位) <500 cm -2。電阻率為0.010 ohm-cm至0.003 ohm-cm。 4” (100 mm) low resistivity p-type SiC wafer. Polytype is 6H. Dopant is P. Orientation is <0001> +/-0.5 degrees. Thickness is 325 μm to 500 μm . Bend <40 μm . Warpage <60 μm . TTV <15 μm . SBIR (LTV) (average 10mm x 10mm) <4 μm . MPD (Microtube) <0.2 cm -2 . TSD (Threaded Screw Density) ) <500 cm -2 . BPD (basal plane dislocation) <500 cm -2 . Resistivity 0.010 ohm-cm to 0.003 ohm-cm.
實例44Example 44
6” (150 mm)的低電阻率n型SiC晶圓。多型體為4H。摻雜劑為P。定向為<0001>+/-0.5度。厚度為325 μm至500 μm。彎曲<40 μm。翹曲<60 μm。TTV <15 μm。SBIR (LTV) (平均為10mm x 10mm) <4 μm。MPD (微管) <0.2 cm -2。TSD (螺紋螺釘密度) <500 cm -2。BPD (基面錯位) <500 cm -2。電阻率為0.010 ohm-cm至0.003 ohm-cm。 6” (150 mm) low resistivity n-type SiC wafer. Polytype is 4H. Dopant is P. Orientation is <0001> +/-0.5 degrees. Thickness is 325 μm to 500 μm . Bend <40 μm . Warpage <60 μm . TTV <15 μm . SBIR (LTV) (average 10mm x 10mm) <4 μm . MPD (Microtube) <0.2 cm -2 . TSD (Threaded Screw Density) ) <500 cm -2 . BPD (basal plane dislocation) <500 cm -2 . Resistivity 0.010 ohm-cm to 0.003 ohm-cm.
實例45Example 45
6” (150 mm)的低電阻率p型SiC晶圓。多型體為6H。摻雜劑為P。定向為<0001>+/-0.5度。厚度為325 μm至500 μm。彎曲<40 μm。翹曲<60 μm。TTV <15 μm。SBIR (LTV) (平均為10mm x 10mm) <4 μm。MPD (微管) <0.2 cm -2。TSD (螺紋螺釘密度) <500 cm -2。BPD (基面錯位) <500 cm -2。電阻率為0.010 ohm-cm至0.003 ohm-cm。 6” (150 mm) low resistivity p-type SiC wafer. Polytype is 6H. Dopant is P. Orientation is <0001> +/-0.5 degrees. Thickness is 325 μm to 500 μm . Bend <40 μm . Warpage <60 μm . TTV <15 μm . SBIR (LTV) (average 10mm x 10mm) <4 μm . MPD (Microtube) <0.2 cm -2 . TSD (Threaded Screw Density) ) <500 cm -2 . BPD (basal plane dislocation) <500 cm -2 . Resistivity 0.010 ohm-cm to 0.003 ohm-cm.
實例46Example 46
4” (100 mm)的低電阻率n型SiC晶圓。多型體為4H。摻雜劑為P。定向為<0001>+/-0.5度。厚度為325 μm至500 μm。彎曲<40 μm。翹曲<60 μm。TTV <15 μm。SBIR (LTV) (平均為10mm x 10mm) <4 μm。MPD (微管) <0.2 cm -2。TSD (螺紋螺釘密度) <500 cm -2。BPD (基面錯位) <500 cm -2。電阻率為0.010 ohm-cm至0.003 ohm-cm。 4” (100 mm) low resistivity n-type SiC wafer. Polytype is 4H. Dopant is P. Orientation is <0001> +/-0.5 degrees. Thickness is 325 μm to 500 μm . Bend <40 μm . Warpage <60 μm . TTV <15 μm . SBIR (LTV) (average 10mm x 10mm) <4 μm . MPD (Microtube) <0.2 cm -2 . TSD (Threaded Screw Density) ) <500 cm -2 . BPD (basal plane dislocation) <500 cm -2 . Resistivity 0.010 ohm-cm to 0.003 ohm-cm.
實例47Example 47
4” (100 mm)的低電阻率p型SiC晶圓。多型體為6H。摻雜劑為p。定向為<0001>+/-0.5度。厚度為325 μm至500 μm。彎曲<40 μm。翹曲<60 μm。TTV <15 μm。SBIR (LTV) (平均為10mm x 10mm) <4 μm。MPD (微管) <0.2 cm -2。TSD (螺紋螺釘密度) <500 cm -2。BPD (基面錯位) <500 cm -2。電阻率為0.010 ohm-cm至0.003 ohm-cm。 4” (100 mm) low resistivity p-type SiC wafer. Polytype is 6H. Dopant is p. Orientation is <0001> +/-0.5 degrees. Thickness is 325 μm to 500 μm . Bend <40 μm . Warpage <60 μm . TTV <15 μm . SBIR (LTV) (average 10mm x 10mm) <4 μm . MPD (Microtube) <0.2 cm -2 . TSD (Threaded Screw Density) ) <500 cm -2 . BPD (basal plane dislocation) <500 cm -2 . Resistivity 0.010 ohm-cm to 0.003 ohm-cm.
實例48Example 48
6” (150 mm)的低電阻率n型SiC晶圓。多型體為4H。摻雜劑為P。定向為<0001>+/-0.5度。厚度為325 μm至500 μm。彎曲<40 μm。翹曲<60 μm。TTV <15 μm。SBIR (LTV) (平均為10mm x 10mm) <4 μm。MPD (微管) <0.2 cm -2。TSD (螺紋螺釘密度) <500 cm -2。BPD (基面錯位) <500 cm -2。電阻率為0.010 ohm-cm至0.003 ohm-cm。 6” (150 mm) low resistivity n-type SiC wafer. Polytype is 4H. Dopant is P. Orientation is <0001> +/-0.5 degrees. Thickness is 325 μm to 500 μm . Bend <40 μm . Warpage <60 μm . TTV <15 μm . SBIR (LTV) (average 10mm x 10mm) <4 μm . MPD (Microtube) <0.2 cm -2 . TSD (Threaded Screw Density) ) <500 cm -2 . BPD (basal plane dislocation) <500 cm -2 . Resistivity 0.010 ohm-cm to 0.003 ohm-cm.
實例49Example 49
6” (150 mm)的低電阻率p型SiC晶圓。多型體為6H。摻雜劑為P。定向為<0001>+/-0.5度。厚度為325 μm至500 μm。彎曲<40 μm。翹曲<60 μm。TTV <15 μm。SBIR (LTV) (平均為10mm x 10mm) <4 μm。MPD (微管) <0.2 cm -2。TSD (螺紋螺釘密度) <500 cm -2。BPD (基面錯位) <500 cm -2。電阻率為0.010 ohm-cm至0.003 ohm-cm。 標題及實施例 6” (150 mm) low resistivity p-type SiC wafer. Polytype is 6H. Dopant is P. Orientation is <0001> +/-0.5 degrees. Thickness is 325 μm to 500 μm . Bend <40 μm . Warpage <60 μm . TTV <15 μm . SBIR (LTV) (average 10mm x 10mm) <4 μm . MPD (Microtube) <0.2 cm -2 . TSD (Threaded Screw Density) ) <500 cm -2 . BPD (basal plane dislocation) <500 cm -2 . Resistivity 0.010 ohm-cm to 0.003 ohm-cm. Title and Examples
應理解,在本說明書中使用標題係為了清楚起見,且以任何方式都沒有限制性。因此,在標題下描述的製程及揭示內容應在本說明書全文(包括各種實例)的上下文中閱讀。在本說明書中使用標題不應限制給予本發明的保護範疇。It should be understood that headings are used in this specification for the sake of clarity and are not limiting in any way. Accordingly, the processes and disclosures described under the headings should be read in the context of the entirety of this specification, including the various examples. The use of headings in this specification shall not limit the scope of protection afforded to the invention.
應注意,不要求提供或化解作為新穎且開創性的製程、材料、效能或其他有益特徵及性質的基礎的理論,該等製程、材料、效能或其他有益特徵及性質係本發明之實施例的標的物或與該等實施例相關聯。然而,本說明書中提供各種理論以進一步推進此項技術領域。此等理論在本說明書中提出,且除非另有明確說明,否則絕不限制、局限或窄化將給予所主張的發明的保護範疇。可能不需要或實踐此等理論就能利用本發明。應進一步理解,本發明可引起新的且迄今未知的理論以解釋本發明的方法、製品、材料、元件及系統的實施例之功能特徵;且此類後開發的理論不應限制給予本發明的保護範疇。It should be noted that there is no requirement to provide or resolve theories underlying the novel and groundbreaking processes, materials, performance, or other beneficial features and properties that are embodiments of the present invention. Subject matter may be associated with these embodiments. However, various theories are provided in this specification to further advance this technical field. These theories are presented in this specification and, unless expressly stated otherwise, in no way limit, limit, or narrow the scope of protection to be afforded to the claimed invention. No such theory may be required or practiced to utilize the invention. It should be further understood that the present invention may give rise to new and heretofore unknown theories to explain the functional characteristics of embodiments of the methods, articles, materials, components and systems of the present invention; and such subsequently developed theories should not limit the scope of the present invention. protection scope.
本說明書中陳述的配方、組合物、製品、塑膠、陶瓷、材料、零件、晶圓、晶棒、體積結構、用途、應用、設備、方法、活動及操作的各種實施例可用於各種其他領域且用於各種其他活動、用途及實施例。另外,此等實施例例如可與現有的系統、製品、組合物、材料、操作或活動一起使用;可與可在未來開發的系統、製品、組合物、材料、操作或活動一起使用;且與可部分地基於本說明書的教示進行修改的此類系統、製品、組合物、材料、操作或活動一起使用。另外,本說明書中陳述的各種實施例及實例可整體地或部分地且以不同的及各種組合與彼此一起使用。因此,例如,本說明書的各種實施例中提供的組態可與彼此一起使用。例如,根據本說明書的教示,具有A、A’及B的實施例的組件及具有A’’、C及D的實施例的組件可以各種組合(例如,A、C、D及A,A’’、C及D等)與彼此一起使用。因此,給予本發明的保護範疇不應限於在特定實施例、實例中或者在特定圖中的實施例中陳述的特定實施例、組態或配置。The various embodiments of formulations, compositions, articles, plastics, ceramics, materials, parts, wafers, ingots, volumetric structures, uses, applications, equipment, methods, activities and operations set forth in this specification may be used in a variety of other fields and for various other activities, uses and embodiments. Additionally, such embodiments may be used, for example, with existing systems, articles, compositions, materials, operations, or activities; with systems, articles, compositions, materials, operations, or activities that may be developed in the future; and with Such systems, articles, compositions, materials, operations, or activities may be used with modifications based in part on the teachings of this specification. Additionally, the various embodiments and examples set forth in this specification may be used with each other, in whole or in part, and in different and various combinations. Thus, for example, configurations provided in various embodiments of this specification may be used with each other. For example, in accordance with the teachings of this specification, components of the embodiments having A, A', and B and components of the embodiments having A'', C, and D may be combined in various combinations (e.g., A, C, D, and A, A' ', C and D, etc.) are used together with each other. Therefore, the scope of protection afforded to this invention should not be limited to the specific embodiments, configurations, or configurations set forth in the specific embodiments, examples, or embodiments in the specific figures.
本發明可體現為除本文中特別揭示的形式以外的其他形式而不脫離本發明的精神或基本特性。所描述的實施例應在所有方面僅被視為說明性的而非限制性的。The present invention may be embodied in other forms than those specifically disclosed herein without departing from the spirit or essential characteristics of the invention. The described embodiments are to be considered in all respects as illustrative only and not restrictive.
150a,150b:儲存罐 150c:單獨的儲存罐、鬥或倉 151a,151b:蒸餾裝置 152:混合器 153:容器 154:爐 155a,155b,155c:熱解爐 157a:無塵室環境 158a,158b,158c:掃氣入口線路 159a,159b,159c,160a,160b,160c:廢氣排放線路 161:掃氣入口 162:廢氣排放線路 163:廢氣處理總成 164:入口線路 170:黏結劑罐 171:線路 172:混合容器 173:混合元件 175:形成裝置 177:烘箱 180:包裝元件 190:體積形狀形成區域 190a,190b,190c:無塵室或無塵室區域 500:N通道E-MOSFET元件 501:p型基板 502:n型SiC 503:n型SiC 504:金屬氧化物層 505:金屬電極 507:電極 508:汲極 509:源極 510:主體 511:電路 512:閘極 600:P通道E-MOSFET元件 601:n型基板 602:p型SiC 603:p型SiC 604:金屬氧化物層 605:金屬電極 607:電極 608:汲極 609:源極 610:主體 611:電路 612:閘極 700:晶圓 705:形狀 706:平面 710:頂部或頂部表面 711:底部或底部表面 712:晶圓的厚度 730:外邊緣 750:N通道D-MOSFET元件 751:N通道 752:n型SiC 753:n型SiC 754:金屬氧化物層 755:金屬電極 756:金屬氧化物層 757:電極 758:汲極 759:源極 760:主體 761:電路 762:p型基板 763:p型基板 764:通道長度 800:P通道D-MOSFET元件 801:P通道 802:p型SiC 803:p型SiC 804:金屬氧化物層 805:金屬電極 806:金屬氧化物層 807:電極 808:汲極 809:源極 810:主體 811:電路 812:閘極 813:n型基板 814:通道長度 900:SiC IGBT元件 901:層 1000:SiC橫向擴散MOSFET元件 1001:層 1100:SiC VMOS MOSFET元件 1200:SiC UMOS MOSFET元件 1300:SiC IGBT元件 1400:SiC CMOS化合物元件 1500:SiC快閃記憶體元件 1501:線源 1502:位元線 1503:字線控制閘極 1504:浮動閘極 1505:n型SiC組件 1506:第二n型SiC組件 1507:p型層 1600:SiC CMOS化合物元件 1800:氣相沉積元件 1801:成形裝藥 1802:種晶 1802a:表面 1803:可移動平台 1804:加熱元件 1805,1806,1807:埠 1808:側壁 1809:底部或底部壁 1810:頂部或頂部壁 1820:成形裝藥的直徑 1821:成形裝藥的高度 1822:種晶的橫截面或直徑 1823:上表面或頂部表面 1824:底部表面 1850:區域 150a,150b: storage tank 150c: Separate storage tank, bucket or warehouse 151a,151b: Distillation device 152:Mixer 153:Container 154:furnace 155a, 155b, 155c: Pyrolysis furnace 157a: Clean room environment 158a, 158b, 158c: scavenging inlet line 159a, 159b, 159c, 160a, 160b, 160c: exhaust gas emission lines 161:Scavenging air inlet 162: Exhaust gas emission line 163: Exhaust gas treatment assembly 164: Entrance line 170:Binder tank 171:Line 172: Mixing container 173: Mixing element 175: Forming device 177:Oven 180:Packaging components 190:Volume shape forming area 190a, 190b, 190c: Clean room or clean room area 500:N-channel E-MOSFET component 501: p-type substrate 502:n-type SiC 503:n-type SiC 504: Metal oxide layer 505: Metal electrode 507:Electrode 508:Jiji 509:Source 510:Subject 511:Circuit 512: Gate 600:P channel E-MOSFET component 601: n-type substrate 602: p-type SiC 603: p-type SiC 604: Metal oxide layer 605: Metal electrode 607:Electrode 608:Jiji 609:Source 610:Subject 611:Circuit 612: Gate 700:wafer 705:Shape 706:Plane 710:Top or top surface 711: Bottom or bottom surface 712: Wafer thickness 730:Outer edge 750:N-channel D-MOSFET component 751:N channel 752:n-type SiC 753:n-type SiC 754: Metal oxide layer 755:Metal electrode 756: Metal oxide layer 757:Electrode 758:Jiji 759:Source 760:Subject 761:Circuit 762: p-type substrate 763: p-type substrate 764:Channel length 800:P channel D-MOSFET component 801:P channel 802: p-type SiC 803: p-type SiC 804: Metal oxide layer 805: Metal electrode 806: Metal oxide layer 807:Electrode 808: Drainage 809:Source 810:Subject 811:Circuit 812: Gate 813: n-type substrate 814:Channel length 900:SiC IGBT component 901:Layer 1000:SiC lateral diffusion MOSFET element 1001:Layer 1100:SiC VMOS MOSFET components 1200:SiC UMOS MOSFET components 1300:SiC IGBT components 1400:SiC CMOS compound element 1500:SiC flash memory device 1501: Line source 1502:Bit line 1503: Word line control gate 1504: Floating gate 1505: n-type SiC component 1506: Second n-type SiC component 1507: p-type layer 1600:SiC CMOS compound element 1800: Vapor deposition components 1801: shaped charge 1802:Seed crystal 1802a: Surface 1803:Mobile platform 1804:Heating element 1805,1806,1807:port 1808:Side wall 1809: Bottom or bottom wall 1810:Top or top wall 1820: Diameter of shaped charge 1821:Height of shaped charge 1822: Cross-section or diameter of seed crystal 1823: Upper surface or top surface 1824: Bottom surface 1850:Region
第1圖係根據本發明之150 mm p型SiC晶體的實施例的相片。Figure 1 is a photograph of an embodiment of a 150 mm p-type SiC crystal according to the present invention.
第2A圖係根據本發明之摻雜SiC晶圓的實施例的平面示意圖。Figure 2A is a schematic plan view of an embodiment of a doped SiC wafer according to the present invention.
第2B圖係第2A圖的晶圓之沿著線B-B獲得的橫截面示意圖。Figure 2B is a schematic cross-sectional view of the wafer of Figure 2A taken along line B-B.
第3圖係根據本發明之系統及方法的實施例的製程流程圖。Figure 3 is a process flow diagram according to an embodiment of the system and method of the present invention.
第4圖係根據本發明之氣相沉積裝置及製程的實施例的示意性橫截面示意圖。Figure 4 is a schematic cross-sectional view of an embodiment of a vapor deposition apparatus and process according to the present invention.
第5圖係根據本發明之利用p型SiC晶圓的N通道E-MOSFET元件的實施例的示意性橫截面示意圖。Figure 5 is a schematic cross-sectional view of an embodiment of an N-channel E-MOSFET device using a p-type SiC wafer according to the present invention.
第6圖係根據本發明之利用p型SiC晶圓的P通道E-MOSFET元件的實施例的示意性橫截面視圖。Figure 6 is a schematic cross-sectional view of an embodiment of a P-channel E-MOSFET device using a p-type SiC wafer according to the present invention.
第7圖係根據本發明之利用p型SiC晶圓的N通道D-MOSFET元件的實施例的示意性橫截面示意圖。Figure 7 is a schematic cross-sectional view of an embodiment of an N-channel D-MOSFET device using a p-type SiC wafer according to the present invention.
第8圖係根據本發明之利用p型SiC晶圓的P通道D-MOSFET元件的實施例的示意性橫截面示意圖。Figure 8 is a schematic cross-sectional view of an embodiment of a P-channel D-MOSFET device using a p-type SiC wafer according to the present invention.
第9圖係根據本發明之利用p型SiC晶圓的IGBT元件的實施例的示意性橫截面示意圖。Figure 9 is a schematic cross-sectional view of an embodiment of an IGBT element using a p-type SiC wafer according to the present invention.
第10圖係根據本發明之利用p型SiC晶圓的橫向擴散MOSFET (Laterally Diffused MOSFET,LDMOS)元件的實施例的示意性橫截面示意圖。Figure 10 is a schematic cross-sectional view of an embodiment of a Laterally Diffused MOSFET (LDMOS) device using a p-type SiC wafer according to the present invention.
第11圖係根據本發明之利用p型SiC晶圓的VMOS MOSFET元件的實施例的示意性橫截面示意圖。FIG. 11 is a schematic cross-sectional view of an embodiment of a VMOS MOSFET device using a p-type SiC wafer according to the present invention.
第12圖係根據本發明之利用p型SiC晶圓的UMOS MOSFET元件的實施例的示意性橫截面示意圖。FIG. 12 is a schematic cross-sectional view of an embodiment of a UMOS MOSFET device using a p-type SiC wafer according to the present invention.
第13圖係根據本發明之利用p型SiC晶圓的IGTB元件的實施例的示意性橫截面示意圖。Figure 13 is a schematic cross-sectional view of an embodiment of an IGTB device using a p-type SiC wafer according to the present invention.
第14圖係根據本發明之利用p型SiC晶圓的CMOS化合物元件的實施例的示意性橫截面視圖。Figure 14 is a schematic cross-sectional view of an embodiment of a CMOS compound device using a p-type SiC wafer according to the present invention.
第15圖係根據本發明之利用p型SiC晶圓的快閃記憶體元件的實施例的示意性橫截面視圖。Figure 15 is a schematic cross-sectional view of an embodiment of a flash memory device using a p-type SiC wafer according to the present invention.
第16圖係根據本發明之利用p型SiC晶圓的f CMOS化合物元件的示意性橫截面視圖。Figure 16 is a schematic cross-sectional view of an f CMOS compound device using a p-type SiC wafer according to the present invention.
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